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dt-bindings: phy: airoha: Add PCIe PHY controller

Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY
controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/656133f865433c1d02f00a3abbb1aa9312d2a24e.1718485860.git.lorenzo@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Lorenzo Bianconi and committed by
Vinod Koul e2d0317e aefa036b

+58
+58
Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Airoha EN7581 PCI-Express PHY 8 + 9 + maintainers: 10 + - Lorenzo Bianconi <lorenzo@kernel.org> 11 + 12 + description: 13 + The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port. 14 + 15 + properties: 16 + compatible: 17 + const: airoha,en7581-pcie-phy 18 + 19 + reg: 20 + items: 21 + - description: PCIE analog base address 22 + - description: PCIE lane0 base address 23 + - description: PCIE lane1 base address 24 + 25 + reg-names: 26 + items: 27 + - const: csr-2l 28 + - const: pma0 29 + - const: pma1 30 + 31 + "#phy-cells": 32 + const: 0 33 + 34 + required: 35 + - compatible 36 + - reg 37 + - reg-names 38 + - "#phy-cells" 39 + 40 + additionalProperties: false 41 + 42 + examples: 43 + - | 44 + #include <dt-bindings/phy/phy.h> 45 + 46 + soc { 47 + #address-cells = <2>; 48 + #size-cells = <2>; 49 + 50 + phy@11e80000 { 51 + compatible = "airoha,en7581-pcie-phy"; 52 + #phy-cells = <0>; 53 + reg = <0x0 0x1fa5a000 0x0 0xfff>, 54 + <0x0 0x1fa5b000 0x0 0xfff>, 55 + <0x0 0x1fa5c000 0x0 0xfff>; 56 + reg-names = "csr-2l", "pma0", "pma1"; 57 + }; 58 + };