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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge tag 'renesas-fixes-for-v7.0-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes
Renesas fixes for v7.0
- Fix SD card initialization on the RZ/T2H and RZ/N2H EVK boards,
- Remove WDT nodes meant for other CPU cores on the RZ/V2H(P) SoC,
- Fix Clock Pulse Generator registers on the RZ/T2H and RZ/N2H SoCs,
- Fix Versa3-related boot hangs on the RZ/G3S SoM,
- Fix Extended SPI interrupts on the R-Car X5H SoC.
* tag 'renesas-fixes-for-v7.0-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: r8a78000: Fix out-of-range SPI interrupt numbers
arm64: dts: renesas: rzg3s-smarc-som: Set bypass for Versa3 PLL2
arm64: dts: renesas: r9a09g087: Fix CPG register region sizes
arm64: dts: renesas: r9a09g077: Fix CPG register region sizes
arm64: dts: renesas: r9a09g057: Remove wdt{0,2,3} nodes
arm64: dts: renesas: rzv2-evk-cn15-sd: Add ramp delay for SD0 regulator
arm64: dts: renesas: rzt2h-n2h-evk: Add ramp delay for SD0 card regulator
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
+15
-43
+8
-8
arch/arm64/boot/dts/renesas/r8a78000.dtsi
+8
-8
arch/arm64/boot/dts/renesas/r8a78000.dtsi
···
698
698
compatible = "renesas,scif-r8a78000",
699
699
"renesas,rcar-gen5-scif", "renesas,scif";
700
700
reg = <0 0xc0700000 0 0x40>;
701
-
interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>;
701
+
interrupts = <GIC_ESPI 10 IRQ_TYPE_LEVEL_HIGH>;
702
702
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
703
703
clock-names = "fck", "brg_int", "scif_clk";
704
704
status = "disabled";
···
708
708
compatible = "renesas,scif-r8a78000",
709
709
"renesas,rcar-gen5-scif", "renesas,scif";
710
710
reg = <0 0xc0704000 0 0x40>;
711
-
interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>;
711
+
interrupts = <GIC_ESPI 11 IRQ_TYPE_LEVEL_HIGH>;
712
712
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
713
713
clock-names = "fck", "brg_int", "scif_clk";
714
714
status = "disabled";
···
718
718
compatible = "renesas,scif-r8a78000",
719
719
"renesas,rcar-gen5-scif", "renesas,scif";
720
720
reg = <0 0xc0708000 0 0x40>;
721
-
interrupts = <GIC_SPI 4076 IRQ_TYPE_LEVEL_HIGH>;
721
+
interrupts = <GIC_ESPI 12 IRQ_TYPE_LEVEL_HIGH>;
722
722
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
723
723
clock-names = "fck", "brg_int", "scif_clk";
724
724
status = "disabled";
···
728
728
compatible = "renesas,scif-r8a78000",
729
729
"renesas,rcar-gen5-scif", "renesas,scif";
730
730
reg = <0 0xc070c000 0 0x40>;
731
-
interrupts = <GIC_SPI 4077 IRQ_TYPE_LEVEL_HIGH>;
731
+
interrupts = <GIC_ESPI 13 IRQ_TYPE_LEVEL_HIGH>;
732
732
clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>;
733
733
clock-names = "fck", "brg_int", "scif_clk";
734
734
status = "disabled";
···
738
738
compatible = "renesas,hscif-r8a78000",
739
739
"renesas,rcar-gen5-hscif", "renesas,hscif";
740
740
reg = <0 0xc0710000 0 0x60>;
741
-
interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>;
741
+
interrupts = <GIC_ESPI 14 IRQ_TYPE_LEVEL_HIGH>;
742
742
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
743
743
clock-names = "fck", "brg_int", "scif_clk";
744
744
status = "disabled";
···
748
748
compatible = "renesas,hscif-r8a78000",
749
749
"renesas,rcar-gen5-hscif", "renesas,hscif";
750
750
reg = <0 0xc0714000 0 0x60>;
751
-
interrupts = <GIC_SPI 4079 IRQ_TYPE_LEVEL_HIGH>;
751
+
interrupts = <GIC_ESPI 15 IRQ_TYPE_LEVEL_HIGH>;
752
752
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
753
753
clock-names = "fck", "brg_int", "scif_clk";
754
754
status = "disabled";
···
758
758
compatible = "renesas,hscif-r8a78000",
759
759
"renesas,rcar-gen5-hscif", "renesas,hscif";
760
760
reg = <0 0xc0718000 0 0x60>;
761
-
interrupts = <GIC_SPI 4080 IRQ_TYPE_LEVEL_HIGH>;
761
+
interrupts = <GIC_ESPI 16 IRQ_TYPE_LEVEL_HIGH>;
762
762
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
763
763
clock-names = "fck", "brg_int", "scif_clk";
764
764
status = "disabled";
···
768
768
compatible = "renesas,hscif-r8a78000",
769
769
"renesas,rcar-gen5-hscif", "renesas,hscif";
770
770
reg = <0 0xc071c000 0 0x60>;
771
-
interrupts = <GIC_SPI 4081 IRQ_TYPE_LEVEL_HIGH>;
771
+
interrupts = <GIC_ESPI 17 IRQ_TYPE_LEVEL_HIGH>;
772
772
clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
773
773
clock-names = "fck", "brg_int", "scif_clk";
774
774
status = "disabled";
-30
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
-30
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
···
581
581
status = "disabled";
582
582
};
583
583
584
-
wdt0: watchdog@11c00400 {
585
-
compatible = "renesas,r9a09g057-wdt";
586
-
reg = <0 0x11c00400 0 0x400>;
587
-
clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
588
-
clock-names = "pclk", "oscclk";
589
-
resets = <&cpg 0x75>;
590
-
power-domains = <&cpg>;
591
-
status = "disabled";
592
-
};
593
-
594
584
wdt1: watchdog@14400000 {
595
585
compatible = "renesas,r9a09g057-wdt";
596
586
reg = <0 0x14400000 0 0x400>;
597
587
clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
598
588
clock-names = "pclk", "oscclk";
599
589
resets = <&cpg 0x76>;
600
-
power-domains = <&cpg>;
601
-
status = "disabled";
602
-
};
603
-
604
-
wdt2: watchdog@13000000 {
605
-
compatible = "renesas,r9a09g057-wdt";
606
-
reg = <0 0x13000000 0 0x400>;
607
-
clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
608
-
clock-names = "pclk", "oscclk";
609
-
resets = <&cpg 0x77>;
610
-
power-domains = <&cpg>;
611
-
status = "disabled";
612
-
};
613
-
614
-
wdt3: watchdog@13000400 {
615
-
compatible = "renesas,r9a09g057-wdt";
616
-
reg = <0 0x13000400 0 0x400>;
617
-
clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
618
-
clock-names = "pclk", "oscclk";
619
-
resets = <&cpg 0x78>;
620
590
power-domains = <&cpg>;
621
591
status = "disabled";
622
592
};
+2
-2
arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+2
-2
arch/arm64/boot/dts/renesas/r9a09g077.dtsi
···
974
974
975
975
cpg: clock-controller@80280000 {
976
976
compatible = "renesas,r9a09g077-cpg-mssr";
977
-
reg = <0 0x80280000 0 0x1000>,
978
-
<0 0x81280000 0 0x9000>;
977
+
reg = <0 0x80280000 0 0x10000>,
978
+
<0 0x81280000 0 0x10000>;
979
979
clocks = <&extal_clk>;
980
980
clock-names = "extal";
981
981
#clock-cells = <2>;
+2
-2
arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+2
-2
arch/arm64/boot/dts/renesas/r9a09g087.dtsi
···
977
977
978
978
cpg: clock-controller@80280000 {
979
979
compatible = "renesas,r9a09g087-cpg-mssr";
980
-
reg = <0 0x80280000 0 0x1000>,
981
-
<0 0x81280000 0 0x9000>;
980
+
reg = <0 0x80280000 0 0x10000>,
981
+
<0 0x81280000 0 0x10000>;
982
982
clocks = <&extal_clk>;
983
983
clock-names = "extal";
984
984
#clock-cells = <2>;
+1
-1
arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+1
-1
arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+1
arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+1
arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi