tjh.dev / kernel
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phy: samsung-ufs: move cdr offset to drvdata

Move CDR lock offset to drv data so that it can be extended for other SoCs
which are having CDR lock at different register offset.

Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220610104119.66401-3-alim.akhtar@samsung.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Alim Akhtar and committed by
Vinod Koul e313216b 63f4676d

+9 -2
+3
drivers/phy/samsung/phy-exynos7-ufs.c
··· 11 11 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 12 12 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) 13 13 14 + #define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e 15 + 14 16 /* Calibration for phy initialization */ 15 17 static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = { 16 18 PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY), ··· 76 74 .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN, 77 75 }, 78 76 .has_symbol_clk = 1, 77 + .cdr_lock_status_offset = EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS, 79 78 };
+2
drivers/phy/samsung/phy-exynosautov9-ufs.c
··· 10 10 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728 11 11 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 12 12 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) 13 + #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e 13 14 14 15 #define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \ 15 16 PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50) ··· 65 64 .en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN, 66 65 }, 67 66 .has_symbol_clk = 0, 67 + .cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS, 68 68 };
+3 -1
drivers/phy/samsung/phy-samsung-ufs.c
··· 63 63 } 64 64 65 65 err = readl_poll_timeout( 66 - ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS), 66 + ufs_phy->reg_pma + 67 + PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset), 67 68 val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us); 68 69 if (err) 69 70 dev_err(ufs_phy->dev, ··· 328 327 329 328 drvdata = match->data; 330 329 phy->dev = dev; 330 + phy->drvdata = drvdata; 331 331 phy->cfgs = drvdata->cfgs; 332 332 phy->has_symbol_clk = drvdata->has_symbol_clk; 333 333 memcpy(&phy->isol, &drvdata->isol, sizeof(phy->isol));
+1 -1
drivers/phy/samsung/phy-samsung-ufs.h
··· 40 40 41 41 /* UFS PHY registers */ 42 42 #define PHY_PLL_LOCK_STATUS 0x1e 43 - #define PHY_CDR_LOCK_STATUS 0x5e 44 43 45 44 #define PHY_PLL_LOCK_BIT BIT(5) 46 45 #define PHY_CDR_LOCK_BIT BIT(4) ··· 110 111 const struct samsung_ufs_phy_cfg **cfgs; 111 112 struct samsung_ufs_phy_pmu_isol isol; 112 113 bool has_symbol_clk; 114 + u32 cdr_lock_status_offset; 113 115 }; 114 116 115 117 struct samsung_ufs_phy {