Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDI
To enable pll clock on DDI move part of the pll enabling
sequence into a ddi clock enabling function.
Simililarly, do the same for pll disabling sequence.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-30-mika.kahola@intel.com
+64
-16
+23
-11
drivers/gpu/drm/i915/display/intel_cx0_phy.c
+23
-11
drivers/gpu/drm/i915/display/intel_cx0_phy.c
···
3280
3280
* Frequency Change. We handle this step in bxt_set_cdclk().
3281
3281
*/
3282
3282
3283
-
/* TODO: enable TBT-ALT mode */
3284
3283
intel_cx0_phy_transaction_end(encoder, wakeref);
3285
3284
}
3286
3285
···
3345
3346
}
3346
3347
}
3347
3348
3348
-
void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
3349
-
const struct intel_crtc_state *crtc_state)
3349
+
void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder, int port_clock)
3350
3350
{
3351
3351
struct intel_display *display = to_intel_display(encoder);
3352
3352
enum phy phy = intel_encoder_to_phy(encoder);
···
3359
3361
3360
3362
mask = XELPDP_DDI_CLOCK_SELECT_MASK(display);
3361
3363
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
3362
-
intel_mtl_tbt_clock_select(display, crtc_state->port_clock));
3364
+
intel_mtl_tbt_clock_select(display, port_clock));
3363
3365
3364
3366
mask |= XELPDP_FORWARD_CLOCK_UNGATE;
3365
3367
val |= XELPDP_FORWARD_CLOCK_UNGATE;
···
3397
3399
* clock frequency.
3398
3400
*/
3399
3401
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
3400
-
crtc_state->port_clock);
3402
+
port_clock);
3401
3403
}
3402
3404
3403
3405
void intel_mtl_pll_enable(struct intel_encoder *encoder,
3404
-
const struct intel_crtc_state *crtc_state)
3406
+
struct intel_dpll *pll,
3407
+
const struct intel_dpll_hw_state *dpll_hw_state)
3408
+
{
3409
+
intel_cx0pll_enable(encoder, &dpll_hw_state->cx0pll);
3410
+
}
3411
+
3412
+
void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
3413
+
const struct intel_crtc_state *crtc_state)
3405
3414
{
3406
3415
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3407
3416
3408
3417
if (intel_tc_port_in_tbt_alt_mode(dig_port))
3409
-
intel_mtl_tbt_pll_enable(encoder, crtc_state);
3418
+
intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
3410
3419
else
3411
-
intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll);
3420
+
/* TODO: remove when PLL mgr is in place. */
3421
+
intel_mtl_pll_enable(encoder, NULL, &crtc_state->dpll_hw_state);
3412
3422
}
3413
3423
3414
3424
/*
···
3531
3525
intel_cx0_get_pclk_pll_request(lane);
3532
3526
}
3533
3527
3534
-
void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
3528
+
void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder)
3535
3529
{
3536
3530
struct intel_display *display = to_intel_display(encoder);
3537
3531
enum phy phy = intel_encoder_to_phy(encoder);
···
3571
3565
3572
3566
void intel_mtl_pll_disable(struct intel_encoder *encoder)
3573
3567
{
3568
+
intel_cx0pll_disable(encoder);
3569
+
}
3570
+
3571
+
void intel_mtl_pll_disable_clock(struct intel_encoder *encoder)
3572
+
{
3574
3573
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3575
3574
3576
3575
if (intel_tc_port_in_tbt_alt_mode(dig_port))
3577
-
intel_mtl_tbt_pll_disable(encoder);
3576
+
intel_mtl_tbt_pll_disable_clock(encoder);
3578
3577
else
3579
-
intel_cx0pll_disable(encoder);
3578
+
/* TODO: remove when PLL mgr is in place. */
3579
+
intel_mtl_pll_disable(encoder);
3580
3580
}
3581
3581
3582
3582
enum icl_port_dpll_id
+10
-1
drivers/gpu/drm/i915/display/intel_cx0_phy.h
+10
-1
drivers/gpu/drm/i915/display/intel_cx0_phy.h
···
20
20
struct intel_crtc_state;
21
21
struct intel_cx0pll_state;
22
22
struct intel_display;
23
+
struct intel_dpll;
23
24
struct intel_dpll_hw_state;
24
25
struct intel_encoder;
25
26
struct intel_hdmi;
···
29
28
int lane);
30
29
bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
31
30
void intel_mtl_pll_enable(struct intel_encoder *encoder,
32
-
const struct intel_crtc_state *crtc_state);
31
+
struct intel_dpll *pll,
32
+
const struct intel_dpll_hw_state *dpll_hw_state);
33
33
void intel_mtl_pll_disable(struct intel_encoder *encoder);
34
34
enum icl_port_dpll_id
35
35
intel_mtl_port_pll_type(struct intel_encoder *encoder,
36
36
const struct intel_crtc_state *crtc_state);
37
+
void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
38
+
const struct intel_crtc_state *crtc_state);
39
+
void intel_mtl_pll_disable_clock(struct intel_encoder *encoder);
40
+
void intel_mtl_pll_disable_clock(struct intel_encoder *encoder);
41
+
void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder,
42
+
int port_clock);
43
+
void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder);
37
44
38
45
int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
39
46
struct intel_encoder *encoder,
+4
-2
drivers/gpu/drm/i915/display/intel_ddi.c
+4
-2
drivers/gpu/drm/i915/display/intel_ddi.c
···
89
89
#include "skl_scaler.h"
90
90
#include "skl_universal_plane.h"
91
91
92
+
struct intel_dpll;
93
+
92
94
static const u8 index_to_dp_signal_levels[] = {
93
95
[0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
94
96
[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
···
5254
5252
encoder->port_pll_type = intel_mtl_port_pll_type;
5255
5253
encoder->get_config = xe3plpd_ddi_get_config;
5256
5254
} else if (DISPLAY_VER(display) >= 14) {
5257
-
encoder->enable_clock = intel_mtl_pll_enable;
5258
-
encoder->disable_clock = intel_mtl_pll_disable;
5255
+
encoder->enable_clock = intel_mtl_pll_enable_clock;
5256
+
encoder->disable_clock = intel_mtl_pll_disable_clock;
5259
5257
encoder->port_pll_type = intel_mtl_port_pll_type;
5260
5258
encoder->get_config = mtl_ddi_get_config;
5261
5259
} else if (display->platform.dg2) {
+25
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+25
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
···
4391
4391
return intel_cx0pll_calc_port_clock(encoder, &dpll_hw_state->cx0pll);
4392
4392
}
4393
4393
4394
+
static void mtl_pll_enable(struct intel_display *display,
4395
+
struct intel_dpll *pll,
4396
+
const struct intel_dpll_hw_state *dpll_hw_state)
4397
+
{
4398
+
struct intel_encoder *encoder = get_intel_encoder(display, pll);
4399
+
4400
+
if (drm_WARN_ON(display->drm, !encoder))
4401
+
return;
4402
+
4403
+
intel_mtl_pll_enable(encoder, pll, dpll_hw_state);
4404
+
}
4405
+
4406
+
static void mtl_pll_disable(struct intel_display *display,
4407
+
struct intel_dpll *pll)
4408
+
{
4409
+
struct intel_encoder *encoder = get_intel_encoder(display, pll);
4410
+
4411
+
if (drm_WARN_ON(display->drm, !encoder))
4412
+
return;
4413
+
4414
+
intel_mtl_pll_disable(encoder);
4415
+
}
4416
+
4394
4417
static const struct intel_dpll_funcs mtl_pll_funcs = {
4418
+
.enable = mtl_pll_enable,
4419
+
.disable = mtl_pll_disable,
4395
4420
.get_hw_state = mtl_pll_get_hw_state,
4396
4421
.get_freq = mtl_pll_get_freq,
4397
4422
};
+2
-2
drivers/gpu/drm/i915/display/intel_lt_phy.c
+2
-2
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
2310
2310
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2311
2311
2312
2312
if (intel_tc_port_in_tbt_alt_mode(dig_port))
2313
-
intel_mtl_tbt_pll_enable(encoder, crtc_state);
2313
+
intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
2314
2314
else
2315
2315
intel_lt_phy_pll_enable(encoder, crtc_state);
2316
2316
}
···
2320
2320
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2321
2321
2322
2322
if (intel_tc_port_in_tbt_alt_mode(dig_port))
2323
-
intel_mtl_tbt_pll_disable(encoder);
2323
+
intel_mtl_tbt_pll_disable_clock(encoder);
2324
2324
else
2325
2325
intel_lt_phy_pll_disable(encoder);
2326
2326