Merge tag 'pci-v3.13-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

+1 -1

drivers/pci/ats.c

··· 410 410 * Otherwise is returns a bitmask with supported features. Current 411 411 * features reported are: 412 412 * PCI_PASID_CAP_EXEC - Execute permission supported 413 - * PCI_PASID_CAP_PRIV - Priviledged mode supported 413 + * PCI_PASID_CAP_PRIV - Privileged mode supported 414 414 */ 415 415 int pci_pasid_features(struct pci_dev *pdev) 416 416 {

+6 -6

drivers/pci/host/pci-tegra.c

··· 249 249 void __iomem *afi; 250 250 int irq; 251 251 252 - struct list_head busses; 252 + struct list_head buses; 253 253 struct resource *cs; 254 254 255 255 struct resource io; ··· 399 399 400 400 /* 401 401 * Look up a virtual address mapping for the specified bus number. If no such 402 - * mapping existis, try to create one. 402 + * mapping exists, try to create one. 403 403 */ 404 404 static void __iomem *tegra_pcie_bus_map(struct tegra_pcie *pcie, 405 405 unsigned int busnr) 406 406 { 407 407 struct tegra_pcie_bus *bus; 408 408 409 - list_for_each_entry(bus, &pcie->busses, list) 409 + list_for_each_entry(bus, &pcie->buses, list) 410 410 if (bus->nr == busnr) 411 411 return (void __iomem *)bus->area->addr; 412 412 ··· 414 414 if (IS_ERR(bus)) 415 415 return NULL; 416 416 417 - list_add_tail(&bus->list, &pcie->busses); 417 + list_add_tail(&bus->list, &pcie->buses); 418 418 419 419 return (void __iomem *)bus->area->addr; 420 420 } ··· 808 808 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 809 809 afi_writel(pcie, value, AFI_FUSE); 810 810 811 - /* initialze internal PHY, enable up to 16 PCIE lanes */ 811 + /* initialize internal PHY, enable up to 16 PCIE lanes */ 812 812 pads_writel(pcie, 0x0, PADS_CTL_SEL); 813 813 814 814 /* override IDDQ to 1 on all 4 lanes */ ··· 1624 1624 if (!pcie) 1625 1625 return -ENOMEM; 1626 1626 1627 - INIT_LIST_HEAD(&pcie->busses); 1627 + INIT_LIST_HEAD(&pcie->buses); 1628 1628 INIT_LIST_HEAD(&pcie->ports); 1629 1629 pcie->soc_data = match->data; 1630 1630 pcie->dev = &pdev->dev;

+1 -1

drivers/pci/host/pcie-designware.c

··· 197 197 return -ENOSPC; 198 198 /* 199 199 * Check if this position is at correct offset.nvec is always a 200 - * power of two. pos0 must be nvec bit alligned. 200 + * power of two. pos0 must be nvec bit aligned. 201 201 */ 202 202 if (pos % msgvec) 203 203 pos += msgvec - (pos % msgvec);

+2 -2

drivers/pci/hotplug/Kconfig

··· 133 133 134 134 To compile this driver as a module, choose M here: the 135 135 module will be called rpadlpar_io. 136 - 137 - When in doubt, say N. 136 + 137 + When in doubt, say N. 138 138 139 139 config HOTPLUG_PCI_SGI 140 140 tristate "SGI PCI Hotplug Support"

+1 -1

drivers/pci/hotplug/Makefile

··· 31 31 cpci_hotplug_pci.o 32 32 endif 33 33 ifdef CONFIG_ACPI 34 - pci_hotplug-objs += acpi_pcihp.o 34 + pci_hotplug-objs += acpi_pcihp.o 35 35 endif 36 36 37 37 cpqphp-objs := cpqphp_core.o \

+6 -6

drivers/pci/hotplug/acpiphp_core.c

··· 111 111 * @info: must match the pointer used to register 112 112 * 113 113 * Description: This is used to un-register a hardware specific acpi 114 - * driver that manipulates the attention LED. The pointer to the 114 + * driver that manipulates the attention LED. The pointer to the 115 115 * info struct must be the same as the one used to set it. 116 116 */ 117 117 int acpiphp_unregister_attention(struct acpiphp_attention_info *info) ··· 169 169 * was registered with us. This allows hardware specific 170 170 * ACPI implementations to blink the light for us. 171 171 */ 172 - static int set_attention_status(struct hotplug_slot *hotplug_slot, u8 status) 173 - { 172 + static int set_attention_status(struct hotplug_slot *hotplug_slot, u8 status) 173 + { 174 174 int retval = -ENODEV; 175 175 176 176 pr_debug("%s - physical_slot = %s\n", __func__, ··· 182 182 } else 183 183 attention_info = NULL; 184 184 return retval; 185 - } 186 - 185 + } 186 + 187 187 188 188 /** 189 189 * get_power_status - get power status of a slot ··· 323 323 if (retval) { 324 324 pr_err("pci_hp_register failed with error %d\n", retval); 325 325 goto error_hpslot; 326 - } 326 + } 327 327 328 328 pr_info("Slot [%s] registered\n", slot_name(slot)); 329 329

+1 -1

drivers/pci/hotplug/acpiphp_glue.c

··· 325 325 326 326 list_add_tail(&slot->node, &bridge->slots); 327 327 328 - /* Register slots for ejectable funtions only. */ 328 + /* Register slots for ejectable functions only. */ 329 329 if (acpi_pci_check_ejectable(pbus, handle) || is_dock_device(handle)) { 330 330 unsigned long long sun; 331 331 int retval;

+7 -7

drivers/pci/hotplug/acpiphp_ibm.c

··· 116 116 .read = ibm_read_apci_table, 117 117 .write = NULL, 118 118 }; 119 - static struct acpiphp_attention_info ibm_attention_info = 119 + static struct acpiphp_attention_info ibm_attention_info = 120 120 { 121 121 .set_attn = ibm_set_attention_status, 122 122 .get_attn = ibm_get_attention_status, ··· 171 171 */ 172 172 static int ibm_set_attention_status(struct hotplug_slot *slot, u8 status) 173 173 { 174 - union acpi_object args[2]; 174 + union acpi_object args[2]; 175 175 struct acpi_object_list params = { .pointer = args, .count = 2 }; 176 - acpi_status stat; 176 + acpi_status stat; 177 177 unsigned long long rc; 178 178 union apci_descriptor *ibm_slot; 179 179 ··· 208 208 * 209 209 * Description: This method is registered with the acpiphp module as a 210 210 * callback to do the device specific task of getting the LED status. 211 - * 211 + * 212 212 * Because there is no direct method of getting the LED status directly 213 213 * from an ACPI call, we read the aPCI table and parse out our 214 214 * slot descriptor to read the status from that. ··· 259 259 pr_debug("%s: Received notification %02x\n", __func__, event); 260 260 261 261 if (subevent == 0x80) { 262 - pr_debug("%s: generationg bus event\n", __func__); 262 + pr_debug("%s: generating bus event\n", __func__); 263 263 acpi_bus_generate_netlink_event(note->device->pnp.device_class, 264 264 dev_name(&note->device->dev), 265 265 note->event, detail); ··· 387 387 u32 lvl, void *context, void **rv) 388 388 { 389 389 acpi_handle *phandle = (acpi_handle *)context; 390 - acpi_status status; 390 + acpi_status status; 391 391 struct acpi_device_info *info; 392 392 int retval = 0; 393 393 ··· 405 405 info->hardware_id.string, handle); 406 406 *phandle = handle; 407 407 /* returning non-zero causes the search to stop 408 - * and returns this value to the caller of 408 + * and returns this value to the caller of 409 409 * acpi_walk_namespace, but it also causes some warnings 410 410 * in the acpi debug code to print... 411 411 */

+1 -1

drivers/pci/hotplug/cpci_hotplug_core.c

··· 46 46 do { \ 47 47 if (cpci_debug) \ 48 48 printk (KERN_DEBUG "%s: " format "\n", \ 49 - MY_NAME , ## arg); \ 49 + MY_NAME , ## arg); \ 50 50 } while (0) 51 51 #define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME , ## arg) 52 52 #define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME , ## arg)

+1 -1

drivers/pci/hotplug/cpci_hotplug_pci.c

··· 39 39 do { \ 40 40 if (cpci_debug) \ 41 41 printk (KERN_DEBUG "%s: " format "\n", \ 42 - MY_NAME , ## arg); \ 42 + MY_NAME , ## arg); \ 43 43 } while (0) 44 44 #define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME , ## arg) 45 45 #define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME , ## arg)

+10 -10

drivers/pci/hotplug/cpcihp_generic.c

··· 13 13 * option) any later version. 14 14 * 15 15 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 16 - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 17 - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 18 - * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 16 + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 17 + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 18 + * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 25 * 26 26 * You should have received a copy of the GNU General Public License along ··· 53 53 54 54 #define dbg(format, arg...) \ 55 55 do { \ 56 - if(debug) \ 56 + if (debug) \ 57 57 printk (KERN_DEBUG "%s: " format "\n", \ 58 - MY_NAME , ## arg); \ 58 + MY_NAME , ## arg); \ 59 59 } while(0) 60 60 #define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME , ## arg) 61 61 #define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME , ## arg)

+11 -11

drivers/pci/hotplug/cpcihp_zt5550.c

··· 13 13 * option) any later version. 14 14 * 15 15 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 16 - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 17 - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 18 - * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 16 + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 17 + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 18 + * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 25 * 26 26 * You should have received a copy of the GNU General Public License along ··· 48 48 49 49 #define dbg(format, arg...) \ 50 50 do { \ 51 - if(debug) \ 51 + if (debug) \ 52 52 printk (KERN_DEBUG "%s: " format "\n", \ 53 - MY_NAME , ## arg); \ 53 + MY_NAME , ## arg); \ 54 54 } while(0) 55 55 #define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME , ## arg) 56 56 #define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME , ## arg) ··· 285 285 { 0, } 286 286 }; 287 287 MODULE_DEVICE_TABLE(pci, zt5550_hc_pci_tbl); 288 - 288 + 289 289 static struct pci_driver zt5550_hc_driver = { 290 290 .name = "zt5550_hc", 291 291 .id_table = zt5550_hc_pci_tbl,

+9 -9

drivers/pci/hotplug/cpcihp_zt5550.h

··· 13 13 * option) any later version. 14 14 * 15 15 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 16 - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 17 - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 18 - * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 16 + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 17 + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 18 + * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 25 * 26 26 * You should have received a copy of the GNU General Public License along ··· 55 55 #define HC_CMD_REG 0x0C 56 56 #define ARB_CONFIG_GNT_REG 0x10 57 57 #define ARB_CONFIG_CFG_REG 0x12 58 - #define ARB_CONFIG_REG 0x10 58 + #define ARB_CONFIG_REG 0x10 59 59 #define ISOL_CONFIG_REG 0x18 60 60 #define FAULT_STATUS_REG 0x20 61 61 #define FAULT_CONFIG_REG 0x24

+2 -2

drivers/pci/hotplug/cpqphp_core.c

··· 862 862 goto err_disable_device; 863 863 } 864 864 865 - /* Check for the proper subsystem ID's 865 + /* Check for the proper subsystem IDs 866 866 * Intel uses a different SSID programming model than Compaq. 867 867 * For Intel, each SSID bit identifies a PHP capability. 868 - * Also Intel HPC's may have RID=0. 868 + * Also Intel HPCs may have RID=0. 869 869 */ 870 870 if ((pdev->revision <= 2) && (vendor_id != PCI_VENDOR_ID_INTEL)) { 871 871 err(msg_HPC_not_supported);

+5 -5

drivers/pci/hotplug/cpqphp_ctrl.c

··· 1231 1231 1232 1232 /* Only if mode change...*/ 1233 1233 if (((bus->cur_bus_speed == PCI_SPEED_66MHz) && (adapter_speed == PCI_SPEED_66MHz_PCIX)) || 1234 - ((bus->cur_bus_speed == PCI_SPEED_66MHz_PCIX) && (adapter_speed == PCI_SPEED_66MHz))) 1234 + ((bus->cur_bus_speed == PCI_SPEED_66MHz_PCIX) && (adapter_speed == PCI_SPEED_66MHz))) 1235 1235 set_SOGO(ctrl); 1236 1236 1237 1237 wait_for_ctrl_irq(ctrl); ··· 1828 1828 1829 1829 if (ctrl->event_queue[loop].event_type == INT_BUTTON_PRESS) { 1830 1830 dbg("button pressed\n"); 1831 - } else if (ctrl->event_queue[loop].event_type == 1831 + } else if (ctrl->event_queue[loop].event_type == 1832 1832 INT_BUTTON_CANCEL) { 1833 1833 dbg("button cancel\n"); 1834 1834 del_timer(&p_slot->task_event); ··· 2411 2411 if (rc) 2412 2412 return rc; 2413 2413 2414 - /* find range of busses to use */ 2414 + /* find range of buses to use */ 2415 2415 dbg("find ranges of buses to use\n"); 2416 2416 bus_node = get_max_resource(&(resources->bus_head), 1); 2417 2417 2418 - /* If we don't have any busses to allocate, we can't continue */ 2418 + /* If we don't have any buses to allocate, we can't continue */ 2419 2419 if (!bus_node) 2420 2420 return -ENOMEM; 2421 2421 ··· 2900 2900 2901 2901 /* If this function needs an interrupt and we are behind 2902 2902 * a bridge and the pin is tied to something that's 2903 - * alread mapped, set this one the same */ 2903 + * already mapped, set this one the same */ 2904 2904 if (temp_byte && resources->irqs && 2905 2905 (resources->irqs->valid_INT & 2906 2906 (0x01 << ((temp_byte + resources->irqs->barber_pole - 1) & 0x03)))) {

+2 -3

drivers/pci/hotplug/cpqphp_pci.c

··· 291 291 * 292 292 * Reads configuration for all slots in a PCI bus and saves info. 293 293 * 294 - * Note: For non-hot plug busses, the slot # saved is the device # 294 + * Note: For non-hot plug buses, the slot # saved is the device # 295 295 * 296 296 * returns 0 if success 297 297 */ ··· 455 455 * cpqhp_save_slot_config 456 456 * 457 457 * Saves configuration info for all PCI devices in a given slot 458 - * including subordinate busses. 458 + * including subordinate buses. 459 459 * 460 460 * returns 0 if success 461 461 */ ··· 1556 1556 kfree(tres); 1557 1557 } 1558 1558 } 1559 -

+6 -6

drivers/pci/hotplug/ibmphp.h

··· 59 59 60 60 61 61 /************************************************************ 62 - * RESOURE TYPE * 62 + * RESOURCE TYPE * 63 63 ************************************************************/ 64 64 65 65 #define EBDA_RSRC_TYPE_MASK 0x03 ··· 103 103 //-------------------------------------------------------------- 104 104 105 105 struct rio_table_hdr { 106 - u8 ver_num; 106 + u8 ver_num; 107 107 u8 scal_count; 108 108 u8 riodev_count; 109 109 u16 offset; ··· 127 127 }; 128 128 129 129 //-------------------------------------------------------------- 130 - // RIO DETAIL 130 + // RIO DETAIL 131 131 //-------------------------------------------------------------- 132 132 133 133 struct rio_detail { ··· 152 152 u8 first_slot_num; 153 153 u8 middle_num; 154 154 struct list_head opt_rio_list; 155 - }; 155 + }; 156 156 157 157 struct opt_rio_lo { 158 158 u8 rio_type; ··· 161 161 u8 middle_num; 162 162 u8 pack_count; 163 163 struct list_head opt_rio_lo_list; 164 - }; 164 + }; 165 165 166 166 /**************************************************************** 167 167 * HPC DESCRIPTOR NODE * ··· 574 574 #define HPC_CTLR_IRQ_PENDG 0x80 575 575 576 576 //---------------------------------------------------------------------------- 577 - // HPC_CTLR_WROKING status return codes 577 + // HPC_CTLR_WORKING status return codes 578 578 //---------------------------------------------------------------------------- 579 579 #define HPC_CTLR_WORKING_NO 0x00 580 580 #define HPC_CTLR_WORKING_YES 0x01

+55 -54

drivers/pci/hotplug/ibmphp_core.c

··· 58 58 struct pci_bus *ibmphp_pci_bus; 59 59 static int max_slots; 60 60 61 - static int irqs[16]; /* PIC mode IRQ's we're using so far (in case MPS 61 + static int irqs[16]; /* PIC mode IRQs we're using so far (in case MPS 62 62 * tables don't provide default info for empty slots */ 63 63 64 64 static int init_flag; ··· 71 71 return get_max_adapter_speed_1 (hs, value, 1); 72 72 } 73 73 */ 74 - static inline int get_cur_bus_info(struct slot **sl) 74 + static inline int get_cur_bus_info(struct slot **sl) 75 75 { 76 76 int rc = 1; 77 77 struct slot * slot_cur = *sl; 78 78 79 79 debug("options = %x\n", slot_cur->ctrl->options); 80 - debug("revision = %x\n", slot_cur->ctrl->revision); 80 + debug("revision = %x\n", slot_cur->ctrl->revision); 81 81 82 - if (READ_BUS_STATUS(slot_cur->ctrl)) 82 + if (READ_BUS_STATUS(slot_cur->ctrl)) 83 83 rc = ibmphp_hpc_readslot(slot_cur, READ_BUSSTATUS, NULL); 84 - 85 - if (rc) 84 + 85 + if (rc) 86 86 return rc; 87 - 87 + 88 88 slot_cur->bus_on->current_speed = CURRENT_BUS_SPEED(slot_cur->busstatus); 89 89 if (READ_BUS_MODE(slot_cur->ctrl)) 90 90 slot_cur->bus_on->current_bus_mode = ··· 96 96 slot_cur->busstatus, 97 97 slot_cur->bus_on->current_speed, 98 98 slot_cur->bus_on->current_bus_mode); 99 - 99 + 100 100 *sl = slot_cur; 101 101 return 0; 102 102 } ··· 104 104 static inline int slot_update(struct slot **sl) 105 105 { 106 106 int rc; 107 - rc = ibmphp_hpc_readslot(*sl, READ_ALLSTAT, NULL); 108 - if (rc) 107 + rc = ibmphp_hpc_readslot(*sl, READ_ALLSTAT, NULL); 108 + if (rc) 109 109 return rc; 110 110 if (!init_flag) 111 111 rc = get_cur_bus_info(sl); ··· 172 172 debug("(*cur_slot)->irq[3] = %x\n", 173 173 (*cur_slot)->irq[3]); 174 174 175 - debug("rtable->exlusive_irqs = %x\n", 175 + debug("rtable->exclusive_irqs = %x\n", 176 176 rtable->exclusive_irqs); 177 177 debug("rtable->slots[loop].irq[0].bitmap = %x\n", 178 178 rtable->slots[loop].irq[0].bitmap); ··· 271 271 else 272 272 rc = -ENODEV; 273 273 } 274 - } else 274 + } else 275 275 rc = -ENODEV; 276 276 277 277 ibmphp_unlock_operations(); ··· 288 288 289 289 debug("get_attention_status - Entry hotplug_slot[%lx] pvalue[%lx]\n", 290 290 (ulong) hotplug_slot, (ulong) value); 291 - 291 + 292 292 ibmphp_lock_operations(); 293 293 if (hotplug_slot) { 294 294 pslot = hotplug_slot->private; ··· 406 406 407 407 ibmphp_lock_operations(); 408 408 mode = slot->supported_bus_mode; 409 - speed = slot->supported_speed; 409 + speed = slot->supported_speed; 410 410 ibmphp_unlock_operations(); 411 411 412 412 switch (speed) { 413 413 case BUS_SPEED_33: 414 414 break; 415 415 case BUS_SPEED_66: 416 - if (mode == BUS_MODE_PCIX) 416 + if (mode == BUS_MODE_PCIX) 417 417 speed += 0x01; 418 418 break; 419 419 case BUS_SPEED_100: ··· 515 515 516 516 debug("BEFORE GETTING SLOT STATUS, slot # %x\n", 517 517 slot_cur->number); 518 - if (slot_cur->ctrl->revision == 0xFF) 518 + if (slot_cur->ctrl->revision == 0xFF) 519 519 if (get_ctrl_revision(slot_cur, 520 520 &slot_cur->ctrl->revision)) 521 521 return -1; 522 522 523 - if (slot_cur->bus_on->current_speed == 0xFF) 524 - if (get_cur_bus_info(&slot_cur)) 523 + if (slot_cur->bus_on->current_speed == 0xFF) 524 + if (get_cur_bus_info(&slot_cur)) 525 525 return -1; 526 526 get_max_bus_speed(slot_cur); 527 527 ··· 539 539 debug("SLOT_PRESENT = %x\n", SLOT_PRESENT(slot_cur->status)); 540 540 debug("SLOT_LATCH = %x\n", SLOT_LATCH(slot_cur->status)); 541 541 542 - if ((SLOT_PWRGD(slot_cur->status)) && 543 - !(SLOT_PRESENT(slot_cur->status)) && 542 + if ((SLOT_PWRGD(slot_cur->status)) && 543 + !(SLOT_PRESENT(slot_cur->status)) && 544 544 !(SLOT_LATCH(slot_cur->status))) { 545 545 debug("BEFORE POWER OFF COMMAND\n"); 546 546 rc = power_off(slot_cur); ··· 581 581 582 582 switch (opn) { 583 583 case ENABLE: 584 - if (!(SLOT_PWRGD(slot_cur->status)) && 585 - (SLOT_PRESENT(slot_cur->status)) && 584 + if (!(SLOT_PWRGD(slot_cur->status)) && 585 + (SLOT_PRESENT(slot_cur->status)) && 586 586 !(SLOT_LATCH(slot_cur->status))) 587 587 return 0; 588 588 break; 589 589 case DISABLE: 590 - if ((SLOT_PWRGD(slot_cur->status)) && 590 + if ((SLOT_PWRGD(slot_cur->status)) && 591 591 (SLOT_PRESENT(slot_cur->status)) && 592 592 !(SLOT_LATCH(slot_cur->status))) 593 593 return 0; ··· 617 617 err("out of system memory\n"); 618 618 return -ENOMEM; 619 619 } 620 - 620 + 621 621 info->power_status = SLOT_PWRGD(slot_cur->status); 622 622 info->attention_status = SLOT_ATTN(slot_cur->status, 623 623 slot_cur->ext_status); ··· 638 638 case BUS_SPEED_33: 639 639 break; 640 640 case BUS_SPEED_66: 641 - if (mode == BUS_MODE_PCIX) 641 + if (mode == BUS_MODE_PCIX) 642 642 bus_speed += 0x01; 643 643 else if (mode == BUS_MODE_PCI) 644 644 ; ··· 654 654 } 655 655 656 656 bus->cur_bus_speed = bus_speed; 657 - // To do: bus_names 658 - 657 + // To do: bus_names 658 + 659 659 rc = pci_hp_change_slot_info(slot_cur->hotplug_slot, info); 660 660 kfree(info); 661 661 return rc; ··· 729 729 } 730 730 731 731 /* 732 - * The following function is to fix kernel bug regarding 733 - * getting bus entries, here we manually add those primary 732 + * The following function is to fix kernel bug regarding 733 + * getting bus entries, here we manually add those primary 734 734 * bus entries to kernel bus structure whenever apply 735 735 */ 736 736 static u8 bus_structure_fixup(u8 busno) ··· 814 814 } 815 815 816 816 /******************************************************* 817 - * Returns whether the bus is empty or not 817 + * Returns whether the bus is empty or not 818 818 *******************************************************/ 819 819 static int is_bus_empty(struct slot * slot_cur) 820 820 { ··· 842 842 } 843 843 844 844 /*********************************************************** 845 - * If the HPC permits and the bus currently empty, tries to set the 845 + * If the HPC permits and the bus currently empty, tries to set the 846 846 * bus speed and mode at the maximum card and bus capability 847 847 * Parameters: slot 848 848 * Returns: bus is set (0) or error code ··· 856 856 static struct pci_device_id ciobx[] = { 857 857 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 0x0101) }, 858 858 { }, 859 - }; 859 + }; 860 860 861 861 debug("%s - entry slot # %d\n", __func__, slot_cur->number); 862 862 if (SET_BUS_STATUS(slot_cur->ctrl) && is_bus_empty(slot_cur)) { ··· 877 877 else if (!SLOT_BUS_MODE(slot_cur->ext_status)) 878 878 /* if max slot/bus capability is 66 pci 879 879 and there's no bus mode mismatch, then 880 - the adapter supports 66 pci */ 880 + the adapter supports 66 pci */ 881 881 cmd = HPC_BUS_66CONVMODE; 882 882 else 883 883 cmd = HPC_BUS_33CONVMODE; ··· 930 930 return -EIO; 931 931 } 932 932 } 933 - /* This is for x440, once Brandon fixes the firmware, 933 + /* This is for x440, once Brandon fixes the firmware, 934 934 will not need this delay */ 935 935 msleep(1000); 936 936 debug("%s -Exit\n", __func__); ··· 938 938 } 939 939 940 940 /* This routine checks the bus limitations that the slot is on from the BIOS. 941 - * This is used in deciding whether or not to power up the slot. 941 + * This is used in deciding whether or not to power up the slot. 942 942 * (electrical/spec limitations. For example, >1 133 MHz or >2 66 PCI cards on 943 - * same bus) 943 + * same bus) 944 944 * Parameters: slot 945 945 * Returns: 0 = no limitations, -EINVAL = exceeded limitations on the bus 946 946 */ ··· 986 986 static inline void print_card_capability(struct slot *slot_cur) 987 987 { 988 988 info("capability of the card is "); 989 - if ((slot_cur->ext_status & CARD_INFO) == PCIX133) 989 + if ((slot_cur->ext_status & CARD_INFO) == PCIX133) 990 990 info(" 133 MHz PCI-X\n"); 991 991 else if ((slot_cur->ext_status & CARD_INFO) == PCIX66) 992 992 info(" 66 MHz PCI-X\n"); ··· 1020 1020 } 1021 1021 1022 1022 attn_LED_blink(slot_cur); 1023 - 1023 + 1024 1024 rc = set_bus(slot_cur); 1025 1025 if (rc) { 1026 1026 err("was not able to set the bus\n"); ··· 1082 1082 rc = slot_update(&slot_cur); 1083 1083 if (rc) 1084 1084 goto error_power; 1085 - 1085 + 1086 1086 rc = -EINVAL; 1087 1087 if (SLOT_POWER(slot_cur->status) && !(SLOT_PWRGD(slot_cur->status))) { 1088 1088 err("power fault occurred trying to power up...\n"); ··· 1093 1093 "speed and card capability\n"); 1094 1094 print_card_capability(slot_cur); 1095 1095 goto error_power; 1096 - } 1096 + } 1097 1097 /* Don't think this case will happen after above checks... 1098 1098 * but just in case, for paranoia sake */ 1099 1099 if (!(SLOT_POWER(slot_cur->status))) { ··· 1144 1144 ibmphp_print_test(); 1145 1145 rc = ibmphp_update_slot_info(slot_cur); 1146 1146 exit: 1147 - ibmphp_unlock_operations(); 1147 + ibmphp_unlock_operations(); 1148 1148 return rc; 1149 1149 1150 1150 error_nopower: ··· 1180 1180 { 1181 1181 struct slot *slot = hotplug_slot->private; 1182 1182 int rc; 1183 - 1183 + 1184 1184 ibmphp_lock_operations(); 1185 1185 rc = ibmphp_do_disable_slot(slot); 1186 1186 ibmphp_unlock_operations(); ··· 1192 1192 int rc; 1193 1193 u8 flag; 1194 1194 1195 - debug("DISABLING SLOT...\n"); 1196 - 1195 + debug("DISABLING SLOT...\n"); 1196 + 1197 1197 if ((slot_cur == NULL) || (slot_cur->ctrl == NULL)) { 1198 1198 return -ENODEV; 1199 1199 } 1200 - 1200 + 1201 1201 flag = slot_cur->flag; 1202 1202 slot_cur->flag = 1; 1203 1203 ··· 1210 1210 attn_LED_blink(slot_cur); 1211 1211 1212 1212 if (slot_cur->func == NULL) { 1213 - /* We need this for fncs's that were there on bootup */ 1213 + /* We need this for functions that were there on bootup */ 1214 1214 slot_cur->func = kzalloc(sizeof(struct pci_func), GFP_KERNEL); 1215 1215 if (!slot_cur->func) { 1216 1216 err("out of system memory\n"); ··· 1222 1222 } 1223 1223 1224 1224 ibm_unconfigure_device(slot_cur->func); 1225 - 1226 - /* If we got here from latch suddenly opening on operating card or 1227 - a power fault, there's no power to the card, so cannot 1228 - read from it to determine what resources it occupied. This operation 1229 - is forbidden anyhow. The best we can do is remove it from kernel 1230 - lists at least */ 1225 + 1226 + /* 1227 + * If we got here from latch suddenly opening on operating card or 1228 + * a power fault, there's no power to the card, so cannot 1229 + * read from it to determine what resources it occupied. This operation 1230 + * is forbidden anyhow. The best we can do is remove it from kernel 1231 + * lists at least */ 1231 1232 1232 1233 if (!flag) { 1233 1234 attn_off(slot_cur); ··· 1265 1264 rc = -EFAULT; 1266 1265 goto exit; 1267 1266 } 1268 - if (flag) 1267 + if (flag) 1269 1268 ibmphp_update_slot_info(slot_cur); 1270 1269 goto exit; 1271 1270 } ··· 1340 1339 debug("AFTER Resource & EBDA INITIALIZATIONS\n"); 1341 1340 1342 1341 max_slots = get_max_slots(); 1343 - 1342 + 1344 1343 if ((rc = ibmphp_register_pci())) 1345 1344 goto error; 1346 1345

+51 -52

drivers/pci/hotplug/ibmphp_ebda.c

··· 123 123 static void __init print_bus_info (void) 124 124 { 125 125 struct bus_info *ptr; 126 - 126 + 127 127 list_for_each_entry(ptr, &bus_info_head, bus_info_list) { 128 128 debug ("%s - slot_min = %x\n", __func__, ptr->slot_min); 129 129 debug ("%s - slot_max = %x\n", __func__, ptr->slot_max); ··· 131 131 debug ("%s - bus# = %x\n", __func__, ptr->busno); 132 132 debug ("%s - current_speed = %x\n", __func__, ptr->current_speed); 133 133 debug ("%s - controller_id = %x\n", __func__, ptr->controller_id); 134 - 134 + 135 135 debug ("%s - slots_at_33_conv = %x\n", __func__, ptr->slots_at_33_conv); 136 136 debug ("%s - slots_at_66_conv = %x\n", __func__, ptr->slots_at_66_conv); 137 137 debug ("%s - slots_at_66_pcix = %x\n", __func__, ptr->slots_at_66_pcix); ··· 144 144 static void print_lo_info (void) 145 145 { 146 146 struct rio_detail *ptr; 147 - debug ("print_lo_info ----\n"); 147 + debug ("print_lo_info ----\n"); 148 148 list_for_each_entry(ptr, &rio_lo_head, rio_detail_list) { 149 149 debug ("%s - rio_node_id = %x\n", __func__, ptr->rio_node_id); 150 150 debug ("%s - rio_type = %x\n", __func__, ptr->rio_type); ··· 176 176 struct ebda_pci_rsrc *ptr; 177 177 178 178 list_for_each_entry(ptr, &ibmphp_ebda_pci_rsrc_head, ebda_pci_rsrc_list) { 179 - debug ("%s - rsrc type: %x bus#: %x dev_func: %x start addr: %x end addr: %x\n", 179 + debug ("%s - rsrc type: %x bus#: %x dev_func: %x start addr: %x end addr: %x\n", 180 180 __func__, ptr->rsrc_type ,ptr->bus_num, ptr->dev_fun,ptr->start_addr, ptr->end_addr); 181 181 } 182 182 } ··· 259 259 ebda_seg = readw (io_mem); 260 260 iounmap (io_mem); 261 261 debug ("returned ebda segment: %x\n", ebda_seg); 262 - 262 + 263 263 io_mem = ioremap(ebda_seg<<4, 1); 264 264 if (!io_mem) 265 265 return -ENOMEM; ··· 310 310 re = readw (io_mem + sub_addr); /* next sub blk */ 311 311 312 312 sub_addr += 2; 313 - rc_id = readw (io_mem + sub_addr); /* sub blk id */ 313 + rc_id = readw (io_mem + sub_addr); /* sub blk id */ 314 314 315 315 sub_addr += 2; 316 316 if (rc_id != 0x5243) ··· 330 330 debug ("info about hpc descriptor---\n"); 331 331 debug ("hot blk format: %x\n", format); 332 332 debug ("num of controller: %x\n", num_ctlrs); 333 - debug ("offset of hpc data structure enteries: %x\n ", sub_addr); 333 + debug ("offset of hpc data structure entries: %x\n ", sub_addr); 334 334 335 335 sub_addr = base + re; /* re sub blk */ 336 336 /* FIXME: rc is never used/checked */ ··· 359 359 debug ("info about rsrc descriptor---\n"); 360 360 debug ("format: %x\n", format); 361 361 debug ("num of rsrc: %x\n", num_entries); 362 - debug ("offset of rsrc data structure enteries: %x\n ", sub_addr); 362 + debug ("offset of rsrc data structure entries: %x\n ", sub_addr); 363 363 364 364 hs_complete = 1; 365 365 } else { ··· 376 376 rio_table_ptr->scal_count = readb (io_mem + offset + 1); 377 377 rio_table_ptr->riodev_count = readb (io_mem + offset + 2); 378 378 rio_table_ptr->offset = offset +3 ; 379 - 379 + 380 380 debug("info about rio table hdr ---\n"); 381 381 debug("ver_num: %x\nscal_count: %x\nriodev_count: %x\noffset of rio table: %x\n ", 382 382 rio_table_ptr->ver_num, rio_table_ptr->scal_count, ··· 440 440 rio_detail_ptr->chassis_num = readb (io_mem + offset + 14); 441 441 // debug ("rio_node_id: %x\nbbar: %x\nrio_type: %x\nowner_id: %x\nport0_node: %x\nport0_port: %x\nport1_node: %x\nport1_port: %x\nfirst_slot_num: %x\nstatus: %x\n", rio_detail_ptr->rio_node_id, rio_detail_ptr->bbar, rio_detail_ptr->rio_type, rio_detail_ptr->owner_id, rio_detail_ptr->port0_node_connect, rio_detail_ptr->port0_port_connect, rio_detail_ptr->port1_node_connect, rio_detail_ptr->port1_port_connect, rio_detail_ptr->first_slot_num, rio_detail_ptr->status); 442 442 //create linked list of chassis 443 - if (rio_detail_ptr->rio_type == 4 || rio_detail_ptr->rio_type == 5) 443 + if (rio_detail_ptr->rio_type == 4 || rio_detail_ptr->rio_type == 5) 444 444 list_add (&rio_detail_ptr->rio_detail_list, &rio_vg_head); 445 - //create linked list of expansion box 446 - else if (rio_detail_ptr->rio_type == 6 || rio_detail_ptr->rio_type == 7) 445 + //create linked list of expansion box 446 + else if (rio_detail_ptr->rio_type == 6 || rio_detail_ptr->rio_type == 7) 447 447 list_add (&rio_detail_ptr->rio_detail_list, &rio_lo_head); 448 - else 448 + else 449 449 // not in my concern 450 450 kfree (rio_detail_ptr); 451 451 offset += 15; ··· 456 456 } 457 457 458 458 /* 459 - * reorganizing linked list of chassis 459 + * reorganizing linked list of chassis 460 460 */ 461 461 static struct opt_rio *search_opt_vg (u8 chassis_num) 462 462 { ··· 464 464 list_for_each_entry(ptr, &opt_vg_head, opt_rio_list) { 465 465 if (ptr->chassis_num == chassis_num) 466 466 return ptr; 467 - } 467 + } 468 468 return NULL; 469 469 } 470 470 ··· 472 472 { 473 473 struct opt_rio *opt_rio_ptr = NULL; 474 474 struct rio_detail *rio_detail_ptr = NULL; 475 - 475 + 476 476 list_for_each_entry(rio_detail_ptr, &rio_vg_head, rio_detail_list) { 477 477 opt_rio_ptr = search_opt_vg (rio_detail_ptr->chassis_num); 478 478 if (!opt_rio_ptr) { ··· 484 484 opt_rio_ptr->first_slot_num = rio_detail_ptr->first_slot_num; 485 485 opt_rio_ptr->middle_num = rio_detail_ptr->first_slot_num; 486 486 list_add (&opt_rio_ptr->opt_rio_list, &opt_vg_head); 487 - } else { 487 + } else { 488 488 opt_rio_ptr->first_slot_num = min (opt_rio_ptr->first_slot_num, rio_detail_ptr->first_slot_num); 489 489 opt_rio_ptr->middle_num = max (opt_rio_ptr->middle_num, rio_detail_ptr->first_slot_num); 490 - } 490 + } 491 491 } 492 492 print_opt_vg (); 493 - return 0; 494 - } 493 + return 0; 494 + } 495 495 496 496 /* 497 497 * reorganizing linked list of expansion box ··· 502 502 list_for_each_entry(ptr, &opt_lo_head, opt_rio_lo_list) { 503 503 if (ptr->chassis_num == chassis_num) 504 504 return ptr; 505 - } 505 + } 506 506 return NULL; 507 507 } 508 508 ··· 510 510 { 511 511 struct opt_rio_lo *opt_rio_lo_ptr = NULL; 512 512 struct rio_detail *rio_detail_ptr = NULL; 513 - 513 + 514 514 list_for_each_entry(rio_detail_ptr, &rio_lo_head, rio_detail_list) { 515 515 opt_rio_lo_ptr = search_opt_lo (rio_detail_ptr->chassis_num); 516 516 if (!opt_rio_lo_ptr) { ··· 522 522 opt_rio_lo_ptr->first_slot_num = rio_detail_ptr->first_slot_num; 523 523 opt_rio_lo_ptr->middle_num = rio_detail_ptr->first_slot_num; 524 524 opt_rio_lo_ptr->pack_count = 1; 525 - 525 + 526 526 list_add (&opt_rio_lo_ptr->opt_rio_lo_list, &opt_lo_head); 527 - } else { 527 + } else { 528 528 opt_rio_lo_ptr->first_slot_num = min (opt_rio_lo_ptr->first_slot_num, rio_detail_ptr->first_slot_num); 529 529 opt_rio_lo_ptr->middle_num = max (opt_rio_lo_ptr->middle_num, rio_detail_ptr->first_slot_num); 530 530 opt_rio_lo_ptr->pack_count = 2; 531 - } 531 + } 532 532 } 533 - return 0; 533 + return 0; 534 534 } 535 - 535 + 536 536 537 537 /* Since we don't know the max slot number per each chassis, hence go 538 538 * through the list of all chassis to find out the range 539 - * Arguments: slot_num, 1st slot number of the chassis we think we are on, 540 - * var (0 = chassis, 1 = expansion box) 539 + * Arguments: slot_num, 1st slot number of the chassis we think we are on, 540 + * var (0 = chassis, 1 = expansion box) 541 541 */ 542 542 static int first_slot_num (u8 slot_num, u8 first_slot, u8 var) 543 543 { ··· 547 547 548 548 if (!var) { 549 549 list_for_each_entry(opt_vg_ptr, &opt_vg_head, opt_rio_list) { 550 - if ((first_slot < opt_vg_ptr->first_slot_num) && (slot_num >= opt_vg_ptr->first_slot_num)) { 550 + if ((first_slot < opt_vg_ptr->first_slot_num) && (slot_num >= opt_vg_ptr->first_slot_num)) { 551 551 rc = -ENODEV; 552 552 break; 553 553 } ··· 569 569 570 570 list_for_each_entry(opt_lo_ptr, &opt_lo_head, opt_rio_lo_list) { 571 571 //check to see if this slot_num belongs to expansion box 572 - if ((slot_num >= opt_lo_ptr->first_slot_num) && (!first_slot_num (slot_num, opt_lo_ptr->first_slot_num, 1))) 572 + if ((slot_num >= opt_lo_ptr->first_slot_num) && (!first_slot_num (slot_num, opt_lo_ptr->first_slot_num, 1))) 573 573 return opt_lo_ptr; 574 574 } 575 575 return NULL; ··· 580 580 struct opt_rio *opt_vg_ptr; 581 581 582 582 list_for_each_entry(opt_vg_ptr, &opt_vg_head, opt_rio_list) { 583 - //check to see if this slot_num belongs to chassis 584 - if ((slot_num >= opt_vg_ptr->first_slot_num) && (!first_slot_num (slot_num, opt_vg_ptr->first_slot_num, 0))) 583 + //check to see if this slot_num belongs to chassis 584 + if ((slot_num >= opt_vg_ptr->first_slot_num) && (!first_slot_num (slot_num, opt_vg_ptr->first_slot_num, 0))) 585 585 return opt_vg_ptr; 586 586 } 587 587 return NULL; ··· 594 594 { 595 595 u8 first_slot = 1; 596 596 struct slot * slot_cur; 597 - 597 + 598 598 list_for_each_entry(slot_cur, &ibmphp_slot_head, ibm_slot_list) { 599 599 if (slot_cur->ctrl) { 600 - if ((slot_cur->ctrl->ctlr_type != 4) && (slot_cur->ctrl->ending_slot_num > first_slot) && (slot_num > slot_cur->ctrl->ending_slot_num)) 600 + if ((slot_cur->ctrl->ctlr_type != 4) && (slot_cur->ctrl->ending_slot_num > first_slot) && (slot_num > slot_cur->ctrl->ending_slot_num)) 601 601 first_slot = slot_cur->ctrl->ending_slot_num; 602 602 } 603 - } 603 + } 604 604 return first_slot + 1; 605 605 606 606 } ··· 622 622 err ("Structure passed is empty\n"); 623 623 return NULL; 624 624 } 625 - 625 + 626 626 slot_num = slot_cur->number; 627 627 628 628 memset (str, 0, sizeof(str)); 629 - 629 + 630 630 if (rio_table_ptr) { 631 631 if (rio_table_ptr->ver_num == 3) { 632 632 opt_vg_ptr = find_chassis_num (slot_num); ··· 660 660 /* if both NULL and we DO have correct RIO table in BIOS */ 661 661 return NULL; 662 662 } 663 - } 663 + } 664 664 if (!flag) { 665 665 if (slot_cur->ctrl->ctlr_type == 4) { 666 666 first_slot = calculate_first_slot (slot_num); ··· 798 798 slot_ptr->ctl_index = readb (io_mem + addr_slot + 2*slot_num); 799 799 slot_ptr->slot_cap = readb (io_mem + addr_slot + 3*slot_num); 800 800 801 - // create bus_info lined list --- if only one slot per bus: slot_min = slot_max 801 + // create bus_info lined list --- if only one slot per bus: slot_min = slot_max 802 802 803 803 bus_info_ptr2 = ibmphp_find_same_bus_num (slot_ptr->slot_bus_num); 804 804 if (!bus_info_ptr2) { ··· 814 814 bus_info_ptr1->index = bus_index++; 815 815 bus_info_ptr1->current_speed = 0xff; 816 816 bus_info_ptr1->current_bus_mode = 0xff; 817 - 817 + 818 818 bus_info_ptr1->controller_id = hpc_ptr->ctlr_id; 819 - 819 + 820 820 list_add_tail (&bus_info_ptr1->bus_info_list, &bus_info_head); 821 821 822 822 } else { ··· 851 851 bus_info_ptr2->slots_at_66_conv = bus_ptr->slots_at_66_conv; 852 852 bus_info_ptr2->slots_at_66_pcix = bus_ptr->slots_at_66_pcix; 853 853 bus_info_ptr2->slots_at_100_pcix = bus_ptr->slots_at_100_pcix; 854 - bus_info_ptr2->slots_at_133_pcix = bus_ptr->slots_at_133_pcix; 854 + bus_info_ptr2->slots_at_133_pcix = bus_ptr->slots_at_133_pcix; 855 855 } 856 856 bus_ptr++; 857 857 } ··· 864 864 hpc_ptr->u.pci_ctlr.dev_fun = readb (io_mem + addr + 1); 865 865 hpc_ptr->irq = readb (io_mem + addr + 2); 866 866 addr += 3; 867 - debug ("ctrl bus = %x, ctlr devfun = %x, irq = %x\n", 867 + debug ("ctrl bus = %x, ctlr devfun = %x, irq = %x\n", 868 868 hpc_ptr->u.pci_ctlr.bus, 869 869 hpc_ptr->u.pci_ctlr.dev_fun, hpc_ptr->irq); 870 870 break; ··· 932 932 tmp_slot->supported_speed = 2; 933 933 else if ((hpc_ptr->slots[index].slot_cap & EBDA_SLOT_66_MAX) == EBDA_SLOT_66_MAX) 934 934 tmp_slot->supported_speed = 1; 935 - 935 + 936 936 if ((hpc_ptr->slots[index].slot_cap & EBDA_SLOT_PCIX_CAP) == EBDA_SLOT_PCIX_CAP) 937 937 tmp_slot->supported_bus_mode = 1; 938 938 else ··· 1000 1000 return rc; 1001 1001 } 1002 1002 1003 - /* 1003 + /* 1004 1004 * map info (bus, devfun, start addr, end addr..) of i/o, memory, 1005 1005 * pfm from the physical addr to a list of resource. 1006 1006 */ ··· 1057 1057 addr += 10; 1058 1058 1059 1059 debug ("rsrc from mem or pfm ---\n"); 1060 - debug ("rsrc type: %x bus#: %x dev_func: %x start addr: %x end addr: %x\n", 1060 + debug ("rsrc type: %x bus#: %x dev_func: %x start addr: %x end addr: %x\n", 1061 1061 rsrc_ptr->rsrc_type, rsrc_ptr->bus_num, rsrc_ptr->dev_fun, rsrc_ptr->start_addr, rsrc_ptr->end_addr); 1062 1062 1063 1063 list_add (&rsrc_ptr->ebda_pci_rsrc_list, &ibmphp_ebda_pci_rsrc_head); ··· 1096 1096 struct bus_info *ptr; 1097 1097 1098 1098 list_for_each_entry(ptr, &bus_info_head, bus_info_list) { 1099 - if (ptr->busno == num) 1099 + if (ptr->busno == num) 1100 1100 return ptr; 1101 1101 } 1102 1102 return NULL; ··· 1110 1110 struct bus_info *ptr; 1111 1111 1112 1112 list_for_each_entry(ptr, &bus_info_head, bus_info_list) { 1113 - if (ptr->busno == num) 1113 + if (ptr->busno == num) 1114 1114 return ptr->index; 1115 1115 } 1116 1116 return -ENODEV; ··· 1168 1168 .subdevice = HPC_SUBSYSTEM_ID, 1169 1169 .class = ((PCI_CLASS_SYSTEM_PCI_HOTPLUG << 8) | 0x00), 1170 1170 }, {} 1171 - }; 1171 + }; 1172 1172 1173 1173 MODULE_DEVICE_TABLE(pci, id_table); 1174 1174 ··· 1197 1197 struct controller *ctrl; 1198 1198 1199 1199 debug ("inside ibmphp_probe\n"); 1200 - 1200 + 1201 1201 list_for_each_entry(ctrl, &ebda_hpc_head, ebda_hpc_list) { 1202 1202 if (ctrl->ctlr_type == 1) { 1203 1203 if ((dev->devfn == ctrl->u.pci_ctlr.dev_fun) && (dev->bus->number == ctrl->u.pci_ctlr.bus)) { ··· 1210 1210 } 1211 1211 return -ENODEV; 1212 1212 } 1213 -

+12 -12

drivers/pci/hotplug/ibmphp_hpc.c

··· 258 258 { 259 259 u8 rc; 260 260 void __iomem *wpg_addr; // base addr + offset 261 - unsigned long wpg_data; // data to/from WPG LOHI format 261 + unsigned long wpg_data; // data to/from WPG LOHI format 262 262 unsigned long ultemp; 263 263 unsigned long data; // actual data HILO format 264 264 int i; ··· 351 351 } 352 352 353 353 //------------------------------------------------------------ 354 - // Read from ISA type HPC 354 + // Read from ISA type HPC 355 355 //------------------------------------------------------------ 356 356 static u8 isa_ctrl_read (struct controller *ctlr_ptr, u8 offset) 357 357 { ··· 372 372 { 373 373 u16 start_address; 374 374 u16 port_address; 375 - 375 + 376 376 start_address = ctlr_ptr->u.isa_ctlr.io_start; 377 377 port_address = start_address + (u16) offset; 378 378 outb (data, port_address); ··· 656 656 //-------------------------------------------------------------------- 657 657 // cleanup 658 658 //-------------------------------------------------------------------- 659 - 659 + 660 660 // remove physical to logical address mapping 661 661 if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) 662 662 iounmap (wpg_bbar); 663 - 663 + 664 664 free_hpc_access (); 665 665 666 666 debug_polling ("%s - Exit rc[%d]\n", __func__, rc); ··· 835 835 down (&semOperations); 836 836 837 837 switch (poll_state) { 838 - case POLL_LATCH_REGISTER: 838 + case POLL_LATCH_REGISTER: 839 839 oldlatchlow = curlatchlow; 840 840 ctrl_count = 0x00; 841 841 list_for_each (pslotlist, &ibmphp_slot_head) { ··· 892 892 893 893 if (kthread_should_stop()) 894 894 goto out_sleep; 895 - 895 + 896 896 down (&semOperations); 897 - 897 + 898 898 if (poll_count >= POLL_LATCH_CNT) { 899 899 poll_count = 0; 900 900 poll_state = POLL_SLOTS; 901 901 } else 902 902 poll_state = POLL_LATCH_REGISTER; 903 903 break; 904 - } 904 + } 905 905 /* give up the hardware semaphore */ 906 906 up (&semOperations); 907 907 /* sleep for a short time just for good measure */ ··· 958 958 // bit 5 - HPC_SLOT_PWRGD 959 959 if ((pslot->status & 0x20) != (poldslot->status & 0x20)) 960 960 // OFF -> ON: ignore, ON -> OFF: disable slot 961 - if ((poldslot->status & 0x20) && (SLOT_CONNECT (poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT (poldslot->status))) 961 + if ((poldslot->status & 0x20) && (SLOT_CONNECT (poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT (poldslot->status))) 962 962 disable = 1; 963 963 964 964 // bit 6 - HPC_SLOT_BUS_SPEED ··· 980 980 pslot->status &= ~HPC_SLOT_POWER; 981 981 } 982 982 } 983 - // CLOSE -> OPEN 983 + // CLOSE -> OPEN 984 984 else if ((SLOT_PWRGD (poldslot->status) == HPC_SLOT_PWRGD_GOOD) 985 985 && (SLOT_CONNECT (poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT (poldslot->status))) { 986 986 disable = 1; ··· 1075 1075 debug ("before locking operations \n"); 1076 1076 ibmphp_lock_operations (); 1077 1077 debug ("after locking operations \n"); 1078 - 1078 + 1079 1079 // wait for poll thread to exit 1080 1080 debug ("before sem_exit down \n"); 1081 1081 down (&sem_exit);

+35 -36

drivers/pci/hotplug/ibmphp_pci.c

··· 1 1 /* 2 2 * IBM Hot Plug Controller Driver 3 - * 3 + * 4 4 * Written By: Irene Zubarev, IBM Corporation 5 - * 5 + * 6 6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 7 7 * Copyright (C) 2001,2002 IBM Corp. 8 8 * ··· 42 42 43 43 /* 44 44 * NOTE..... If BIOS doesn't provide default routing, we assign: 45 - * 9 for SCSI, 10 for LAN adapters, and 11 for everything else. 45 + * 9 for SCSI, 10 for LAN adapters, and 11 for everything else. 46 46 * If adapter is bridged, then we assign 11 to it and devices behind it. 47 47 * We also assign the same irq numbers for multi function devices. 48 48 * These are PIC mode, so shouldn't matter n.e.ways (hopefully) ··· 71 71 * Configures the device to be added (will allocate needed resources if it 72 72 * can), the device can be a bridge or a regular pci device, can also be 73 73 * multi-functional 74 - * 74 + * 75 75 * Input: function to be added 76 - * 76 + * 77 77 * TO DO: The error case with Multifunction device or multi function bridge, 78 - * if there is an error, will need to go through all previous functions and 78 + * if there is an error, will need to go through all previous functions and 79 79 * unconfigure....or can add some code into unconfigure_card.... 80 80 */ 81 81 int ibmphp_configure_card (struct pci_func *func, u8 slotno) ··· 98 98 cur_func = func; 99 99 100 100 /* We only get bus and device from IRQ routing table. So at this point, 101 - * func->busno is correct, and func->device contains only device (at the 5 101 + * func->busno is correct, and func->device contains only device (at the 5 102 102 * highest bits) 103 103 */ 104 104 ··· 151 151 cur_func->device, cur_func->busno); 152 152 cleanup_count = 6; 153 153 goto error; 154 - } 154 + } 155 155 cur_func->next = NULL; 156 156 function = 0x8; 157 157 break; ··· 339 339 } 340 340 341 341 /* 342 - * This function configures the pci BARs of a single device. 342 + * This function configures the pci BARs of a single device. 343 343 * Input: pointer to the pci_func 344 344 * Output: configured PCI, 0, or error 345 345 */ ··· 371 371 372 372 for (count = 0; address[count]; count++) { /* for 6 BARs */ 373 373 374 - /* not sure if i need this. per scott, said maybe need smth like this 374 + /* not sure if i need this. per scott, said maybe need * something like this 375 375 if devices don't adhere 100% to the spec, so don't want to write 376 376 to the reserved bits 377 377 378 - pcibios_read_config_byte(cur_func->busno, cur_func->device, 378 + pcibios_read_config_byte(cur_func->busno, cur_func->device, 379 379 PCI_BASE_ADDRESS_0 + 4 * count, &tmp); 380 380 if (tmp & 0x01) // IO 381 - pcibios_write_config_dword(cur_func->busno, cur_func->device, 381 + pcibios_write_config_dword(cur_func->busno, cur_func->device, 382 382 PCI_BASE_ADDRESS_0 + 4 * count, 0xFFFFFFFD); 383 383 else // Memory 384 - pcibios_write_config_dword(cur_func->busno, cur_func->device, 384 + pcibios_write_config_dword(cur_func->busno, cur_func->device, 385 385 PCI_BASE_ADDRESS_0 + 4 * count, 0xFFFFFFFF); 386 386 */ 387 387 pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], 0xFFFFFFFF); ··· 421 421 return -EIO; 422 422 } 423 423 pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], func->io[count]->start); 424 - 425 - /* _______________This is for debugging purposes only_____________________ */ 424 + 425 + /* _______________This is for debugging purposes only_____________________ */ 426 426 debug ("b4 writing, the IO address is %x\n", func->io[count]->start); 427 427 pci_bus_read_config_dword (ibmphp_pci_bus, devfn, address[count], &bar[count]); 428 428 debug ("after writing.... the start address is %x\n", bar[count]); ··· 484 484 485 485 pci_bus_write_config_dword (ibmphp_pci_bus, devfn, address[count], func->pfmem[count]->start); 486 486 487 - /*_______________This is for debugging purposes only______________________________*/ 487 + /*_______________This is for debugging purposes only______________________________*/ 488 488 debug ("b4 writing, start address is %x\n", func->pfmem[count]->start); 489 489 pci_bus_read_config_dword (ibmphp_pci_bus, devfn, address[count], &bar[count]); 490 490 debug ("after writing, start address is %x\n", bar[count]); ··· 559 559 /****************************************************************************** 560 560 * This routine configures a PCI-2-PCI bridge and the functions behind it 561 561 * Parameters: pci_func 562 - * Returns: 562 + * Returns: 563 563 ******************************************************************************/ 564 564 static int configure_bridge (struct pci_func **func_passed, u8 slotno) 565 565 { ··· 622 622 debug ("AFTER FIND_SEC_NUMBER, func->busno IS %x\n", func->busno); 623 623 624 624 pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, sec_number); 625 - 625 + 626 626 /* __________________For debugging purposes only __________________________________ 627 627 pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, &sec_number); 628 628 debug ("sec_number after write/read is %x\n", sec_number); ··· 644 644 645 645 646 646 /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 647 - !!!!!!!!!!!!!!!NEED TO ADD!!! FAST BACK-TO-BACK ENABLE!!!!!!!!!!!!!!!!!!!! 647 + !!!!!!!!!!!!!!!NEED TO ADD!!! FAST BACK-TO-BACK ENABLE!!!!!!!!!!!!!!!!!!!! 648 648 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ 649 649 650 650 ··· 670 670 debug ("len[count] in IO = %x\n", len[count]); 671 671 672 672 bus_io[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL); 673 - 673 + 674 674 if (!bus_io[count]) { 675 675 err ("out of system memory\n"); 676 676 retval = -ENOMEM; ··· 735 735 ibmphp_add_pfmem_from_mem (bus_pfmem[count]); 736 736 func->pfmem[count] = bus_pfmem[count]; 737 737 } else { 738 - err ("cannot allocate requested pfmem for bus %x, device %x, len %x\n", 738 + err ("cannot allocate requested pfmem for bus %x, device %x, len %x\n", 739 739 func->busno, func->device, len[count]); 740 740 kfree (mem_tmp); 741 741 kfree (bus_pfmem[count]); ··· 805 805 debug ("amount_needed->mem = %x\n", amount_needed->mem); 806 806 debug ("amount_needed->pfmem = %x\n", amount_needed->pfmem); 807 807 808 - if (amount_needed->not_correct) { 808 + if (amount_needed->not_correct) { 809 809 debug ("amount_needed is not correct\n"); 810 810 for (count = 0; address[count]; count++) { 811 811 /* for 2 BARs */ ··· 830 830 } else { 831 831 debug ("it wants %x IO behind the bridge\n", amount_needed->io); 832 832 io = kzalloc(sizeof(*io), GFP_KERNEL); 833 - 833 + 834 834 if (!io) { 835 835 err ("out of system memory\n"); 836 836 retval = -ENOMEM; ··· 959 959 960 960 if (bus->noIORanges) { 961 961 pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_IO_BASE, 0x00 | bus->rangeIO->start >> 8); 962 - pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_IO_LIMIT, 0x00 | bus->rangeIO->end >> 8); 962 + pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_IO_LIMIT, 0x00 | bus->rangeIO->end >> 8); 963 963 964 964 /* _______________This is for debugging purposes only ____________________ 965 965 pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_IO_BASE, &temp); ··· 980 980 if (bus->noMemRanges) { 981 981 pci_bus_write_config_word (ibmphp_pci_bus, devfn, PCI_MEMORY_BASE, 0x0000 | bus->rangeMem->start >> 16); 982 982 pci_bus_write_config_word (ibmphp_pci_bus, devfn, PCI_MEMORY_LIMIT, 0x0000 | bus->rangeMem->end >> 16); 983 - 983 + 984 984 /* ____________________This is for debugging purposes only ________________________ 985 985 pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_MEMORY_BASE, &temp); 986 986 debug ("mem_base = %x\n", (temp & PCI_MEMORY_RANGE_TYPE_MASK) << 16); ··· 1017 1017 pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_INTERRUPT_PIN, &irq); 1018 1018 if ((irq > 0x00) && (irq < 0x05)) 1019 1019 pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_INTERRUPT_LINE, func->irq[irq - 1]); 1020 - /* 1020 + /* 1021 1021 pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_BRIDGE_CONTROL, ctrl); 1022 1022 pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_PARITY); 1023 1023 pci_bus_write_config_byte (ibmphp_pci_bus, devfn, PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_SERR); ··· 1071 1071 * This function adds up the amount of resources needed behind the PPB bridge 1072 1072 * and passes it to the configure_bridge function 1073 1073 * Input: bridge function 1074 - * Ouput: amount of resources needed 1074 + * Output: amount of resources needed 1075 1075 *****************************************************************************/ 1076 1076 static struct res_needed *scan_behind_bridge (struct pci_func * func, u8 busno) 1077 1077 { ··· 1204 1204 return amount; 1205 1205 } 1206 1206 1207 - /* The following 3 unconfigure_boot_ routines deal with the case when we had the card 1208 - * upon bootup in the system, since we don't allocate func to such case, we need to read 1209 - * the start addresses from pci config space and then find the corresponding entries in 1207 + /* The following 3 unconfigure_boot_ routines deal with the case when we had the card 1208 + * upon bootup in the system, since we don't allocate func to such case, we need to read 1209 + * the start addresses from pci config space and then find the corresponding entries in 1210 1210 * our resource lists. The functions return either 0, -ENODEV, or -1 (general failure) 1211 1211 * Change: we also call these functions even if we configured the card ourselves (i.e., not 1212 1212 * the bootup case), since it should work same way ··· 1561 1561 * unconfiguring the device 1562 1562 * TO DO: will probably need to add some code in case there was some resource, 1563 1563 * to remove it... this is from when we have errors in the configure_card... 1564 - * !!!!!!!!!!!!!!!!!!!!!!!!!FOR BUSES!!!!!!!!!!!! 1565 - * Returns: 0, -1, -ENODEV 1564 + * !!!!!!!!!!!!!!!!!!!!!!!!!FOR BUSES!!!!!!!!!!!! 1565 + * Returns: 0, -1, -ENODEV 1566 1566 */ 1567 1567 int ibmphp_unconfigure_card (struct slot **slot_cur, int the_end) 1568 1568 { ··· 1634 1634 * Input: bus and the amount of resources needed (we know we can assign those, 1635 1635 * since they've been checked already 1636 1636 * Output: bus added to the correct spot 1637 - * 0, -1, error 1637 + * 0, -1, error 1638 1638 */ 1639 1639 static int add_new_bus (struct bus_node *bus, struct resource_node *io, struct resource_node *mem, struct resource_node *pfmem, u8 parent_busno) 1640 1640 { ··· 1650 1650 err ("strange, cannot find bus which is supposed to be at the system... something is terribly wrong...\n"); 1651 1651 return -ENODEV; 1652 1652 } 1653 - 1653 + 1654 1654 list_add (&bus->bus_list, &cur_bus->bus_list); 1655 1655 } 1656 1656 if (io) { ··· 1679 1679 } 1680 1680 if (pfmem) { 1681 1681 pfmem_range = kzalloc(sizeof(*pfmem_range), GFP_KERNEL); 1682 - if (!pfmem_range) { 1682 + if (!pfmem_range) { 1683 1683 err ("out of system memory\n"); 1684 1684 return -ENOMEM; 1685 1685 } ··· 1726 1726 return busno; 1727 1727 return 0xff; 1728 1728 } 1729 -

+38 -38

drivers/pci/hotplug/ibmphp_res.c

··· 72 72 static struct resource_node * __init alloc_resources (struct ebda_pci_rsrc * curr) 73 73 { 74 74 struct resource_node *rs; 75 - 75 + 76 76 if (!curr) { 77 77 err ("NULL passed to allocate\n"); 78 78 return NULL; ··· 128 128 } 129 129 newrange->start = curr->start_addr; 130 130 newrange->end = curr->end_addr; 131 - 131 + 132 132 if (first_bus || (!num_ranges)) 133 133 newrange->rangeno = 1; 134 134 else { ··· 162 162 newbus->rangePFMem = newrange; 163 163 if (first_bus) 164 164 newbus->noPFMemRanges = 1; 165 - else { 165 + else { 166 166 debug ("1st PFMemory Primary on Bus %x [%x - %x]\n", newbus->busno, newrange->start, newrange->end); 167 167 ++newbus->noPFMemRanges; 168 168 fix_resources (newbus); ··· 190 190 * This is the Resource Management initialization function. It will go through 191 191 * the Resource list taken from EBDA and fill in this module's data structures 192 192 * 193 - * THIS IS NOT TAKING INTO CONSIDERATION IO RESTRICTIONS OF PRIMARY BUSES, 193 + * THIS IS NOT TAKING INTO CONSIDERATION IO RESTRICTIONS OF PRIMARY BUSES, 194 194 * SINCE WE'RE GOING TO ASSUME FOR NOW WE DON'T HAVE THOSE ON OUR BUSES FOR NOW 195 195 * 196 196 * Input: ptr to the head of the resource list from EBDA ··· 382 382 * pci devices' resources for the appropriate resource 383 383 * 384 384 * Input: type of the resource, range to add, current bus 385 - * Output: 0 or -1, bus and range ptrs 385 + * Output: 0 or -1, bus and range ptrs 386 386 ********************************************************************************/ 387 387 static int add_bus_range (int type, struct range_node *range, struct bus_node *bus_cur) 388 388 { ··· 466 466 467 467 switch (type) { 468 468 case MEM: 469 - if (bus_cur->firstMem) 469 + if (bus_cur->firstMem) 470 470 res = bus_cur->firstMem; 471 471 break; 472 472 case PFMEM: ··· 583 583 } 584 584 585 585 /******************************************************************************* 586 - * This routine adds a resource to the list of resources to the appropriate bus 586 + * This routine adds a resource to the list of resources to the appropriate bus 587 587 * based on their resource type and sorted by their starting addresses. It assigns 588 588 * the ptrs to next and nextRange if needed. 589 589 * ··· 605 605 err ("NULL passed to add\n"); 606 606 return -ENODEV; 607 607 } 608 - 608 + 609 609 bus_cur = find_bus_wprev (res->busno, NULL, 0); 610 - 610 + 611 611 if (!bus_cur) { 612 - /* didn't find a bus, smth's wrong!!! */ 612 + /* didn't find a bus, something's wrong!!! */ 613 613 debug ("no bus in the system, either pci_dev's wrong or allocation failed\n"); 614 614 return -ENODEV; 615 615 } ··· 648 648 if (!range_cur) { 649 649 switch (res->type) { 650 650 case IO: 651 - ++bus_cur->needIOUpdate; 651 + ++bus_cur->needIOUpdate; 652 652 break; 653 653 case MEM: 654 654 ++bus_cur->needMemUpdate; ··· 659 659 } 660 660 res->rangeno = -1; 661 661 } 662 - 662 + 663 663 debug ("The range is %d\n", res->rangeno); 664 664 if (!res_start) { 665 665 /* no first{IO,Mem,Pfmem} on the bus, 1st IO/Mem/Pfmem resource ever */ 666 666 switch (res->type) { 667 667 case IO: 668 - bus_cur->firstIO = res; 668 + bus_cur->firstIO = res; 669 669 break; 670 670 case MEM: 671 671 bus_cur->firstMem = res; ··· 673 673 case PFMEM: 674 674 bus_cur->firstPFMem = res; 675 675 break; 676 - } 676 + } 677 677 res->next = NULL; 678 678 res->nextRange = NULL; 679 679 } else { ··· 770 770 * This routine will remove the resource from the list of resources 771 771 * 772 772 * Input: io, mem, and/or pfmem resource to be deleted 773 - * Ouput: modified resource list 773 + * Output: modified resource list 774 774 * 0 or error code 775 775 ****************************************************************************/ 776 776 int ibmphp_remove_resource (struct resource_node *res) ··· 825 825 826 826 if (!res_cur) { 827 827 if (res->type == PFMEM) { 828 - /* 828 + /* 829 829 * case where pfmem might be in the PFMemFromMem list 830 830 * so will also need to remove the corresponding mem 831 831 * entry ··· 961 961 } 962 962 963 963 /***************************************************************************** 964 - * This routine will check to make sure the io/mem/pfmem->len that the device asked for 964 + * This routine will check to make sure the io/mem/pfmem->len that the device asked for 965 965 * can fit w/i our list of available IO/MEM/PFMEM resources. If cannot, returns -EINVAL, 966 966 * otherwise, returns 0 967 967 * 968 968 * Input: resource 969 - * Ouput: the correct start and end address are inputted into the resource node, 969 + * Output: the correct start and end address are inputted into the resource node, 970 970 * 0 or -EINVAL 971 971 *****************************************************************************/ 972 972 int ibmphp_check_resource (struct resource_node *res, u8 bridge) ··· 996 996 bus_cur = find_bus_wprev (res->busno, NULL, 0); 997 997 998 998 if (!bus_cur) { 999 - /* didn't find a bus, smth's wrong!!! */ 999 + /* didn't find a bus, something's wrong!!! */ 1000 1000 debug ("no bus in the system, either pci_dev's wrong or allocation failed\n"); 1001 1001 return -EINVAL; 1002 1002 } ··· 1066 1066 break; 1067 1067 } 1068 1068 } 1069 - 1069 + 1070 1070 if (flag && len_cur == res->len) { 1071 1071 debug ("but we are not here, right?\n"); 1072 1072 res->start = start_cur; ··· 1118 1118 if (res_prev) { 1119 1119 if (res_prev->rangeno != res_cur->rangeno) { 1120 1120 /* 1st device on this range */ 1121 - if ((res_cur->start != range->start) && 1121 + if ((res_cur->start != range->start) && 1122 1122 ((len_tmp = res_cur->start - 1 - range->start) >= res->len)) { 1123 1123 if ((len_tmp < len_cur) || (len_cur == 0)) { 1124 - if ((range->start % tmp_divide) == 0) { 1124 + if ((range->start % tmp_divide) == 0) { 1125 1125 /* just perfect, starting address is divisible by length */ 1126 1126 flag = 1; 1127 1127 len_cur = len_tmp; ··· 1344 1344 * This routine is called from remove_card if the card contained PPB. 1345 1345 * It will remove all the resources on the bus as well as the bus itself 1346 1346 * Input: Bus 1347 - * Ouput: 0, -ENODEV 1347 + * Output: 0, -ENODEV 1348 1348 ********************************************************************************/ 1349 1349 int ibmphp_remove_bus (struct bus_node *bus, u8 parent_busno) 1350 1350 { ··· 1353 1353 struct bus_node *prev_bus; 1354 1354 int rc; 1355 1355 1356 - prev_bus = find_bus_wprev (parent_busno, NULL, 0); 1356 + prev_bus = find_bus_wprev (parent_busno, NULL, 0); 1357 1357 1358 1358 if (!prev_bus) { 1359 1359 debug ("something terribly wrong. Cannot find parent bus to the one to remove\n"); ··· 1424 1424 } 1425 1425 1426 1426 /****************************************************************************** 1427 - * This routine deletes the ranges from a given bus, and the entries from the 1427 + * This routine deletes the ranges from a given bus, and the entries from the 1428 1428 * parent's bus in the resources 1429 1429 * Input: current bus, previous bus 1430 1430 * Output: 0, -EINVAL ··· 1453 1453 if (bus_cur->noMemRanges) { 1454 1454 range_cur = bus_cur->rangeMem; 1455 1455 for (i = 0; i < bus_cur->noMemRanges; i++) { 1456 - if (ibmphp_find_resource (bus_prev, range_cur->start, &res, MEM) < 0) 1456 + if (ibmphp_find_resource (bus_prev, range_cur->start, &res, MEM) < 0) 1457 1457 return -EINVAL; 1458 1458 1459 1459 ibmphp_remove_resource (res); ··· 1467 1467 if (bus_cur->noPFMemRanges) { 1468 1468 range_cur = bus_cur->rangePFMem; 1469 1469 for (i = 0; i < bus_cur->noPFMemRanges; i++) { 1470 - if (ibmphp_find_resource (bus_prev, range_cur->start, &res, PFMEM) < 0) 1470 + if (ibmphp_find_resource (bus_prev, range_cur->start, &res, PFMEM) < 0) 1471 1471 return -EINVAL; 1472 1472 1473 1473 ibmphp_remove_resource (res); ··· 1482 1482 } 1483 1483 1484 1484 /* 1485 - * find the resource node in the bus 1485 + * find the resource node in the bus 1486 1486 * Input: Resource needed, start address of the resource, type of resource 1487 1487 */ 1488 1488 int ibmphp_find_resource (struct bus_node *bus, u32 start_address, struct resource_node **res, int flag) ··· 1512 1512 err ("wrong type of flag\n"); 1513 1513 return -EINVAL; 1514 1514 } 1515 - 1515 + 1516 1516 while (res_cur) { 1517 1517 if (res_cur->start == start_address) { 1518 1518 *res = res_cur; ··· 1718 1718 } /* end for pfmem */ 1719 1719 } /* end if */ 1720 1720 } /* end list_for_each bus */ 1721 - return 0; 1721 + return 0; 1722 1722 } 1723 1723 1724 1724 int ibmphp_add_pfmem_from_mem (struct resource_node *pfmem) ··· 1760 1760 list_for_each (tmp, &gbuses) { 1761 1761 tmp_prev = tmp->prev; 1762 1762 bus_cur = list_entry (tmp, struct bus_node, bus_list); 1763 - if (flag) 1763 + if (flag) 1764 1764 *prev = list_entry (tmp_prev, struct bus_node, bus_list); 1765 - if (bus_cur->busno == bus_number) 1765 + if (bus_cur->busno == bus_number) 1766 1766 return bus_cur; 1767 1767 } 1768 1768 ··· 1776 1776 struct range_node *range; 1777 1777 struct resource_node *res; 1778 1778 struct list_head *tmp; 1779 - 1779 + 1780 1780 debug_pci ("*****************START**********************\n"); 1781 1781 1782 1782 if ((!list_empty(&gbuses)) && flags) { ··· 1906 1906 return 1; 1907 1907 range_cur = range_cur->next; 1908 1908 } 1909 - 1909 + 1910 1910 return 0; 1911 1911 } 1912 1912 ··· 1920 1920 * Returns: none 1921 1921 * Note: this function doesn't take into account IO restrictions etc, 1922 1922 * so will only work for bridges with no video/ISA devices behind them It 1923 - * also will not work for onboard PPB's that can have more than 1 *bus 1923 + * also will not work for onboard PPBs that can have more than 1 *bus 1924 1924 * behind them All these are TO DO. 1925 1925 * Also need to add more error checkings... (from fnc returns etc) 1926 1926 */ ··· 1963 1963 case PCI_HEADER_TYPE_BRIDGE: 1964 1964 function = 0x8; 1965 1965 case PCI_HEADER_TYPE_MULTIBRIDGE: 1966 - /* We assume here that only 1 bus behind the bridge 1966 + /* We assume here that only 1 bus behind the bridge 1967 1967 TO DO: add functionality for several: 1968 1968 temp = secondary; 1969 1969 while (temp < subordinate) { ··· 1972 1972 } 1973 1973 */ 1974 1974 pci_bus_read_config_byte (ibmphp_pci_bus, devfn, PCI_SECONDARY_BUS, &sec_busno); 1975 - bus_sec = find_bus_wprev (sec_busno, NULL, 0); 1975 + bus_sec = find_bus_wprev (sec_busno, NULL, 0); 1976 1976 /* this bus structure doesn't exist yet, PPB was configured during previous loading of ibmphp */ 1977 1977 if (!bus_sec) { 1978 1978 bus_sec = alloc_error_bus (NULL, sec_busno, 1); ··· 2028 2028 io->len = io->end - io->start + 1; 2029 2029 ibmphp_add_resource (io); 2030 2030 } 2031 - } 2031 + } 2032 2032 2033 2033 pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_MEMORY_BASE, &start_mem_address); 2034 2034 pci_bus_read_config_word (ibmphp_pci_bus, devfn, PCI_MEMORY_LIMIT, &end_mem_address);

+4 -4

drivers/pci/hotplug/pci_hotplug_core.c

··· 131 131 } 132 132 module_put(slot->ops->owner); 133 133 134 - exit: 134 + exit: 135 135 if (retval) 136 136 return retval; 137 137 return count; ··· 177 177 retval = ops->set_attention_status(slot->hotplug, attention); 178 178 module_put(ops->owner); 179 179 180 - exit: 180 + exit: 181 181 if (retval) 182 182 return retval; 183 183 return count; ··· 247 247 retval = slot->ops->hardware_test(slot, test); 248 248 module_put(slot->ops->owner); 249 249 250 - exit: 250 + exit: 251 251 if (retval) 252 252 return retval; 253 253 return count; ··· 512 512 * @hotplug: pointer to the slot whose info has changed 513 513 * @info: pointer to the info copy into the slot's info structure 514 514 * 515 - * @slot must have been registered with the pci 515 + * @slot must have been registered with the pci 516 516 * hotplug subsystem previously with a call to pci_hp_register(). 517 517 * 518 518 * Returns 0 if successful, anything else for an error.

+1 -1

drivers/pci/hotplug/pciehp.h

··· 180 180 { 181 181 return 0; 182 182 } 183 - #endif /* CONFIG_ACPI */ 183 + #endif /* CONFIG_ACPI */ 184 184 #endif /* _PCIEHP_H */

+1 -1

drivers/pci/hotplug/pciehp_acpi.c

··· 78 78 static int __initdata acpi_slot_detected; 79 79 static struct list_head __initdata dummy_slots = LIST_HEAD_INIT(dummy_slots); 80 80 81 - /* Dummy driver for dumplicate name detection */ 81 + /* Dummy driver for duplicate name detection */ 82 82 static int __init dummy_probe(struct pcie_device *dev) 83 83 { 84 84 u32 slot_cap;

+2 -2

drivers/pci/hotplug/pciehp_core.c

··· 351 351 352 352 pciehp_firmware_init(); 353 353 retval = pcie_port_service_register(&hpdriver_portdrv); 354 - dbg("pcie_port_service_register = %d\n", retval); 355 - info(DRIVER_DESC " version: " DRIVER_VERSION "\n"); 354 + dbg("pcie_port_service_register = %d\n", retval); 355 + info(DRIVER_DESC " version: " DRIVER_VERSION "\n"); 356 356 if (retval) 357 357 dbg("Failure to register service\n"); 358 358

+3 -3

drivers/pci/hotplug/pciehp_hpc.c

··· 92 92 { 93 93 /* Clamp to sane value */ 94 94 if ((sec <= 0) || (sec > 60)) 95 - sec = 2; 95 + sec = 2; 96 96 97 97 ctrl->poll_timer.function = &int_poll_timeout; 98 98 ctrl->poll_timer.data = (unsigned long)ctrl; ··· 194 194 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); 195 195 } else if (!NO_CMD_CMPL(ctrl)) { 196 196 /* 197 - * This controller semms to notify of command completed 197 + * This controller seems to notify of command completed 198 198 * event even though it supports none of power 199 199 * controller, attention led, power led and EMI. 200 200 */ ··· 926 926 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) 927 927 goto abort_ctrl; 928 928 929 - /* Disable sotfware notification */ 929 + /* Disable software notification */ 930 930 pcie_disable_notification(ctrl); 931 931 932 932 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",

+4 -4

drivers/pci/hotplug/pcihp_skeleton.c

··· 52 52 do { \ 53 53 if (debug) \ 54 54 printk (KERN_DEBUG "%s: " format "\n", \ 55 - MY_NAME , ## arg); \ 55 + MY_NAME , ## arg); \ 56 56 } while (0) 57 57 #define err(format, arg...) printk(KERN_ERR "%s: " format "\n", MY_NAME , ## arg) 58 58 #define info(format, arg...) printk(KERN_INFO "%s: " format "\n", MY_NAME , ## arg) ··· 287 287 hotplug_slot->release = &release_slot; 288 288 make_slot_name(slot); 289 289 hotplug_slot->ops = &skel_hotplug_slot_ops; 290 - 290 + 291 291 /* 292 292 * Initialize the slot info structure with some known 293 293 * good values. ··· 296 296 get_attention_status(hotplug_slot, &info->attention_status); 297 297 get_latch_status(hotplug_slot, &info->latch_status); 298 298 get_adapter_status(hotplug_slot, &info->adapter_status); 299 - 299 + 300 300 dbg("registering slot %d\n", i); 301 301 retval = pci_hp_register(slot->hotplug_slot); 302 302 if (retval) { ··· 336 336 pci_hp_deregister(slot->hotplug_slot); 337 337 } 338 338 } 339 - 339 + 340 340 static int __init pcihp_skel_init(void) 341 341 { 342 342 int retval;

+1 -1

drivers/pci/hotplug/rpadlpar_core.c

··· 217 217 if (!pcibios_find_pci_bus(dn)) 218 218 return -EINVAL; 219 219 220 - /* If pci slot is hotplugable, use hotplug to remove it */ 220 + /* If pci slot is hotpluggable, use hotplug to remove it */ 221 221 slot = find_php_slot(dn); 222 222 if (slot && rpaphp_deregister_slot(slot)) { 223 223 printk(KERN_ERR "%s: unable to remove hotplug slot %s\n",

+3 -3

drivers/pci/hotplug/rpaphp.h

··· 49 49 extern bool rpaphp_debug; 50 50 #define dbg(format, arg...) \ 51 51 do { \ 52 - if (rpaphp_debug) \ 52 + if (rpaphp_debug) \ 53 53 printk(KERN_DEBUG "%s: " format, \ 54 - MY_NAME , ## arg); \ 54 + MY_NAME , ## arg); \ 55 55 } while (0) 56 56 #define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg) 57 57 #define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg) ··· 99 99 struct slot *alloc_slot_struct(struct device_node *dn, int drc_index, char *drc_name, int power_domain); 100 100 int rpaphp_register_slot(struct slot *slot); 101 101 int rpaphp_deregister_slot(struct slot *slot); 102 - 102 + 103 103 #endif /* _PPC64PHP_H */

+4 -4

drivers/pci/hotplug/rpaphp_core.c

··· 226 226 for (i = 0; i < indexes[0]; i++) { 227 227 if ((unsigned int) indexes[i + 1] == *my_index) { 228 228 if (drc_name) 229 - *drc_name = name_tmp; 229 + *drc_name = name_tmp; 230 230 if (drc_type) 231 231 *drc_type = type_tmp; 232 232 if (drc_index) ··· 289 289 * rpaphp_add_slot -- declare a hotplug slot to the hotplug subsystem. 290 290 * @dn: device node of slot 291 291 * 292 - * This subroutine will register a hotplugable slot with the 292 + * This subroutine will register a hotpluggable slot with the 293 293 * PCI hotplug infrastructure. This routine is typically called 294 294 * during boot time, if the hotplug slots are present at boot time, 295 295 * or is called later, by the dlpar add code, if the slot is ··· 328 328 return -ENOMEM; 329 329 330 330 slot->type = simple_strtoul(type, NULL, 10); 331 - 331 + 332 332 dbg("Found drc-index:0x%x drc-name:%s drc-type:%s\n", 333 333 indexes[i + 1], name, type); 334 334 ··· 356 356 /* 357 357 * Unregister all of our slots with the pci_hotplug subsystem, 358 358 * and free up all memory that we had allocated. 359 - * memory will be freed in release_slot callback. 359 + * memory will be freed in release_slot callback. 360 360 */ 361 361 362 362 list_for_each_safe(tmp, n, &rpaphp_slot_head) {

+1 -2

drivers/pci/hotplug/rpaphp_pci.c

··· 44 44 dbg("%s: slot must be power up to get sensor-state\n", 45 45 __func__); 46 46 47 - /* some slots have to be powered up 47 + /* some slots have to be powered up 48 48 * before get-sensor will succeed. 49 49 */ 50 50 rc = rtas_set_power_level(slot->power_domain, POWER_ON, ··· 133 133 134 134 return 0; 135 135 } 136 -

+9 -10

drivers/pci/hotplug/rpaphp_slot.c

··· 1 1 /* 2 - * RPA Virtual I/O device functions 2 + * RPA Virtual I/O device functions 3 3 * Copyright (C) 2004 Linda Xie <lxie@us.ibm.com> 4 4 * 5 5 * All rights reserved. ··· 51 51 int drc_index, char *drc_name, int power_domain) 52 52 { 53 53 struct slot *slot; 54 - 54 + 55 55 slot = kzalloc(sizeof(struct slot), GFP_KERNEL); 56 56 if (!slot) 57 57 goto error_nomem; 58 58 slot->hotplug_slot = kzalloc(sizeof(struct hotplug_slot), GFP_KERNEL); 59 59 if (!slot->hotplug_slot) 60 - goto error_slot; 60 + goto error_slot; 61 61 slot->hotplug_slot->info = kzalloc(sizeof(struct hotplug_slot_info), 62 62 GFP_KERNEL); 63 63 if (!slot->hotplug_slot->info) 64 64 goto error_hpslot; 65 65 slot->name = kstrdup(drc_name, GFP_KERNEL); 66 66 if (!slot->name) 67 - goto error_info; 67 + goto error_info; 68 68 slot->dn = dn; 69 69 slot->index = drc_index; 70 70 slot->power_domain = power_domain; 71 71 slot->hotplug_slot->private = slot; 72 72 slot->hotplug_slot->ops = &rpaphp_hotplug_slot_ops; 73 73 slot->hotplug_slot->release = &rpaphp_release_slot; 74 - 74 + 75 75 return (slot); 76 76 77 77 error_info: ··· 91 91 list_for_each_entry(tmp_slot, &rpaphp_slot_head, rpaphp_slot_list) { 92 92 if (!strcmp(tmp_slot->name, slot->name)) 93 93 return 1; 94 - } 94 + } 95 95 return 0; 96 96 } 97 97 ··· 104 104 __func__, slot->name); 105 105 106 106 list_del(&slot->rpaphp_slot_list); 107 - 107 + 108 108 retval = pci_hp_deregister(php_slot); 109 109 if (retval) 110 110 err("Problem unregistering a slot %s\n", slot->name); ··· 120 120 int retval; 121 121 int slotno; 122 122 123 - dbg("%s registering slot:path[%s] index[%x], name[%s] pdomain[%x] type[%d]\n", 123 + dbg("%s registering slot:path[%s] index[%x], name[%s] pdomain[%x] type[%d]\n", 124 124 __func__, slot->dn->full_name, slot->index, slot->name, 125 125 slot->power_domain, slot->type); 126 126 ··· 128 128 if (is_registered(slot)) { 129 129 err("rpaphp_register_slot: slot[%s] is already registered\n", slot->name); 130 130 return -EAGAIN; 131 - } 131 + } 132 132 133 133 if (slot->dn->child) 134 134 slotno = PCI_SLOT(PCI_DN(slot->dn->child)->devfn); ··· 145 145 info("Slot [%s] registered\n", slot->name); 146 146 return 0; 147 147 } 148 -

+4 -4

drivers/pci/hotplug/shpchp.h

··· 216 216 217 217 /* offsets to the controller registers based on the above structure layout */ 218 218 enum ctrl_offsets { 219 - BASE_OFFSET = offsetof(struct ctrl_reg, base_offset), 220 - SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1), 219 + BASE_OFFSET = offsetof(struct ctrl_reg, base_offset), 220 + SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1), 221 221 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2), 222 - SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config), 222 + SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config), 223 223 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config), 224 224 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl), 225 - PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface), 225 + PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface), 226 226 CMD = offsetof(struct ctrl_reg, cmd), 227 227 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status), 228 228 INTR_LOC = offsetof(struct ctrl_reg, intr_loc),

+5 -5

drivers/pci/hotplug/shpchp_core.c

··· 143 143 snprintf(name, SLOT_NAME_SIZE, "%d", slot->number); 144 144 hotplug_slot->ops = &shpchp_hotplug_slot_ops; 145 145 146 - ctrl_dbg(ctrl, "Registering domain:bus:dev=%04x:%02x:%02x " 147 - "hp_slot=%x sun=%x slot_device_offset=%x\n", 148 - pci_domain_nr(ctrl->pci_dev->subordinate), 149 - slot->bus, slot->device, slot->hp_slot, slot->number, 150 - ctrl->slot_device_offset); 146 + ctrl_dbg(ctrl, "Registering domain:bus:dev=%04x:%02x:%02x " 147 + "hp_slot=%x sun=%x slot_device_offset=%x\n", 148 + pci_domain_nr(ctrl->pci_dev->subordinate), 149 + slot->bus, slot->device, slot->hp_slot, slot->number, 150 + ctrl->slot_device_offset); 151 151 retval = pci_hp_register(slot->hotplug_slot, 152 152 ctrl->pci_dev->subordinate, slot->device, name); 153 153 if (retval) {

+1 -1

drivers/pci/hotplug/shpchp_hpc.c

··· 116 116 #define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21)) 117 117 118 118 /* 119 - * SHPC Command Code definitnions 119 + * SHPC Command Code definitions 120 120 * 121 121 * Slot Operation 00h - 3Fh 122 122 * Set Bus Segment Speed/Mode A 40h - 47h

+1 -1

drivers/pci/iov.c

··· 610 610 struct resource tmp; 611 611 enum pci_bar_type type; 612 612 int reg = pci_iov_resource_bar(dev, resno, &type); 613 - 613 + 614 614 if (!reg) 615 615 return 0; 616 616

+1 -1

drivers/pci/irq.c

··· 25 25 /** 26 26 * pci_lost_interrupt - reports a lost PCI interrupt 27 27 * @pdev: device whose interrupt is lost 28 - * 28 + * 29 29 * The primary function of this routine is to report a lost interrupt 30 30 * in a standard way which users can recognise (instead of blaming the 31 31 * driver).

+1 -1

drivers/pci/msi.c

··· 784 784 * @nvec: how many MSIs have been requested ? 785 785 * @type: are we checking for MSI or MSI-X ? 786 786 * 787 - * Look at global flags, the device itself, and its parent busses 787 + * Look at global flags, the device itself, and its parent buses 788 788 * to determine if MSI/-X are supported for the device. If MSI/-X is 789 789 * supported return 0, else return an error code. 790 790 **/

+1 -1

drivers/pci/pci-acpi.c

··· 141 141 * if (_PRW at S-state x) 142 142 * choose from highest power _SxD to lowest power _SxW 143 143 * else // no _PRW at S-state x 144 - * choose highest power _SxD or any lower power 144 + * choose highest power _SxD or any lower power 145 145 */ 146 146 147 147 static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)

+8 -8

drivers/pci/pci-driver.c

··· 312 312 * __pci_device_probe - check if a driver wants to claim a specific PCI device 313 313 * @drv: driver to call to check if it wants the PCI device 314 314 * @pci_dev: PCI device being probed 315 - * 315 + * 316 316 * returns 0 on success, else error. 317 317 * side-effect: pci_dev->driver is set to drv when drv claims pci_dev. 318 318 */ ··· 378 378 * We would love to complain here if pci_dev->is_enabled is set, that 379 379 * the driver should have called pci_disable_device(), but the 380 380 * unfortunate fact is there are too many odd BIOS and bridge setups 381 - * that don't like drivers doing that all of the time. 381 + * that don't like drivers doing that all of the time. 382 382 * Oh well, we can dream of sane hardware when we sleep, no matter how 383 383 * horrible the crap we have to deal with is when we are awake... 384 384 */ ··· 1156 1156 * @drv: the driver structure to register 1157 1157 * @owner: owner module of drv 1158 1158 * @mod_name: module name string 1159 - * 1159 + * 1160 1160 * Adds the driver structure to the list of registered drivers. 1161 - * Returns a negative value on error, otherwise 0. 1162 - * If no error occurred, the driver remains registered even if 1161 + * Returns a negative value on error, otherwise 0. 1162 + * If no error occurred, the driver remains registered even if 1163 1163 * no device was claimed during registration. 1164 1164 */ 1165 1165 int __pci_register_driver(struct pci_driver *drv, struct module *owner, ··· 1181 1181 /** 1182 1182 * pci_unregister_driver - unregister a pci driver 1183 1183 * @drv: the driver structure to unregister 1184 - * 1184 + * 1185 1185 * Deletes the driver structure from the list of registered PCI drivers, 1186 1186 * gives it a chance to clean up by calling its remove() function for 1187 1187 * each device it was responsible for, and marks those devices as ··· 1203 1203 * pci_dev_driver - get the pci_driver of a device 1204 1204 * @dev: the device to query 1205 1205 * 1206 - * Returns the appropriate pci_driver structure or %NULL if there is no 1206 + * Returns the appropriate pci_driver structure or %NULL if there is no 1207 1207 * registered driver for the device. 1208 1208 */ 1209 1209 struct pci_driver * ··· 1224 1224 * pci_bus_match - Tell if a PCI device structure has a matching PCI device id structure 1225 1225 * @dev: the PCI device structure to match against 1226 1226 * @drv: the device driver to search for matching PCI device id structures 1227 - * 1227 + * 1228 1228 * Used by a driver to check whether a PCI device present in the 1229 1229 * system is in its list of supported devices. Returns the matching 1230 1230 * pci_device_id structure or %NULL if there is no match.

+2 -2

drivers/pci/pci-stub.c

··· 2 2 * 3 3 * Copyright (C) 2008 Red Hat, Inc. 4 4 * Author: 5 - * Chris Wright 5 + * Chris Wright 6 6 * 7 7 * This work is licensed under the terms of the GNU GPL, version 2. 8 8 * 9 9 * Usage is simple, allocate a new id to the stub driver and bind the 10 10 * device to it. For example: 11 - * 11 + * 12 12 * # echo "8086 10f5" > /sys/bus/pci/drivers/pci-stub/new_id 13 13 * # echo -n 0000:00:19.0 > /sys/bus/pci/drivers/e1000e/unbind 14 14 * # echo -n 0000:00:19.0 > /sys/bus/pci/drivers/pci-stub/bind

+16 -12

drivers/pci/pci-sysfs.c

··· 10 10 * 11 11 * File attributes for PCI devices 12 12 * 13 - * Modeled after usb's driverfs.c 13 + * Modeled after usb's driverfs.c 14 14 * 15 15 */ 16 16 ··· 270 270 if (kstrtoul(buf, 0, &val) < 0) 271 271 return -EINVAL; 272 272 273 - /* bad things may happen if the no_msi flag is changed 274 - * while some drivers are loaded */ 273 + /* 274 + * Bad things may happen if the no_msi flag is changed 275 + * while drivers are loaded. 276 + */ 275 277 if (!capable(CAP_SYS_ADMIN)) 276 278 return -EPERM; 277 279 278 - /* Maybe pci devices without subordinate busses shouldn't even have this 279 - * attribute in the first place? */ 280 + /* 281 + * Maybe devices without subordinate buses shouldn't have this 282 + * attribute in the first place? 283 + */ 280 284 if (!pdev->subordinate) 281 285 return count; 282 286 ··· 674 670 size = dev->cfg_size - off; 675 671 count = size; 676 672 } 677 - 673 + 678 674 pci_config_pm_runtime_get(dev); 679 675 680 676 if ((off & 1) && size) { ··· 682 678 off++; 683 679 size--; 684 680 } 685 - 681 + 686 682 if ((off & 3) && size > 2) { 687 683 u16 val = data[off - init_off]; 688 684 val |= (u16) data[off - init_off + 1] << 8; ··· 700 696 off += 4; 701 697 size -= 4; 702 698 } 703 - 699 + 704 700 if (size >= 2) { 705 701 u16 val = data[off - init_off]; 706 702 val |= (u16) data[off - init_off + 1] << 8; ··· 1233 1229 1234 1230 if (!pdev->rom_attr_enabled) 1235 1231 return -EINVAL; 1236 - 1232 + 1237 1233 rom = pci_map_rom(pdev, &size); /* size starts out as PCI window size */ 1238 1234 if (!rom || !size) 1239 1235 return -EIO; 1240 - 1236 + 1241 1237 if (off >= size) 1242 1238 count = 0; 1243 1239 else { 1244 1240 if (off + count > size) 1245 1241 count = size - off; 1246 - 1242 + 1247 1243 memcpy_fromio(buf, rom + off, count); 1248 1244 } 1249 1245 pci_unmap_rom(pdev, rom); 1250 - 1246 + 1251 1247 return count; 1252 1248 } 1253 1249

+23 -23

drivers/pci/pci.c

··· 198 198 } 199 199 200 200 /** 201 - * pci_find_capability - query for devices' capabilities 201 + * pci_find_capability - query for devices' capabilities 202 202 * @dev: PCI device to query 203 203 * @cap: capability code 204 204 * ··· 207 207 * device's PCI configuration space or 0 in case the device does not 208 208 * support it. Possible values for @cap: 209 209 * 210 - * %PCI_CAP_ID_PM Power Management 211 - * %PCI_CAP_ID_AGP Accelerated Graphics Port 212 - * %PCI_CAP_ID_VPD Vital Product Data 213 - * %PCI_CAP_ID_SLOTID Slot Identification 210 + * %PCI_CAP_ID_PM Power Management 211 + * %PCI_CAP_ID_AGP Accelerated Graphics Port 212 + * %PCI_CAP_ID_VPD Vital Product Data 213 + * %PCI_CAP_ID_SLOTID Slot Identification 214 214 * %PCI_CAP_ID_MSI Message Signalled Interrupts 215 - * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 215 + * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 216 216 * %PCI_CAP_ID_PCIX PCI-X 217 217 * %PCI_CAP_ID_EXP PCI Express 218 218 */ ··· 228 228 } 229 229 230 230 /** 231 - * pci_bus_find_capability - query for devices' capabilities 231 + * pci_bus_find_capability - query for devices' capabilities 232 232 * @bus: the PCI bus to query 233 233 * @devfn: PCI device to query 234 234 * @cap: capability code 235 235 * 236 236 * Like pci_find_capability() but works for pci devices that do not have a 237 - * pci_dev structure set up yet. 237 + * pci_dev structure set up yet. 238 238 * 239 239 * Returns the address of the requested capability structure within the 240 240 * device's PCI configuration space or 0 in case the device does not ··· 515 515 return -EINVAL; 516 516 517 517 /* Validate current state: 518 - * Can enter D0 from any state, but if we can only go deeper 518 + * Can enter D0 from any state, but if we can only go deeper 519 519 * to sleep if we're already in a low power state 520 520 */ 521 521 if (state != PCI_D0 && dev->current_state <= PCI_D3cold ··· 998 998 } 999 999 } 1000 1000 1001 - /** 1001 + /** 1002 1002 * pci_restore_state - Restore the saved state of a PCI device 1003 1003 * @dev: - PCI device that we're dealing with 1004 1004 */ ··· 1030 1030 * the device saved state. 1031 1031 * @dev: PCI device that we're dealing with 1032 1032 * 1033 - * Rerturn NULL if no state or error. 1033 + * Return NULL if no state or error. 1034 1034 */ 1035 1035 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) 1036 1036 { ··· 1880 1880 * pci_dev_run_wake - Check if device can generate run-time wake-up events. 1881 1881 * @dev: Device to check. 1882 1882 * 1883 - * Return true if the device itself is cabable of generating wake-up events 1883 + * Return true if the device itself is capable of generating wake-up events 1884 1884 * (through the platform or using the native PCIe PME) or if the device supports 1885 1885 * PME and one of its upstream bridges can generate wake-up events. 1886 1886 */ ··· 2447 2447 switch (pci_pcie_type(pdev)) { 2448 2448 /* 2449 2449 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, 2450 - * but since their primary inteface is PCI/X, we conservatively 2450 + * but since their primary interface is PCI/X, we conservatively 2451 2451 * handle them as we would a non-PCIe device. 2452 2452 */ 2453 2453 case PCI_EXP_TYPE_PCIE_BRIDGE: ··· 2471 2471 /* 2472 2472 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be 2473 2473 * implemented by the remaining PCIe types to indicate peer-to-peer 2474 - * capabilities, but only when they are part of a multifunciton 2474 + * capabilities, but only when they are part of a multifunction 2475 2475 * device. The footnote for section 6.12 indicates the specific 2476 2476 * PCIe types included here. 2477 2477 */ ··· 2486 2486 } 2487 2487 2488 2488 /* 2489 - * PCIe 3.0, 6.12.1.3 specifies no ACS capabilties are applicable 2489 + * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable 2490 2490 * to single function devices with the exception of downstream ports. 2491 2491 */ 2492 2492 return true; ··· 2622 2622 * 2623 2623 * If @exclusive is set, then the region is marked so that userspace 2624 2624 * is explicitly not allowed to map the resource via /dev/mem or 2625 - * sysfs MMIO access. 2625 + * sysfs MMIO access. 2626 2626 * 2627 2627 * Returns 0 on success, or %EBUSY on error. A warning 2628 2628 * message is also printed on failure. ··· 2634 2634 2635 2635 if (pci_resource_len(pdev, bar) == 0) 2636 2636 return 0; 2637 - 2637 + 2638 2638 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 2639 2639 if (!request_region(pci_resource_start(pdev, bar), 2640 2640 pci_resource_len(pdev, bar), res_name)) ··· 2694 2694 * 2695 2695 * The key difference that _exclusive makes it that userspace is 2696 2696 * explicitly not allowed to map the resource via /dev/mem or 2697 - * sysfs. 2697 + * sysfs. 2698 2698 */ 2699 2699 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) 2700 2700 { ··· 2799 2799 * successfully. 2800 2800 * 2801 2801 * pci_request_regions_exclusive() will mark the region so that 2802 - * /dev/mem and the sysfs MMIO access will not be allowed. 2802 + * /dev/mem and the sysfs MMIO access will not be allowed. 2803 2803 * 2804 2804 * Returns 0 on success, or %EBUSY on error. A warning 2805 2805 * message is also printed on failure. ··· 2967 2967 cmd |= PCI_COMMAND_INVALIDATE; 2968 2968 pci_write_config_word(dev, PCI_COMMAND, cmd); 2969 2969 } 2970 - 2970 + 2971 2971 return 0; 2972 2972 } 2973 2973 ··· 3292 3292 * 3293 3293 * NOTE: This causes the caller to sleep for twice the device power transition 3294 3294 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms 3295 - * by devault (i.e. unless the @dev's d3_delay field has a different value). 3295 + * by default (i.e. unless the @dev's d3_delay field has a different value). 3296 3296 * Moreover, only devices in D0 can be reset by this function. 3297 3297 */ 3298 3298 static int pci_pm_reset(struct pci_dev *dev, int probe) ··· 3341 3341 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 3342 3342 /* 3343 3343 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double 3344 - * this to 2ms to ensure that we meet the minium requirement. 3344 + * this to 2ms to ensure that we meet the minimum requirement. 3345 3345 */ 3346 3346 msleep(2); 3347 3347 ··· 3998 3998 return -EINVAL; 3999 3999 4000 4000 v = ffs(mps) - 8; 4001 - if (v > dev->pcie_mpss) 4001 + if (v > dev->pcie_mpss) 4002 4002 return -EINVAL; 4003 4003 v <<= 5; 4004 4004

+1 -1

drivers/pci/pcie/aer/aerdrv_core.c

··· 525 525 526 526 if (info->severity == AER_CORRECTABLE) { 527 527 /* 528 - * Correctable error does not need software intevention. 528 + * Correctable error does not need software intervention. 529 529 * No need to go through error recovery process. 530 530 */ 531 531 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);

+1 -1

drivers/pci/pcie/aspm.c

··· 548 548 549 549 /* 550 550 * pcie_aspm_init_link_state: Initiate PCI express link state. 551 - * It is called after the pcie and its children devices are scaned. 551 + * It is called after the pcie and its children devices are scanned. 552 552 * @pdev: the root port or switch downstream port 553 553 */ 554 554 void pcie_aspm_init_link_state(struct pci_dev *pdev)

+2 -2

drivers/pci/pcie/pme.c

··· 419 419 420 420 static struct pcie_port_service_driver pcie_pme_driver = { 421 421 .name = "pcie_pme", 422 - .port_type = PCI_EXP_TYPE_ROOT_PORT, 423 - .service = PCIE_PORT_SERVICE_PME, 422 + .port_type = PCI_EXP_TYPE_ROOT_PORT, 423 + .service = PCIE_PORT_SERVICE_PME, 424 424 425 425 .probe = pcie_pme_probe, 426 426 .suspend = pcie_pme_suspend,

+1 -1

drivers/pci/pcie/portdrv.h

··· 14 14 #define PCIE_PORT_DEVICE_MAXSERVICES 4 15 15 /* 16 16 * According to the PCI Express Base Specification 2.0, the indices of 17 - * the MSI-X table entires used by port services must not exceed 31 17 + * the MSI-X table entries used by port services must not exceed 31 18 18 */ 19 19 #define PCIE_PORT_MAX_MSIX_ENTRIES 32 20 20

+2 -2

drivers/pci/pcie/portdrv_bus.c

··· 18 18 static int pcie_port_bus_match(struct device *dev, struct device_driver *drv); 19 19 20 20 struct bus_type pcie_port_bus_type = { 21 - .name = "pci_express", 22 - .match = pcie_port_bus_match, 21 + .name = "pci_express", 22 + .match = pcie_port_bus_match, 23 23 }; 24 24 EXPORT_SYMBOL_GPL(pcie_port_bus_type); 25 25

+1 -1

drivers/pci/pcie/portdrv_core.c

··· 46 46 * pcie_port_msix_add_entry - add entry to given array of MSI-X entries 47 47 * @entries: Array of MSI-X entries 48 48 * @new_entry: Index of the entry to add to the array 49 - * @nr_entries: Number of entries aleady in the array 49 + * @nr_entries: Number of entries already in the array 50 50 * 51 51 * Return value: Position of the added entry in the array 52 52 */

+3 -4

drivers/pci/pcie/portdrv_pci.c

··· 223 223 static void pcie_portdrv_remove(struct pci_dev *dev) 224 224 { 225 225 pcie_port_device_remove(dev); 226 - pci_disable_device(dev); 227 226 } 228 227 229 228 static int error_detected_iter(struct device *device, void *data) ··· 389 390 .probe = pcie_portdrv_probe, 390 391 .remove = pcie_portdrv_remove, 391 392 392 - .err_handler = &pcie_portdrv_err_handler, 393 + .err_handler = &pcie_portdrv_err_handler, 393 394 394 - .driver.pm = PCIE_PORTDRV_PM_OPS, 395 + .driver.pm = PCIE_PORTDRV_PM_OPS, 395 396 }; 396 397 397 398 static int __init dmi_pcie_pme_disable_msi(const struct dmi_system_id *d) ··· 411 412 .ident = "MSI Wind U-100", 412 413 .matches = { 413 414 DMI_MATCH(DMI_SYS_VENDOR, 414 - "MICRO-STAR INTERNATIONAL CO., LTD"), 415 + "MICRO-STAR INTERNATIONAL CO., LTD"), 415 416 DMI_MATCH(DMI_PRODUCT_NAME, "U-100"), 416 417 }, 417 418 },

+5 -5

drivers/pci/probe.c

··· 582 582 index = 1; 583 583 else 584 584 goto out; 585 - 585 + 586 586 if (agp3) { 587 587 index += 2; 588 588 if (index == 5) ··· 789 789 } 790 790 791 791 /* Disable MasterAbortMode during probing to avoid reporting 792 - of bus errors (in some architectures) */ 792 + of bus errors (in some architectures) */ 793 793 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 794 794 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 795 795 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); ··· 1005 1005 * pci_setup_device - fill in class and map information of a device 1006 1006 * @dev: the device structure to fill 1007 1007 * 1008 - * Initialize the device structure with information about the device's 1008 + * Initialize the device structure with information about the device's 1009 1009 * vendor,class,memory and IO-space addresses,IRQ lines etc. 1010 1010 * Called at initialisation of the PCI subsystem and by CardBus services. 1011 1011 * Returns 0 on success and negative if unknown type of device (not normal, ··· 1111 1111 goto bad; 1112 1112 /* The PCI-to-PCI bridge spec requires that subtractive 1113 1113 decoding (i.e. transparent) bridge must have programming 1114 - interface code of 0x01. */ 1114 + interface code of 0x01. */ 1115 1115 pci_read_irq(dev); 1116 1116 dev->transparent = ((dev->class & 0xff) == 1); 1117 1117 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); ··· 1570 1570 * subsequent read will verify if the value is acceptable or not. 1571 1571 * If the MRRS value provided is not acceptable (e.g., too large), 1572 1572 * shrink the value until it is acceptable to the HW. 1573 - */ 1573 + */ 1574 1574 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 1575 1575 rc = pcie_set_readrq(dev, mrrs); 1576 1576 if (!rc)

+1 -1

drivers/pci/proc.c

··· 222 222 default: 223 223 ret = -EINVAL; 224 224 break; 225 - }; 225 + } 226 226 227 227 return ret; 228 228 }

+52 -52

drivers/pci/quirks.c

··· 55 55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); 56 56 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); 57 57 58 - /* Deal with broken BIOS'es that neglect to enable passive release, 58 + /* Deal with broken BIOSes that neglect to enable passive release, 59 59 which can cause problems in combination with the 82441FX/PPro MTRRs */ 60 60 static void quirk_passive_release(struct pci_dev *dev) 61 61 { ··· 78 78 79 79 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 80 80 but VIA don't answer queries. If you happen to have good contacts at VIA 81 - ask them for me please -- Alan 82 - 83 - This appears to be BIOS not version dependent. So presumably there is a 81 + ask them for me please -- Alan 82 + 83 + This appears to be BIOS not version dependent. So presumably there is a 84 84 chipset level fix */ 85 - 85 + 86 86 static void quirk_isa_dma_hangs(struct pci_dev *dev) 87 87 { 88 88 if (!isa_dma_bridge_buggy) { ··· 97 97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 98 98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 99 99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 100 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 100 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 101 101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 102 102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 103 103 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); ··· 157 157 pci_pci_problems |= PCIPCI_TRITON; 158 158 } 159 159 } 160 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 161 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 162 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 163 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 160 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 161 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 162 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 163 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 164 164 165 165 /* 166 166 * VIA Apollo KT133 needs PCI latency patch ··· 171 171 * the info on which Mr Breese based his work. 172 172 * 173 173 * Updated based on further information from the site and also on 174 - * information provided by VIA 174 + * information provided by VIA 175 175 */ 176 176 static void quirk_vialatency(struct pci_dev *dev) 177 177 { ··· 179 179 u8 busarb; 180 180 /* Ok we have a potential problem chipset here. Now see if we have 181 181 a buggy southbridge */ 182 - 182 + 183 183 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 184 184 if (p!=NULL) { 185 185 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ ··· 194 194 if (p->revision < 0x10 || p->revision > 0x12) 195 195 goto exit; 196 196 } 197 - 197 + 198 198 /* 199 - * Ok we have the problem. Now set the PCI master grant to 199 + * Ok we have the problem. Now set the PCI master grant to 200 200 * occur every master grant. The apparent bug is that under high 201 201 * PCI load (quite common in Linux of course) you can get data 202 202 * loss when the CPU is held off the bus for 3 bus master requests ··· 209 209 */ 210 210 211 211 pci_read_config_byte(dev, 0x76, &busarb); 212 - /* Set bit 4 and bi 5 of byte 76 to 0x01 212 + /* Set bit 4 and bi 5 of byte 76 to 0x01 213 213 "Master priority rotation on every PCI master grant */ 214 214 busarb &= ~(1<<5); 215 215 busarb |= (1<<4); ··· 252 252 * that DMA to AGP space. Latency must be set to 0xA and triton 253 253 * workaround applied too 254 254 * [Info kindly provided by ALi] 255 - */ 255 + */ 256 256 static void quirk_alimagik(struct pci_dev *dev) 257 257 { 258 258 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { ··· 260 260 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 261 261 } 262 262 } 263 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 264 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 263 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 264 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 265 265 266 266 /* 267 267 * Natoma has some interesting boundary conditions with Zoran stuff ··· 274 274 pci_pci_problems |= PCIPCI_NATOMA; 275 275 } 276 276 } 277 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 278 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 279 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 280 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 281 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 282 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 277 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 278 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 279 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 280 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 281 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 282 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 283 283 284 284 /* 285 285 * This chip can cause PCI parity errors if config register 0xA0 is read ··· 400 400 /* 401 401 * For now we only print it out. Eventually we'll want to 402 402 * reserve it (at least if it's in the 0x1000+ range), but 403 - * let's get enough confirmation reports first. 403 + * let's get enough confirmation reports first. 404 404 */ 405 405 base &= -size; 406 406 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); ··· 425 425 } 426 426 /* 427 427 * For now we only print it out. Eventually we'll want to 428 - * reserve it, but let's get enough confirmation reports first. 428 + * reserve it, but let's get enough confirmation reports first. 429 429 */ 430 430 base &= -size; 431 431 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); ··· 682 682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 683 683 quirk_xio2000a); 684 684 685 - #ifdef CONFIG_X86_IO_APIC 685 + #ifdef CONFIG_X86_IO_APIC 686 686 687 687 #include <asm/io_apic.h> 688 688 ··· 696 696 static void quirk_via_ioapic(struct pci_dev *dev) 697 697 { 698 698 u8 tmp; 699 - 699 + 700 700 if (nr_ioapics < 1) 701 701 tmp = 0; /* nothing routed to external APIC */ 702 702 else 703 703 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 704 - 704 + 705 705 dev_info(&dev->dev, "%sbling VIA external APIC routing\n", 706 706 tmp == 0 ? "Disa" : "Ena"); 707 707 ··· 712 712 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 713 713 714 714 /* 715 - * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 715 + * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 716 716 * This leads to doubled level interrupt rates. 717 717 * Set this bit to get rid of cycle wastage. 718 718 * Otherwise uncritical. ··· 986 986 static void quirk_disable_pxb(struct pci_dev *pdev) 987 987 { 988 988 u16 config; 989 - 989 + 990 990 if (pdev->revision != 0x04) /* Only C0 requires this */ 991 991 return; 992 992 pci_read_config_word(pdev, 0x40, &config); ··· 1094 1094 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1095 1095 * is not activated. The myth is that Asus said that they do not want the 1096 1096 * users to be irritated by just another PCI Device in the Win98 device 1097 - * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1097 + * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1098 1098 * package 2.7.0 for details) 1099 1099 * 1100 - * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1101 - * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1100 + * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1101 + * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1102 1102 * becomes necessary to do this tweak in two steps -- the chosen trigger 1103 1103 * is either the Host bridge (preferred) or on-board VGA controller. 1104 1104 * ··· 1253 1253 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1254 1254 { 1255 1255 u16 val; 1256 - 1256 + 1257 1257 if (likely(!asus_hides_smbus)) 1258 1258 return; 1259 1259 ··· 1640 1640 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1641 1641 dev->vendor, dev->device); 1642 1642 } 1643 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1644 - DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1643 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1644 + DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); 1645 1645 1646 1646 /* 1647 1647 * disable boot interrupts on HT-1000 ··· 1673 1673 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1674 1674 dev->vendor, dev->device); 1675 1675 } 1676 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1677 - DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1676 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1677 + DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 1678 1678 1679 1679 /* 1680 1680 * disable boot interrupts on AMD and ATI chipsets ··· 1730 1730 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", 1731 1731 dev->vendor, dev->device); 1732 1732 } 1733 - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1734 - DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1733 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1734 + DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 1735 1735 #endif /* CONFIG_X86_IO_APIC */ 1736 1736 1737 1737 /* ··· 2127 2127 #ifdef CONFIG_PCI_MSI 2128 2128 /* Some chipsets do not support MSI. We cannot easily rely on setting 2129 2129 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 2130 - * some other busses controlled by the chipset even if Linux is not 2131 - * aware of it. Instead of setting the flag on all busses in the 2130 + * some other buses controlled by the chipset even if Linux is not 2131 + * aware of it. Instead of setting the flag on all buses in the 2132 2132 * machine, simply disable MSI globally. 2133 2133 */ 2134 2134 static void quirk_disable_all_msi(struct pci_dev *dev) ··· 2288 2288 nvenet_msi_disable); 2289 2289 2290 2290 /* 2291 - * Some versions of the MCP55 bridge from nvidia have a legacy irq routing 2292 - * config register. This register controls the routing of legacy interrupts 2293 - * from devices that route through the MCP55. If this register is misprogramed 2294 - * interrupts are only sent to the bsp, unlike conventional systems where the 2295 - * irq is broadxast to all online cpus. Not having this register set 2296 - * properly prevents kdump from booting up properly, so lets make sure that 2297 - * we have it set correctly. 2298 - * Note this is an undocumented register. 2291 + * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2292 + * config register. This register controls the routing of legacy 2293 + * interrupts from devices that route through the MCP55. If this register 2294 + * is misprogrammed, interrupts are only sent to the BSP, unlike 2295 + * conventional systems where the IRQ is broadcast to all online CPUs. Not 2296 + * having this register set properly prevents kdump from booting up 2297 + * properly, so let's make sure that we have it set correctly. 2298 + * Note that this is an undocumented register. 2299 2299 */ 2300 2300 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2301 2301 { ··· 2626 2626 /* Allow manual resource allocation for PCI hotplug bridges 2627 2627 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For 2628 2628 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), 2629 - * kernel fails to allocate resources when hotplug device is 2629 + * kernel fails to allocate resources when hotplug device is 2630 2630 * inserted and PCI bus is rescanned. 2631 2631 */ 2632 2632 static void quirk_hotplug_bridge(struct pci_dev *dev)

+1 -1

drivers/pci/remove.c

··· 7 7 { 8 8 int i; 9 9 10 - msi_remove_pci_irq_vectors(dev); 10 + msi_remove_pci_irq_vectors(dev); 11 11 12 12 pci_cleanup_rom(dev); 13 13 for (i = 0; i < PCI_NUM_RESOURCES; i++) {

+6 -6

drivers/pci/search.c

··· 1 1 /* 2 - * PCI searching functions. 2 + * PCI searching functions. 3 3 * 4 4 * Copyright (C) 1993 -- 1997 Drew Eckhardt, Frederic Potter, 5 5 * David Mosberger-Tang ··· 96 96 * pci_find_next_bus - begin or continue searching for a PCI bus 97 97 * @from: Previous PCI bus found, or %NULL for new search. 98 98 * 99 - * Iterates through the list of known PCI busses. A new search is 99 + * Iterates through the list of known PCI buses. A new search is 100 100 * initiated by passing %NULL as the @from argument. Otherwise if 101 101 * @from is not %NULL, searches continue from next device on the 102 102 * global list. 103 103 */ 104 - struct pci_bus * 104 + struct pci_bus * 105 105 pci_find_next_bus(const struct pci_bus *from) 106 106 { 107 107 struct list_head *n; ··· 119 119 /** 120 120 * pci_get_slot - locate PCI device for a given PCI slot 121 121 * @bus: PCI bus on which desired PCI device resides 122 - * @devfn: encodes number of PCI slot in which the desired PCI 123 - * device resides and the logical device number within that slot 122 + * @devfn: encodes number of PCI slot in which the desired PCI 123 + * device resides and the logical device number within that slot 124 124 * in case of multi-function devices. 125 125 * 126 - * Given a PCI bus and slot/function number, the desired PCI device 126 + * Given a PCI bus and slot/function number, the desired PCI device 127 127 * is located in the list of PCI devices. 128 128 * If the device is found, its reference count is increased and this 129 129 * function returns a pointer to its data structure. The caller must

+9 -9

drivers/pci/setup-bus.c

··· 292 292 (!(res->flags & IORESOURCE_ROM_ENABLE)))) 293 293 add_to_list(fail_head, 294 294 dev_res->dev, res, 295 - 0 /* dont care */, 296 - 0 /* dont care */); 295 + 0 /* don't care */, 296 + 0 /* don't care */); 297 297 } 298 298 reset_resource(res); 299 299 } ··· 667 667 if (!io) { 668 668 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); 669 669 pci_read_config_word(bridge, PCI_IO_BASE, &io); 670 - pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 671 - } 672 - if (io) 670 + pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 671 + } 672 + if (io) 673 673 b_res[0].flags |= IORESOURCE_IO; 674 674 /* DECchip 21050 pass 2 errata: the bridge may miss an address 675 675 disconnect boundary by one PCI data phase. ··· 819 819 resource_size_t min_align, align; 820 820 821 821 if (!b_res) 822 - return; 822 + return; 823 823 824 824 min_align = window_alignment(bus, IORESOURCE_IO); 825 825 list_for_each_entry(dev, &bus->devices, bus_list) { ··· 950 950 if (realloc_head && i >= PCI_IOV_RESOURCES && 951 951 i <= PCI_IOV_RESOURCE_END) { 952 952 r->end = r->start - 1; 953 - add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */); 953 + add_to_list(realloc_head, dev, r, r_size, 0/* don't care */); 954 954 children_add_size += r_size; 955 955 continue; 956 956 } ··· 1456 1456 1457 1457 /* 1458 1458 * first try will not touch pci bridge res 1459 - * second and later try will clear small leaf bridge res 1460 - * will stop till to the max deepth if can not find good one 1459 + * second and later try will clear small leaf bridge res 1460 + * will stop till to the max depth if can not find good one 1461 1461 */ 1462 1462 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) 1463 1463 {

+1 -1

drivers/pci/setup-res.c

··· 159 159 return 0; 160 160 } 161 161 162 - static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, 162 + static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, 163 163 int resno, resource_size_t size) 164 164 { 165 165 struct resource *root, *conflict;

+1 -1

drivers/pci/slot.c

··· 53 53 static const char *pci_bus_speed_strings[] = { 54 54 "33 MHz PCI", /* 0x00 */ 55 55 "66 MHz PCI", /* 0x01 */ 56 - "66 MHz PCI-X", /* 0x02 */ 56 + "66 MHz PCI-X", /* 0x02 */ 57 57 "100 MHz PCI-X", /* 0x03 */ 58 58 "133 MHz PCI-X", /* 0x04 */ 59 59 NULL, /* 0x05 */

+1 -1

drivers/pci/syscall.c

··· 44 44 default: 45 45 err = -EINVAL; 46 46 goto error; 47 - }; 47 + } 48 48 49 49 err = -EIO; 50 50 if (cfg_ret != PCIBIOS_SUCCESSFUL)

+5 -5

include/linux/msi.h

··· 26 26 struct { 27 27 __u8 is_msix : 1; 28 28 __u8 multiple: 3; /* log2 number of messages */ 29 - __u8 maskbit : 1; /* mask-pending bit supported ? */ 30 - __u8 is_64 : 1; /* Address size: 0=32bit 1=64bit */ 31 - __u8 pos; /* Location of the msi capability */ 32 - __u16 entry_nr; /* specific enabled entry */ 33 - unsigned default_irq; /* default pre-assigned irq */ 29 + __u8 maskbit : 1; /* mask-pending bit supported ? */ 30 + __u8 is_64 : 1; /* Address size: 0=32bit 1=64bit */ 31 + __u8 pos; /* Location of the msi capability */ 32 + __u16 entry_nr; /* specific enabled entry */ 33 + unsigned default_irq; /* default pre-assigned irq */ 34 34 } msi_attrib; 35 35 36 36 u32 masked; /* mask bits */

+27 -28

include/linux/pci.h

··· 32 32 #include <linux/irqreturn.h> 33 33 #include <uapi/linux/pci.h> 34 34 35 - /* Include the ID list */ 36 35 #include <linux/pci_ids.h> 37 36 38 37 /* ··· 41 42 * 42 43 * 7:3 = slot 43 44 * 2:0 = function 44 - * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined uapi/linux/pci.h 45 + * 46 + * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 45 47 * In the interest of not exposing interfaces to user-space unnecessarily, 46 - * the following kernel only defines are being added here. 48 + * the following kernel-only defines are being added here. 47 49 */ 48 50 #define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn) 49 51 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ ··· 153 153 /* Reset is NOT asserted (Use to deassert reset) */ 154 154 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 155 155 156 - /* Use #PERST to reset PCI-E device */ 156 + /* Use #PERST to reset PCIe device */ 157 157 pcie_warm_reset = (__force pcie_reset_state_t) 2, 158 158 159 - /* Use PCI-E Hot Reset to reset device */ 159 + /* Use PCIe Hot Reset to reset device */ 160 160 pcie_hot_reset = (__force pcie_reset_state_t) 3 161 161 }; 162 162 ··· 259 259 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 260 260 u8 revision; /* PCI revision, low byte of class word */ 261 261 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 262 - u8 pcie_cap; /* PCI-E capability offset */ 262 + u8 pcie_cap; /* PCIe capability offset */ 263 263 u8 msi_cap; /* MSI capability offset */ 264 264 u8 msix_cap; /* MSI-X capability offset */ 265 - u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ 265 + u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 266 266 u8 rom_base_reg; /* which config register controls the ROM */ 267 - u8 pin; /* which interrupt pin this device uses */ 268 - u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */ 267 + u8 pin; /* which interrupt pin this device uses */ 268 + u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 269 269 270 270 struct pci_driver *driver; /* which driver has allocated this device */ 271 271 u64 dma_mask; /* Mask of the bits of bus address this ··· 300 300 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 301 301 302 302 #ifdef CONFIG_PCIEASPM 303 - struct pcie_link_state *link_state; /* ASPM link state. */ 303 + struct pcie_link_state *link_state; /* ASPM link state */ 304 304 #endif 305 305 306 306 pci_channel_state_t error_state; /* current connectivity state */ ··· 317 317 318 318 bool match_driver; /* Skip attaching driver */ 319 319 /* These fields are used by common fixups */ 320 - unsigned int transparent:1; /* Transparent PCI bridge */ 320 + unsigned int transparent:1; /* Subtractive decode PCI bridge */ 321 321 unsigned int multifunction:1;/* Part of multi-function device */ 322 322 /* keep track of device state */ 323 323 unsigned int is_added:1; ··· 326 326 unsigned int block_cfg_access:1; /* config space access is blocked */ 327 327 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 328 328 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 329 - unsigned int msi_enabled:1; 329 + unsigned int msi_enabled:1; 330 330 unsigned int msix_enabled:1; 331 331 unsigned int ari_enabled:1; /* ARI forwarding */ 332 332 unsigned int is_managed:1; ··· 371 371 if (dev->is_virtfn) 372 372 dev = dev->physfn; 373 373 #endif 374 - 375 374 return dev; 376 375 } 377 376 ··· 455 456 char name[48]; 456 457 457 458 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 458 - pci_bus_flags_t bus_flags; /* Inherited by child busses */ 459 + pci_bus_flags_t bus_flags; /* inherited by child buses */ 459 460 struct device *bridge; 460 461 struct device dev; 461 462 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ ··· 467 468 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 468 469 469 470 /* 470 - * Returns true if the pci bus is root (behind host-pci bridge), 471 + * Returns true if the PCI bus is root (behind host-PCI bridge), 471 472 * false otherwise 472 473 * 473 474 * Some code assumes that "bus->self == NULL" means that bus is a root bus. ··· 509 510 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 510 511 511 512 /* 512 - * Translate above to generic errno for passing back through non-pci. 513 + * Translate above to generic errno for passing back through non-PCI code. 513 514 */ 514 515 static inline int pcibios_err_to_errno(int err) 515 516 { ··· 560 561 struct list_head list; /* for IDs added at runtime */ 561 562 }; 562 563 563 - /* ---------------------------------------------------------------- */ 564 - /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 565 - * a set of callbacks in struct pci_error_handlers, then that device driver 566 - * will be notified of PCI bus errors, and will be driven to recovery 567 - * when an error occurs. 564 + 565 + /* 566 + * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 567 + * a set of callbacks in struct pci_error_handlers, that device driver 568 + * will be notified of PCI bus errors, and will be driven to recovery 569 + * when an error occurs. 568 570 */ 569 571 570 572 typedef unsigned int __bitwise pci_ers_result_t; ··· 609 609 void (*resume)(struct pci_dev *dev); 610 610 }; 611 611 612 - /* ---------------------------------------------------------------- */ 613 612 614 613 struct module; 615 614 struct pci_driver { ··· 712 713 713 714 extern struct bus_type pci_bus_type; 714 715 715 - /* Do NOT directly access these two variables, unless you are arch specific pci 716 - * code, or pci core code. */ 716 + /* Do NOT directly access these two variables, unless you are arch-specific PCI 717 + * code, or PCI core code. */ 717 718 extern struct list_head pci_root_buses; /* list of all known PCI buses */ 718 - /* Some device drivers need know if pci is initiated */ 719 + /* Some device drivers need know if PCI is initiated */ 719 720 int no_pci_devices(void); 720 721 721 722 void pcibios_resource_survey_bus(struct pci_bus *bus); ··· 723 724 void pcibios_remove_bus(struct pci_bus *bus); 724 725 void pcibios_fixup_bus(struct pci_bus *); 725 726 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 726 - /* Architecture specific versions may override this (weak) */ 727 + /* Architecture-specific versions may override this (weak) */ 727 728 char *pcibios_setup(char *str); 728 729 729 730 /* Used only when drivers/pci/setup.c is used */ ··· 1257 1258 1258 1259 /* 1259 1260 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 1260 - * a PCI domain is defined to be a set of PCI busses which share 1261 + * a PCI domain is defined to be a set of PCI buses which share 1261 1262 * configuration space. 1262 1263 */ 1263 1264 #ifdef CONFIG_PCI_DOMAINS ··· 1671 1672 extern unsigned long pci_hotplug_io_size; 1672 1673 extern unsigned long pci_hotplug_mem_size; 1673 1674 1674 - /* Architecture specific versions may override these (weak) */ 1675 + /* Architecture-specific versions may override these (weak) */ 1675 1676 int pcibios_add_platform_entries(struct pci_dev *dev); 1676 1677 void pcibios_disable_device(struct pci_dev *dev); 1677 1678 void pcibios_set_master(struct pci_dev *dev);

+2 -3

include/linux/pci_hotplug.h

··· 39 39 * @hardware_test: Called to run a specified hardware test on the specified 40 40 * slot. 41 41 * @get_power_status: Called to get the current power status of a slot. 42 - * If this field is NULL, the value passed in the struct hotplug_slot_info 43 - * will be used when this value is requested by a user. 42 + * If this field is NULL, the value passed in the struct hotplug_slot_info 43 + * will be used when this value is requested by a user. 44 44 * @get_attention_status: Called to get the current attention status of a slot. 45 45 * If this field is NULL, the value passed in the struct hotplug_slot_info 46 46 * will be used when this value is requested by a user. ··· 191 191 192 192 void pci_configure_slot(struct pci_dev *dev); 193 193 #endif 194 -

+1 -1

include/linux/pcieport_if.h

··· 23 23 #define PCIE_PORT_SERVICE_VC (1 << PCIE_PORT_SERVICE_VC_SHIFT) 24 24 25 25 struct pcie_device { 26 - int irq; /* Service IRQ/MSI/MSI-X Vector */ 26 + int irq; /* Service IRQ/MSI/MSI-X Vector */ 27 27 struct pci_dev *port; /* Root/Upstream/Downstream Port */ 28 28 u32 service; /* Port service this device represents */ 29 29 void *priv_data; /* Service Private Data */

+36 -36

include/uapi/linux/pci_regs.h

··· 13 13 * PCI to PCI Bridge Specification 14 14 * PCI System Design Guide 15 15 * 16 - * For hypertransport information, please consult the following manuals 17 - * from http://www.hypertransport.org 16 + * For HyperTransport information, please consult the following manuals 17 + * from http://www.hypertransport.org 18 18 * 19 - * The Hypertransport I/O Link Specification 19 + * The HyperTransport I/O Link Specification 20 20 */ 21 21 22 22 #ifndef LINUX_PCI_REGS_H ··· 37 37 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 38 38 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 39 39 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 40 - #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 40 + #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 41 41 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 42 42 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 43 43 #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ ··· 45 45 #define PCI_STATUS 0x06 /* 16 bits */ 46 46 #define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ 47 47 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 48 - #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 48 + #define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */ 49 49 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 50 50 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 51 51 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ ··· 205 205 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 206 206 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ 207 207 #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ 208 - #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ 208 + #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */ 209 209 #define PCI_CAP_ID_DBG 0x0A /* Debug port */ 210 210 #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ 211 - #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ 211 + #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ 212 212 #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ 213 213 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ 214 214 #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ 215 - #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 215 + #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 216 216 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ 217 217 #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ 218 218 #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ ··· 268 268 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 269 269 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 270 270 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 271 - #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 272 - #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 271 + #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 272 + #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 273 273 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 274 274 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ 275 275 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ ··· 321 321 #define PCI_MSIX_PBA_OFFSET 0xfffffff8 /* Offset into specified BAR */ 322 322 #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ 323 323 324 - /* MSI-X entry's format */ 324 + /* MSI-X Table entry format */ 325 325 #define PCI_MSIX_ENTRY_SIZE 16 326 326 #define PCI_MSIX_ENTRY_LOWER_ADDR 0 327 327 #define PCI_MSIX_ENTRY_UPPER_ADDR 4 ··· 372 372 #define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */ 373 373 #define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */ 374 374 #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ 375 - #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 375 + #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 376 376 #define PCI_X_STATUS 4 /* PCI-X capabilities */ 377 377 #define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */ 378 378 #define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ ··· 407 407 408 408 /* PCI Bridge Subsystem ID registers */ 409 409 410 - #define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */ 411 - #define PCI_SSVID_DEVICE_ID 6 /* PCI-Bridge subsystem device id register */ 410 + #define PCI_SSVID_VENDOR_ID 4 /* PCI Bridge subsystem vendor ID */ 411 + #define PCI_SSVID_DEVICE_ID 6 /* PCI Bridge subsystem device ID */ 412 412 413 413 /* PCI Express capability registers */ 414 414 ··· 484 484 #define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */ 485 485 #define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */ 486 486 #define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */ 487 - #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */ 487 + #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Link Autonomous Bandwidth Interrupt Enable */ 488 488 #define PCI_EXP_LNKSTA 18 /* Link Status */ 489 489 #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ 490 490 #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ 491 491 #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ 492 - #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */ 492 + #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ 493 493 #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ 494 494 #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ 495 495 #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ ··· 593 593 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ 594 594 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ 595 595 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ 596 - #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor Specific */ 596 + #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ 597 597 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ 598 598 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ 599 599 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ ··· 602 602 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ 603 603 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ 604 604 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ 605 - #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* reserved for AMD */ 606 - #define PCI_EXT_CAP_ID_REBAR 0x15 /* resizable BAR */ 607 - #define PCI_EXT_CAP_ID_DPA 0x16 /* dynamic power alloc */ 608 - #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH request */ 609 - #define PCI_EXT_CAP_ID_LTR 0x18 /* latency tolerance reporting */ 610 - #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe */ 605 + #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ 606 + #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ 607 + #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ 608 + #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ 609 + #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ 610 + #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ 611 611 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ 612 612 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ 613 613 #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID ··· 667 667 #define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ 668 668 /* Multi ERR_COR Received */ 669 669 #define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 670 - /* ERR_FATAL/NONFATAL Recevied */ 670 + /* ERR_FATAL/NONFATAL Received */ 671 671 #define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 672 - /* Multi ERR_FATAL/NONFATAL Recevied */ 672 + /* Multi ERR_FATAL/NONFATAL Received */ 673 673 #define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 674 674 #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */ 675 675 #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ ··· 678 678 679 679 /* Virtual Channel */ 680 680 #define PCI_VC_PORT_REG1 4 681 - #define PCI_VC_REG1_EVCC 0x7 /* extended vc count */ 681 + #define PCI_VC_REG1_EVCC 0x7 /* extended VC count */ 682 682 #define PCI_VC_PORT_REG2 8 683 683 #define PCI_VC_REG2_32_PHASE 0x2 684 684 #define PCI_VC_REG2_64_PHASE 0x4 ··· 711 711 #define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) 712 712 713 713 /* 714 - * Hypertransport sub capability types 714 + * HyperTransport sub capability types 715 715 * 716 716 * Unfortunately there are both 3 bit and 5 bit capability types defined 717 717 * in the HT spec, catering for that is a little messy. You probably don't ··· 739 739 #define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */ 740 740 #define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */ 741 741 #define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ 742 - #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */ 743 - #define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */ 742 + #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 HyperTransport configuration */ 743 + #define HT_CAPTYPE_PM 0xE0 /* HyperTransport power management configuration */ 744 744 #define HT_CAP_SIZEOF_LONG 28 /* slave & primary */ 745 745 #define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */ 746 746 ··· 777 777 #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ 778 778 #define PCI_EXT_CAP_PRI_SIZEOF 16 779 779 780 - /* PASID capability */ 780 + /* Process Address Space ID */ 781 781 #define PCI_PASID_CAP 0x04 /* PASID feature register */ 782 782 #define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ 783 - #define PCI_PASID_CAP_PRIV 0x04 /* Priviledge Mode Supported */ 783 + #define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ 784 784 #define PCI_PASID_CTRL 0x06 /* PASID control register */ 785 785 #define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ 786 786 #define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ 787 - #define PCI_PASID_CTRL_PRIV 0x04 /* Priviledge Mode Enable */ 787 + #define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ 788 788 #define PCI_EXT_CAP_PASID_SIZEOF 8 789 789 790 790 /* Single Root I/O Virtualization */ ··· 839 839 #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ 840 840 #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ 841 841 842 - #define PCI_VSEC_HDR 4 /* extended cap - vendor specific */ 842 + #define PCI_VSEC_HDR 4 /* extended cap - vendor-specific */ 843 843 #define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */ 844 844 845 - /* sata capability */ 845 + /* SATA capability */ 846 846 #define PCI_SATA_REGS 4 /* SATA REGs specifier */ 847 847 #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */ 848 848 #define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */ 849 849 #define PCI_SATA_SIZEOF_SHORT 8 850 850 #define PCI_SATA_SIZEOF_LONG 16 851 851 852 - /* resizable BARs */ 852 + /* Resizable BARs */ 853 853 #define PCI_REBAR_CTRL 8 /* control register */ 854 854 #define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */ 855 855 #define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */ 856 856 857 - /* dynamic power allocation */ 857 + /* Dynamic Power Allocation */ 858 858 #define PCI_DPA_CAP 4 /* capability register */ 859 859 #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */ 860 860 #define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */

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