Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2022-10-28' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Regularly scheduled fixes for drm, live from a Red Hat office for the
first time in a while.
The core has two fixes, one for scheduler leak and one for aperture
uninit read.
Otherwise a single bridge fix, and msm, amdgpu/kfd and i915 have a set
of fixes each.
sched:
- Stop leaking fences when killing a sched entity.
aperture:
- Avoid uninitialized read in aperture_remove_conflicting_pci_device()
bridge:
- Fix HPD on bridge/ps8640.
msm:
- Fix shrinker deadlock
- Fix crash during suspend after unbind
- Fix IRQ lifetime issues
- Fix potential memory corruption with too many bridges
- Fix memory corruption on GPU state capture
amdgpu:
- Stable pstate fix
- SMU 13.x updates
- SR-IOV fixes
- PCI AER fix
- GC 11.x fixes
- Display fixes
- Expose IMU firmware version for debugging
- Plane modifier fix
- S0i3 fix
amdkfd:
- Fix possible memory leak
- Fix GC 10.x cache info reporting
i915:
- Extend Wa_1607297627 to Alderlake-P
- Keep PCI autosuspend control 'on' by default on all dGPU
- Reset frl trained flag before restarting FRL training"
* tag 'drm-fixes-2022-10-28' of git://anongit.freedesktop.org/drm/drm: (39 commits)
fbdev/core: Avoid uninitialized read in aperture_remove_conflicting_pci_device()
drm/amdgpu: disallow gfxoff until GC IP blocks complete s2idle resume
drm/scheduler: fix fence ref counting
drm/amd/display: Revert logic for plane modifiers
drm/amdkfd: correct the cache info for gfx1036
drm/amdkfd: update gfx1037 Lx cache setting
drm/amdgpu: skip mes self test for gc 11.0.3 in recover
drm/amd: Add IMU fw version to fw version queries
drm/amd/display: Don't return false if no stream
drm/amd/display: Remove wrong pipe control lock
drm/amd/pm: allow gfxoff on gc_11_0_3
drm/amdkfd: Fix memory leak in kfd_mem_dmamap_userptr()
drm/amdgpu: Remove ATC L2 access for MMHUB 2.1.x
drm/i915/dp: Reset frl trained flag before restarting FRL training
drm/i915/dgfx: Keep PCI autosuspend control 'on' by default on all dGPU
drm/i915: Extend Wa_1607297627 to Alderlake-P
drm/amdgpu: Adjust MES polling timeout for sriov
drm/amd/pm: update driver-if header for smu_v13_0_10
drm/amdgpu: fix pstate setting issue
drm/bridge: ps8640: Add back the 50 ms mystery delay after HPD
...
+421
-161
+3
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+3
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
···
510
510
struct ttm_tt *ttm = bo->tbo.ttm;
511
511
int ret;
512
512
513
+
if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
514
+
return -EINVAL;
515
+
513
516
ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
514
517
if (unlikely(!ttm->sg))
515
518
return -ENOMEM;
516
-
517
-
if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
518
-
return -EINVAL;
519
519
520
520
/* Same sequence as in amdgpu_ttm_tt_pin_userptr */
521
521
ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
+4
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+4
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
···
326
326
if (r)
327
327
return r;
328
328
329
-
ctx->stable_pstate = current_stable_pstate;
329
+
if (mgr->adev->pm.stable_pstate_ctx)
330
+
ctx->stable_pstate = mgr->adev->pm.stable_pstate_ctx->stable_pstate;
331
+
else
332
+
ctx->stable_pstate = current_stable_pstate;
330
333
331
334
return 0;
332
335
}
+17
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+17
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
3210
3210
return r;
3211
3211
}
3212
3212
adev->ip_blocks[i].status.hw = true;
3213
+
3214
+
if (adev->in_s0ix && adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3215
+
/* disable gfxoff for IP resume. The gfxoff will be re-enabled in
3216
+
* amdgpu_device_resume() after IP resume.
3217
+
*/
3218
+
amdgpu_gfx_off_ctrl(adev, false);
3219
+
DRM_DEBUG("will disable gfxoff for re-initializing other blocks\n");
3220
+
}
3221
+
3213
3222
}
3214
3223
3215
3224
return 0;
···
4194
4185
/* Make sure IB tests flushed */
4195
4186
flush_delayed_work(&adev->delayed_init_work);
4196
4187
4188
+
if (adev->in_s0ix) {
4189
+
/* re-enable gfxoff after IP resume. This re-enables gfxoff after
4190
+
* it was disabled for IP resume in amdgpu_device_ip_resume_phase2().
4191
+
*/
4192
+
amdgpu_gfx_off_ctrl(adev, true);
4193
+
DRM_DEBUG("will enable gfxoff for the mission mode\n");
4194
+
}
4197
4195
if (fbcon)
4198
4196
drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
4199
4197
···
5397
5381
drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
5398
5382
}
5399
5383
5400
-
if (adev->enable_mes)
5384
+
if (adev->enable_mes && adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))
5401
5385
amdgpu_mes_self_test(tmp_adev);
5402
5386
5403
5387
if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) {
+13
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+13
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
···
344
344
fw_info->ver = adev->mes.ucode_fw_version[1];
345
345
fw_info->feature = 0;
346
346
break;
347
+
case AMDGPU_INFO_FW_IMU:
348
+
fw_info->ver = adev->gfx.imu_fw_version;
349
+
fw_info->feature = 0;
350
+
break;
347
351
default:
348
352
return -EINVAL;
349
353
}
···
1523
1519
seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1524
1520
fw_info.feature, fw_info.ver);
1525
1521
}
1522
+
1523
+
/* IMU */
1524
+
query_fw.fw_type = AMDGPU_INFO_FW_IMU;
1525
+
query_fw.index = 0;
1526
+
ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1527
+
if (ret)
1528
+
return ret;
1529
+
seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",
1530
+
fw_info.feature, fw_info.ver);
1526
1531
1527
1532
/* PSP SOS */
1528
1533
query_fw.fw_type = AMDGPU_INFO_FW_SOS;
+3
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+3
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
···
698
698
FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
699
699
FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
700
700
FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
701
+
FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version);
701
702
FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version);
702
703
FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version);
703
704
FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version);
···
720
719
&dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
721
720
&dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
722
721
&dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
723
-
&dev_attr_dmcu_fw_version.attr, NULL
722
+
&dev_attr_dmcu_fw_version.attr, &dev_attr_imu_fw_version.attr,
723
+
NULL
724
724
};
725
725
726
726
static const struct attribute_group fw_attr_group = {
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
···
547
547
POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version);
548
548
POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version);
549
549
POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version);
550
+
POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_IMU, adev->gfx.imu_fw_version);
550
551
POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version);
551
552
POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD,
552
553
adev->psp.asd_context.bin_desc.fw_version);
+1
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
+1
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
+1
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+1
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+8
-1
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+8
-1
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
···
98
98
struct amdgpu_device *adev = mes->adev;
99
99
struct amdgpu_ring *ring = &mes->ring;
100
100
unsigned long flags;
101
+
signed long timeout = adev->usec_timeout;
101
102
103
+
if (amdgpu_emu_mode) {
104
+
timeout *= 100;
105
+
} else if (amdgpu_sriov_vf(adev)) {
106
+
/* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
107
+
timeout = 15 * 600 * 1000;
108
+
}
102
109
BUG_ON(size % 4 != 0);
103
110
104
111
spin_lock_irqsave(&mes->ring_lock, flags);
···
125
118
DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode);
126
119
127
120
r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq,
128
-
adev->usec_timeout * (amdgpu_emu_mode ? 100 : 1));
121
+
timeout);
129
122
if (r < 1) {
130
123
DRM_ERROR("MES failed to response msg=%d\n",
131
124
x_pkt->header.opcode);
+8
-20
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+8
-20
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
···
32
32
#include "gc/gc_10_1_0_offset.h"
33
33
#include "soc15_common.h"
34
34
35
-
#define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid 0x064d
36
-
#define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid_BASE_IDX 0
37
35
#define mmDAGB0_CNTL_MISC2_Sienna_Cichlid 0x0070
38
36
#define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX 0
39
37
···
572
574
case IP_VERSION(2, 1, 0):
573
575
case IP_VERSION(2, 1, 1):
574
576
case IP_VERSION(2, 1, 2):
575
-
def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
576
577
def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
577
578
break;
578
579
default:
···
605
608
case IP_VERSION(2, 1, 0):
606
609
case IP_VERSION(2, 1, 1):
607
610
case IP_VERSION(2, 1, 2):
608
-
if (def != data)
609
-
WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
610
611
if (def1 != data1)
611
612
WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid, data1);
612
613
break;
···
629
634
case IP_VERSION(2, 1, 0):
630
635
case IP_VERSION(2, 1, 1):
631
636
case IP_VERSION(2, 1, 2):
632
-
def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
633
-
break;
637
+
/* There is no ATCL2 in MMHUB for 2.1.x */
638
+
return;
634
639
default:
635
640
def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
636
641
break;
···
641
646
else
642
647
data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
643
648
644
-
if (def != data) {
645
-
switch (adev->ip_versions[MMHUB_HWIP][0]) {
646
-
case IP_VERSION(2, 1, 0):
647
-
case IP_VERSION(2, 1, 1):
648
-
case IP_VERSION(2, 1, 2):
649
-
WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
650
-
break;
651
-
default:
652
-
WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
653
-
break;
654
-
}
655
-
}
649
+
if (def != data)
650
+
WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
656
651
}
657
652
658
653
static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
···
680
695
case IP_VERSION(2, 1, 0):
681
696
case IP_VERSION(2, 1, 1):
682
697
case IP_VERSION(2, 1, 2):
683
-
data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
698
+
/* There is no ATCL2 in MMHUB for 2.1.x. Keep the status
699
+
* based on DAGB
700
+
*/
701
+
data = MM_ATC_L2_MISC_CG__ENABLE_MASK;
684
702
data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
685
703
break;
686
704
default:
+104
-2
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+104
-2
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
···
795
795
},
796
796
};
797
797
798
+
static struct kfd_gpu_cache_info gfx1037_cache_info[] = {
799
+
{
800
+
/* TCP L1 Cache per CU */
801
+
.cache_size = 16,
802
+
.cache_level = 1,
803
+
.flags = (CRAT_CACHE_FLAGS_ENABLED |
804
+
CRAT_CACHE_FLAGS_DATA_CACHE |
805
+
CRAT_CACHE_FLAGS_SIMD_CACHE),
806
+
.num_cu_shared = 1,
807
+
},
808
+
{
809
+
/* Scalar L1 Instruction Cache per SQC */
810
+
.cache_size = 32,
811
+
.cache_level = 1,
812
+
.flags = (CRAT_CACHE_FLAGS_ENABLED |
813
+
CRAT_CACHE_FLAGS_INST_CACHE |
814
+
CRAT_CACHE_FLAGS_SIMD_CACHE),
815
+
.num_cu_shared = 2,
816
+
},
817
+
{
818
+
/* Scalar L1 Data Cache per SQC */
819
+
.cache_size = 16,
820
+
.cache_level = 1,
821
+
.flags = (CRAT_CACHE_FLAGS_ENABLED |
822
+
CRAT_CACHE_FLAGS_DATA_CACHE |
823
+
CRAT_CACHE_FLAGS_SIMD_CACHE),
824
+
.num_cu_shared = 2,
825
+
},
826
+
{
827
+
/* GL1 Data Cache per SA */
828
+
.cache_size = 128,
829
+
.cache_level = 1,
830
+
.flags = (CRAT_CACHE_FLAGS_ENABLED |
831
+
CRAT_CACHE_FLAGS_DATA_CACHE |
832
+
CRAT_CACHE_FLAGS_SIMD_CACHE),
833
+
.num_cu_shared = 2,
834
+
},
835
+
{
836
+
/* L2 Data Cache per GPU (Total Tex Cache) */
837
+
.cache_size = 256,
838
+
.cache_level = 2,
839
+
.flags = (CRAT_CACHE_FLAGS_ENABLED |
840
+
CRAT_CACHE_FLAGS_DATA_CACHE |
841
+
CRAT_CACHE_FLAGS_SIMD_CACHE),
842
+
.num_cu_shared = 2,
843
+
},
844
+
};
845
+
846
+
static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = {
847
+
{
848
+
/* TCP L1 Cache per CU */
849
+
.cache_size = 16,
850
+
.cache_level = 1,
851
+
.flags = (CRAT_CACHE_FLAGS_ENABLED |
852
+
CRAT_CACHE_FLAGS_DATA_CACHE |
853
+
CRAT_CACHE_FLAGS_SIMD_CACHE),
854
+
.num_cu_shared = 1,
855
+
},
856
+
{
857
+
/* Scalar L1 Instruction Cache per SQC */
858
+
.cache_size = 32,
859
+
.cache_level = 1,
860
+
.flags = (CRAT_CACHE_FLAGS_ENABLED |
861
+
CRAT_CACHE_FLAGS_INST_CACHE |
862
+
CRAT_CACHE_FLAGS_SIMD_CACHE),
863
+
.num_cu_shared = 2,
864
+
},
865
+
{
866
+
/* Scalar L1 Data Cache per SQC */
867
+
.cache_size = 16,
868
+
.cache_level = 1,
869
+
.flags = (CRAT_CACHE_FLAGS_ENABLED |
870
+
CRAT_CACHE_FLAGS_DATA_CACHE |
871
+
CRAT_CACHE_FLAGS_SIMD_CACHE),
872
+
.num_cu_shared = 2,
873
+
},
874
+
{
875
+
/* GL1 Data Cache per SA */
876
+
.cache_size = 128,
877
+
.cache_level = 1,
878
+
.flags = (CRAT_CACHE_FLAGS_ENABLED |
879
+
CRAT_CACHE_FLAGS_DATA_CACHE |
880
+
CRAT_CACHE_FLAGS_SIMD_CACHE),
881
+
.num_cu_shared = 2,
882
+
},
883
+
{
884
+
/* L2 Data Cache per GPU (Total Tex Cache) */
885
+
.cache_size = 256,
886
+
.cache_level = 2,
887
+
.flags = (CRAT_CACHE_FLAGS_ENABLED |
888
+
CRAT_CACHE_FLAGS_DATA_CACHE |
889
+
CRAT_CACHE_FLAGS_SIMD_CACHE),
890
+
.num_cu_shared = 2,
891
+
},
892
+
};
893
+
798
894
static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
799
895
struct crat_subtype_computeunit *cu)
800
896
{
···
1610
1514
num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
1611
1515
break;
1612
1516
case IP_VERSION(10, 3, 3):
1613
-
case IP_VERSION(10, 3, 6): /* TODO: Double check these on production silicon */
1614
-
case IP_VERSION(10, 3, 7): /* TODO: Double check these on production silicon */
1615
1517
pcache_info = yellow_carp_cache_info;
1616
1518
num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
1519
+
break;
1520
+
case IP_VERSION(10, 3, 6):
1521
+
pcache_info = gc_10_3_6_cache_info;
1522
+
num_of_cache_types = ARRAY_SIZE(gc_10_3_6_cache_info);
1523
+
break;
1524
+
case IP_VERSION(10, 3, 7):
1525
+
pcache_info = gfx1037_cache_info;
1526
+
num_of_cache_types = ARRAY_SIZE(gfx1037_cache_info);
1617
1527
break;
1618
1528
case IP_VERSION(11, 0, 0):
1619
1529
case IP_VERSION(11, 0, 1):
+7
-43
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+7
-43
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
···
1369
1369
{
1370
1370
struct amdgpu_device *adev = drm_to_adev(plane->dev);
1371
1371
const struct drm_format_info *info = drm_format_info(format);
1372
-
struct hw_asic_id asic_id = adev->dm.dc->ctx->asic_id;
1372
+
int i;
1373
1373
1374
1374
enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3;
1375
1375
···
1386
1386
return true;
1387
1387
}
1388
1388
1389
-
/* check if swizzle mode is supported by this version of DCN */
1390
-
switch (asic_id.chip_family) {
1391
-
case FAMILY_SI:
1392
-
case FAMILY_CI:
1393
-
case FAMILY_KV:
1394
-
case FAMILY_CZ:
1395
-
case FAMILY_VI:
1396
-
/* asics before AI does not have modifier support */
1397
-
return false;
1398
-
case FAMILY_AI:
1399
-
case FAMILY_RV:
1400
-
case FAMILY_NV:
1401
-
case FAMILY_VGH:
1402
-
case FAMILY_YELLOW_CARP:
1403
-
case AMDGPU_FAMILY_GC_10_3_6:
1404
-
case AMDGPU_FAMILY_GC_10_3_7:
1405
-
switch (AMD_FMT_MOD_GET(TILE, modifier)) {
1406
-
case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
1407
-
case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
1408
-
case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
1409
-
case AMD_FMT_MOD_TILE_GFX9_64K_D:
1410
-
return true;
1411
-
default:
1412
-
return false;
1413
-
}
1414
-
break;
1415
-
case AMDGPU_FAMILY_GC_11_0_0:
1416
-
case AMDGPU_FAMILY_GC_11_0_1:
1417
-
switch (AMD_FMT_MOD_GET(TILE, modifier)) {
1418
-
case AMD_FMT_MOD_TILE_GFX11_256K_R_X:
1419
-
case AMD_FMT_MOD_TILE_GFX9_64K_R_X:
1420
-
case AMD_FMT_MOD_TILE_GFX9_64K_D_X:
1421
-
case AMD_FMT_MOD_TILE_GFX9_64K_S_X:
1422
-
case AMD_FMT_MOD_TILE_GFX9_64K_D:
1423
-
return true;
1424
-
default:
1425
-
return false;
1426
-
}
1427
-
break;
1428
-
default:
1429
-
ASSERT(0); /* Unknown asic */
1430
-
break;
1389
+
/* Check that the modifier is on the list of the plane's supported modifiers. */
1390
+
for (i = 0; i < plane->modifier_count; i++) {
1391
+
if (modifier == plane->modifiers[i])
1392
+
break;
1431
1393
}
1394
+
if (i == plane->modifier_count)
1395
+
return false;
1432
1396
1433
1397
/*
1434
1398
* For D swizzle the canonical modifier depends on the bpp, so check
+1
-11
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+1
-11
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
···
1270
1270
lock,
1271
1271
&hw_locks,
1272
1272
&inst_flags);
1273
-
} else if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
1274
-
union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
1275
-
hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
1276
-
hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
1277
-
hw_lock_cmd.bits.lock_pipe = 1;
1278
-
hw_lock_cmd.bits.otg_inst = pipe->stream_res.tg->inst;
1279
-
hw_lock_cmd.bits.lock = lock;
1280
-
if (!lock)
1281
-
hw_lock_cmd.bits.should_release = 1;
1282
-
dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
1283
1273
} else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1284
1274
if (lock)
1285
1275
pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
···
1846
1856
1847
1857
for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
1848
1858
&& hubp->funcs->hubp_is_flip_pending(hubp); j++)
1849
-
mdelay(1);
1859
+
udelay(1);
1850
1860
}
1851
1861
}
1852
1862
+1
-1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+1
-1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
+81
-30
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
+81
-30
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h
···
25
25
#define SMU13_DRIVER_IF_V13_0_0_H
26
26
27
27
//Increment this version if SkuTable_t or BoardTable_t change
28
-
#define PPTABLE_VERSION 0x24
28
+
#define PPTABLE_VERSION 0x26
29
29
30
30
#define NUM_GFXCLK_DPM_LEVELS 16
31
31
#define NUM_SOCCLK_DPM_LEVELS 8
···
109
109
#define FEATURE_SPARE_63_BIT 63
110
110
#define NUM_FEATURES 64
111
111
112
+
#define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL
113
+
#define ALLOWED_FEATURE_CTRL_SCPM ((1 << FEATURE_DPM_GFXCLK_BIT) | \
114
+
(1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \
115
+
(1 << FEATURE_DPM_UCLK_BIT) | \
116
+
(1 << FEATURE_DPM_FCLK_BIT) | \
117
+
(1 << FEATURE_DPM_SOCCLK_BIT) | \
118
+
(1 << FEATURE_DPM_MP0CLK_BIT) | \
119
+
(1 << FEATURE_DPM_LINK_BIT) | \
120
+
(1 << FEATURE_DPM_DCN_BIT) | \
121
+
(1 << FEATURE_DS_GFXCLK_BIT) | \
122
+
(1 << FEATURE_DS_SOCCLK_BIT) | \
123
+
(1 << FEATURE_DS_FCLK_BIT) | \
124
+
(1 << FEATURE_DS_LCLK_BIT) | \
125
+
(1 << FEATURE_DS_DCFCLK_BIT) | \
126
+
(1 << FEATURE_DS_UCLK_BIT))
127
+
112
128
//For use with feature control messages
113
129
typedef enum {
114
130
FEATURE_PWR_ALL,
···
149
133
#define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200
150
134
#define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400
151
135
#define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800
136
+
#define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE 0x00001000
152
137
153
138
// VR Mapping Bit Defines
154
139
#define VR_MAPPING_VR_SELECT_MASK 0x01
···
279
262
} I2cControllerPort_e;
280
263
281
264
typedef enum {
282
-
I2C_CONTROLLER_NAME_VR_GFX = 0,
283
-
I2C_CONTROLLER_NAME_VR_SOC,
284
-
I2C_CONTROLLER_NAME_VR_VMEMP,
285
-
I2C_CONTROLLER_NAME_VR_VDDIO,
286
-
I2C_CONTROLLER_NAME_LIQUID0,
287
-
I2C_CONTROLLER_NAME_LIQUID1,
288
-
I2C_CONTROLLER_NAME_PLX,
289
-
I2C_CONTROLLER_NAME_OTHER,
290
-
I2C_CONTROLLER_NAME_COUNT,
265
+
I2C_CONTROLLER_NAME_VR_GFX = 0,
266
+
I2C_CONTROLLER_NAME_VR_SOC,
267
+
I2C_CONTROLLER_NAME_VR_VMEMP,
268
+
I2C_CONTROLLER_NAME_VR_VDDIO,
269
+
I2C_CONTROLLER_NAME_LIQUID0,
270
+
I2C_CONTROLLER_NAME_LIQUID1,
271
+
I2C_CONTROLLER_NAME_PLX,
272
+
I2C_CONTROLLER_NAME_FAN_INTAKE,
273
+
I2C_CONTROLLER_NAME_COUNT,
291
274
} I2cControllerName_e;
292
275
293
276
typedef enum {
···
299
282
I2C_CONTROLLER_THROTTLER_LIQUID0,
300
283
I2C_CONTROLLER_THROTTLER_LIQUID1,
301
284
I2C_CONTROLLER_THROTTLER_PLX,
285
+
I2C_CONTROLLER_THROTTLER_FAN_INTAKE,
302
286
I2C_CONTROLLER_THROTTLER_INA3221,
303
287
I2C_CONTROLLER_THROTTLER_COUNT,
304
288
} I2cControllerThrottler_e;
305
289
306
290
typedef enum {
307
-
I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5,
308
-
I2C_CONTROLLER_PROTOCOL_VR_IR35217,
309
-
I2C_CONTROLLER_PROTOCOL_TMP_TMP102A,
310
-
I2C_CONTROLLER_PROTOCOL_INA3221,
311
-
I2C_CONTROLLER_PROTOCOL_COUNT,
291
+
I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5,
292
+
I2C_CONTROLLER_PROTOCOL_VR_IR35217,
293
+
I2C_CONTROLLER_PROTOCOL_TMP_MAX31875,
294
+
I2C_CONTROLLER_PROTOCOL_INA3221,
295
+
I2C_CONTROLLER_PROTOCOL_COUNT,
312
296
} I2cControllerProtocol_e;
313
297
314
298
typedef struct {
···
676
658
677
659
#define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1
678
660
661
+
typedef enum {
662
+
FAN_MODE_AUTO = 0,
663
+
FAN_MODE_MANUAL_LINEAR,
664
+
} FanMode_e;
679
665
680
666
typedef struct {
681
667
uint32_t FeatureCtrlMask;
682
668
683
669
//Voltage control
684
670
int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS];
685
-
uint16_t reserved[2];
671
+
uint16_t VddGfxVmax; // in mV
672
+
673
+
uint8_t IdlePwrSavingFeaturesCtrl;
674
+
uint8_t RuntimePwrSavingFeaturesCtrl;
686
675
687
676
//Frequency changes
688
677
int16_t GfxclkFmin; // MHz
···
699
674
700
675
//PPT
701
676
int16_t Ppt; // %
702
-
int16_t reserved1;
677
+
int16_t Tdc;
703
678
704
679
//Fan control
705
680
uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
···
726
701
uint32_t FeatureCtrlMask;
727
702
728
703
int16_t VoltageOffsetPerZoneBoundary;
729
-
uint16_t reserved[2];
704
+
uint16_t VddGfxVmax; // in mV
730
705
731
-
uint16_t GfxclkFmin; // MHz
732
-
uint16_t GfxclkFmax; // MHz
706
+
uint8_t IdlePwrSavingFeaturesCtrl;
707
+
uint8_t RuntimePwrSavingFeaturesCtrl;
708
+
709
+
int16_t GfxclkFmin; // MHz
710
+
int16_t GfxclkFmax; // MHz
733
711
uint16_t UclkFmin; // MHz
734
712
uint16_t UclkFmax; // MHz
735
713
736
714
//PPT
737
715
int16_t Ppt; // %
738
-
int16_t reserved1;
716
+
int16_t Tdc;
739
717
740
718
uint8_t FanLinearPwmPoints;
741
719
uint8_t FanLinearTempPoints;
···
885
857
uint16_t FanStartTempMin;
886
858
uint16_t FanStartTempMax;
887
859
888
-
uint32_t Spare[12];
860
+
uint16_t PowerMinPpt0[POWER_SOURCE_COUNT];
861
+
uint32_t Spare[11];
889
862
890
863
} MsgLimits_t;
891
864
···
1070
1041
uint32_t GfxoffSpare[15];
1071
1042
1072
1043
// GFX GPO
1073
-
uint32_t GfxGpoSpare[16];
1044
+
uint32_t DfllBtcMasterScalerM;
1045
+
int32_t DfllBtcMasterScalerB;
1046
+
uint32_t DfllBtcSlaveScalerM;
1047
+
int32_t DfllBtcSlaveScalerB;
1048
+
1049
+
uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg
1050
+
uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg
1051
+
1052
+
uint32_t DfllL2FrequencyBoostM; //Unitless (float)
1053
+
uint32_t DfllL2FrequencyBoostB; //In MHz (integer)
1054
+
uint32_t GfxGpoSpare[8];
1074
1055
1075
1056
// GFX DCS
1076
1057
···
1153
1114
uint16_t IntakeTempHighIntakeAcousticLimit;
1154
1115
uint16_t IntakeTempAcouticLimitReleaseRate;
1155
1116
1156
-
uint16_t FanStalledTempLimitOffset;
1117
+
int16_t FanAbnormalTempLimitOffset;
1157
1118
uint16_t FanStalledTriggerRpm;
1158
-
uint16_t FanAbnormalTriggerRpm;
1159
-
uint16_t FanPadding;
1119
+
uint16_t FanAbnormalTriggerRpmCoeff;
1120
+
uint16_t FanAbnormalDetectionEnable;
1160
1121
1161
-
uint32_t FanSpare[14];
1122
+
uint8_t FanIntakeSensorSupport;
1123
+
uint8_t FanIntakePadding[3];
1124
+
uint32_t FanSpare[13];
1162
1125
1163
1126
// SECTION: VDD_GFX AVFS
1164
1127
···
1239
1198
int16_t TotalBoardPowerM;
1240
1199
int16_t TotalBoardPowerB;
1241
1200
1201
+
//PMFW-11158
1202
+
QuadraticInt_t qFeffCoeffGameClock[POWER_SOURCE_COUNT];
1203
+
QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT];
1204
+
QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT];
1205
+
1242
1206
// SECTION: Sku Reserved
1243
-
uint32_t Spare[61];
1207
+
uint32_t Spare[43];
1244
1208
1245
1209
// Padding for MMHUB - do not modify this
1246
1210
uint32_t MmHubPadding[8];
···
1334
1288
uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued
1335
1289
uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS
1336
1290
1291
+
uint8_t FuseWritePowerMuxPresent;
1292
+
uint8_t FuseWritePadding[3];
1293
+
1337
1294
// SECTION: Board Reserved
1338
-
uint32_t BoardSpare[64];
1295
+
uint32_t BoardSpare[63];
1339
1296
1340
1297
// SECTION: Structure Padding
1341
1298
···
1430
1381
uint16_t AverageTotalBoardPower;
1431
1382
1432
1383
uint16_t AvgTemperature[TEMP_COUNT];
1433
-
uint16_t TempPadding;
1384
+
uint16_t AvgTemperatureFanIntake;
1434
1385
1435
1386
uint8_t PcieRate ;
1436
1387
uint8_t PcieWidth ;
···
1599
1550
#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5
1600
1551
#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6
1601
1552
#define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7
1553
+
#define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8
1554
+
#define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9
1602
1555
1603
1556
#endif
+1
-1
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+1
-1
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
···
30
30
#define SMU13_DRIVER_IF_VERSION_ALDE 0x08
31
31
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x07
32
32
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04
33
-
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x30
33
+
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10 0x32
34
34
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x2C
35
35
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_10 0x1D
36
36
+3
-4
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+3
-4
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
···
289
289
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;
290
290
break;
291
291
case IP_VERSION(13, 0, 0):
292
-
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0;
292
+
case IP_VERSION(13, 0, 10):
293
+
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10;
293
294
break;
294
295
case IP_VERSION(13, 0, 7):
295
296
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_7;
···
305
304
break;
306
305
case IP_VERSION(13, 0, 5):
307
306
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_5;
308
-
break;
309
-
case IP_VERSION(13, 0, 10):
310
-
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_10;
311
307
break;
312
308
default:
313
309
dev_err(adev->dev, "smu unsupported IP version: 0x%x.\n",
···
840
842
case IP_VERSION(13, 0, 5):
841
843
case IP_VERSION(13, 0, 7):
842
844
case IP_VERSION(13, 0, 8):
845
+
case IP_VERSION(13, 0, 10):
843
846
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
844
847
return 0;
845
848
if (enable)
+23
-2
drivers/gpu/drm/bridge/parade-ps8640.c
+23
-2
drivers/gpu/drm/bridge/parade-ps8640.c
···
105
105
struct gpio_desc *gpio_powerdown;
106
106
struct device_link *link;
107
107
bool pre_enabled;
108
+
bool need_post_hpd_delay;
108
109
};
109
110
110
111
static const struct regmap_config ps8640_regmap_config[] = {
···
174
173
{
175
174
struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
176
175
int status;
176
+
int ret;
177
177
178
178
/*
179
179
* Apparently something about the firmware in the chip signals that
180
180
* HPD goes high by reporting GPIO9 as high (even though HPD isn't
181
181
* actually connected to GPIO9).
182
182
*/
183
-
return regmap_read_poll_timeout(map, PAGE2_GPIO_H, status,
184
-
status & PS_GPIO9, wait_us / 10, wait_us);
183
+
ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status,
184
+
status & PS_GPIO9, wait_us / 10, wait_us);
185
+
186
+
/*
187
+
* The first time we see HPD go high after a reset we delay an extra
188
+
* 50 ms. The best guess is that the MCU is doing "stuff" during this
189
+
* time (maybe talking to the panel) and we don't want to interrupt it.
190
+
*
191
+
* No locking is done around "need_post_hpd_delay". If we're here we
192
+
* know we're holding a PM Runtime reference and the only other place
193
+
* that touches this is PM Runtime resume.
194
+
*/
195
+
if (!ret && ps_bridge->need_post_hpd_delay) {
196
+
ps_bridge->need_post_hpd_delay = false;
197
+
msleep(50);
198
+
}
199
+
200
+
return ret;
185
201
}
186
202
187
203
static int ps8640_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
···
398
380
gpiod_set_value(ps_bridge->gpio_reset, 1);
399
381
msleep(50);
400
382
gpiod_set_value(ps_bridge->gpio_reset, 0);
383
+
384
+
/* We just reset things, so we need a delay after the first HPD */
385
+
ps_bridge->need_post_hpd_delay = true;
401
386
402
387
/*
403
388
* Mystery 200 ms delay for the "MCU to be ready". It's unclear if
+2
drivers/gpu/drm/i915/display/intel_dp.c
+2
drivers/gpu/drm/i915/display/intel_dp.c
+2
-2
drivers/gpu/drm/i915/gt/intel_workarounds.c
+2
-2
drivers/gpu/drm/i915/gt/intel_workarounds.c
···
2293
2293
}
2294
2294
2295
2295
if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
2296
-
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
2296
+
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) {
2297
2297
/*
2298
2298
* Wa_1607030317:tgl
2299
2299
* Wa_1607186500:tgl
2300
-
* Wa_1607297627:tgl,rkl,dg1[a0]
2300
+
* Wa_1607297627:tgl,rkl,dg1[a0],adlp
2301
2301
*
2302
2302
* On TGL and RKL there are multiple entries for this WA in the
2303
2303
* BSpec; some indicate this is an A0-only WA, others indicate
+9
-2
drivers/gpu/drm/i915/intel_runtime_pm.c
+9
-2
drivers/gpu/drm/i915/intel_runtime_pm.c
···
591
591
pm_runtime_use_autosuspend(kdev);
592
592
}
593
593
594
-
/* Enable by default */
595
-
pm_runtime_allow(kdev);
594
+
/*
595
+
* FIXME: Temp hammer to keep autosupend disable on lmem supported platforms.
596
+
* As per PCIe specs 5.3.1.4.1, all iomem read write request over a PCIe
597
+
* function will be unsupported in case PCIe endpoint function is in D3.
598
+
* Let's keep i915 autosuspend control 'on' till we fix all known issue
599
+
* with lmem access in D3.
600
+
*/
601
+
if (!IS_DGFX(i915))
602
+
pm_runtime_allow(kdev);
596
603
597
604
/*
598
605
* The core calls the driver load handler with an RPM reference held.
+1
-1
drivers/gpu/drm/msm/Kconfig
+1
-1
drivers/gpu/drm/msm/Kconfig
···
155
155
Compile in support for the HDMI output MSM DRM driver. It can
156
156
be a primary or a secondary display on device. Note that this is used
157
157
only for the direct HDMI output. If the device outputs HDMI data
158
-
throught some kind of DSI-to-HDMI bridge, this option can be disabled.
158
+
through some kind of DSI-to-HDMI bridge, this option can be disabled.
159
159
160
160
config DRM_MSM_HDMI_HDCP
161
161
bool "Enable HDMI HDCP support in MSM DRM driver"
+11
-3
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+11
-3
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
···
91
91
static void *state_kcalloc(struct a6xx_gpu_state *a6xx_state, int nr, size_t objsize)
92
92
{
93
93
struct a6xx_state_memobj *obj =
94
-
kzalloc((nr * objsize) + sizeof(*obj), GFP_KERNEL);
94
+
kvzalloc((nr * objsize) + sizeof(*obj), GFP_KERNEL);
95
95
96
96
if (!obj)
97
97
return NULL;
···
813
813
{
814
814
struct msm_gpu_state_bo *snapshot;
815
815
816
+
if (!bo->size)
817
+
return NULL;
818
+
816
819
snapshot = state_kcalloc(a6xx_state, 1, sizeof(*snapshot));
817
820
if (!snapshot)
818
821
return NULL;
···
1043
1040
if (a6xx_state->gmu_hfi)
1044
1041
kvfree(a6xx_state->gmu_hfi->data);
1045
1042
1046
-
list_for_each_entry_safe(obj, tmp, &a6xx_state->objs, node)
1047
-
kfree(obj);
1043
+
if (a6xx_state->gmu_debug)
1044
+
kvfree(a6xx_state->gmu_debug->data);
1045
+
1046
+
list_for_each_entry_safe(obj, tmp, &a6xx_state->objs, node) {
1047
+
list_del(&obj->node);
1048
+
kvfree(obj);
1049
+
}
1048
1050
1049
1051
adreno_gpu_state_destroy(state);
1050
1052
kfree(a6xx_state);
+9
-1
drivers/gpu/drm/msm/adreno/adreno_device.c
+9
-1
drivers/gpu/drm/msm/adreno/adreno_device.c
···
679
679
struct msm_gpu *gpu = dev_to_gpu(dev);
680
680
int remaining, ret;
681
681
682
+
if (!gpu)
683
+
return 0;
684
+
682
685
suspend_scheduler(gpu);
683
686
684
687
remaining = wait_event_timeout(gpu->retire_event,
···
703
700
704
701
static int adreno_system_resume(struct device *dev)
705
702
{
706
-
resume_scheduler(dev_to_gpu(dev));
703
+
struct msm_gpu *gpu = dev_to_gpu(dev);
704
+
705
+
if (!gpu)
706
+
return 0;
707
+
708
+
resume_scheduler(gpu);
707
709
return pm_runtime_force_resume(dev);
708
710
}
709
711
+6
-1
drivers/gpu/drm/msm/adreno/adreno_gpu.c
+6
-1
drivers/gpu/drm/msm/adreno/adreno_gpu.c
···
729
729
return buf;
730
730
}
731
731
732
-
/* len is expected to be in bytes */
732
+
/* len is expected to be in bytes
733
+
*
734
+
* WARNING: *ptr should be allocated with kvmalloc or friends. It can be free'd
735
+
* with kvfree() and replaced with a newly kvmalloc'd buffer on the first call
736
+
* when the unencoded raw data is encoded
737
+
*/
733
738
void adreno_show_object(struct drm_printer *p, void **ptr, int len,
734
739
bool *encoded)
735
740
{
+3
-2
drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_connector.c
+3
-2
drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_connector.c
···
56
56
return ret;
57
57
}
58
58
59
-
static int mdp4_lvds_connector_mode_valid(struct drm_connector *connector,
60
-
struct drm_display_mode *mode)
59
+
static enum drm_mode_status
60
+
mdp4_lvds_connector_mode_valid(struct drm_connector *connector,
61
+
struct drm_display_mode *mode)
61
62
{
62
63
struct mdp4_lvds_connector *mdp4_lvds_connector =
63
64
to_mdp4_lvds_connector(connector);
+5
-8
drivers/gpu/drm/msm/dp/dp_ctrl.c
+5
-8
drivers/gpu/drm/msm/dp/dp_ctrl.c
···
1243
1243
{
1244
1244
int ret = 0;
1245
1245
const u8 *dpcd = ctrl->panel->dpcd;
1246
-
u8 encoding = DP_SET_ANSI_8B10B;
1247
-
u8 ssc;
1246
+
u8 encoding[] = { 0, DP_SET_ANSI_8B10B };
1248
1247
u8 assr;
1249
1248
struct dp_link_info link_info = {0};
1250
1249
···
1255
1256
1256
1257
dp_aux_link_configure(ctrl->aux, &link_info);
1257
1258
1258
-
if (drm_dp_max_downspread(dpcd)) {
1259
-
ssc = DP_SPREAD_AMP_0_5;
1260
-
drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, &ssc, 1);
1261
-
}
1259
+
if (drm_dp_max_downspread(dpcd))
1260
+
encoding[0] |= DP_SPREAD_AMP_0_5;
1262
1261
1263
-
drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
1264
-
&encoding, 1);
1262
+
/* config DOWNSPREAD_CTRL and MAIN_LINK_CHANNEL_CODING_SET */
1263
+
drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2);
1265
1264
1266
1265
if (drm_dp_alternate_scrambler_reset_cap(dpcd)) {
1267
1266
assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
+20
-3
drivers/gpu/drm/msm/dp/dp_display.c
+20
-3
drivers/gpu/drm/msm/dp/dp_display.c
···
1249
1249
return -EINVAL;
1250
1250
}
1251
1251
1252
-
rc = devm_request_irq(&dp->pdev->dev, dp->irq,
1252
+
rc = devm_request_irq(dp_display->drm_dev->dev, dp->irq,
1253
1253
dp_display_irq_handler,
1254
1254
IRQF_TRIGGER_HIGH, "dp_display_isr", dp);
1255
1255
if (rc < 0) {
···
1528
1528
}
1529
1529
}
1530
1530
1531
+
static void of_dp_aux_depopulate_bus_void(void *data)
1532
+
{
1533
+
of_dp_aux_depopulate_bus(data);
1534
+
}
1535
+
1531
1536
static int dp_display_get_next_bridge(struct msm_dp *dp)
1532
1537
{
1533
1538
int rc;
···
1557
1552
* panel driver is probed asynchronously but is the best we
1558
1553
* can do without a bigger driver reorganization.
1559
1554
*/
1560
-
rc = devm_of_dp_aux_populate_ep_devices(dp_priv->aux);
1555
+
rc = of_dp_aux_populate_bus(dp_priv->aux, NULL);
1561
1556
of_node_put(aux_bus);
1557
+
if (rc)
1558
+
goto error;
1559
+
1560
+
rc = devm_add_action_or_reset(dp->drm_dev->dev,
1561
+
of_dp_aux_depopulate_bus_void,
1562
+
dp_priv->aux);
1562
1563
if (rc)
1563
1564
goto error;
1564
1565
} else if (dp->is_edp) {
···
1579
1568
* For DisplayPort interfaces external bridges are optional, so
1580
1569
* silently ignore an error if one is not present (-ENODEV).
1581
1570
*/
1582
-
rc = dp_parser_find_next_bridge(dp_priv->parser);
1571
+
rc = devm_dp_parser_find_next_bridge(dp->drm_dev->dev, dp_priv->parser);
1583
1572
if (!dp->is_edp && rc == -ENODEV)
1584
1573
return 0;
1585
1574
···
1608
1597
return -EINVAL;
1609
1598
1610
1599
priv = dev->dev_private;
1600
+
1601
+
if (priv->num_bridges == ARRAY_SIZE(priv->bridges)) {
1602
+
DRM_DEV_ERROR(dev->dev, "too many bridges\n");
1603
+
return -ENOSPC;
1604
+
}
1605
+
1611
1606
dp_display->drm_dev = dev;
1612
1607
1613
1608
dp_priv = container_of(dp_display, struct dp_display_private, dp_display);
+34
drivers/gpu/drm/msm/dp/dp_drm.c
+34
drivers/gpu/drm/msm/dp/dp_drm.c
···
31
31
connector_status_disconnected;
32
32
}
33
33
34
+
static int dp_bridge_atomic_check(struct drm_bridge *bridge,
35
+
struct drm_bridge_state *bridge_state,
36
+
struct drm_crtc_state *crtc_state,
37
+
struct drm_connector_state *conn_state)
38
+
{
39
+
struct msm_dp *dp;
40
+
41
+
dp = to_dp_bridge(bridge)->dp_display;
42
+
43
+
drm_dbg_dp(dp->drm_dev, "is_connected = %s\n",
44
+
(dp->is_connected) ? "true" : "false");
45
+
46
+
/*
47
+
* There is no protection in the DRM framework to check if the display
48
+
* pipeline has been already disabled before trying to disable it again.
49
+
* Hence if the sink is unplugged, the pipeline gets disabled, but the
50
+
* crtc->active is still true. Any attempt to set the mode or manually
51
+
* disable this encoder will result in the crash.
52
+
*
53
+
* TODO: add support for telling the DRM subsystem that the pipeline is
54
+
* disabled by the hardware and thus all access to it should be forbidden.
55
+
* After that this piece of code can be removed.
56
+
*/
57
+
if (bridge->ops & DRM_BRIDGE_OP_HPD)
58
+
return (dp->is_connected) ? 0 : -ENOTCONN;
59
+
60
+
return 0;
61
+
}
62
+
63
+
34
64
/**
35
65
* dp_bridge_get_modes - callback to add drm modes via drm_mode_probed_add()
36
66
* @bridge: Poiner to drm bridge
···
91
61
}
92
62
93
63
static const struct drm_bridge_funcs dp_bridge_ops = {
64
+
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
65
+
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
66
+
.atomic_reset = drm_atomic_helper_bridge_reset,
94
67
.enable = dp_bridge_enable,
95
68
.disable = dp_bridge_disable,
96
69
.post_disable = dp_bridge_post_disable,
···
101
68
.mode_valid = dp_bridge_mode_valid,
102
69
.get_modes = dp_bridge_get_modes,
103
70
.detect = dp_bridge_detect,
71
+
.atomic_check = dp_bridge_atomic_check,
104
72
};
105
73
106
74
struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev,
+3
-3
drivers/gpu/drm/msm/dp/dp_parser.c
+3
-3
drivers/gpu/drm/msm/dp/dp_parser.c
···
240
240
return 0;
241
241
}
242
242
243
-
int dp_parser_find_next_bridge(struct dp_parser *parser)
243
+
int devm_dp_parser_find_next_bridge(struct device *dev, struct dp_parser *parser)
244
244
{
245
-
struct device *dev = &parser->pdev->dev;
245
+
struct platform_device *pdev = parser->pdev;
246
246
struct drm_bridge *bridge;
247
247
248
-
bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
248
+
bridge = devm_drm_of_get_bridge(dev, pdev->dev.of_node, 1, 0);
249
249
if (IS_ERR(bridge))
250
250
return PTR_ERR(bridge);
251
251
+3
-2
drivers/gpu/drm/msm/dp/dp_parser.h
+3
-2
drivers/gpu/drm/msm/dp/dp_parser.h
···
138
138
struct dp_parser *dp_parser_get(struct platform_device *pdev);
139
139
140
140
/**
141
-
* dp_parser_find_next_bridge() - find an additional bridge to DP
141
+
* devm_dp_parser_find_next_bridge() - find an additional bridge to DP
142
142
*
143
+
* @dev: device to tie bridge lifetime to
143
144
* @parser: dp_parser data from client
144
145
*
145
146
* This function is used to find any additional bridge attached to
···
148
147
*
149
148
* Return: 0 if able to get the bridge, otherwise negative errno for failure.
150
149
*/
151
-
int dp_parser_find_next_bridge(struct dp_parser *parser);
150
+
int devm_dp_parser_find_next_bridge(struct device *dev, struct dp_parser *parser);
152
151
153
152
#endif
+6
drivers/gpu/drm/msm/dsi/dsi.c
+6
drivers/gpu/drm/msm/dsi/dsi.c
···
218
218
return -EINVAL;
219
219
220
220
priv = dev->dev_private;
221
+
222
+
if (priv->num_bridges == ARRAY_SIZE(priv->bridges)) {
223
+
DRM_DEV_ERROR(dev->dev, "too many bridges\n");
224
+
return -ENOSPC;
225
+
}
226
+
221
227
msm_dsi->dev = dev;
222
228
223
229
ret = msm_dsi_host_modeset_init(msm_dsi->host, dev);
+6
-1
drivers/gpu/drm/msm/hdmi/hdmi.c
+6
-1
drivers/gpu/drm/msm/hdmi/hdmi.c
···
300
300
struct platform_device *pdev = hdmi->pdev;
301
301
int ret;
302
302
303
+
if (priv->num_bridges == ARRAY_SIZE(priv->bridges)) {
304
+
DRM_DEV_ERROR(dev->dev, "too many bridges\n");
305
+
return -ENOSPC;
306
+
}
307
+
303
308
hdmi->dev = dev;
304
309
hdmi->encoder = encoder;
305
310
···
344
339
goto fail;
345
340
}
346
341
347
-
ret = devm_request_irq(&pdev->dev, hdmi->irq,
342
+
ret = devm_request_irq(dev->dev, hdmi->irq,
348
343
msm_hdmi_irq, IRQF_TRIGGER_HIGH,
349
344
"hdmi_isr", hdmi);
350
345
if (ret < 0) {
+1
drivers/gpu/drm/msm/msm_drv.c
+1
drivers/gpu/drm/msm/msm_drv.c
+4
-5
drivers/gpu/drm/msm/msm_gem_submit.c
+4
-5
drivers/gpu/drm/msm/msm_gem_submit.c
···
501
501
*/
502
502
static void submit_cleanup(struct msm_gem_submit *submit, bool error)
503
503
{
504
-
unsigned cleanup_flags = BO_LOCKED | BO_OBJ_PINNED;
504
+
unsigned cleanup_flags = BO_LOCKED;
505
505
unsigned i;
506
506
507
507
if (error)
508
-
cleanup_flags |= BO_VMA_PINNED;
508
+
cleanup_flags |= BO_VMA_PINNED | BO_OBJ_PINNED;
509
509
510
510
for (i = 0; i < submit->nr_bos; i++) {
511
511
struct msm_gem_object *msm_obj = submit->bos[i].obj;
···
706
706
struct msm_drm_private *priv = dev->dev_private;
707
707
struct drm_msm_gem_submit *args = data;
708
708
struct msm_file_private *ctx = file->driver_priv;
709
-
struct msm_gem_submit *submit = NULL;
709
+
struct msm_gem_submit *submit;
710
710
struct msm_gpu *gpu = priv->gpu;
711
711
struct msm_gpu_submitqueue *queue;
712
712
struct msm_ringbuffer *ring;
···
946
946
put_unused_fd(out_fence_fd);
947
947
mutex_unlock(&queue->lock);
948
948
out_post_unlock:
949
-
if (submit)
950
-
msm_gem_submit_put(submit);
949
+
msm_gem_submit_put(submit);
951
950
if (!IS_ERR_OR_NULL(post_deps)) {
952
951
for (i = 0; i < args->nr_out_syncobjs; ++i) {
953
952
kfree(post_deps[i].chain);
+2
drivers/gpu/drm/msm/msm_gpu.c
+2
drivers/gpu/drm/msm/msm_gpu.c
+4
drivers/gpu/drm/msm/msm_gpu.h
+4
drivers/gpu/drm/msm/msm_gpu.h
+2
-1
drivers/gpu/drm/msm/msm_ringbuffer.c
+2
-1
drivers/gpu/drm/msm/msm_ringbuffer.c
+5
-1
drivers/gpu/drm/scheduler/sched_entity.c
+5
-1
drivers/gpu/drm/scheduler/sched_entity.c
···
207
207
struct drm_sched_job *job = container_of(cb, struct drm_sched_job,
208
208
finish_cb);
209
209
210
+
dma_fence_put(f);
210
211
INIT_WORK(&job->work, drm_sched_entity_kill_jobs_work);
211
212
schedule_work(&job->work);
212
213
}
···
235
234
struct drm_sched_fence *s_fence = job->s_fence;
236
235
237
236
/* Wait for all dependencies to avoid data corruptions */
238
-
while ((f = drm_sched_job_dependency(job, entity)))
237
+
while ((f = drm_sched_job_dependency(job, entity))) {
239
238
dma_fence_wait(f, false);
239
+
dma_fence_put(f);
240
+
}
240
241
241
242
drm_sched_fence_scheduled(s_fence);
242
243
dma_fence_set_error(&s_fence->finished, -ESRCH);
···
253
250
continue;
254
251
}
255
252
253
+
dma_fence_get(entity->last_scheduled);
256
254
r = dma_fence_add_callback(entity->last_scheduled,
257
255
&job->finish_cb,
258
256
drm_sched_entity_kill_jobs_cb);
+1
-4
drivers/video/aperture.c
+1
-4
drivers/video/aperture.c
···
340
340
size = pci_resource_len(pdev, bar);
341
341
ret = aperture_remove_conflicting_devices(base, size, primary, name);
342
342
if (ret)
343
-
break;
343
+
return ret;
344
344
}
345
-
346
-
if (ret)
347
-
return ret;
348
345
349
346
/*
350
347
* WARNING: Apparently we must kick fbdev drivers before vgacon,
+2
include/uapi/drm/amdgpu_drm.h
+2
include/uapi/drm/amdgpu_drm.h
···
763
763
#define AMDGPU_INFO_FW_MES_KIQ 0x19
764
764
/* Subquery id: Query MES firmware version */
765
765
#define AMDGPU_INFO_FW_MES 0x1a
766
+
/* Subquery id: Query IMU firmware version */
767
+
#define AMDGPU_INFO_FW_IMU 0x1b
766
768
767
769
/* number of bytes moved for TTM migration */
768
770
#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f