Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mtd/changes-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD updates from Miquel Raynal:
"There has been a lot of activity in the MTD subsystem recently, with a
number of SPI-NOR cleanups as well as the introduction of ECC engines
that can be used by SPI controllers (hence a few SPI patches in here).
Core MTD changes:
- Replace the expert mode symbols with a single helper
- Fix misuses of of_match_ptr()
- Remove partid and partname debugfs files
- tests: Fix eraseblock read speed miscalculation for lower partition
sizes
- TRX parser: Allow to use on MediaTek MIPS SoCs
MTD driver changes:
- spear_smi: use GFP_KERNEL
- mchp48l640: Add SPI ID table
- mchp23k256: Add SPI ID table
- blkdevs: Avoid soft lockups with some mtd/spi devices
- aspeed-smc: Improve probe resilience
Hyperbus changes:
- HBMC_AM654 should depend on ARCH_K3
NAND core changes:
- ECC:
- Add infrastructure to support hardware engines
- Add a new helper to retrieve the ECC context
- Provide a helper to retrieve a pilelined engine device
NAND-ECC changes:
- Macronix ECC engine:
- Add Macronix external ECC engine support
- Support SPI pipelined mode
- Make two read-only arrays static const
- Fix compile test issue
Raw NAND core changes:
- Fix misuses of of_match_node()
- Rework of_get_nand_bus_width()
- Remove of_get_nand_on_flash_bbt() wrapper
- Protect access to rawnand devices while in suspend
- bindings: Document the wp-gpios property
Rax NAND controller driver changes:
- atmel: Fix refcount issue in atmel_nand_controller_init
- nandsim:
- Add NS_PAGE_BYTE_SHIFT macro to replace the repeat pattern
- Merge repeat codes in ns_switch_state
- Replace overflow check with kzalloc to single kcalloc
- rockchip: Fix platform_get_irq.cocci warning
- stm32_fmc2: Add NAND Write Protect support
- pl353: Set the nand chip node as the flash node
- brcmnand: Fix sparse warnings in bcma_nand
- omap_elm: Remove redundant variable 'errors'
- gpmi:
- Support fast edo timings for mx28
- Validate controller clock rate
- Fix controller timings setting
- brcmnand:
- Add BCMA shim
- BCMA controller uses command shift of 0
- Allow platform data instantation
- Add platform data structure for BCMA
- Allow working without interrupts
- Move OF operations out of brcmnand_init_cs()
- Avoid pdev in brcmnand_init_cs()
- Allow SoC to provide I/O operations
- Assign soc as early as possible
Onenand changes:
- Check for error irq
SPI-NAND core changes:
- Delay a little bit the dirmap creation
- Create direct mapping descriptors for ECC operations
SPI-NAND driver changes:
- macronix: Use random program load
SPI NOR core changes:
- Move vendor specific code out of the core into vendor drivers.
- Unify all function and object names in the vendor modules.
- Make setup() callback optional to improve readability.
- Skip erase logic when the SPI_NOR_NO_ERASE flag is set at flash
declaration.
SPI changes:
- Macronix SPI controller:
- Fix the transmit path
- Create a helper to configure the controller before an operation
- Create a helper to ease the start of an operation
- Add support for direct mapping
- Add support for pipelined ECC operations
- spi-mem:
- Introduce a capability structure
- Check the controller extra capabilities
- cadence-quadspi/mxic: Provide capability structures
- Kill the spi_mem_dtr_supports_op() helper
- Add an ecc parameter to the spi_mem_op structure
Binding changes:
- Dropped mtd/cortina,gemini-flash.txt
- Convert BCM47xx partitions to json-schema
- Vendor prefixes: Clarify Macronix prefix
- SPI NAND: Convert spi-nand description file to yaml
- Raw NAND chip: Create a NAND chip description
- Raw NAND controller:
- Harmonize the property types
- Fix a comment in the examples
- Fix the reg property description
- Describe Macronix NAND ECC engine
- Macronix SPI controller:
- Document the nand-ecc-engine property
- Convert to yaml
- The interrupt property is not mandatory"
* tag 'mtd/changes-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (104 commits)
mtd: nand: ecc: mxic: Fix compile test issue
mtd: nand: mxic-ecc: make two read-only arrays static const
mtd: hyperbus: HBMC_AM654 should depend on ARCH_K3
mtd: core: Remove partid and partname debugfs files
dt-bindings: mtd: partitions: convert BCM47xx to the json-schema
mtd: tests: Fix eraseblock read speed miscalculation for lower partition sizes
mtd: rawnand: atmel: fix refcount issue in atmel_nand_controller_init
mtd: rawnand: rockchip: fix platform_get_irq.cocci warning
mtd: spi-nor: Skip erase logic when SPI_NOR_NO_ERASE is set
mtd: spi-nor: renumber flags
mtd: spi-nor: slightly change code style in spi_nor_sr_ready()
mtd: spi-nor: spansion: rename vendor specific functions and defines
mtd: spi-nor: spansion: convert USE_CLSR to a manufacturer flag
mtd: spi-nor: move all spansion specifics into spansion.c
mtd: spi-nor: spansion: slightly rework control flow in late_init()
mtd: spi-nor: micron-st: rename vendor specific functions and defines
mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flag
mtd: spi-nor: move all micron-st specifics into micron-st.c
mtd: spi-nor: xilinx: correct the debug message
mtd: spi-nor: xilinx: rename vendor specific functions and defines
...
+2924
-1002
-24
Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt
-24
Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt
···
1
-
Flash device on Cortina Systems Gemini SoC
2
-
3
-
This flash is regular CFI compatible (Intel or AMD extended) flash chips with
4
-
some special bits that can be controlled by the machine's system controller.
5
-
6
-
Required properties:
7
-
- compatible : must be "cortina,gemini-flash", "cfi-flash";
8
-
- reg : memory address for the flash chip
9
-
- syscon : must be a phandle to the system controller
10
-
- bank-width : width in bytes of flash interface, should be <2>
11
-
12
-
For the rest of the properties, see mtd-physmap.yaml.
13
-
14
-
The device tree may optionally contain sub-nodes describing partitions of the
15
-
address space. See partition.txt for more detail.
16
-
17
-
Example:
18
-
19
-
flash@30000000 {
20
-
compatible = "cortina,gemini-flash", "cfi-flash";
21
-
reg = <0x30000000 0x01000000>;
22
-
syscon = <&syscon>;
23
-
bank-width = <2>;
24
-
};
+17
-1
Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
+17
-1
Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
···
44
44
- numonyx,js28f128
45
45
- sst,sst39vf320
46
46
- xlnx,xps-mch-emc-2.00.a
47
-
- const: cfi-flash
47
+
- enum:
48
+
- cfi-flash
49
+
- jedec-flash
48
50
- items:
49
51
- enum:
50
52
- cypress,cy7c1019dv33-10zsxi
···
128
126
required:
129
127
- compatible
130
128
- reg
129
+
130
+
if:
131
+
properties:
132
+
compatible:
133
+
contains:
134
+
const: cortina,gemini-flash
135
+
then:
136
+
properties:
137
+
syscon:
138
+
$ref: /schemas/types.yaml#/definitions/phandle
139
+
description:
140
+
Phandle to the syscon controller
141
+
required:
142
+
- syscon
131
143
132
144
# FIXME: A parent bus may define timing properties
133
145
additionalProperties: true
+77
Documentation/devicetree/bindings/mtd/mxicy,nand-ecc-engine.yaml
+77
Documentation/devicetree/bindings/mtd/mxicy,nand-ecc-engine.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Macronix NAND ECC engine device tree bindings
8
+
9
+
maintainers:
10
+
- Miquel Raynal <miquel.raynal@bootlin.com>
11
+
12
+
properties:
13
+
compatible:
14
+
const: mxicy,nand-ecc-engine-rev3
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
clocks:
20
+
maxItems: 1
21
+
22
+
interrupts:
23
+
maxItems: 1
24
+
25
+
required:
26
+
- compatible
27
+
- reg
28
+
29
+
additionalProperties: false
30
+
31
+
examples:
32
+
- |
33
+
/* External configuration */
34
+
spi_controller0: spi@43c30000 {
35
+
compatible = "mxicy,mx25f0a-spi";
36
+
reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
37
+
reg-names = "regs", "dirmap";
38
+
clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
39
+
clock-names = "send_clk", "send_dly_clk", "ps_clk";
40
+
#address-cells = <1>;
41
+
#size-cells = <0>;
42
+
43
+
flash@0 {
44
+
compatible = "spi-nand";
45
+
reg = <0>;
46
+
nand-ecc-engine = <&ecc_engine0>;
47
+
};
48
+
};
49
+
50
+
ecc_engine0: ecc@43c40000 {
51
+
compatible = "mxicy,nand-ecc-engine-rev3";
52
+
reg = <0x43c40000 0x10000>;
53
+
};
54
+
55
+
- |
56
+
/* Pipelined configuration */
57
+
spi_controller1: spi@43c30000 {
58
+
compatible = "mxicy,mx25f0a-spi";
59
+
reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
60
+
reg-names = "regs", "dirmap";
61
+
clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
62
+
clock-names = "send_clk", "send_dly_clk", "ps_clk";
63
+
#address-cells = <1>;
64
+
#size-cells = <0>;
65
+
nand-ecc-engine = <&ecc_engine1>;
66
+
67
+
flash@0 {
68
+
compatible = "spi-nand";
69
+
reg = <0>;
70
+
nand-ecc-engine = <&spi_controller1>;
71
+
};
72
+
};
73
+
74
+
ecc_engine1: ecc@43c40000 {
75
+
compatible = "mxicy,nand-ecc-engine-rev3";
76
+
reg = <0x43c40000 0x10000>;
77
+
};
+70
Documentation/devicetree/bindings/mtd/nand-chip.yaml
+70
Documentation/devicetree/bindings/mtd/nand-chip.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NAND Chip and NAND Controller Generic Binding
8
+
9
+
maintainers:
10
+
- Miquel Raynal <miquel.raynal@bootlin.com>
11
+
12
+
description: |
13
+
This file covers the generic description of a NAND chip. It implies that the
14
+
bus interface should not be taken into account: both raw NAND devices and
15
+
SPI-NAND devices are concerned by this description.
16
+
17
+
properties:
18
+
reg:
19
+
description:
20
+
Contains the chip-select IDs.
21
+
22
+
nand-ecc-engine:
23
+
description: |
24
+
A phandle on the hardware ECC engine if any. There are
25
+
basically three possibilities:
26
+
1/ The ECC engine is part of the NAND controller, in this
27
+
case the phandle should reference the parent node.
28
+
2/ The ECC engine is part of the NAND part (on-die), in this
29
+
case the phandle should reference the node itself.
30
+
3/ The ECC engine is external, in this case the phandle should
31
+
reference the specific ECC engine node.
32
+
$ref: /schemas/types.yaml#/definitions/phandle
33
+
34
+
nand-use-soft-ecc-engine:
35
+
description: Use a software ECC engine.
36
+
type: boolean
37
+
38
+
nand-no-ecc-engine:
39
+
description: Do not use any ECC correction.
40
+
type: boolean
41
+
42
+
nand-ecc-algo:
43
+
description:
44
+
Desired ECC algorithm.
45
+
$ref: /schemas/types.yaml#/definitions/string
46
+
enum: [hamming, bch, rs]
47
+
48
+
nand-ecc-strength:
49
+
description:
50
+
Maximum number of bits that can be corrected per ECC step.
51
+
$ref: /schemas/types.yaml#/definitions/uint32
52
+
minimum: 1
53
+
54
+
nand-ecc-step-size:
55
+
description:
56
+
Number of data bytes covered by a single ECC step.
57
+
$ref: /schemas/types.yaml#/definitions/uint32
58
+
minimum: 1
59
+
60
+
secure-regions:
61
+
description:
62
+
Regions in the NAND chip which are protected using a secure element
63
+
like Trustzone. This property contains the start address and size of
64
+
the secure regions present.
65
+
$ref: /schemas/types.yaml#/definitions/uint64-matrix
66
+
67
+
required:
68
+
- reg
69
+
70
+
additionalProperties: true
+16
-57
Documentation/devicetree/bindings/mtd/nand-controller.yaml
+16
-57
Documentation/devicetree/bindings/mtd/nand-controller.yaml
···
39
39
ranges: true
40
40
41
41
cs-gpios:
42
-
minItems: 1
43
-
maxItems: 8
44
42
description:
45
43
Array of chip-select available to the controller. The first
46
44
entries are a 1:1 mapping of the available chip-select on the
···
46
48
chip-select as needed may follow and should be phandles of GPIO
47
49
lines. 'reg' entries of the NAND chip subnodes become indexes of
48
50
this array when this property is present.
51
+
minItems: 1
52
+
maxItems: 8
49
53
50
54
patternProperties:
51
55
"^nand@[a-f0-9]$":
52
56
type: object
57
+
$ref: "nand-chip.yaml#"
58
+
53
59
properties:
54
60
reg:
55
61
description:
56
-
Contains the native Ready/Busy IDs.
57
-
58
-
nand-ecc-engine:
59
-
allOf:
60
-
- $ref: /schemas/types.yaml#/definitions/phandle
61
-
description: |
62
-
A phandle on the hardware ECC engine if any. There are
63
-
basically three possibilities:
64
-
1/ The ECC engine is part of the NAND controller, in this
65
-
case the phandle should reference the parent node.
66
-
2/ The ECC engine is part of the NAND part (on-die), in this
67
-
case the phandle should reference the node itself.
68
-
3/ The ECC engine is external, in this case the phandle should
69
-
reference the specific ECC engine node.
70
-
71
-
nand-use-soft-ecc-engine:
72
-
type: boolean
73
-
description: Use a software ECC engine.
74
-
75
-
nand-no-ecc-engine:
76
-
type: boolean
77
-
description: Do not use any ECC correction.
62
+
Contains the chip-select IDs.
78
63
79
64
nand-ecc-placement:
80
-
allOf:
81
-
- $ref: /schemas/types.yaml#/definitions/string
82
-
- enum: [ oob, interleaved ]
83
65
description:
84
66
Location of the ECC bytes. This location is unknown by default
85
67
but can be explicitly set to "oob", if all ECC bytes are
86
68
known to be stored in the OOB area, or "interleaved" if ECC
87
69
bytes will be interleaved with regular data in the main area.
88
-
89
-
nand-ecc-algo:
90
-
description:
91
-
Desired ECC algorithm.
92
70
$ref: /schemas/types.yaml#/definitions/string
93
-
enum: [hamming, bch, rs]
71
+
enum: [ oob, interleaved ]
94
72
95
73
nand-bus-width:
96
74
description:
···
76
102
default: 8
77
103
78
104
nand-on-flash-bbt:
79
-
$ref: /schemas/types.yaml#/definitions/flag
80
105
description:
81
106
With this property, the OS will search the device for a Bad
82
107
Block Table (BBT). If not found, it will create one, reserve
···
84
111
few pages of all the blocks will be scanned at boot time to
85
112
find Bad Block Markers (BBM). These markers will help to
86
113
build a volatile BBT in RAM.
87
-
88
-
nand-ecc-strength:
89
-
description:
90
-
Maximum number of bits that can be corrected per ECC step.
91
-
$ref: /schemas/types.yaml#/definitions/uint32
92
-
minimum: 1
93
-
94
-
nand-ecc-step-size:
95
-
description:
96
-
Number of data bytes covered by a single ECC step.
97
-
$ref: /schemas/types.yaml#/definitions/uint32
98
-
minimum: 1
114
+
$ref: /schemas/types.yaml#/definitions/flag
99
115
100
116
nand-ecc-maximize:
101
-
$ref: /schemas/types.yaml#/definitions/flag
102
117
description:
103
118
Whether or not the ECC strength should be maximized. The
104
119
maximum ECC strength is both controller and chip
···
95
134
constraint into account. This is particularly useful when
96
135
only the in-band area is used by the upper layers, and you
97
136
want to make your NAND as reliable as possible.
137
+
$ref: /schemas/types.yaml#/definitions/flag
98
138
99
139
nand-is-boot-medium:
100
-
$ref: /schemas/types.yaml#/definitions/flag
101
140
description:
102
141
Whether or not the NAND chip is a boot medium. Drivers might
103
142
use this information to select ECC algorithms supported by
104
143
the boot ROM or similar restrictions.
144
+
$ref: /schemas/types.yaml#/definitions/flag
105
145
106
146
nand-rb:
107
-
$ref: /schemas/types.yaml#/definitions/uint32-array
108
147
description:
109
148
Contains the native Ready/Busy IDs.
149
+
$ref: /schemas/types.yaml#/definitions/uint32-array
110
150
111
151
rb-gpios:
112
152
description:
···
116
154
Ready/Busy pins. Active state refers to the NAND ready state and
117
155
should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
118
156
119
-
secure-regions:
120
-
$ref: /schemas/types.yaml#/definitions/uint64-matrix
157
+
wp-gpios:
121
158
description:
122
-
Regions in the NAND chip which are protected using a secure element
123
-
like Trustzone. This property contains the start address and size of
124
-
the secure regions present.
159
+
Contains one GPIO descriptor for the Write Protect pin.
160
+
Active state refers to the NAND Write Protect state and should be
161
+
set to GPIOD_ACTIVE_LOW unless the signal is inverted.
162
+
maxItems: 1
125
163
126
164
required:
127
165
- reg
···
143
181
144
182
nand@0 {
145
183
reg = <0>; /* Native CS */
146
-
nand-use-soft-ecc-engine;
147
-
nand-ecc-algo = "bch";
148
-
149
-
/* controller specific properties */
184
+
/* NAND chip specific properties */
150
185
};
151
186
152
187
nand@1 {
-42
Documentation/devicetree/bindings/mtd/partitions/brcm,bcm947xx-cfe-partitions.txt
-42
Documentation/devicetree/bindings/mtd/partitions/brcm,bcm947xx-cfe-partitions.txt
···
1
-
Broadcom BCM47xx Partitions
2
-
===========================
3
-
4
-
Broadcom is one of hardware manufacturers providing SoCs (BCM47xx) used in
5
-
home routers. Their BCM947xx boards using CFE bootloader have several partitions
6
-
without any on-flash partition table. On some devices their sizes and/or
7
-
meanings can also vary so fixed partitioning can't be used.
8
-
9
-
Discovering partitions on these devices is possible thanks to having a special
10
-
header and/or magic signature at the beginning of each of them. They are also
11
-
block aligned which is important for determinig a size.
12
-
13
-
Most of partitions use ASCII text based magic for determining a type. More
14
-
complex partitions (like TRX with its HDR0 magic) may include extra header
15
-
containing some details, including a length.
16
-
17
-
A list of supported partitions includes:
18
-
1) Bootloader with Broadcom's CFE (Common Firmware Environment)
19
-
2) NVRAM with configuration/calibration data
20
-
3) Device manufacturer's data with some default values (e.g. SSIDs)
21
-
4) TRX firmware container which can hold up to 4 subpartitions
22
-
5) Backup TRX firmware used after failed upgrade
23
-
24
-
As mentioned earlier, role of some partitions may depend on extra configuration.
25
-
For example both: main firmware and backup firmware use the same TRX format with
26
-
the same header. To distinguish currently used firmware a CFE's environment
27
-
variable "bootpartition" is used.
28
-
29
-
30
-
Devices using Broadcom partitions described above should should have flash node
31
-
with a subnode named "partitions" using following properties:
32
-
33
-
Required properties:
34
-
- compatible : (required) must be "brcm,bcm947xx-cfe-partitions"
35
-
36
-
Example:
37
-
38
-
flash@0 {
39
-
partitions {
40
-
compatible = "brcm,bcm947xx-cfe-partitions";
41
-
};
42
-
};
+48
Documentation/devicetree/bindings/mtd/partitions/brcm,bcm947xx-cfe-partitions.yaml
+48
Documentation/devicetree/bindings/mtd/partitions/brcm,bcm947xx-cfe-partitions.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mtd/partitions/brcm,bcm947xx-cfe-partitions.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Broadcom BCM47xx Partitions
8
+
9
+
description: |
10
+
Broadcom is one of hardware manufacturers providing SoCs (BCM47xx) used in
11
+
home routers. Their BCM947xx boards using CFE bootloader have several
12
+
partitions without any on-flash partition table. On some devices their sizes
13
+
and/or meanings can also vary so fixed partitioning can't be used.
14
+
15
+
Discovering partitions on these devices is possible thanks to having a special
16
+
header and/or magic signature at the beginning of each of them. They are also
17
+
block aligned which is important for determinig a size.
18
+
19
+
Most of partitions use ASCII text based magic for determining a type. More
20
+
complex partitions (like TRX with its HDR0 magic) may include extra header
21
+
containing some details, including a length.
22
+
23
+
A list of supported partitions includes:
24
+
1) Bootloader with Broadcom's CFE (Common Firmware Environment)
25
+
2) NVRAM with configuration/calibration data
26
+
3) Device manufacturer's data with some default values (e.g. SSIDs)
27
+
4) TRX firmware container which can hold up to 4 subpartitions
28
+
5) Backup TRX firmware used after failed upgrade
29
+
30
+
As mentioned earlier, role of some partitions may depend on extra
31
+
configuration. For example both: main firmware and backup firmware use the
32
+
same TRX format with the same header. To distinguish currently used firmware a
33
+
CFE's environment variable "bootpartition" is used.
34
+
35
+
maintainers:
36
+
- Rafał Miłecki <rafal@milecki.pl>
37
+
38
+
properties:
39
+
compatible:
40
+
const: brcm,bcm947xx-cfe-partitions
41
+
42
+
additionalProperties: false
43
+
44
+
examples:
45
+
- |
46
+
partitions {
47
+
compatible = "brcm,bcm947xx-cfe-partitions";
48
+
};
-5
Documentation/devicetree/bindings/mtd/spi-nand.txt
-5
Documentation/devicetree/bindings/mtd/spi-nand.txt
+27
Documentation/devicetree/bindings/mtd/spi-nand.yaml
+27
Documentation/devicetree/bindings/mtd/spi-nand.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/mtd/spi-nand.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: SPI-NAND flash device tree bindings
8
+
9
+
maintainers:
10
+
- Miquel Raynal <miquel.raynal@bootlin.com>
11
+
12
+
allOf:
13
+
- $ref: "nand-chip.yaml#"
14
+
15
+
properties:
16
+
compatible:
17
+
const: spi-nand
18
+
19
+
reg:
20
+
description: Encode the chip-select line on the SPI bus
21
+
maxItems: 1
22
+
23
+
required:
24
+
- compatible
25
+
- reg
26
+
27
+
unevaluatedProperties: false
+65
Documentation/devicetree/bindings/spi/mxicy,mx25f0a-spi.yaml
+65
Documentation/devicetree/bindings/spi/mxicy,mx25f0a-spi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/spi/mxicy,mx25f0a-spi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Macronix SPI controller device tree bindings
8
+
9
+
maintainers:
10
+
- Miquel Raynal <miquel.raynal@bootlin.com>
11
+
12
+
allOf:
13
+
- $ref: "spi-controller.yaml#"
14
+
15
+
properties:
16
+
compatible:
17
+
const: mxicy,mx25f0a-spi
18
+
19
+
reg:
20
+
minItems: 2
21
+
maxItems: 2
22
+
23
+
reg-names:
24
+
items:
25
+
- const: regs
26
+
- const: dirmap
27
+
28
+
interrupts:
29
+
maxItems: 1
30
+
31
+
clocks:
32
+
minItems: 3
33
+
maxItems: 3
34
+
35
+
clock-names:
36
+
items:
37
+
- const: send_clk
38
+
- const: send_dly_clk
39
+
- const: ps_clk
40
+
41
+
nand-ecc-engine:
42
+
description: NAND ECC engine used by the SPI controller in order to perform
43
+
on-the-fly correction when using a SPI-NAND memory.
44
+
$ref: /schemas/types.yaml#/definitions/phandle
45
+
46
+
required:
47
+
- compatible
48
+
- reg
49
+
- reg-names
50
+
- clocks
51
+
- clock-names
52
+
53
+
unevaluatedProperties: false
54
+
55
+
examples:
56
+
- |
57
+
spi@43c30000 {
58
+
compatible = "mxicy,mx25f0a-spi";
59
+
reg = <0x43c30000 0x10000>, <0xa0000000 0x20000000>;
60
+
reg-names = "regs", "dirmap";
61
+
clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 18>;
62
+
clock-names = "send_clk", "send_dly_clk", "ps_clk";
63
+
#address-cells = <1>;
64
+
#size-cells = <0>;
65
+
};
-34
Documentation/devicetree/bindings/spi/spi-mxic.txt
-34
Documentation/devicetree/bindings/spi/spi-mxic.txt
···
1
-
Macronix SPI controller Device Tree Bindings
2
-
--------------------------------------------
3
-
4
-
Required properties:
5
-
- compatible: should be "mxicy,mx25f0a-spi"
6
-
- #address-cells: should be 1
7
-
- #size-cells: should be 0
8
-
- reg: should contain 2 entries, one for the registers and one for the direct
9
-
mapping area
10
-
- reg-names: should contain "regs" and "dirmap"
11
-
- interrupts: interrupt line connected to the SPI controller
12
-
- clock-names: should contain "ps_clk", "send_clk" and "send_dly_clk"
13
-
- clocks: should contain 3 entries for the "ps_clk", "send_clk" and
14
-
"send_dly_clk" clocks
15
-
16
-
Example:
17
-
18
-
spi@43c30000 {
19
-
compatible = "mxicy,mx25f0a-spi";
20
-
reg = <0x43c30000 0x10000>, <0xa0000000 0x20000000>;
21
-
reg-names = "regs", "dirmap";
22
-
clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 18>;
23
-
clock-names = "send_clk", "send_dly_clk", "ps_clk";
24
-
#address-cells = <1>;
25
-
#size-cells = <0>;
26
-
27
-
flash@0 {
28
-
compatible = "jedec,spi-nor";
29
-
reg = <0>;
30
-
spi-max-frequency = <25000000>;
31
-
spi-tx-bus-width = <4>;
32
-
spi-rx-bus-width = <4>;
33
-
};
34
-
};
+3
Documentation/devicetree/bindings/vendor-prefixes.yaml
+3
Documentation/devicetree/bindings/vendor-prefixes.yaml
···
816
816
description: Mundo Reader S.L.
817
817
"^murata,.*":
818
818
description: Murata Manufacturing Co., Ltd.
819
+
"^mxic,.*":
820
+
description: Macronix International Co., Ltd.
821
+
deprecated: true
819
822
"^mxicy,.*":
820
823
description: Macronix International Co., Ltd.
821
824
"^myir,.*":
+1
MAINTAINERS
+1
MAINTAINERS
+19
-1
drivers/bcma/driver_chipcommon_nflash.c
+19
-1
drivers/bcma/driver_chipcommon_nflash.c
···
7
7
8
8
#include "bcma_private.h"
9
9
10
+
#include <linux/bitops.h>
10
11
#include <linux/platform_device.h>
12
+
#include <linux/platform_data/brcmnand.h>
11
13
#include <linux/bcma/bcma.h>
14
+
15
+
/* Alternate NAND controller driver name in order to allow both bcm47xxnflash
16
+
* and bcma_brcmnand to be built into the same kernel image.
17
+
*/
18
+
static const char *bcma_nflash_alt_name = "bcma_brcmnand";
12
19
13
20
struct platform_device bcma_nflash_dev = {
14
21
.name = "bcma_nflash",
15
22
.num_resources = 0,
16
23
};
17
24
25
+
static const char *probes[] = { "bcm47xxpart", NULL };
26
+
18
27
/* Initialize NAND flash access */
19
28
int bcma_nflash_init(struct bcma_drv_cc *cc)
20
29
{
21
30
struct bcma_bus *bus = cc->core->bus;
31
+
u32 reg;
22
32
23
33
if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
24
34
cc->core->id.rev != 38) {
···
43
33
44
34
cc->nflash.present = true;
45
35
if (cc->core->id.rev == 38 &&
46
-
(cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
36
+
(cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)) {
47
37
cc->nflash.boot = true;
38
+
/* Determine the chip select that is being used */
39
+
reg = bcma_cc_read32(cc, BCMA_CC_NAND_CS_NAND_SELECT) & 0xff;
40
+
cc->nflash.brcmnand_info.chip_select = ffs(reg) - 1;
41
+
cc->nflash.brcmnand_info.part_probe_types = probes;
42
+
cc->nflash.brcmnand_info.ecc_stepsize = 512;
43
+
cc->nflash.brcmnand_info.ecc_strength = 1;
44
+
bcma_nflash_dev.name = bcma_nflash_alt_name;
45
+
}
48
46
49
47
/* Prepare platform device, but don't register it yet. It's too early,
50
48
* malloc (required by device_private_init) is not available yet. */
+15
-1
drivers/mtd/devices/mchp23k256.c
+15
-1
drivers/mtd/devices/mchp23k256.c
···
229
229
};
230
230
MODULE_DEVICE_TABLE(of, mchp23k256_of_table);
231
231
232
+
static const struct spi_device_id mchp23k256_spi_ids[] = {
233
+
{
234
+
.name = "mchp23k256",
235
+
.driver_data = (kernel_ulong_t)&mchp23k256_caps,
236
+
},
237
+
{
238
+
.name = "mchp23lcv1024",
239
+
.driver_data = (kernel_ulong_t)&mchp23lcv1024_caps,
240
+
},
241
+
{}
242
+
};
243
+
MODULE_DEVICE_TABLE(spi, mchp23k256_spi_ids);
244
+
232
245
static struct spi_driver mchp23k256_driver = {
233
246
.driver = {
234
247
.name = "mchp23k256",
235
-
.of_match_table = of_match_ptr(mchp23k256_of_table),
248
+
.of_match_table = mchp23k256_of_table,
236
249
},
237
250
.probe = mchp23k256_probe,
238
251
.remove = mchp23k256_remove,
252
+
.id_table = mchp23k256_spi_ids,
239
253
};
240
254
241
255
module_spi_driver(mchp23k256_driver);
+11
-1
drivers/mtd/devices/mchp48l640.c
+11
-1
drivers/mtd/devices/mchp48l640.c
···
357
357
};
358
358
MODULE_DEVICE_TABLE(of, mchp48l640_of_table);
359
359
360
+
static const struct spi_device_id mchp48l640_spi_ids[] = {
361
+
{
362
+
.name = "48l640",
363
+
.driver_data = (kernel_ulong_t)&mchp48l640_caps,
364
+
},
365
+
{}
366
+
};
367
+
MODULE_DEVICE_TABLE(spi, mchp48l640_spi_ids);
368
+
360
369
static struct spi_driver mchp48l640_driver = {
361
370
.driver = {
362
371
.name = "mchp48l640",
363
-
.of_match_table = of_match_ptr(mchp48l640_of_table),
372
+
.of_match_table = mchp48l640_of_table,
364
373
},
365
374
.probe = mchp48l640_probe,
366
375
.remove = mchp48l640_remove,
376
+
.id_table = mchp48l640_spi_ids,
367
377
};
368
378
369
379
module_spi_driver(mchp48l640_driver);
+1
-1
drivers/mtd/devices/spear_smi.c
+1
-1
drivers/mtd/devices/spear_smi.c
+1
-1
drivers/mtd/hyperbus/Kconfig
+1
-1
drivers/mtd/hyperbus/Kconfig
+1
drivers/mtd/mtd_blkdevs.c
+1
drivers/mtd/mtd_blkdevs.c
+12
-38
drivers/mtd/mtdcore.c
+12
-38
drivers/mtd/mtdcore.c
···
336
336
.release = mtd_release,
337
337
};
338
338
339
-
static int mtd_partid_debug_show(struct seq_file *s, void *p)
339
+
static bool mtd_expert_analysis_mode;
340
+
341
+
#ifdef CONFIG_DEBUG_FS
342
+
bool mtd_check_expert_analysis_mode(void)
340
343
{
341
-
struct mtd_info *mtd = s->private;
344
+
const char *mtd_expert_analysis_warning =
345
+
"Bad block checks have been entirely disabled.\n"
346
+
"This is only reserved for post-mortem forensics and debug purposes.\n"
347
+
"Never enable this mode if you do not know what you are doing!\n";
342
348
343
-
seq_printf(s, "%s\n", mtd->dbg.partid);
344
-
345
-
return 0;
349
+
return WARN_ONCE(mtd_expert_analysis_mode, mtd_expert_analysis_warning);
346
350
}
347
-
348
-
DEFINE_SHOW_ATTRIBUTE(mtd_partid_debug);
349
-
350
-
static int mtd_partname_debug_show(struct seq_file *s, void *p)
351
-
{
352
-
struct mtd_info *mtd = s->private;
353
-
354
-
seq_printf(s, "%s\n", mtd->dbg.partname);
355
-
356
-
return 0;
357
-
}
358
-
359
-
DEFINE_SHOW_ATTRIBUTE(mtd_partname_debug);
351
+
EXPORT_SYMBOL_GPL(mtd_check_expert_analysis_mode);
352
+
#endif
360
353
361
354
static struct dentry *dfs_dir_mtd;
362
355
363
356
static void mtd_debugfs_populate(struct mtd_info *mtd)
364
357
{
365
-
struct mtd_info *master = mtd_get_master(mtd);
366
358
struct device *dev = &mtd->dev;
367
-
struct dentry *root;
368
359
369
360
if (IS_ERR_OR_NULL(dfs_dir_mtd))
370
361
return;
371
362
372
-
root = debugfs_create_dir(dev_name(dev), dfs_dir_mtd);
373
-
mtd->dbg.dfs_dir = root;
374
-
375
-
if (master->dbg.partid)
376
-
debugfs_create_file("partid", 0400, root, master,
377
-
&mtd_partid_debug_fops);
378
-
379
-
if (master->dbg.partname)
380
-
debugfs_create_file("partname", 0400, root, master,
381
-
&mtd_partname_debug_fops);
363
+
mtd->dbg.dfs_dir = debugfs_create_dir(dev_name(dev), dfs_dir_mtd);
382
364
}
383
365
384
366
#ifndef CONFIG_MMU
···
2353
2371
2354
2372
return ret ? ERR_PTR(ret) : bdi;
2355
2373
}
2356
-
2357
-
char *mtd_expert_analysis_warning =
2358
-
"Bad block checks have been entirely disabled.\n"
2359
-
"This is only reserved for post-mortem forensics and debug purposes.\n"
2360
-
"Never enable this mode if you do not know what you are doing!\n";
2361
-
EXPORT_SYMBOL_GPL(mtd_expert_analysis_warning);
2362
-
bool mtd_expert_analysis_mode;
2363
-
EXPORT_SYMBOL_GPL(mtd_expert_analysis_mode);
2364
2374
2365
2375
static struct proc_dir_entry *proc_mtd;
2366
2376
+7
drivers/mtd/nand/Kconfig
+7
drivers/mtd/nand/Kconfig
···
46
46
ECC codes. They are used with NAND devices requiring more than 1 bit
47
47
of error correction.
48
48
49
+
config MTD_NAND_ECC_MXIC
50
+
bool "Macronix external hardware ECC engine"
51
+
depends on HAS_IOMEM
52
+
select MTD_NAND_ECC
53
+
help
54
+
This enables support for the hardware ECC engine from Macronix.
55
+
49
56
endmenu
50
57
51
58
endmenu
+1
drivers/mtd/nand/Makefile
+1
drivers/mtd/nand/Makefile
+8
-4
drivers/mtd/nand/core.c
+8
-4
drivers/mtd/nand/core.c
···
21
21
*/
22
22
bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos)
23
23
{
24
-
if (WARN_ONCE(mtd_expert_analysis_mode, mtd_expert_analysis_warning))
24
+
if (mtd_check_expert_analysis_mode())
25
25
return false;
26
26
27
27
if (nanddev_bbt_is_initialized(nand)) {
···
235
235
nand->ecc.engine = nand_ecc_get_on_die_hw_engine(nand);
236
236
break;
237
237
case NAND_ECC_ENGINE_TYPE_ON_HOST:
238
-
pr_err("On-host hardware ECC engines not supported yet\n");
238
+
nand->ecc.engine = nand_ecc_get_on_host_hw_engine(nand);
239
+
if (PTR_ERR(nand->ecc.engine) == -EPROBE_DEFER)
240
+
return -EPROBE_DEFER;
239
241
break;
240
242
default:
241
243
pr_err("Missing ECC engine type\n");
···
257
255
{
258
256
switch (nand->ecc.ctx.conf.engine_type) {
259
257
case NAND_ECC_ENGINE_TYPE_ON_HOST:
260
-
pr_err("On-host hardware ECC engines not supported yet\n");
258
+
nand_ecc_put_on_host_hw_engine(nand);
261
259
break;
262
260
case NAND_ECC_ENGINE_TYPE_NONE:
263
261
case NAND_ECC_ENGINE_TYPE_SOFT:
···
302
300
/* Look for the ECC engine to use */
303
301
ret = nanddev_get_ecc_engine(nand);
304
302
if (ret) {
305
-
pr_err("No ECC engine found\n");
303
+
if (ret != -EPROBE_DEFER)
304
+
pr_err("No ECC engine found\n");
305
+
306
306
return ret;
307
307
}
308
308
+879
drivers/mtd/nand/ecc-mxic.c
+879
drivers/mtd/nand/ecc-mxic.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Support for Macronix external hardware ECC engine for NAND devices, also
4
+
* called DPE for Data Processing Engine.
5
+
*
6
+
* Copyright © 2019 Macronix
7
+
* Author: Miquel Raynal <miquel.raynal@bootlin.com>
8
+
*/
9
+
10
+
#include <linux/dma-mapping.h>
11
+
#include <linux/init.h>
12
+
#include <linux/interrupt.h>
13
+
#include <linux/io.h>
14
+
#include <linux/iopoll.h>
15
+
#include <linux/kernel.h>
16
+
#include <linux/module.h>
17
+
#include <linux/mtd/mtd.h>
18
+
#include <linux/mtd/nand.h>
19
+
#include <linux/mtd/nand-ecc-mxic.h>
20
+
#include <linux/mutex.h>
21
+
#include <linux/of_device.h>
22
+
#include <linux/of_platform.h>
23
+
#include <linux/platform_device.h>
24
+
#include <linux/slab.h>
25
+
26
+
/* DPE Configuration */
27
+
#define DP_CONFIG 0x00
28
+
#define ECC_EN BIT(0)
29
+
#define ECC_TYP(idx) (((idx) << 3) & GENMASK(6, 3))
30
+
/* DPE Interrupt Status */
31
+
#define INTRPT_STS 0x04
32
+
#define TRANS_CMPLT BIT(0)
33
+
#define SDMA_MAIN BIT(1)
34
+
#define SDMA_SPARE BIT(2)
35
+
#define ECC_ERR BIT(3)
36
+
#define TO_SPARE BIT(4)
37
+
#define TO_MAIN BIT(5)
38
+
/* DPE Interrupt Status Enable */
39
+
#define INTRPT_STS_EN 0x08
40
+
/* DPE Interrupt Signal Enable */
41
+
#define INTRPT_SIG_EN 0x0C
42
+
/* Host Controller Configuration */
43
+
#define HC_CONFIG 0x10
44
+
#define DEV2MEM 0 /* TRANS_TYP_DMA in the spec */
45
+
#define MEM2MEM BIT(4) /* TRANS_TYP_IO in the spec */
46
+
#define MAPPING BIT(5) /* TRANS_TYP_MAPPING in the spec */
47
+
#define ECC_PACKED 0 /* LAYOUT_TYP_INTEGRATED in the spec */
48
+
#define ECC_INTERLEAVED BIT(2) /* LAYOUT_TYP_DISTRIBUTED in the spec */
49
+
#define BURST_TYP_FIXED 0
50
+
#define BURST_TYP_INCREASING BIT(0)
51
+
/* Host Controller Slave Address */
52
+
#define HC_SLV_ADDR 0x14
53
+
/* ECC Chunk Size */
54
+
#define CHUNK_SIZE 0x20
55
+
/* Main Data Size */
56
+
#define MAIN_SIZE 0x24
57
+
/* Spare Data Size */
58
+
#define SPARE_SIZE 0x28
59
+
#define META_SZ(reg) ((reg) & GENMASK(7, 0))
60
+
#define PARITY_SZ(reg) (((reg) & GENMASK(15, 8)) >> 8)
61
+
#define RSV_SZ(reg) (((reg) & GENMASK(23, 16)) >> 16)
62
+
#define SPARE_SZ(reg) ((reg) >> 24)
63
+
/* ECC Chunk Count */
64
+
#define CHUNK_CNT 0x30
65
+
/* SDMA Control */
66
+
#define SDMA_CTRL 0x40
67
+
#define WRITE_NAND 0
68
+
#define READ_NAND BIT(1)
69
+
#define CONT_NAND BIT(29)
70
+
#define CONT_SYSM BIT(30) /* Continue System Memory? */
71
+
#define SDMA_STRT BIT(31)
72
+
/* SDMA Address of Main Data */
73
+
#define SDMA_MAIN_ADDR 0x44
74
+
/* SDMA Address of Spare Data */
75
+
#define SDMA_SPARE_ADDR 0x48
76
+
/* DPE Version Number */
77
+
#define DP_VER 0xD0
78
+
#define DP_VER_OFFSET 16
79
+
80
+
/* Status bytes between each chunk of spare data */
81
+
#define STAT_BYTES 4
82
+
#define NO_ERR 0x00
83
+
#define MAX_CORR_ERR 0x28
84
+
#define UNCORR_ERR 0xFE
85
+
#define ERASED_CHUNK 0xFF
86
+
87
+
struct mxic_ecc_engine {
88
+
struct device *dev;
89
+
void __iomem *regs;
90
+
int irq;
91
+
struct completion complete;
92
+
struct nand_ecc_engine external_engine;
93
+
struct nand_ecc_engine pipelined_engine;
94
+
struct mutex lock;
95
+
};
96
+
97
+
struct mxic_ecc_ctx {
98
+
/* ECC machinery */
99
+
unsigned int data_step_sz;
100
+
unsigned int oob_step_sz;
101
+
unsigned int parity_sz;
102
+
unsigned int meta_sz;
103
+
u8 *status;
104
+
int steps;
105
+
106
+
/* DMA boilerplate */
107
+
struct nand_ecc_req_tweak_ctx req_ctx;
108
+
u8 *oobwithstat;
109
+
struct scatterlist sg[2];
110
+
struct nand_page_io_req *req;
111
+
unsigned int pageoffs;
112
+
};
113
+
114
+
static struct mxic_ecc_engine *ext_ecc_eng_to_mxic(struct nand_ecc_engine *eng)
115
+
{
116
+
return container_of(eng, struct mxic_ecc_engine, external_engine);
117
+
}
118
+
119
+
static struct mxic_ecc_engine *pip_ecc_eng_to_mxic(struct nand_ecc_engine *eng)
120
+
{
121
+
return container_of(eng, struct mxic_ecc_engine, pipelined_engine);
122
+
}
123
+
124
+
static struct mxic_ecc_engine *nand_to_mxic(struct nand_device *nand)
125
+
{
126
+
struct nand_ecc_engine *eng = nand->ecc.engine;
127
+
128
+
if (eng->integration == NAND_ECC_ENGINE_INTEGRATION_EXTERNAL)
129
+
return ext_ecc_eng_to_mxic(eng);
130
+
else
131
+
return pip_ecc_eng_to_mxic(eng);
132
+
}
133
+
134
+
static int mxic_ecc_ooblayout_ecc(struct mtd_info *mtd, int section,
135
+
struct mtd_oob_region *oobregion)
136
+
{
137
+
struct nand_device *nand = mtd_to_nanddev(mtd);
138
+
struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
139
+
140
+
if (section < 0 || section >= ctx->steps)
141
+
return -ERANGE;
142
+
143
+
oobregion->offset = (section * ctx->oob_step_sz) + ctx->meta_sz;
144
+
oobregion->length = ctx->parity_sz;
145
+
146
+
return 0;
147
+
}
148
+
149
+
static int mxic_ecc_ooblayout_free(struct mtd_info *mtd, int section,
150
+
struct mtd_oob_region *oobregion)
151
+
{
152
+
struct nand_device *nand = mtd_to_nanddev(mtd);
153
+
struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
154
+
155
+
if (section < 0 || section >= ctx->steps)
156
+
return -ERANGE;
157
+
158
+
if (!section) {
159
+
oobregion->offset = 2;
160
+
oobregion->length = ctx->meta_sz - 2;
161
+
} else {
162
+
oobregion->offset = section * ctx->oob_step_sz;
163
+
oobregion->length = ctx->meta_sz;
164
+
}
165
+
166
+
return 0;
167
+
}
168
+
169
+
static const struct mtd_ooblayout_ops mxic_ecc_ooblayout_ops = {
170
+
.ecc = mxic_ecc_ooblayout_ecc,
171
+
.free = mxic_ecc_ooblayout_free,
172
+
};
173
+
174
+
static void mxic_ecc_disable_engine(struct mxic_ecc_engine *mxic)
175
+
{
176
+
u32 reg;
177
+
178
+
reg = readl(mxic->regs + DP_CONFIG);
179
+
reg &= ~ECC_EN;
180
+
writel(reg, mxic->regs + DP_CONFIG);
181
+
}
182
+
183
+
static void mxic_ecc_enable_engine(struct mxic_ecc_engine *mxic)
184
+
{
185
+
u32 reg;
186
+
187
+
reg = readl(mxic->regs + DP_CONFIG);
188
+
reg |= ECC_EN;
189
+
writel(reg, mxic->regs + DP_CONFIG);
190
+
}
191
+
192
+
static void mxic_ecc_disable_int(struct mxic_ecc_engine *mxic)
193
+
{
194
+
writel(0, mxic->regs + INTRPT_SIG_EN);
195
+
}
196
+
197
+
static void mxic_ecc_enable_int(struct mxic_ecc_engine *mxic)
198
+
{
199
+
writel(TRANS_CMPLT, mxic->regs + INTRPT_SIG_EN);
200
+
}
201
+
202
+
static irqreturn_t mxic_ecc_isr(int irq, void *dev_id)
203
+
{
204
+
struct mxic_ecc_engine *mxic = dev_id;
205
+
u32 sts;
206
+
207
+
sts = readl(mxic->regs + INTRPT_STS);
208
+
if (!sts)
209
+
return IRQ_NONE;
210
+
211
+
if (sts & TRANS_CMPLT)
212
+
complete(&mxic->complete);
213
+
214
+
writel(sts, mxic->regs + INTRPT_STS);
215
+
216
+
return IRQ_HANDLED;
217
+
}
218
+
219
+
static int mxic_ecc_init_ctx(struct nand_device *nand, struct device *dev)
220
+
{
221
+
struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
222
+
struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
223
+
struct nand_ecc_props *reqs = &nand->ecc.requirements;
224
+
struct nand_ecc_props *user = &nand->ecc.user_conf;
225
+
struct mtd_info *mtd = nanddev_to_mtd(nand);
226
+
int step_size = 0, strength = 0, desired_correction = 0, steps, idx;
227
+
static const int possible_strength[] = {4, 8, 40, 48};
228
+
static const int spare_size[] = {32, 32, 96, 96};
229
+
struct mxic_ecc_ctx *ctx;
230
+
u32 spare_reg;
231
+
int ret;
232
+
233
+
ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
234
+
if (!ctx)
235
+
return -ENOMEM;
236
+
237
+
nand->ecc.ctx.priv = ctx;
238
+
239
+
/* Only large page NAND chips may use BCH */
240
+
if (mtd->oobsize < 64) {
241
+
pr_err("BCH cannot be used with small page NAND chips\n");
242
+
return -EINVAL;
243
+
}
244
+
245
+
mtd_set_ooblayout(mtd, &mxic_ecc_ooblayout_ops);
246
+
247
+
/* Enable all status bits */
248
+
writel(TRANS_CMPLT | SDMA_MAIN | SDMA_SPARE | ECC_ERR |
249
+
TO_SPARE | TO_MAIN, mxic->regs + INTRPT_STS_EN);
250
+
251
+
/* Configure the correction depending on the NAND device topology */
252
+
if (user->step_size && user->strength) {
253
+
step_size = user->step_size;
254
+
strength = user->strength;
255
+
} else if (reqs->step_size && reqs->strength) {
256
+
step_size = reqs->step_size;
257
+
strength = reqs->strength;
258
+
}
259
+
260
+
if (step_size && strength) {
261
+
steps = mtd->writesize / step_size;
262
+
desired_correction = steps * strength;
263
+
}
264
+
265
+
/* Step size is fixed to 1kiB, strength may vary (4 possible values) */
266
+
conf->step_size = SZ_1K;
267
+
steps = mtd->writesize / conf->step_size;
268
+
269
+
ctx->status = devm_kzalloc(dev, steps * sizeof(u8), GFP_KERNEL);
270
+
if (!ctx->status)
271
+
return -ENOMEM;
272
+
273
+
if (desired_correction) {
274
+
strength = desired_correction / steps;
275
+
276
+
for (idx = 0; idx < ARRAY_SIZE(possible_strength); idx++)
277
+
if (possible_strength[idx] >= strength)
278
+
break;
279
+
280
+
idx = min_t(unsigned int, idx,
281
+
ARRAY_SIZE(possible_strength) - 1);
282
+
} else {
283
+
/* Missing data, maximize the correction */
284
+
idx = ARRAY_SIZE(possible_strength) - 1;
285
+
}
286
+
287
+
/* Tune the selected strength until it fits in the OOB area */
288
+
for (; idx >= 0; idx--) {
289
+
if (spare_size[idx] * steps <= mtd->oobsize)
290
+
break;
291
+
}
292
+
293
+
/* This engine cannot be used with this NAND device */
294
+
if (idx < 0)
295
+
return -EINVAL;
296
+
297
+
/* Configure the engine for the desired strength */
298
+
writel(ECC_TYP(idx), mxic->regs + DP_CONFIG);
299
+
conf->strength = possible_strength[idx];
300
+
spare_reg = readl(mxic->regs + SPARE_SIZE);
301
+
302
+
ctx->steps = steps;
303
+
ctx->data_step_sz = mtd->writesize / steps;
304
+
ctx->oob_step_sz = mtd->oobsize / steps;
305
+
ctx->parity_sz = PARITY_SZ(spare_reg);
306
+
ctx->meta_sz = META_SZ(spare_reg);
307
+
308
+
/* Ensure buffers will contain enough bytes to store the STAT_BYTES */
309
+
ctx->req_ctx.oob_buffer_size = nanddev_per_page_oobsize(nand) +
310
+
(ctx->steps * STAT_BYTES);
311
+
ret = nand_ecc_init_req_tweaking(&ctx->req_ctx, nand);
312
+
if (ret)
313
+
return ret;
314
+
315
+
ctx->oobwithstat = kmalloc(mtd->oobsize + (ctx->steps * STAT_BYTES),
316
+
GFP_KERNEL);
317
+
if (!ctx->oobwithstat) {
318
+
ret = -ENOMEM;
319
+
goto cleanup_req_tweak;
320
+
}
321
+
322
+
sg_init_table(ctx->sg, 2);
323
+
324
+
/* Configuration dump and sanity checks */
325
+
dev_err(dev, "DPE version number: %d\n",
326
+
readl(mxic->regs + DP_VER) >> DP_VER_OFFSET);
327
+
dev_err(dev, "Chunk size: %d\n", readl(mxic->regs + CHUNK_SIZE));
328
+
dev_err(dev, "Main size: %d\n", readl(mxic->regs + MAIN_SIZE));
329
+
dev_err(dev, "Spare size: %d\n", SPARE_SZ(spare_reg));
330
+
dev_err(dev, "Rsv size: %ld\n", RSV_SZ(spare_reg));
331
+
dev_err(dev, "Parity size: %d\n", ctx->parity_sz);
332
+
dev_err(dev, "Meta size: %d\n", ctx->meta_sz);
333
+
334
+
if ((ctx->meta_sz + ctx->parity_sz + RSV_SZ(spare_reg)) !=
335
+
SPARE_SZ(spare_reg)) {
336
+
dev_err(dev, "Wrong OOB configuration: %d + %d + %ld != %d\n",
337
+
ctx->meta_sz, ctx->parity_sz, RSV_SZ(spare_reg),
338
+
SPARE_SZ(spare_reg));
339
+
ret = -EINVAL;
340
+
goto free_oobwithstat;
341
+
}
342
+
343
+
if (ctx->oob_step_sz != SPARE_SZ(spare_reg)) {
344
+
dev_err(dev, "Wrong OOB configuration: %d != %d\n",
345
+
ctx->oob_step_sz, SPARE_SZ(spare_reg));
346
+
ret = -EINVAL;
347
+
goto free_oobwithstat;
348
+
}
349
+
350
+
return 0;
351
+
352
+
free_oobwithstat:
353
+
kfree(ctx->oobwithstat);
354
+
cleanup_req_tweak:
355
+
nand_ecc_cleanup_req_tweaking(&ctx->req_ctx);
356
+
357
+
return ret;
358
+
}
359
+
360
+
static int mxic_ecc_init_ctx_external(struct nand_device *nand)
361
+
{
362
+
struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
363
+
struct device *dev = nand->ecc.engine->dev;
364
+
int ret;
365
+
366
+
dev_info(dev, "Macronix ECC engine in external mode\n");
367
+
368
+
ret = mxic_ecc_init_ctx(nand, dev);
369
+
if (ret)
370
+
return ret;
371
+
372
+
/* Trigger each step manually */
373
+
writel(1, mxic->regs + CHUNK_CNT);
374
+
writel(BURST_TYP_INCREASING | ECC_PACKED | MEM2MEM,
375
+
mxic->regs + HC_CONFIG);
376
+
377
+
return 0;
378
+
}
379
+
380
+
static int mxic_ecc_init_ctx_pipelined(struct nand_device *nand)
381
+
{
382
+
struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
383
+
struct mxic_ecc_ctx *ctx;
384
+
struct device *dev;
385
+
int ret;
386
+
387
+
dev = nand_ecc_get_engine_dev(nand->ecc.engine->dev);
388
+
if (!dev)
389
+
return -EINVAL;
390
+
391
+
dev_info(dev, "Macronix ECC engine in pipelined/mapping mode\n");
392
+
393
+
ret = mxic_ecc_init_ctx(nand, dev);
394
+
if (ret)
395
+
return ret;
396
+
397
+
ctx = nand_to_ecc_ctx(nand);
398
+
399
+
/* All steps should be handled in one go directly by the internal DMA */
400
+
writel(ctx->steps, mxic->regs + CHUNK_CNT);
401
+
402
+
/*
403
+
* Interleaved ECC scheme cannot be used otherwise factory bad block
404
+
* markers would be lost. A packed layout is mandatory.
405
+
*/
406
+
writel(BURST_TYP_INCREASING | ECC_PACKED | MAPPING,
407
+
mxic->regs + HC_CONFIG);
408
+
409
+
return 0;
410
+
}
411
+
412
+
static void mxic_ecc_cleanup_ctx(struct nand_device *nand)
413
+
{
414
+
struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
415
+
416
+
if (ctx) {
417
+
nand_ecc_cleanup_req_tweaking(&ctx->req_ctx);
418
+
kfree(ctx->oobwithstat);
419
+
}
420
+
}
421
+
422
+
static int mxic_ecc_data_xfer_wait_for_completion(struct mxic_ecc_engine *mxic)
423
+
{
424
+
u32 val;
425
+
int ret;
426
+
427
+
if (mxic->irq) {
428
+
reinit_completion(&mxic->complete);
429
+
mxic_ecc_enable_int(mxic);
430
+
ret = wait_for_completion_timeout(&mxic->complete,
431
+
msecs_to_jiffies(1000));
432
+
mxic_ecc_disable_int(mxic);
433
+
} else {
434
+
ret = readl_poll_timeout(mxic->regs + INTRPT_STS, val,
435
+
val & TRANS_CMPLT, 10, USEC_PER_SEC);
436
+
writel(val, mxic->regs + INTRPT_STS);
437
+
}
438
+
439
+
if (ret) {
440
+
dev_err(mxic->dev, "Timeout on data xfer completion\n");
441
+
return -ETIMEDOUT;
442
+
}
443
+
444
+
return 0;
445
+
}
446
+
447
+
static int mxic_ecc_process_data(struct mxic_ecc_engine *mxic,
448
+
unsigned int direction)
449
+
{
450
+
unsigned int dir = (direction == NAND_PAGE_READ) ?
451
+
READ_NAND : WRITE_NAND;
452
+
int ret;
453
+
454
+
mxic_ecc_enable_engine(mxic);
455
+
456
+
/* Trigger processing */
457
+
writel(SDMA_STRT | dir, mxic->regs + SDMA_CTRL);
458
+
459
+
/* Wait for completion */
460
+
ret = mxic_ecc_data_xfer_wait_for_completion(mxic);
461
+
462
+
mxic_ecc_disable_engine(mxic);
463
+
464
+
return ret;
465
+
}
466
+
467
+
int mxic_ecc_process_data_pipelined(struct nand_ecc_engine *eng,
468
+
unsigned int direction, dma_addr_t dirmap)
469
+
{
470
+
struct mxic_ecc_engine *mxic = pip_ecc_eng_to_mxic(eng);
471
+
472
+
if (dirmap)
473
+
writel(dirmap, mxic->regs + HC_SLV_ADDR);
474
+
475
+
return mxic_ecc_process_data(mxic, direction);
476
+
}
477
+
EXPORT_SYMBOL_GPL(mxic_ecc_process_data_pipelined);
478
+
479
+
static void mxic_ecc_extract_status_bytes(struct mxic_ecc_ctx *ctx)
480
+
{
481
+
u8 *buf = ctx->oobwithstat;
482
+
int next_stat_pos;
483
+
int step;
484
+
485
+
/* Extract the ECC status */
486
+
for (step = 0; step < ctx->steps; step++) {
487
+
next_stat_pos = ctx->oob_step_sz +
488
+
((STAT_BYTES + ctx->oob_step_sz) * step);
489
+
490
+
ctx->status[step] = buf[next_stat_pos];
491
+
}
492
+
}
493
+
494
+
static void mxic_ecc_reconstruct_oobbuf(struct mxic_ecc_ctx *ctx,
495
+
u8 *dst, const u8 *src)
496
+
{
497
+
int step;
498
+
499
+
/* Reconstruct the OOB buffer linearly (without the ECC status bytes) */
500
+
for (step = 0; step < ctx->steps; step++)
501
+
memcpy(dst + (step * ctx->oob_step_sz),
502
+
src + (step * (ctx->oob_step_sz + STAT_BYTES)),
503
+
ctx->oob_step_sz);
504
+
}
505
+
506
+
static void mxic_ecc_add_room_in_oobbuf(struct mxic_ecc_ctx *ctx,
507
+
u8 *dst, const u8 *src)
508
+
{
509
+
int step;
510
+
511
+
/* Add some space in the OOB buffer for the status bytes */
512
+
for (step = 0; step < ctx->steps; step++)
513
+
memcpy(dst + (step * (ctx->oob_step_sz + STAT_BYTES)),
514
+
src + (step * ctx->oob_step_sz),
515
+
ctx->oob_step_sz);
516
+
}
517
+
518
+
static int mxic_ecc_count_biterrs(struct mxic_ecc_engine *mxic,
519
+
struct nand_device *nand)
520
+
{
521
+
struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
522
+
struct mtd_info *mtd = nanddev_to_mtd(nand);
523
+
struct device *dev = mxic->dev;
524
+
unsigned int max_bf = 0;
525
+
bool failure = false;
526
+
int step;
527
+
528
+
for (step = 0; step < ctx->steps; step++) {
529
+
u8 stat = ctx->status[step];
530
+
531
+
if (stat == NO_ERR) {
532
+
dev_dbg(dev, "ECC step %d: no error\n", step);
533
+
} else if (stat == ERASED_CHUNK) {
534
+
dev_dbg(dev, "ECC step %d: erased\n", step);
535
+
} else if (stat == UNCORR_ERR || stat > MAX_CORR_ERR) {
536
+
dev_dbg(dev, "ECC step %d: uncorrectable\n", step);
537
+
mtd->ecc_stats.failed++;
538
+
failure = true;
539
+
} else {
540
+
dev_dbg(dev, "ECC step %d: %d bits corrected\n",
541
+
step, stat);
542
+
max_bf = max_t(unsigned int, max_bf, stat);
543
+
mtd->ecc_stats.corrected += stat;
544
+
}
545
+
}
546
+
547
+
return failure ? -EBADMSG : max_bf;
548
+
}
549
+
550
+
/* External ECC engine helpers */
551
+
static int mxic_ecc_prepare_io_req_external(struct nand_device *nand,
552
+
struct nand_page_io_req *req)
553
+
{
554
+
struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
555
+
struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
556
+
struct mtd_info *mtd = nanddev_to_mtd(nand);
557
+
int offset, nents, step, ret;
558
+
559
+
if (req->mode == MTD_OPS_RAW)
560
+
return 0;
561
+
562
+
nand_ecc_tweak_req(&ctx->req_ctx, req);
563
+
ctx->req = req;
564
+
565
+
if (req->type == NAND_PAGE_READ)
566
+
return 0;
567
+
568
+
mxic_ecc_add_room_in_oobbuf(ctx, ctx->oobwithstat,
569
+
ctx->req->oobbuf.out);
570
+
571
+
sg_set_buf(&ctx->sg[0], req->databuf.out, req->datalen);
572
+
sg_set_buf(&ctx->sg[1], ctx->oobwithstat,
573
+
req->ooblen + (ctx->steps * STAT_BYTES));
574
+
575
+
nents = dma_map_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
576
+
if (!nents)
577
+
return -EINVAL;
578
+
579
+
mutex_lock(&mxic->lock);
580
+
581
+
for (step = 0; step < ctx->steps; step++) {
582
+
writel(sg_dma_address(&ctx->sg[0]) + (step * ctx->data_step_sz),
583
+
mxic->regs + SDMA_MAIN_ADDR);
584
+
writel(sg_dma_address(&ctx->sg[1]) + (step * (ctx->oob_step_sz + STAT_BYTES)),
585
+
mxic->regs + SDMA_SPARE_ADDR);
586
+
ret = mxic_ecc_process_data(mxic, ctx->req->type);
587
+
if (ret)
588
+
break;
589
+
}
590
+
591
+
mutex_unlock(&mxic->lock);
592
+
593
+
dma_unmap_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
594
+
595
+
if (ret)
596
+
return ret;
597
+
598
+
/* Retrieve the calculated ECC bytes */
599
+
for (step = 0; step < ctx->steps; step++) {
600
+
offset = ctx->meta_sz + (step * ctx->oob_step_sz);
601
+
mtd_ooblayout_get_eccbytes(mtd,
602
+
(u8 *)ctx->req->oobbuf.out + offset,
603
+
ctx->oobwithstat + (step * STAT_BYTES),
604
+
step * ctx->parity_sz,
605
+
ctx->parity_sz);
606
+
}
607
+
608
+
return 0;
609
+
}
610
+
611
+
static int mxic_ecc_finish_io_req_external(struct nand_device *nand,
612
+
struct nand_page_io_req *req)
613
+
{
614
+
struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
615
+
struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
616
+
int nents, step, ret;
617
+
618
+
if (req->mode == MTD_OPS_RAW)
619
+
return 0;
620
+
621
+
if (req->type == NAND_PAGE_WRITE) {
622
+
nand_ecc_restore_req(&ctx->req_ctx, req);
623
+
return 0;
624
+
}
625
+
626
+
/* Copy the OOB buffer and add room for the ECC engine status bytes */
627
+
mxic_ecc_add_room_in_oobbuf(ctx, ctx->oobwithstat, ctx->req->oobbuf.in);
628
+
629
+
sg_set_buf(&ctx->sg[0], req->databuf.in, req->datalen);
630
+
sg_set_buf(&ctx->sg[1], ctx->oobwithstat,
631
+
req->ooblen + (ctx->steps * STAT_BYTES));
632
+
nents = dma_map_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
633
+
if (!nents)
634
+
return -EINVAL;
635
+
636
+
mutex_lock(&mxic->lock);
637
+
638
+
for (step = 0; step < ctx->steps; step++) {
639
+
writel(sg_dma_address(&ctx->sg[0]) + (step * ctx->data_step_sz),
640
+
mxic->regs + SDMA_MAIN_ADDR);
641
+
writel(sg_dma_address(&ctx->sg[1]) + (step * (ctx->oob_step_sz + STAT_BYTES)),
642
+
mxic->regs + SDMA_SPARE_ADDR);
643
+
ret = mxic_ecc_process_data(mxic, ctx->req->type);
644
+
if (ret)
645
+
break;
646
+
}
647
+
648
+
mutex_unlock(&mxic->lock);
649
+
650
+
dma_unmap_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
651
+
652
+
if (ret) {
653
+
nand_ecc_restore_req(&ctx->req_ctx, req);
654
+
return ret;
655
+
}
656
+
657
+
/* Extract the status bytes and reconstruct the buffer */
658
+
mxic_ecc_extract_status_bytes(ctx);
659
+
mxic_ecc_reconstruct_oobbuf(ctx, ctx->req->oobbuf.in, ctx->oobwithstat);
660
+
661
+
nand_ecc_restore_req(&ctx->req_ctx, req);
662
+
663
+
return mxic_ecc_count_biterrs(mxic, nand);
664
+
}
665
+
666
+
/* Pipelined ECC engine helpers */
667
+
static int mxic_ecc_prepare_io_req_pipelined(struct nand_device *nand,
668
+
struct nand_page_io_req *req)
669
+
{
670
+
struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
671
+
struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
672
+
int nents;
673
+
674
+
if (req->mode == MTD_OPS_RAW)
675
+
return 0;
676
+
677
+
nand_ecc_tweak_req(&ctx->req_ctx, req);
678
+
ctx->req = req;
679
+
680
+
/* Copy the OOB buffer and add room for the ECC engine status bytes */
681
+
mxic_ecc_add_room_in_oobbuf(ctx, ctx->oobwithstat, ctx->req->oobbuf.in);
682
+
683
+
sg_set_buf(&ctx->sg[0], req->databuf.in, req->datalen);
684
+
sg_set_buf(&ctx->sg[1], ctx->oobwithstat,
685
+
req->ooblen + (ctx->steps * STAT_BYTES));
686
+
687
+
nents = dma_map_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
688
+
if (!nents)
689
+
return -EINVAL;
690
+
691
+
mutex_lock(&mxic->lock);
692
+
693
+
writel(sg_dma_address(&ctx->sg[0]), mxic->regs + SDMA_MAIN_ADDR);
694
+
writel(sg_dma_address(&ctx->sg[1]), mxic->regs + SDMA_SPARE_ADDR);
695
+
696
+
return 0;
697
+
}
698
+
699
+
static int mxic_ecc_finish_io_req_pipelined(struct nand_device *nand,
700
+
struct nand_page_io_req *req)
701
+
{
702
+
struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
703
+
struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
704
+
int ret = 0;
705
+
706
+
if (req->mode == MTD_OPS_RAW)
707
+
return 0;
708
+
709
+
mutex_unlock(&mxic->lock);
710
+
711
+
dma_unmap_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
712
+
713
+
if (req->type == NAND_PAGE_READ) {
714
+
mxic_ecc_extract_status_bytes(ctx);
715
+
mxic_ecc_reconstruct_oobbuf(ctx, ctx->req->oobbuf.in,
716
+
ctx->oobwithstat);
717
+
ret = mxic_ecc_count_biterrs(mxic, nand);
718
+
}
719
+
720
+
nand_ecc_restore_req(&ctx->req_ctx, req);
721
+
722
+
return ret;
723
+
}
724
+
725
+
static struct nand_ecc_engine_ops mxic_ecc_engine_external_ops = {
726
+
.init_ctx = mxic_ecc_init_ctx_external,
727
+
.cleanup_ctx = mxic_ecc_cleanup_ctx,
728
+
.prepare_io_req = mxic_ecc_prepare_io_req_external,
729
+
.finish_io_req = mxic_ecc_finish_io_req_external,
730
+
};
731
+
732
+
static struct nand_ecc_engine_ops mxic_ecc_engine_pipelined_ops = {
733
+
.init_ctx = mxic_ecc_init_ctx_pipelined,
734
+
.cleanup_ctx = mxic_ecc_cleanup_ctx,
735
+
.prepare_io_req = mxic_ecc_prepare_io_req_pipelined,
736
+
.finish_io_req = mxic_ecc_finish_io_req_pipelined,
737
+
};
738
+
739
+
struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void)
740
+
{
741
+
return &mxic_ecc_engine_pipelined_ops;
742
+
}
743
+
EXPORT_SYMBOL_GPL(mxic_ecc_get_pipelined_ops);
744
+
745
+
static struct platform_device *
746
+
mxic_ecc_get_pdev(struct platform_device *spi_pdev)
747
+
{
748
+
struct platform_device *eng_pdev;
749
+
struct device_node *np;
750
+
751
+
/* Retrieve the nand-ecc-engine phandle */
752
+
np = of_parse_phandle(spi_pdev->dev.of_node, "nand-ecc-engine", 0);
753
+
if (!np)
754
+
return NULL;
755
+
756
+
/* Jump to the engine's device node */
757
+
eng_pdev = of_find_device_by_node(np);
758
+
of_node_put(np);
759
+
760
+
return eng_pdev;
761
+
}
762
+
763
+
void mxic_ecc_put_pipelined_engine(struct nand_ecc_engine *eng)
764
+
{
765
+
struct mxic_ecc_engine *mxic = pip_ecc_eng_to_mxic(eng);
766
+
767
+
platform_device_put(to_platform_device(mxic->dev));
768
+
}
769
+
EXPORT_SYMBOL_GPL(mxic_ecc_put_pipelined_engine);
770
+
771
+
struct nand_ecc_engine *
772
+
mxic_ecc_get_pipelined_engine(struct platform_device *spi_pdev)
773
+
{
774
+
struct platform_device *eng_pdev;
775
+
struct mxic_ecc_engine *mxic;
776
+
777
+
eng_pdev = mxic_ecc_get_pdev(spi_pdev);
778
+
if (!eng_pdev)
779
+
return ERR_PTR(-ENODEV);
780
+
781
+
mxic = platform_get_drvdata(eng_pdev);
782
+
if (!mxic) {
783
+
platform_device_put(eng_pdev);
784
+
return ERR_PTR(-EPROBE_DEFER);
785
+
}
786
+
787
+
return &mxic->pipelined_engine;
788
+
}
789
+
EXPORT_SYMBOL_GPL(mxic_ecc_get_pipelined_engine);
790
+
791
+
/*
792
+
* Only the external ECC engine is exported as the pipelined is SoC specific, so
793
+
* it is registered directly by the drivers that wrap it.
794
+
*/
795
+
static int mxic_ecc_probe(struct platform_device *pdev)
796
+
{
797
+
struct device *dev = &pdev->dev;
798
+
struct mxic_ecc_engine *mxic;
799
+
int ret;
800
+
801
+
mxic = devm_kzalloc(&pdev->dev, sizeof(*mxic), GFP_KERNEL);
802
+
if (!mxic)
803
+
return -ENOMEM;
804
+
805
+
mxic->dev = &pdev->dev;
806
+
807
+
/*
808
+
* Both memory regions for the ECC engine itself and the AXI slave
809
+
* address are mandatory.
810
+
*/
811
+
mxic->regs = devm_platform_ioremap_resource(pdev, 0);
812
+
if (IS_ERR(mxic->regs)) {
813
+
dev_err(&pdev->dev, "Missing memory region\n");
814
+
return PTR_ERR(mxic->regs);
815
+
}
816
+
817
+
mxic_ecc_disable_engine(mxic);
818
+
mxic_ecc_disable_int(mxic);
819
+
820
+
/* IRQ is optional yet much more efficient */
821
+
mxic->irq = platform_get_irq_byname_optional(pdev, "ecc-engine");
822
+
if (mxic->irq > 0) {
823
+
ret = devm_request_irq(&pdev->dev, mxic->irq, mxic_ecc_isr, 0,
824
+
"mxic-ecc", mxic);
825
+
if (ret)
826
+
return ret;
827
+
} else {
828
+
dev_info(dev, "Invalid or missing IRQ, fallback to polling\n");
829
+
mxic->irq = 0;
830
+
}
831
+
832
+
mutex_init(&mxic->lock);
833
+
834
+
/*
835
+
* In external mode, the device is the ECC engine. In pipelined mode,
836
+
* the device is the host controller. The device is used to match the
837
+
* right ECC engine based on the DT properties.
838
+
*/
839
+
mxic->external_engine.dev = &pdev->dev;
840
+
mxic->external_engine.integration = NAND_ECC_ENGINE_INTEGRATION_EXTERNAL;
841
+
mxic->external_engine.ops = &mxic_ecc_engine_external_ops;
842
+
843
+
nand_ecc_register_on_host_hw_engine(&mxic->external_engine);
844
+
845
+
platform_set_drvdata(pdev, mxic);
846
+
847
+
return 0;
848
+
}
849
+
850
+
static int mxic_ecc_remove(struct platform_device *pdev)
851
+
{
852
+
struct mxic_ecc_engine *mxic = platform_get_drvdata(pdev);
853
+
854
+
nand_ecc_unregister_on_host_hw_engine(&mxic->external_engine);
855
+
856
+
return 0;
857
+
}
858
+
859
+
static const struct of_device_id mxic_ecc_of_ids[] = {
860
+
{
861
+
.compatible = "mxicy,nand-ecc-engine-rev3",
862
+
},
863
+
{ /* sentinel */ },
864
+
};
865
+
MODULE_DEVICE_TABLE(of, mxic_ecc_of_ids);
866
+
867
+
static struct platform_driver mxic_ecc_driver = {
868
+
.driver = {
869
+
.name = "mxic-nand-ecc-engine",
870
+
.of_match_table = mxic_ecc_of_ids,
871
+
},
872
+
.probe = mxic_ecc_probe,
873
+
.remove = mxic_ecc_remove,
874
+
};
875
+
module_platform_driver(mxic_ecc_driver);
876
+
877
+
MODULE_LICENSE("GPL");
878
+
MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
879
+
MODULE_DESCRIPTION("Macronix NAND hardware ECC controller");
+119
drivers/mtd/nand/ecc.c
+119
drivers/mtd/nand/ecc.c
···
96
96
#include <linux/module.h>
97
97
#include <linux/mtd/nand.h>
98
98
#include <linux/slab.h>
99
+
#include <linux/of.h>
100
+
#include <linux/of_device.h>
101
+
#include <linux/of_platform.h>
102
+
103
+
static LIST_HEAD(on_host_hw_engines);
104
+
static DEFINE_MUTEX(on_host_hw_engines_mutex);
99
105
100
106
/**
101
107
* nand_ecc_init_ctx - Init the ECC engine context
···
616
610
return nand->ecc.ondie_engine;
617
611
}
618
612
EXPORT_SYMBOL(nand_ecc_get_on_die_hw_engine);
613
+
614
+
int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine)
615
+
{
616
+
struct nand_ecc_engine *item;
617
+
618
+
if (!engine)
619
+
return -EINVAL;
620
+
621
+
/* Prevent multiple registrations of one engine */
622
+
list_for_each_entry(item, &on_host_hw_engines, node)
623
+
if (item == engine)
624
+
return 0;
625
+
626
+
mutex_lock(&on_host_hw_engines_mutex);
627
+
list_add_tail(&engine->node, &on_host_hw_engines);
628
+
mutex_unlock(&on_host_hw_engines_mutex);
629
+
630
+
return 0;
631
+
}
632
+
EXPORT_SYMBOL(nand_ecc_register_on_host_hw_engine);
633
+
634
+
int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine)
635
+
{
636
+
if (!engine)
637
+
return -EINVAL;
638
+
639
+
mutex_lock(&on_host_hw_engines_mutex);
640
+
list_del(&engine->node);
641
+
mutex_unlock(&on_host_hw_engines_mutex);
642
+
643
+
return 0;
644
+
}
645
+
EXPORT_SYMBOL(nand_ecc_unregister_on_host_hw_engine);
646
+
647
+
static struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev)
648
+
{
649
+
struct nand_ecc_engine *item;
650
+
651
+
list_for_each_entry(item, &on_host_hw_engines, node)
652
+
if (item->dev == dev)
653
+
return item;
654
+
655
+
return NULL;
656
+
}
657
+
658
+
struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand)
659
+
{
660
+
struct nand_ecc_engine *engine = NULL;
661
+
struct device *dev = &nand->mtd.dev;
662
+
struct platform_device *pdev;
663
+
struct device_node *np;
664
+
665
+
if (list_empty(&on_host_hw_engines))
666
+
return NULL;
667
+
668
+
/* Check for an explicit nand-ecc-engine property */
669
+
np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0);
670
+
if (np) {
671
+
pdev = of_find_device_by_node(np);
672
+
if (!pdev)
673
+
return ERR_PTR(-EPROBE_DEFER);
674
+
675
+
engine = nand_ecc_match_on_host_hw_engine(&pdev->dev);
676
+
platform_device_put(pdev);
677
+
of_node_put(np);
678
+
679
+
if (!engine)
680
+
return ERR_PTR(-EPROBE_DEFER);
681
+
}
682
+
683
+
if (engine)
684
+
get_device(engine->dev);
685
+
686
+
return engine;
687
+
}
688
+
EXPORT_SYMBOL(nand_ecc_get_on_host_hw_engine);
689
+
690
+
void nand_ecc_put_on_host_hw_engine(struct nand_device *nand)
691
+
{
692
+
put_device(nand->ecc.engine->dev);
693
+
}
694
+
EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine);
695
+
696
+
/*
697
+
* In the case of a pipelined engine, the device registering the ECC
698
+
* engine is not necessarily the ECC engine itself but may be a host controller.
699
+
* It is then useful to provide a helper to retrieve the right device object
700
+
* which actually represents the ECC engine.
701
+
*/
702
+
struct device *nand_ecc_get_engine_dev(struct device *host)
703
+
{
704
+
struct platform_device *ecc_pdev;
705
+
struct device_node *np;
706
+
707
+
/*
708
+
* If the device node contains this property, it means we need to follow
709
+
* it in order to get the right ECC engine device we are looking for.
710
+
*/
711
+
np = of_parse_phandle(host->of_node, "nand-ecc-engine", 0);
712
+
if (!np)
713
+
return host;
714
+
715
+
ecc_pdev = of_find_device_by_node(np);
716
+
if (!ecc_pdev) {
717
+
of_node_put(np);
718
+
return NULL;
719
+
}
720
+
721
+
platform_device_put(ecc_pdev);
722
+
of_node_put(np);
723
+
724
+
return &ecc_pdev->dev;
725
+
}
619
726
620
727
MODULE_LICENSE("GPL");
621
728
MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
+6
-1
drivers/mtd/nand/onenand/generic.c
+6
-1
drivers/mtd/nand/onenand/generic.c
···
53
53
}
54
54
55
55
info->onenand.mmcontrol = pdata ? pdata->mmcontrol : NULL;
56
-
info->onenand.irq = platform_get_irq(pdev, 0);
56
+
57
+
err = platform_get_irq(pdev, 0);
58
+
if (err < 0)
59
+
goto out_iounmap;
60
+
61
+
info->onenand.irq = err;
57
62
58
63
info->mtd.dev.parent = &pdev->dev;
59
64
info->mtd.priv = &info->onenand;
+13
drivers/mtd/nand/raw/Kconfig
+13
drivers/mtd/nand/raw/Kconfig
···
209
209
originally designed for Set-Top Box but is used on various BCM7xxx,
210
210
BCM3xxx, BCM63xxx, iProc/Cygnus and more.
211
211
212
+
if MTD_NAND_BRCMNAND
213
+
214
+
config MTD_NAND_BRCMNAND_BCMA
215
+
tristate "Broadcom BCMA NAND controller"
216
+
depends on BCMA_NFLASH
217
+
depends on BCMA
218
+
help
219
+
Enables the BRCMNAND controller over BCMA on BCM47186/BCM5358 SoCs.
220
+
The glue driver will take care of performing the low-level I/O
221
+
operations to interface the BRCMNAND controller over the BCMA bus.
222
+
223
+
endif # MTD_NAND_BRCMNAND
224
+
212
225
config MTD_NAND_BCM47XXNFLASH
213
226
tristate "BCM4706 BCMA NAND controller"
214
227
depends on BCMA_NFLASH
+13
-5
drivers/mtd/nand/raw/atmel/nand-controller.c
+13
-5
drivers/mtd/nand/raw/atmel/nand-controller.c
···
1938
1938
.nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16,
1939
1939
};
1940
1940
1941
-
static const struct of_device_id atmel_ebi_csa_regmap_of_ids[] = {
1941
+
static const struct of_device_id __maybe_unused atmel_ebi_csa_regmap_of_ids[] = {
1942
1942
{
1943
1943
.compatible = "atmel,at91sam9260-matrix",
1944
1944
.data = &at91sam9260_ebi_csa,
···
2060
2060
nc->mck = of_clk_get(dev->parent->of_node, 0);
2061
2061
if (IS_ERR(nc->mck)) {
2062
2062
dev_err(dev, "Failed to retrieve MCK clk\n");
2063
-
return PTR_ERR(nc->mck);
2063
+
ret = PTR_ERR(nc->mck);
2064
+
goto out_release_dma;
2064
2065
}
2065
2066
2066
2067
np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2067
2068
if (!np) {
2068
2069
dev_err(dev, "Missing or invalid atmel,smc property\n");
2069
-
return -EINVAL;
2070
+
ret = -EINVAL;
2071
+
goto out_release_dma;
2070
2072
}
2071
2073
2072
2074
nc->smc = syscon_node_to_regmap(np);
···
2076
2074
if (IS_ERR(nc->smc)) {
2077
2075
ret = PTR_ERR(nc->smc);
2078
2076
dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
2079
-
return ret;
2077
+
goto out_release_dma;
2080
2078
}
2081
2079
2082
2080
return 0;
2081
+
2082
+
out_release_dma:
2083
+
if (nc->dmac)
2084
+
dma_release_channel(nc->dmac);
2085
+
2086
+
return ret;
2083
2087
}
2084
2088
2085
2089
static int
···
2656
2648
static struct platform_driver atmel_nand_controller_driver = {
2657
2649
.driver = {
2658
2650
.name = "atmel-nand-controller",
2659
-
.of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
2651
+
.of_match_table = atmel_nand_controller_of_ids,
2660
2652
.pm = &atmel_nand_controller_pm_ops,
2661
2653
},
2662
2654
.probe = atmel_nand_controller_probe,
+2
-2
drivers/mtd/nand/raw/atmel/pmecc.c
+2
-2
drivers/mtd/nand/raw/atmel/pmecc.c
···
920
920
.correct_erased_chunks = true,
921
921
};
922
922
923
-
static const struct of_device_id atmel_pmecc_legacy_match[] = {
923
+
static const struct of_device_id __maybe_unused atmel_pmecc_legacy_match[] = {
924
924
{ .compatible = "atmel,sama5d4-nand", &sama5d4_caps },
925
925
{ .compatible = "atmel,sama5d2-nand", &sama5d2_caps },
926
926
{ /* sentinel */ }
···
1003
1003
static struct platform_driver atmel_pmecc_driver = {
1004
1004
.driver = {
1005
1005
.name = "atmel-pmecc",
1006
-
.of_match_table = of_match_ptr(atmel_pmecc_match),
1006
+
.of_match_table = atmel_pmecc_match,
1007
1007
},
1008
1008
.probe = atmel_pmecc_probe,
1009
1009
};
+2
drivers/mtd/nand/raw/brcmnand/Makefile
+2
drivers/mtd/nand/raw/brcmnand/Makefile
+132
drivers/mtd/nand/raw/brcmnand/bcma_nand.c
+132
drivers/mtd/nand/raw/brcmnand/bcma_nand.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright © 2021 Broadcom
4
+
*/
5
+
#include <linux/bcma/bcma.h>
6
+
#include <linux/bcma/bcma_driver_chipcommon.h>
7
+
#include <linux/device.h>
8
+
#include <linux/module.h>
9
+
#include <linux/platform_device.h>
10
+
11
+
#include "brcmnand.h"
12
+
13
+
struct brcmnand_bcma_soc {
14
+
struct brcmnand_soc soc;
15
+
struct bcma_drv_cc *cc;
16
+
};
17
+
18
+
static inline bool brcmnand_bcma_needs_swapping(u32 offset)
19
+
{
20
+
switch (offset) {
21
+
case BCMA_CC_NAND_SPARE_RD0:
22
+
case BCMA_CC_NAND_SPARE_RD4:
23
+
case BCMA_CC_NAND_SPARE_RD8:
24
+
case BCMA_CC_NAND_SPARE_RD12:
25
+
case BCMA_CC_NAND_SPARE_WR0:
26
+
case BCMA_CC_NAND_SPARE_WR4:
27
+
case BCMA_CC_NAND_SPARE_WR8:
28
+
case BCMA_CC_NAND_SPARE_WR12:
29
+
case BCMA_CC_NAND_DEVID:
30
+
case BCMA_CC_NAND_DEVID_X:
31
+
case BCMA_CC_NAND_SPARE_RD16:
32
+
case BCMA_CC_NAND_SPARE_RD20:
33
+
case BCMA_CC_NAND_SPARE_RD24:
34
+
case BCMA_CC_NAND_SPARE_RD28:
35
+
return true;
36
+
}
37
+
38
+
return false;
39
+
}
40
+
41
+
static inline struct brcmnand_bcma_soc *to_bcma_soc(struct brcmnand_soc *soc)
42
+
{
43
+
return container_of(soc, struct brcmnand_bcma_soc, soc);
44
+
}
45
+
46
+
static u32 brcmnand_bcma_read_reg(struct brcmnand_soc *soc, u32 offset)
47
+
{
48
+
struct brcmnand_bcma_soc *sc = to_bcma_soc(soc);
49
+
u32 val;
50
+
51
+
/* Offset into the NAND block and deal with the flash cache separately */
52
+
if (offset == BRCMNAND_NON_MMIO_FC_ADDR)
53
+
offset = BCMA_CC_NAND_CACHE_DATA;
54
+
else
55
+
offset += BCMA_CC_NAND_REVISION;
56
+
57
+
val = bcma_cc_read32(sc->cc, offset);
58
+
59
+
/* Swap if necessary */
60
+
if (brcmnand_bcma_needs_swapping(offset))
61
+
val = be32_to_cpu((__force __be32)val);
62
+
return val;
63
+
}
64
+
65
+
static void brcmnand_bcma_write_reg(struct brcmnand_soc *soc, u32 val,
66
+
u32 offset)
67
+
{
68
+
struct brcmnand_bcma_soc *sc = to_bcma_soc(soc);
69
+
70
+
/* Offset into the NAND block */
71
+
if (offset == BRCMNAND_NON_MMIO_FC_ADDR)
72
+
offset = BCMA_CC_NAND_CACHE_DATA;
73
+
else
74
+
offset += BCMA_CC_NAND_REVISION;
75
+
76
+
/* Swap if necessary */
77
+
if (brcmnand_bcma_needs_swapping(offset))
78
+
val = (__force u32)cpu_to_be32(val);
79
+
80
+
bcma_cc_write32(sc->cc, offset, val);
81
+
}
82
+
83
+
static struct brcmnand_io_ops brcmnand_bcma_io_ops = {
84
+
.read_reg = brcmnand_bcma_read_reg,
85
+
.write_reg = brcmnand_bcma_write_reg,
86
+
};
87
+
88
+
static void brcmnand_bcma_prepare_data_bus(struct brcmnand_soc *soc, bool prepare,
89
+
bool is_param)
90
+
{
91
+
struct brcmnand_bcma_soc *sc = to_bcma_soc(soc);
92
+
93
+
/* Reset the cache address to ensure we are already accessing the
94
+
* beginning of a sub-page.
95
+
*/
96
+
bcma_cc_write32(sc->cc, BCMA_CC_NAND_CACHE_ADDR, 0);
97
+
}
98
+
99
+
static int brcmnand_bcma_nand_probe(struct platform_device *pdev)
100
+
{
101
+
struct bcma_nflash *nflash = dev_get_platdata(&pdev->dev);
102
+
struct brcmnand_bcma_soc *soc;
103
+
104
+
soc = devm_kzalloc(&pdev->dev, sizeof(*soc), GFP_KERNEL);
105
+
if (!soc)
106
+
return -ENOMEM;
107
+
108
+
soc->cc = container_of(nflash, struct bcma_drv_cc, nflash);
109
+
soc->soc.prepare_data_bus = brcmnand_bcma_prepare_data_bus;
110
+
soc->soc.ops = &brcmnand_bcma_io_ops;
111
+
112
+
if (soc->cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
113
+
dev_err(&pdev->dev, "Use bcm47xxnflash for 4706!\n");
114
+
return -ENODEV;
115
+
}
116
+
117
+
return brcmnand_probe(pdev, &soc->soc);
118
+
}
119
+
120
+
static struct platform_driver brcmnand_bcma_nand_driver = {
121
+
.probe = brcmnand_bcma_nand_probe,
122
+
.remove = brcmnand_remove,
123
+
.driver = {
124
+
.name = "bcma_brcmnand",
125
+
.pm = &brcmnand_pm_ops,
126
+
}
127
+
};
128
+
module_platform_driver(brcmnand_bcma_nand_driver);
129
+
130
+
MODULE_LICENSE("GPL v2");
131
+
MODULE_AUTHOR("Broadcom");
132
+
MODULE_DESCRIPTION("NAND controller driver glue for BCMA chips");
+109
-53
drivers/mtd/nand/raw/brcmnand/brcmnand.c
+109
-53
drivers/mtd/nand/raw/brcmnand/brcmnand.c
···
9
9
#include <linux/delay.h>
10
10
#include <linux/device.h>
11
11
#include <linux/platform_device.h>
12
+
#include <linux/platform_data/brcmnand.h>
12
13
#include <linux/err.h>
13
14
#include <linux/completion.h>
14
15
#include <linux/interrupt.h>
···
26
25
#include <linux/of.h>
27
26
#include <linux/of_platform.h>
28
27
#include <linux/slab.h>
28
+
#include <linux/static_key.h>
29
29
#include <linux/list.h>
30
30
#include <linux/log2.h>
31
31
···
209
207
210
208
struct brcmnand_host;
211
209
210
+
static DEFINE_STATIC_KEY_FALSE(brcmnand_soc_has_ops_key);
211
+
212
212
struct brcmnand_controller {
213
213
struct device *dev;
214
214
struct nand_controller controller;
215
215
void __iomem *nand_base;
216
216
void __iomem *nand_fc; /* flash cache */
217
217
void __iomem *flash_dma_base;
218
-
unsigned int irq;
218
+
int irq;
219
219
unsigned int dma_irq;
220
220
int nand_version;
221
221
···
596
592
INTFC_CTLR_READY = BIT(31),
597
593
};
598
594
595
+
static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl)
596
+
{
597
+
#if IS_ENABLED(CONFIG_MTD_NAND_BRCMNAND_BCMA)
598
+
return static_branch_unlikely(&brcmnand_soc_has_ops_key);
599
+
#else
600
+
return false;
601
+
#endif
602
+
}
603
+
599
604
static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
600
605
{
606
+
if (brcmnand_non_mmio_ops(ctrl))
607
+
return brcmnand_soc_read(ctrl->soc, offs);
601
608
return brcmnand_readl(ctrl->nand_base + offs);
602
609
}
603
610
604
611
static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
605
612
u32 val)
606
613
{
607
-
brcmnand_writel(val, ctrl->nand_base + offs);
614
+
if (brcmnand_non_mmio_ops(ctrl))
615
+
brcmnand_soc_write(ctrl->soc, val, offs);
616
+
else
617
+
brcmnand_writel(val, ctrl->nand_base + offs);
608
618
}
609
619
610
620
static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
···
784
766
785
767
static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
786
768
{
769
+
if (brcmnand_non_mmio_ops(ctrl))
770
+
return brcmnand_soc_read(ctrl->soc, BRCMNAND_NON_MMIO_FC_ADDR);
787
771
return __raw_readl(ctrl->nand_fc + word * 4);
788
772
}
789
773
790
774
static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
791
775
int word, u32 val)
792
776
{
793
-
__raw_writel(val, ctrl->nand_fc + word * 4);
777
+
if (brcmnand_non_mmio_ops(ctrl))
778
+
brcmnand_soc_write(ctrl->soc, val, BRCMNAND_NON_MMIO_FC_ADDR);
779
+
else
780
+
__raw_writel(val, ctrl->nand_fc + word * 4);
794
781
}
795
782
796
783
static inline void edu_writel(struct brcmnand_controller *ctrl,
···
920
897
921
898
static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
922
899
{
900
+
/* Kludge for the BCMA-based NAND controller which does not actually
901
+
* shift the command
902
+
*/
903
+
if (ctrl->nand_version == 0x0304 && brcmnand_non_mmio_ops(ctrl))
904
+
return 0;
905
+
923
906
if (ctrl->nand_version < 0x0602)
924
907
return 24;
925
908
return 0;
···
1621
1592
bool err = false;
1622
1593
int sts;
1623
1594
1624
-
if (mtd->oops_panic_write) {
1595
+
if (mtd->oops_panic_write || ctrl->irq < 0) {
1625
1596
/* switch to interrupt polling and PIO mode */
1626
1597
disable_ctrl_irqs(ctrl);
1627
1598
sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY,
···
2779
2750
.attach_chip = brcmnand_attach_chip,
2780
2751
};
2781
2752
2782
-
static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
2753
+
static int brcmnand_init_cs(struct brcmnand_host *host,
2754
+
const char * const *part_probe_types)
2783
2755
{
2784
2756
struct brcmnand_controller *ctrl = host->ctrl;
2785
-
struct platform_device *pdev = host->pdev;
2757
+
struct device *dev = ctrl->dev;
2786
2758
struct mtd_info *mtd;
2787
2759
struct nand_chip *chip;
2788
2760
int ret;
2789
2761
u16 cfg_offs;
2790
2762
2791
-
ret = of_property_read_u32(dn, "reg", &host->cs);
2792
-
if (ret) {
2793
-
dev_err(&pdev->dev, "can't get chip-select\n");
2794
-
return -ENXIO;
2795
-
}
2796
-
2797
2763
mtd = nand_to_mtd(&host->chip);
2798
2764
chip = &host->chip;
2799
2765
2800
-
nand_set_flash_node(chip, dn);
2801
2766
nand_set_controller_data(chip, host);
2802
-
mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
2767
+
mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d",
2803
2768
host->cs);
2804
2769
if (!mtd->name)
2805
2770
return -ENOMEM;
2806
2771
2807
2772
mtd->owner = THIS_MODULE;
2808
-
mtd->dev.parent = &pdev->dev;
2773
+
mtd->dev.parent = dev;
2809
2774
2810
2775
chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl;
2811
2776
chip->legacy.cmdfunc = brcmnand_cmdfunc;
···
2833
2810
if (ret)
2834
2811
return ret;
2835
2812
2836
-
ret = mtd_device_register(mtd, NULL, 0);
2813
+
ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
2837
2814
if (ret)
2838
2815
nand_cleanup(chip);
2839
2816
···
2937
2914
};
2938
2915
EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2939
2916
2940
-
static const struct of_device_id brcmnand_of_match[] = {
2917
+
static const struct of_device_id __maybe_unused brcmnand_of_match[] = {
2941
2918
{ .compatible = "brcm,brcmnand-v2.1" },
2942
2919
{ .compatible = "brcm,brcmnand-v2.2" },
2943
2920
{ .compatible = "brcm,brcmnand-v4.0" },
···
3002
2979
3003
2980
int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
3004
2981
{
2982
+
struct brcmnand_platform_data *pd = dev_get_platdata(&pdev->dev);
3005
2983
struct device *dev = &pdev->dev;
3006
2984
struct device_node *dn = dev->of_node, *child;
3007
2985
struct brcmnand_controller *ctrl;
2986
+
struct brcmnand_host *host;
3008
2987
struct resource *res;
3009
2988
int ret;
3010
2989
3011
-
/* We only support device-tree instantiation */
3012
-
if (!dn)
3013
-
return -ENODEV;
3014
-
3015
-
if (!of_match_node(brcmnand_of_match, dn))
2990
+
if (dn && !of_match_node(brcmnand_of_match, dn))
3016
2991
return -ENODEV;
3017
2992
3018
2993
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
···
3019
2998
3020
2999
dev_set_drvdata(dev, ctrl);
3021
3000
ctrl->dev = dev;
3001
+
ctrl->soc = soc;
3002
+
3003
+
/* Enable the static key if the soc provides I/O operations indicating
3004
+
* that a non-memory mapped IO access path must be used
3005
+
*/
3006
+
if (brcmnand_soc_has_ops(ctrl->soc))
3007
+
static_branch_enable(&brcmnand_soc_has_ops_key);
3022
3008
3023
3009
init_completion(&ctrl->done);
3024
3010
init_completion(&ctrl->dma_done);
···
3037
3009
/* NAND register range */
3038
3010
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3039
3011
ctrl->nand_base = devm_ioremap_resource(dev, res);
3040
-
if (IS_ERR(ctrl->nand_base))
3012
+
if (IS_ERR(ctrl->nand_base) && !brcmnand_soc_has_ops(soc))
3041
3013
return PTR_ERR(ctrl->nand_base);
3042
3014
3043
3015
/* Enable clock before using NAND registers */
···
3154
3126
}
3155
3127
3156
3128
/* IRQ */
3157
-
ctrl->irq = platform_get_irq(pdev, 0);
3158
-
if ((int)ctrl->irq < 0) {
3159
-
dev_err(dev, "no IRQ defined\n");
3160
-
ret = -ENODEV;
3161
-
goto err;
3162
-
}
3129
+
ctrl->irq = platform_get_irq_optional(pdev, 0);
3130
+
if (ctrl->irq > 0) {
3131
+
/*
3132
+
* Some SoCs integrate this controller (e.g., its interrupt bits) in
3133
+
* interesting ways
3134
+
*/
3135
+
if (soc) {
3136
+
ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
3137
+
DRV_NAME, ctrl);
3163
3138
3164
-
/*
3165
-
* Some SoCs integrate this controller (e.g., its interrupt bits) in
3166
-
* interesting ways
3167
-
*/
3168
-
if (soc) {
3169
-
ctrl->soc = soc;
3170
-
3171
-
ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
3172
-
DRV_NAME, ctrl);
3173
-
3174
-
/* Enable interrupt */
3175
-
ctrl->soc->ctlrdy_ack(ctrl->soc);
3176
-
ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
3177
-
} else {
3178
-
/* Use standard interrupt infrastructure */
3179
-
ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
3180
-
DRV_NAME, ctrl);
3181
-
}
3182
-
if (ret < 0) {
3183
-
dev_err(dev, "can't allocate IRQ %d: error %d\n",
3184
-
ctrl->irq, ret);
3185
-
goto err;
3139
+
/* Enable interrupt */
3140
+
ctrl->soc->ctlrdy_ack(ctrl->soc);
3141
+
ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
3142
+
} else {
3143
+
/* Use standard interrupt infrastructure */
3144
+
ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
3145
+
DRV_NAME, ctrl);
3146
+
}
3147
+
if (ret < 0) {
3148
+
dev_err(dev, "can't allocate IRQ %d: error %d\n",
3149
+
ctrl->irq, ret);
3150
+
goto err;
3151
+
}
3186
3152
}
3187
3153
3188
3154
for_each_available_child_of_node(dn, child) {
3189
3155
if (of_device_is_compatible(child, "brcm,nandcs")) {
3190
-
struct brcmnand_host *host;
3191
3156
3192
3157
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
3193
3158
if (!host) {
···
3191
3170
host->pdev = pdev;
3192
3171
host->ctrl = ctrl;
3193
3172
3194
-
ret = brcmnand_init_cs(host, child);
3173
+
ret = of_property_read_u32(child, "reg", &host->cs);
3174
+
if (ret) {
3175
+
dev_err(dev, "can't get chip-select\n");
3176
+
devm_kfree(dev, host);
3177
+
continue;
3178
+
}
3179
+
3180
+
nand_set_flash_node(&host->chip, child);
3181
+
3182
+
ret = brcmnand_init_cs(host, NULL);
3195
3183
if (ret) {
3196
3184
devm_kfree(dev, host);
3197
3185
continue; /* Try all chip-selects */
···
3209
3179
list_add_tail(&host->node, &ctrl->host_list);
3210
3180
}
3211
3181
}
3182
+
3183
+
if (!list_empty(&ctrl->host_list))
3184
+
return 0;
3185
+
3186
+
if (!pd) {
3187
+
ret = -ENODEV;
3188
+
goto err;
3189
+
}
3190
+
3191
+
/* If we got there we must have been probing via platform data */
3192
+
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
3193
+
if (!host) {
3194
+
ret = -ENOMEM;
3195
+
goto err;
3196
+
}
3197
+
host->pdev = pdev;
3198
+
host->ctrl = ctrl;
3199
+
host->cs = pd->chip_select;
3200
+
host->chip.ecc.size = pd->ecc_stepsize;
3201
+
host->chip.ecc.strength = pd->ecc_strength;
3202
+
3203
+
ret = brcmnand_init_cs(host, pd->part_probe_types);
3204
+
if (ret)
3205
+
goto err;
3206
+
3207
+
list_add_tail(&host->node, &ctrl->host_list);
3212
3208
3213
3209
/* No chip-selects could initialize properly */
3214
3210
if (list_empty(&ctrl->host_list)) {
+29
drivers/mtd/nand/raw/brcmnand/brcmnand.h
+29
drivers/mtd/nand/raw/brcmnand/brcmnand.h
···
11
11
12
12
struct platform_device;
13
13
struct dev_pm_ops;
14
+
struct brcmnand_io_ops;
15
+
16
+
/* Special register offset constant to intercept a non-MMIO access
17
+
* to the flash cache register space. This is intentionally large
18
+
* not to overlap with an existing offset.
19
+
*/
20
+
#define BRCMNAND_NON_MMIO_FC_ADDR 0xffffffff
14
21
15
22
struct brcmnand_soc {
16
23
bool (*ctlrdy_ack)(struct brcmnand_soc *soc);
17
24
void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en);
18
25
void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare,
19
26
bool is_param);
27
+
const struct brcmnand_io_ops *ops;
28
+
};
29
+
30
+
struct brcmnand_io_ops {
31
+
u32 (*read_reg)(struct brcmnand_soc *soc, u32 offset);
32
+
void (*write_reg)(struct brcmnand_soc *soc, u32 val, u32 offset);
20
33
};
21
34
22
35
static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc *soc,
···
69
56
__raw_writel(val, addr);
70
57
else
71
58
writel_relaxed(val, addr);
59
+
}
60
+
61
+
static inline bool brcmnand_soc_has_ops(struct brcmnand_soc *soc)
62
+
{
63
+
return soc && soc->ops && soc->ops->read_reg && soc->ops->write_reg;
64
+
}
65
+
66
+
static inline u32 brcmnand_soc_read(struct brcmnand_soc *soc, u32 offset)
67
+
{
68
+
return soc->ops->read_reg(soc, offset);
69
+
}
70
+
71
+
static inline void brcmnand_soc_write(struct brcmnand_soc *soc, u32 val,
72
+
u32 offset)
73
+
{
74
+
soc->ops->write_reg(soc, val, offset);
72
75
}
73
76
74
77
int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc);
+22
-5
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
+22
-5
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
···
644
644
* RDN_DELAY = ----------------------- {3}
645
645
* RP
646
646
*/
647
-
static void gpmi_nfc_compute_timings(struct gpmi_nand_data *this,
648
-
const struct nand_sdr_timings *sdr)
647
+
static int gpmi_nfc_compute_timings(struct gpmi_nand_data *this,
648
+
const struct nand_sdr_timings *sdr)
649
649
{
650
650
struct gpmi_nfc_hardware_timing *hw = &this->hw;
651
+
struct resources *r = &this->resources;
651
652
unsigned int dll_threshold_ps = this->devdata->max_chain_delay;
652
653
unsigned int period_ps, reference_period_ps;
653
654
unsigned int data_setup_cycles, data_hold_cycles, addr_setup_cycles;
···
657
656
int sample_delay_ps, sample_delay_factor;
658
657
u16 busy_timeout_cycles;
659
658
u8 wrn_dly_sel;
659
+
unsigned long clk_rate, min_rate;
660
660
661
661
if (sdr->tRC_min >= 30000) {
662
662
/* ONFI non-EDO modes [0-3] */
663
663
hw->clk_rate = 22000000;
664
+
min_rate = 0;
664
665
wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS;
665
666
} else if (sdr->tRC_min >= 25000) {
666
667
/* ONFI EDO mode 4 */
667
668
hw->clk_rate = 80000000;
669
+
min_rate = 22000000;
668
670
wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
669
671
} else {
670
672
/* ONFI EDO mode 5 */
671
673
hw->clk_rate = 100000000;
674
+
min_rate = 80000000;
672
675
wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
673
676
}
674
677
678
+
clk_rate = clk_round_rate(r->clock[0], hw->clk_rate);
679
+
if (clk_rate <= min_rate) {
680
+
dev_err(this->dev, "clock setting: expected %ld, got %ld\n",
681
+
hw->clk_rate, clk_rate);
682
+
return -ENOTSUPP;
683
+
}
684
+
685
+
hw->clk_rate = clk_rate;
675
686
/* SDR core timings are given in picoseconds */
676
687
period_ps = div_u64((u64)NSEC_PER_SEC * 1000, hw->clk_rate);
677
688
···
724
711
hw->ctrl1n |= BF_GPMI_CTRL1_RDN_DELAY(sample_delay_factor) |
725
712
BM_GPMI_CTRL1_DLL_ENABLE |
726
713
(use_half_period ? BM_GPMI_CTRL1_HALF_PERIOD : 0);
714
+
return 0;
727
715
}
728
716
729
717
static int gpmi_nfc_apply_timings(struct gpmi_nand_data *this)
···
780
766
{
781
767
struct gpmi_nand_data *this = nand_get_controller_data(chip);
782
768
const struct nand_sdr_timings *sdr;
769
+
int ret;
783
770
784
771
/* Retrieve required NAND timings */
785
772
sdr = nand_get_sdr_timings(conf);
786
773
if (IS_ERR(sdr))
787
774
return PTR_ERR(sdr);
788
775
789
-
/* Only MX6 GPMI controller can reach EDO timings */
790
-
if (sdr->tRC_min <= 25000 && !GPMI_IS_MX6(this))
776
+
/* Only MX28/MX6 GPMI controller can reach EDO timings */
777
+
if (sdr->tRC_min <= 25000 && !GPMI_IS_MX28(this) && !GPMI_IS_MX6(this))
791
778
return -ENOTSUPP;
792
779
793
780
/* Stop here if this call was just a check */
···
796
781
return 0;
797
782
798
783
/* Do the actual derivation of the controller timings */
799
-
gpmi_nfc_compute_timings(this, sdr);
784
+
ret = gpmi_nfc_compute_timings(this, sdr);
785
+
if (ret)
786
+
return ret;
800
787
801
788
this->hw.must_apply_timings = true;
802
789
+1
-1
drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
+1
-1
drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
+1
-1
drivers/mtd/nand/raw/ingenic/jz4780_bch.c
+1
-1
drivers/mtd/nand/raw/ingenic/jz4780_bch.c
+1
-1
drivers/mtd/nand/raw/mtk_ecc.c
+1
-1
drivers/mtd/nand/raw/mtk_ecc.c
+40
-43
drivers/mtd/nand/raw/nand_base.c
+40
-43
drivers/mtd/nand/raw/nand_base.c
···
321
321
if (nand_region_is_secured(chip, ofs, mtd->erasesize))
322
322
return -EIO;
323
323
324
-
if (WARN_ONCE(mtd_expert_analysis_mode, mtd_expert_analysis_warning))
324
+
if (mtd_check_expert_analysis_mode())
325
325
return 0;
326
326
327
327
if (chip->legacy.block_bad)
···
338
338
*
339
339
* Return: -EBUSY if the chip has been suspended, 0 otherwise
340
340
*/
341
-
static int nand_get_device(struct nand_chip *chip)
341
+
static void nand_get_device(struct nand_chip *chip)
342
342
{
343
-
mutex_lock(&chip->lock);
344
-
if (chip->suspended) {
343
+
/* Wait until the device is resumed. */
344
+
while (1) {
345
+
mutex_lock(&chip->lock);
346
+
if (!chip->suspended) {
347
+
mutex_lock(&chip->controller->lock);
348
+
return;
349
+
}
345
350
mutex_unlock(&chip->lock);
346
-
return -EBUSY;
347
-
}
348
-
mutex_lock(&chip->controller->lock);
349
351
350
-
return 0;
352
+
wait_event(chip->resume_wq, !chip->suspended);
353
+
}
351
354
}
352
355
353
356
/**
···
579
576
nand_erase_nand(chip, &einfo, 0);
580
577
581
578
/* Write bad block marker to OOB */
582
-
ret = nand_get_device(chip);
583
-
if (ret)
584
-
return ret;
579
+
nand_get_device(chip);
585
580
586
581
ret = nand_markbad_bbm(chip, ofs);
587
582
nand_release_device(chip);
···
3827
3826
ops->mode != MTD_OPS_RAW)
3828
3827
return -ENOTSUPP;
3829
3828
3830
-
ret = nand_get_device(chip);
3831
-
if (ret)
3832
-
return ret;
3829
+
nand_get_device(chip);
3833
3830
3834
3831
if (!ops->datbuf)
3835
3832
ret = nand_do_read_oob(chip, from, ops);
···
4414
4415
struct mtd_oob_ops *ops)
4415
4416
{
4416
4417
struct nand_chip *chip = mtd_to_nand(mtd);
4417
-
int ret;
4418
+
int ret = 0;
4418
4419
4419
4420
ops->retlen = 0;
4420
4421
4421
-
ret = nand_get_device(chip);
4422
-
if (ret)
4423
-
return ret;
4422
+
nand_get_device(chip);
4424
4423
4425
4424
switch (ops->mode) {
4426
4425
case MTD_OPS_PLACE_OOB:
···
4478
4481
return -EIO;
4479
4482
4480
4483
/* Grab the lock and see if the device is available */
4481
-
ret = nand_get_device(chip);
4482
-
if (ret)
4483
-
return ret;
4484
+
nand_get_device(chip);
4484
4485
4485
4486
/* Shift to get first page */
4486
4487
page = (int)(instr->addr >> chip->page_shift);
···
4565
4570
pr_debug("%s: called\n", __func__);
4566
4571
4567
4572
/* Grab the lock and see if the device is available */
4568
-
WARN_ON(nand_get_device(chip));
4573
+
nand_get_device(chip);
4569
4574
/* Release it and go back */
4570
4575
nand_release_device(chip);
4571
4576
}
···
4582
4587
int ret;
4583
4588
4584
4589
/* Select the NAND device */
4585
-
ret = nand_get_device(chip);
4586
-
if (ret)
4587
-
return ret;
4590
+
nand_get_device(chip);
4588
4591
4589
4592
nand_select_target(chip, chipnr);
4590
4593
···
4653
4660
__func__);
4654
4661
}
4655
4662
mutex_unlock(&chip->lock);
4663
+
4664
+
wake_up_all(&chip->resume_wq);
4656
4665
}
4657
4666
4658
4667
/**
···
5269
5274
user_conf->placement = of_get_rawnand_ecc_placement_legacy(dn);
5270
5275
}
5271
5276
5272
-
static int of_get_nand_bus_width(struct device_node *np)
5277
+
static int of_get_nand_bus_width(struct nand_chip *chip)
5273
5278
{
5279
+
struct device_node *dn = nand_get_flash_node(chip);
5274
5280
u32 val;
5281
+
int ret;
5275
5282
5276
-
if (of_property_read_u32(np, "nand-bus-width", &val))
5277
-
return 8;
5283
+
ret = of_property_read_u32(dn, "nand-bus-width", &val);
5284
+
if (ret == -EINVAL)
5285
+
/* Buswidth defaults to 8 if the property does not exist .*/
5286
+
return 0;
5287
+
else if (ret)
5288
+
return ret;
5278
5289
5279
-
switch (val) {
5280
-
case 8:
5281
-
case 16:
5282
-
return val;
5283
-
default:
5284
-
return -EIO;
5285
-
}
5286
-
}
5287
-
5288
-
static bool of_get_nand_on_flash_bbt(struct device_node *np)
5289
-
{
5290
-
return of_property_read_bool(np, "nand-on-flash-bbt");
5290
+
if (val == 16)
5291
+
chip->options |= NAND_BUSWIDTH_16;
5292
+
else if (val != 8)
5293
+
return -EINVAL;
5294
+
return 0;
5291
5295
}
5292
5296
5293
5297
static int of_get_nand_secure_regions(struct nand_chip *chip)
···
5362
5368
{
5363
5369
struct nand_device *nand = mtd_to_nanddev(nand_to_mtd(chip));
5364
5370
struct device_node *dn = nand_get_flash_node(chip);
5371
+
int ret;
5365
5372
5366
5373
if (!dn)
5367
5374
return 0;
5368
5375
5369
-
if (of_get_nand_bus_width(dn) == 16)
5370
-
chip->options |= NAND_BUSWIDTH_16;
5376
+
ret = of_get_nand_bus_width(chip);
5377
+
if (ret)
5378
+
return ret;
5371
5379
5372
5380
if (of_property_read_bool(dn, "nand-is-boot-medium"))
5373
5381
chip->options |= NAND_IS_BOOT_MEDIUM;
5374
5382
5375
-
if (of_get_nand_on_flash_bbt(dn))
5383
+
if (of_property_read_bool(dn, "nand-on-flash-bbt"))
5376
5384
chip->bbt_options |= NAND_BBT_USE_FLASH;
5377
5385
5378
5386
of_get_nand_ecc_user_config(nand);
···
5433
5437
chip->cur_cs = -1;
5434
5438
5435
5439
mutex_init(&chip->lock);
5440
+
init_waitqueue_head(&chip->resume_wq);
5436
5441
5437
5442
/* Enforce the right timings for reset/detection */
5438
5443
chip->current_interface_config = nand_get_reset_interface_config();
+1
-1
drivers/mtd/nand/raw/nand_bbt.c
+1
-1
drivers/mtd/nand/raw/nand_bbt.c
···
1455
1455
pr_debug("nand_isbad_bbt(): bbt info for offs 0x%08x: (block %d) 0x%02x\n",
1456
1456
(unsigned int)offs, block, res);
1457
1457
1458
-
if (WARN_ONCE(mtd_expert_analysis_mode, mtd_expert_analysis_warning))
1458
+
if (mtd_check_expert_analysis_mode())
1459
1459
return 0;
1460
1460
1461
1461
switch (res) {
+18
-29
drivers/mtd/nand/raw/nandsim.c
+18
-29
drivers/mtd/nand/raw/nandsim.c
···
201
201
/* Calculate the OOB offset in flash RAM image by (row, column) address */
202
202
#define NS_RAW_OFFSET_OOB(ns) (NS_RAW_OFFSET(ns) + ns->geom.pgsz)
203
203
204
+
/* Calculate the byte shift in the next page to access */
205
+
#define NS_PAGE_BYTE_SHIFT(ns) ((ns)->regs.column + (ns)->regs.off)
206
+
204
207
/* After a command is input, the simulator goes to one of the following states */
205
208
#define STATE_CMD_READ0 0x00000001 /* read data from the beginning of page */
206
209
#define STATE_CMD_READ1 0x00000002 /* read data from the second half of page */
···
982
979
983
980
static int ns_setup_wear_reporting(struct mtd_info *mtd)
984
981
{
985
-
size_t mem;
986
-
987
982
wear_eb_count = div_u64(mtd->size, mtd->erasesize);
988
-
mem = wear_eb_count * sizeof(unsigned long);
989
-
if (mem / sizeof(unsigned long) != wear_eb_count) {
990
-
NS_ERR("Too many erase blocks for wear reporting\n");
991
-
return -ENOMEM;
992
-
}
993
-
erase_block_wear = kzalloc(mem, GFP_KERNEL);
983
+
erase_block_wear = kcalloc(wear_eb_count, sizeof(unsigned long), GFP_KERNEL);
994
984
if (!erase_block_wear) {
995
985
NS_ERR("Too many erase blocks for wear reporting\n");
996
986
return -ENOMEM;
···
1385
1389
*/
1386
1390
static inline u_char *NS_PAGE_BYTE_OFF(struct nandsim *ns)
1387
1391
{
1388
-
return NS_GET_PAGE(ns)->byte + ns->regs.column + ns->regs.off;
1392
+
return NS_GET_PAGE(ns)->byte + NS_PAGE_BYTE_SHIFT(ns);
1389
1393
}
1390
1394
1391
1395
static int ns_do_read_error(struct nandsim *ns, int num)
···
1411
1415
ns->buf.byte[pos / 8] ^= (1 << (pos % 8));
1412
1416
NS_WARN("read_page: flipping bit %d in page %d "
1413
1417
"reading from %d ecc: corrected=%u failed=%u\n",
1414
-
pos, ns->regs.row, ns->regs.column + ns->regs.off,
1418
+
pos, ns->regs.row, NS_PAGE_BYTE_SHIFT(ns),
1415
1419
nsmtd->ecc_stats.corrected, nsmtd->ecc_stats.failed);
1416
1420
}
1417
1421
}
···
1433
1437
ssize_t tx;
1434
1438
1435
1439
NS_DBG("read_page: page %d written, reading from %d\n",
1436
-
ns->regs.row, ns->regs.column + ns->regs.off);
1440
+
ns->regs.row, NS_PAGE_BYTE_SHIFT(ns));
1437
1441
if (ns_do_read_error(ns, num))
1438
1442
return;
1439
1443
pos = (loff_t)NS_RAW_OFFSET(ns) + ns->regs.off;
···
1454
1458
memset(ns->buf.byte, 0xFF, num);
1455
1459
} else {
1456
1460
NS_DBG("read_page: page %d allocated, reading from %d\n",
1457
-
ns->regs.row, ns->regs.column + ns->regs.off);
1461
+
ns->regs.row, NS_PAGE_BYTE_SHIFT(ns));
1458
1462
if (ns_do_read_error(ns, num))
1459
1463
return;
1460
1464
memcpy(ns->buf.byte, NS_PAGE_BYTE_OFF(ns), num);
···
1505
1509
int all;
1506
1510
1507
1511
NS_DBG("prog_page: writing page %d\n", ns->regs.row);
1508
-
pg_off = ns->file_buf + ns->regs.column + ns->regs.off;
1512
+
pg_off = ns->file_buf + NS_PAGE_BYTE_SHIFT(ns);
1509
1513
off = (loff_t)NS_RAW_OFFSET(ns) + ns->regs.off;
1510
1514
if (!test_bit(ns->regs.row, ns->pages_written)) {
1511
1515
all = 1;
···
1594
1598
NS_ERR("do_state_action: column number is too large\n");
1595
1599
break;
1596
1600
}
1597
-
num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1601
+
num = ns->geom.pgszoob - NS_PAGE_BYTE_SHIFT(ns);
1598
1602
ns_read_page(ns, num);
1599
1603
1600
1604
NS_DBG("do_state_action: (ACTION_CPY:) copy %d bytes to int buf, raw offset %d\n",
···
1662
1666
return -1;
1663
1667
}
1664
1668
1665
-
num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1669
+
num = ns->geom.pgszoob - NS_PAGE_BYTE_SHIFT(ns);
1666
1670
if (num != ns->regs.count) {
1667
1671
NS_ERR("do_state_action: too few bytes were input (%d instead of %d)\n",
1668
1672
ns->regs.count, num);
···
1734
1738
"state: %s, nxstate: %s\n",
1735
1739
ns_get_state_name(ns->state),
1736
1740
ns_get_state_name(ns->nxstate));
1737
-
1738
-
/* See, whether we need to do some action */
1739
-
if ((ns->state & ACTION_MASK) &&
1740
-
ns_do_state_action(ns, ns->state) < 0) {
1741
-
ns_switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1742
-
return;
1743
-
}
1744
-
1745
1741
} else {
1746
1742
/*
1747
1743
* We don't yet know which operation we perform.
···
1750
1762
1751
1763
if (ns_find_operation(ns, 0))
1752
1764
return;
1765
+
}
1753
1766
1754
-
if ((ns->state & ACTION_MASK) &&
1755
-
ns_do_state_action(ns, ns->state) < 0) {
1756
-
ns_switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1757
-
return;
1758
-
}
1767
+
/* See, whether we need to do some action */
1768
+
if ((ns->state & ACTION_MASK) &&
1769
+
ns_do_state_action(ns, ns->state) < 0) {
1770
+
ns_switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1771
+
return;
1759
1772
}
1760
1773
1761
1774
/* For 16x devices column means the page offset in words */
···
1806
1817
switch (NS_STATE(ns->state)) {
1807
1818
case STATE_DATAIN:
1808
1819
case STATE_DATAOUT:
1809
-
ns->regs.num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1820
+
ns->regs.num = ns->geom.pgszoob - NS_PAGE_BYTE_SHIFT(ns);
1810
1821
break;
1811
1822
1812
1823
case STATE_DATAOUT_ID:
+1
-1
drivers/mtd/nand/raw/omap2.c
+1
-1
drivers/mtd/nand/raw/omap2.c
+1
-3
drivers/mtd/nand/raw/omap_elm.c
+1
-3
drivers/mtd/nand/raw/omap_elm.c
···
282
282
static void elm_error_correction(struct elm_info *info,
283
283
struct elm_errorvec *err_vec)
284
284
{
285
-
int i, j, errors = 0;
285
+
int i, j;
286
286
int offset;
287
287
u32 reg_val;
288
288
···
312
312
/* Update error location register */
313
313
offset += 4;
314
314
}
315
-
316
-
errors += err_vec[i].error_count;
317
315
} else {
318
316
err_vec[i].error_uncorrectable = true;
319
317
}
+1
-1
drivers/mtd/nand/raw/pl35x-nand-controller.c
+1
-1
drivers/mtd/nand/raw/pl35x-nand-controller.c
···
1062
1062
chip->controller = &nfc->controller;
1063
1063
mtd = nand_to_mtd(chip);
1064
1064
mtd->dev.parent = nfc->dev;
1065
-
nand_set_flash_node(chip, nfc->dev->of_node);
1065
+
nand_set_flash_node(chip, np);
1066
1066
if (!mtd->name) {
1067
1067
mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
1068
1068
"%s", PL35X_NANDC_DRIVER_NAME);
+1
-1
drivers/mtd/nand/raw/renesas-nand-controller.c
+1
-1
drivers/mtd/nand/raw/renesas-nand-controller.c
-1
drivers/mtd/nand/raw/rockchip-nand-controller.c
-1
drivers/mtd/nand/raw/rockchip-nand-controller.c
+1
-1
drivers/mtd/nand/raw/sh_flctl.c
+1
-1
drivers/mtd/nand/raw/sh_flctl.c
+39
-1
drivers/mtd/nand/raw/stm32_fmc2_nand.c
+39
-1
drivers/mtd/nand/raw/stm32_fmc2_nand.c
···
9
9
#include <linux/dmaengine.h>
10
10
#include <linux/dma-mapping.h>
11
11
#include <linux/errno.h>
12
+
#include <linux/gpio/consumer.h>
12
13
#include <linux/interrupt.h>
13
14
#include <linux/iopoll.h>
14
15
#include <linux/mfd/syscon.h>
···
232
231
233
232
struct stm32_fmc2_nand {
234
233
struct nand_chip chip;
234
+
struct gpio_desc *wp_gpio;
235
235
struct stm32_fmc2_timings timings;
236
236
int ncs;
237
237
int cs_used[FMC2_MAX_CE];
···
1749
1747
.setup_interface = stm32_fmc2_nfc_setup_interface,
1750
1748
};
1751
1749
1750
+
static void stm32_fmc2_nfc_wp_enable(struct stm32_fmc2_nand *nand)
1751
+
{
1752
+
if (nand->wp_gpio)
1753
+
gpiod_set_value(nand->wp_gpio, 1);
1754
+
}
1755
+
1756
+
static void stm32_fmc2_nfc_wp_disable(struct stm32_fmc2_nand *nand)
1757
+
{
1758
+
if (nand->wp_gpio)
1759
+
gpiod_set_value(nand->wp_gpio, 0);
1760
+
}
1761
+
1752
1762
static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc,
1753
1763
struct device_node *dn)
1754
1764
{
···
1797
1783
1798
1784
nfc->cs_assigned |= BIT(cs);
1799
1785
nand->cs_used[i] = cs;
1786
+
}
1787
+
1788
+
nand->wp_gpio = devm_gpiod_get_from_of_node(nfc->dev, dn,
1789
+
"wp-gpios", 0,
1790
+
GPIOD_OUT_HIGH, "wp");
1791
+
if (IS_ERR(nand->wp_gpio)) {
1792
+
ret = PTR_ERR(nand->wp_gpio);
1793
+
if (ret != -ENOENT)
1794
+
return dev_err_probe(nfc->dev, ret,
1795
+
"failed to request WP GPIO\n");
1796
+
1797
+
nand->wp_gpio = NULL;
1800
1798
}
1801
1799
1802
1800
nand_set_flash_node(&nand->chip, dn);
···
1982
1956
chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
1983
1957
NAND_USES_DMA;
1984
1958
1959
+
stm32_fmc2_nfc_wp_disable(nand);
1960
+
1985
1961
/* Scan to find existence of the device */
1986
1962
ret = nand_scan(chip, nand->ncs);
1987
1963
if (ret)
1988
-
goto err_release_dma;
1964
+
goto err_wp_enable;
1989
1965
1990
1966
ret = mtd_device_register(mtd, NULL, 0);
1991
1967
if (ret)
···
1999
1971
2000
1972
err_nand_cleanup:
2001
1973
nand_cleanup(chip);
1974
+
1975
+
err_wp_enable:
1976
+
stm32_fmc2_nfc_wp_enable(nand);
2002
1977
2003
1978
err_release_dma:
2004
1979
if (nfc->dma_ecc_ch)
···
2043
2012
2044
2013
clk_disable_unprepare(nfc->clk);
2045
2014
2015
+
stm32_fmc2_nfc_wp_enable(nand);
2016
+
2046
2017
return 0;
2047
2018
}
2048
2019
2049
2020
static int __maybe_unused stm32_fmc2_nfc_suspend(struct device *dev)
2050
2021
{
2051
2022
struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev);
2023
+
struct stm32_fmc2_nand *nand = &nfc->nand;
2052
2024
2053
2025
clk_disable_unprepare(nfc->clk);
2026
+
2027
+
stm32_fmc2_nfc_wp_enable(nand);
2054
2028
2055
2029
pinctrl_pm_select_sleep_state(dev);
2056
2030
···
2077
2041
}
2078
2042
2079
2043
stm32_fmc2_nfc_init(nfc);
2044
+
2045
+
stm32_fmc2_nfc_wp_disable(nand);
2080
2046
2081
2047
for (chip_cs = 0; chip_cs < FMC2_MAX_CE; chip_cs++) {
2082
2048
if (!(nfc->cs_assigned & BIT(chip_cs)))
+41
-10
drivers/mtd/nand/spi/core.c
+41
-10
drivers/mtd/nand/spi/core.c
···
381
381
}
382
382
}
383
383
384
-
rdesc = spinand->dirmaps[req->pos.plane].rdesc;
384
+
if (req->mode == MTD_OPS_RAW)
385
+
rdesc = spinand->dirmaps[req->pos.plane].rdesc;
386
+
else
387
+
rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc;
385
388
386
389
while (nbytes) {
387
390
ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf);
···
455
452
req->ooblen);
456
453
}
457
454
458
-
wdesc = spinand->dirmaps[req->pos.plane].wdesc;
455
+
if (req->mode == MTD_OPS_RAW)
456
+
wdesc = spinand->dirmaps[req->pos.plane].wdesc;
457
+
else
458
+
wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc;
459
459
460
460
while (nbytes) {
461
461
ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf);
···
871
865
872
866
spinand->dirmaps[plane].rdesc = desc;
873
867
868
+
if (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) {
869
+
spinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc;
870
+
spinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc;
871
+
872
+
return 0;
873
+
}
874
+
875
+
info.op_tmpl = *spinand->op_templates.update_cache;
876
+
info.op_tmpl.data.ecc = true;
877
+
desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
878
+
spinand->spimem, &info);
879
+
if (IS_ERR(desc))
880
+
return PTR_ERR(desc);
881
+
882
+
spinand->dirmaps[plane].wdesc_ecc = desc;
883
+
884
+
info.op_tmpl = *spinand->op_templates.read_cache;
885
+
info.op_tmpl.data.ecc = true;
886
+
desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
887
+
spinand->spimem, &info);
888
+
if (IS_ERR(desc))
889
+
return PTR_ERR(desc);
890
+
891
+
spinand->dirmaps[plane].rdesc_ecc = desc;
892
+
874
893
return 0;
875
894
}
876
895
···
1239
1208
if (ret)
1240
1209
goto err_free_bufs;
1241
1210
1242
-
ret = spinand_create_dirmaps(spinand);
1243
-
if (ret) {
1244
-
dev_err(dev,
1245
-
"Failed to create direct mappings for read/write operations (err = %d)\n",
1246
-
ret);
1247
-
goto err_manuf_cleanup;
1248
-
}
1249
-
1250
1211
ret = nanddev_init(nand, &spinand_ops, THIS_MODULE);
1251
1212
if (ret)
1252
1213
goto err_manuf_cleanup;
···
1272
1249
/* Propagate ECC information to mtd_info */
1273
1250
mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength;
1274
1251
mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size;
1252
+
1253
+
ret = spinand_create_dirmaps(spinand);
1254
+
if (ret) {
1255
+
dev_err(dev,
1256
+
"Failed to create direct mappings for read/write operations (err = %d)\n",
1257
+
ret);
1258
+
goto err_cleanup_ecc_engine;
1259
+
}
1275
1260
1276
1261
return 0;
1277
1262
+1
-1
drivers/mtd/nand/spi/macronix.c
+1
-1
drivers/mtd/nand/spi/macronix.c
···
20
20
21
21
static SPINAND_OP_VARIANTS(write_cache_variants,
22
22
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
23
-
SPINAND_PROG_LOAD(true, 0, NULL, 0));
23
+
SPINAND_PROG_LOAD(false, 0, NULL, 0));
24
24
25
25
static SPINAND_OP_VARIANTS(update_cache_variants,
26
26
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+1
-1
drivers/mtd/parsers/Kconfig
+1
-1
drivers/mtd/parsers/Kconfig
···
115
115
116
116
config MTD_PARSER_TRX
117
117
tristate "Parser for TRX format partitions"
118
-
depends on MTD && (BCM47XX || ARCH_BCM_5301X || ARCH_MEDIATEK || COMPILE_TEST)
118
+
depends on MTD && (BCM47XX || ARCH_BCM_5301X || ARCH_MEDIATEK || RALINK || COMPILE_TEST)
119
119
help
120
120
TRX is a firmware format used by Broadcom on their devices. It
121
121
may contain up to 3/4 partitions (depending on the version).
+42
-39
drivers/mtd/spi-nor/atmel.c
+42
-39
drivers/mtd/spi-nor/atmel.c
···
16
16
* is to unlock the whole flash array on startup. Therefore, we have to support
17
17
* exactly this operation.
18
18
*/
19
-
static int atmel_at25fs_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
19
+
static int at25fs_nor_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
20
20
{
21
21
return -EOPNOTSUPP;
22
22
}
23
23
24
-
static int atmel_at25fs_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
24
+
static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
25
25
{
26
26
int ret;
27
27
···
37
37
return ret;
38
38
}
39
39
40
-
static int atmel_at25fs_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
40
+
static int at25fs_nor_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
41
41
{
42
42
return -EOPNOTSUPP;
43
43
}
44
44
45
-
static const struct spi_nor_locking_ops atmel_at25fs_locking_ops = {
46
-
.lock = atmel_at25fs_lock,
47
-
.unlock = atmel_at25fs_unlock,
48
-
.is_locked = atmel_at25fs_is_locked,
45
+
static const struct spi_nor_locking_ops at25fs_nor_locking_ops = {
46
+
.lock = at25fs_nor_lock,
47
+
.unlock = at25fs_nor_unlock,
48
+
.is_locked = at25fs_nor_is_locked,
49
49
};
50
50
51
-
static void atmel_at25fs_late_init(struct spi_nor *nor)
51
+
static void at25fs_nor_late_init(struct spi_nor *nor)
52
52
{
53
-
nor->params->locking_ops = &atmel_at25fs_locking_ops;
53
+
nor->params->locking_ops = &at25fs_nor_locking_ops;
54
54
}
55
55
56
-
static const struct spi_nor_fixups atmel_at25fs_fixups = {
57
-
.late_init = atmel_at25fs_late_init,
56
+
static const struct spi_nor_fixups at25fs_nor_fixups = {
57
+
.late_init = at25fs_nor_late_init,
58
58
};
59
59
60
60
/**
61
-
* atmel_set_global_protection - Do a Global Protect or Unprotect command
61
+
* atmel_nor_set_global_protection - Do a Global Protect or Unprotect command
62
62
* @nor: pointer to 'struct spi_nor'
63
63
* @ofs: offset in bytes
64
64
* @len: len in bytes
···
66
66
*
67
67
* Return: 0 on success, -error otherwise.
68
68
*/
69
-
static int atmel_set_global_protection(struct spi_nor *nor, loff_t ofs,
70
-
uint64_t len, bool is_protect)
69
+
static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
70
+
uint64_t len, bool is_protect)
71
71
{
72
72
int ret;
73
73
u8 sr;
···
116
116
return spi_nor_write_sr(nor, nor->bouncebuf, 1);
117
117
}
118
118
119
-
static int atmel_global_protect(struct spi_nor *nor, loff_t ofs, uint64_t len)
119
+
static int atmel_nor_global_protect(struct spi_nor *nor, loff_t ofs,
120
+
uint64_t len)
120
121
{
121
-
return atmel_set_global_protection(nor, ofs, len, true);
122
+
return atmel_nor_set_global_protection(nor, ofs, len, true);
122
123
}
123
124
124
-
static int atmel_global_unprotect(struct spi_nor *nor, loff_t ofs, uint64_t len)
125
+
static int atmel_nor_global_unprotect(struct spi_nor *nor, loff_t ofs,
126
+
uint64_t len)
125
127
{
126
-
return atmel_set_global_protection(nor, ofs, len, false);
128
+
return atmel_nor_set_global_protection(nor, ofs, len, false);
127
129
}
128
130
129
-
static int atmel_is_global_protected(struct spi_nor *nor, loff_t ofs, uint64_t len)
131
+
static int atmel_nor_is_global_protected(struct spi_nor *nor, loff_t ofs,
132
+
uint64_t len)
130
133
{
131
134
int ret;
132
135
···
143
140
return ((nor->bouncebuf[0] & ATMEL_SR_GLOBAL_PROTECT_MASK) == ATMEL_SR_GLOBAL_PROTECT_MASK);
144
141
}
145
142
146
-
static const struct spi_nor_locking_ops atmel_global_protection_ops = {
147
-
.lock = atmel_global_protect,
148
-
.unlock = atmel_global_unprotect,
149
-
.is_locked = atmel_is_global_protected,
143
+
static const struct spi_nor_locking_ops atmel_nor_global_protection_ops = {
144
+
.lock = atmel_nor_global_protect,
145
+
.unlock = atmel_nor_global_unprotect,
146
+
.is_locked = atmel_nor_is_global_protected,
150
147
};
151
148
152
-
static void atmel_global_protection_late_init(struct spi_nor *nor)
149
+
static void atmel_nor_global_protection_late_init(struct spi_nor *nor)
153
150
{
154
-
nor->params->locking_ops = &atmel_global_protection_ops;
151
+
nor->params->locking_ops = &atmel_nor_global_protection_ops;
155
152
}
156
153
157
-
static const struct spi_nor_fixups atmel_global_protection_fixups = {
158
-
.late_init = atmel_global_protection_late_init,
154
+
static const struct spi_nor_fixups atmel_nor_global_protection_fixups = {
155
+
.late_init = atmel_nor_global_protection_late_init,
159
156
};
160
157
161
-
static const struct flash_info atmel_parts[] = {
158
+
static const struct flash_info atmel_nor_parts[] = {
162
159
/* Atmel -- some are (confusingly) marketed as "DataFlash" */
163
160
{ "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4)
164
161
FLAGS(SPI_NOR_HAS_LOCK)
165
162
NO_SFDP_FLAGS(SECT_4K)
166
-
.fixups = &atmel_at25fs_fixups },
163
+
.fixups = &at25fs_nor_fixups },
167
164
{ "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8)
168
165
FLAGS(SPI_NOR_HAS_LOCK)
169
166
NO_SFDP_FLAGS(SECT_4K)
170
-
.fixups = &atmel_at25fs_fixups },
167
+
.fixups = &at25fs_nor_fixups },
171
168
{ "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8)
172
169
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
173
170
NO_SFDP_FLAGS(SECT_4K)
174
-
.fixups = &atmel_global_protection_fixups },
171
+
.fixups = &atmel_nor_global_protection_fixups },
175
172
{ "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64)
176
173
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
177
174
NO_SFDP_FLAGS(SECT_4K)
178
-
.fixups = &atmel_global_protection_fixups },
175
+
.fixups = &atmel_nor_global_protection_fixups },
179
176
{ "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64)
180
177
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
181
178
NO_SFDP_FLAGS(SECT_4K)
182
-
.fixups = &atmel_global_protection_fixups },
179
+
.fixups = &atmel_nor_global_protection_fixups },
183
180
{ "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128)
184
181
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
185
182
NO_SFDP_FLAGS(SECT_4K)
186
-
.fixups = &atmel_global_protection_fixups },
183
+
.fixups = &atmel_nor_global_protection_fixups },
187
184
{ "at25sl321", INFO(0x1f4216, 0, 64 * 1024, 64)
188
185
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
189
186
{ "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8)
···
191
188
{ "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16)
192
189
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
193
190
NO_SFDP_FLAGS(SECT_4K)
194
-
.fixups = &atmel_global_protection_fixups },
191
+
.fixups = &atmel_nor_global_protection_fixups },
195
192
{ "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32)
196
193
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
197
194
NO_SFDP_FLAGS(SECT_4K)
198
-
.fixups = &atmel_global_protection_fixups },
195
+
.fixups = &atmel_nor_global_protection_fixups },
199
196
{ "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64)
200
197
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
201
198
NO_SFDP_FLAGS(SECT_4K)
202
-
.fixups = &atmel_global_protection_fixups },
199
+
.fixups = &atmel_nor_global_protection_fixups },
203
200
{ "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16)
204
201
NO_SFDP_FLAGS(SECT_4K) },
205
202
};
206
203
207
204
const struct spi_nor_manufacturer spi_nor_atmel = {
208
205
.name = "atmel",
209
-
.parts = atmel_parts,
210
-
.nparts = ARRAY_SIZE(atmel_parts),
206
+
.parts = atmel_nor_parts,
207
+
.nparts = ARRAY_SIZE(atmel_nor_parts),
211
208
};
+3
-3
drivers/mtd/spi-nor/catalyst.c
+3
-3
drivers/mtd/spi-nor/catalyst.c
···
8
8
9
9
#include "core.h"
10
10
11
-
static const struct flash_info catalyst_parts[] = {
11
+
static const struct flash_info catalyst_nor_parts[] = {
12
12
/* Catalyst / On Semiconductor -- non-JEDEC */
13
13
{ "cat25c11", CAT25_INFO(16, 8, 16, 1) },
14
14
{ "cat25c03", CAT25_INFO(32, 8, 16, 2) },
···
19
19
20
20
const struct spi_nor_manufacturer spi_nor_catalyst = {
21
21
.name = "catalyst",
22
-
.parts = catalyst_parts,
23
-
.nparts = ARRAY_SIZE(catalyst_parts),
22
+
.parts = catalyst_nor_parts,
23
+
.nparts = ARRAY_SIZE(catalyst_nor_parts),
24
24
};
+13
-2
drivers/mtd/spi-nor/controllers/aspeed-smc.c
+13
-2
drivers/mtd/spi-nor/controllers/aspeed-smc.c
···
769
769
struct device_node *child;
770
770
unsigned int cs;
771
771
int ret = -ENODEV;
772
+
bool found_one = false;
772
773
773
774
for_each_available_child_of_node(np, child) {
774
775
struct aspeed_smc_chip *chip;
···
828
827
* by of property.
829
828
*/
830
829
ret = spi_nor_scan(nor, NULL, &hwcaps);
831
-
if (ret)
832
-
break;
830
+
/*
831
+
* If we fail to scan the device it might not be present or
832
+
* broken. Don't fail the whole controller if others work.
833
+
*/
834
+
if (ret) {
835
+
if (found_one)
836
+
ret = 0;
837
+
838
+
devm_kfree(controller->dev, chip);
839
+
continue;
840
+
}
833
841
834
842
ret = aspeed_smc_chip_setup_finish(chip);
835
843
if (ret)
···
849
839
break;
850
840
851
841
controller->chips[cs] = chip;
842
+
found_one = true;
852
843
}
853
844
854
845
if (ret) {
+18
-250
drivers/mtd/spi-nor/core.c
+18
-250
drivers/mtd/spi-nor/core.c
···
157
157
return spi_mem_exec_op(nor->spimem, op);
158
158
}
159
159
160
-
static int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,
161
-
u8 *buf, size_t len)
160
+
int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,
161
+
u8 *buf, size_t len)
162
162
{
163
163
if (spi_nor_protocol_is_dtr(nor->reg_proto))
164
164
return -EOPNOTSUPP;
···
166
166
return nor->controller_ops->read_reg(nor, opcode, buf, len);
167
167
}
168
168
169
-
static int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
170
-
const u8 *buf, size_t len)
169
+
int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
170
+
const u8 *buf, size_t len)
171
171
{
172
172
if (spi_nor_protocol_is_dtr(nor->reg_proto))
173
173
return -EOPNOTSUPP;
···
413
413
}
414
414
415
415
/**
416
-
* spi_nor_read_fsr() - Read the Flag Status Register.
417
-
* @nor: pointer to 'struct spi_nor'
418
-
* @fsr: pointer to a DMA-able buffer where the value of the
419
-
* Flag Status Register will be written. Should be at least 2
420
-
* bytes.
421
-
*
422
-
* Return: 0 on success, -errno otherwise.
423
-
*/
424
-
static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
425
-
{
426
-
int ret;
427
-
428
-
if (nor->spimem) {
429
-
struct spi_mem_op op =
430
-
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0),
431
-
SPI_MEM_OP_NO_ADDR,
432
-
SPI_MEM_OP_NO_DUMMY,
433
-
SPI_MEM_OP_DATA_IN(1, fsr, 0));
434
-
435
-
if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
436
-
op.addr.nbytes = nor->params->rdsr_addr_nbytes;
437
-
op.dummy.nbytes = nor->params->rdsr_dummy;
438
-
/*
439
-
* We don't want to read only one byte in DTR mode. So,
440
-
* read 2 and then discard the second byte.
441
-
*/
442
-
op.data.nbytes = 2;
443
-
}
444
-
445
-
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
446
-
447
-
ret = spi_mem_exec_op(nor->spimem, &op);
448
-
} else {
449
-
ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr,
450
-
1);
451
-
}
452
-
453
-
if (ret)
454
-
dev_dbg(nor->dev, "error %d reading FSR\n", ret);
455
-
456
-
return ret;
457
-
}
458
-
459
-
/**
460
416
* spi_nor_read_cr() - Read the Configuration Register using the
461
417
* SPINOR_OP_RDCR (35h) command.
462
418
* @nor: pointer to 'struct spi_nor'
···
555
599
}
556
600
557
601
/**
558
-
* spi_nor_xread_sr() - Read the Status Register on S3AN flashes.
559
-
* @nor: pointer to 'struct spi_nor'.
560
-
* @sr: pointer to a DMA-able buffer where the value of the
561
-
* Status Register will be written.
562
-
*
563
-
* Return: 0 on success, -errno otherwise.
564
-
*/
565
-
int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)
566
-
{
567
-
int ret;
568
-
569
-
if (nor->spimem) {
570
-
struct spi_mem_op op =
571
-
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_XRDSR, 0),
572
-
SPI_MEM_OP_NO_ADDR,
573
-
SPI_MEM_OP_NO_DUMMY,
574
-
SPI_MEM_OP_DATA_IN(1, sr, 0));
575
-
576
-
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
577
-
578
-
ret = spi_mem_exec_op(nor->spimem, &op);
579
-
} else {
580
-
ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_XRDSR, sr,
581
-
1);
582
-
}
583
-
584
-
if (ret)
585
-
dev_dbg(nor->dev, "error %d reading XRDSR\n", ret);
586
-
587
-
return ret;
588
-
}
589
-
590
-
/**
591
-
* spi_nor_xsr_ready() - Query the Status Register of the S3AN flash to see if
592
-
* the flash is ready for new commands.
593
-
* @nor: pointer to 'struct spi_nor'.
594
-
*
595
-
* Return: 1 if ready, 0 if not ready, -errno on errors.
596
-
*/
597
-
static int spi_nor_xsr_ready(struct spi_nor *nor)
598
-
{
599
-
int ret;
600
-
601
-
ret = spi_nor_xread_sr(nor, nor->bouncebuf);
602
-
if (ret)
603
-
return ret;
604
-
605
-
return !!(nor->bouncebuf[0] & XSR_RDY);
606
-
}
607
-
608
-
/**
609
-
* spi_nor_clear_sr() - Clear the Status Register.
610
-
* @nor: pointer to 'struct spi_nor'.
611
-
*/
612
-
static void spi_nor_clear_sr(struct spi_nor *nor)
613
-
{
614
-
int ret;
615
-
616
-
if (nor->spimem) {
617
-
struct spi_mem_op op =
618
-
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0),
619
-
SPI_MEM_OP_NO_ADDR,
620
-
SPI_MEM_OP_NO_DUMMY,
621
-
SPI_MEM_OP_NO_DATA);
622
-
623
-
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
624
-
625
-
ret = spi_mem_exec_op(nor->spimem, &op);
626
-
} else {
627
-
ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR,
628
-
NULL, 0);
629
-
}
630
-
631
-
if (ret)
632
-
dev_dbg(nor->dev, "error %d clearing SR\n", ret);
633
-
}
634
-
635
-
/**
636
602
* spi_nor_sr_ready() - Query the Status Register to see if the flash is ready
637
603
* for new commands.
638
604
* @nor: pointer to 'struct spi_nor'.
639
605
*
640
606
* Return: 1 if ready, 0 if not ready, -errno on errors.
641
607
*/
642
-
static int spi_nor_sr_ready(struct spi_nor *nor)
643
-
{
644
-
int ret = spi_nor_read_sr(nor, nor->bouncebuf);
645
-
646
-
if (ret)
647
-
return ret;
648
-
649
-
if (nor->flags & SNOR_F_USE_CLSR &&
650
-
nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
651
-
if (nor->bouncebuf[0] & SR_E_ERR)
652
-
dev_err(nor->dev, "Erase Error occurred\n");
653
-
else
654
-
dev_err(nor->dev, "Programming Error occurred\n");
655
-
656
-
spi_nor_clear_sr(nor);
657
-
658
-
/*
659
-
* WEL bit remains set to one when an erase or page program
660
-
* error occurs. Issue a Write Disable command to protect
661
-
* against inadvertent writes that can possibly corrupt the
662
-
* contents of the memory.
663
-
*/
664
-
ret = spi_nor_write_disable(nor);
665
-
if (ret)
666
-
return ret;
667
-
668
-
return -EIO;
669
-
}
670
-
671
-
return !(nor->bouncebuf[0] & SR_WIP);
672
-
}
673
-
674
-
/**
675
-
* spi_nor_clear_fsr() - Clear the Flag Status Register.
676
-
* @nor: pointer to 'struct spi_nor'.
677
-
*/
678
-
static void spi_nor_clear_fsr(struct spi_nor *nor)
608
+
int spi_nor_sr_ready(struct spi_nor *nor)
679
609
{
680
610
int ret;
681
611
682
-
if (nor->spimem) {
683
-
struct spi_mem_op op =
684
-
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0),
685
-
SPI_MEM_OP_NO_ADDR,
686
-
SPI_MEM_OP_NO_DUMMY,
687
-
SPI_MEM_OP_NO_DATA);
688
-
689
-
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
690
-
691
-
ret = spi_mem_exec_op(nor->spimem, &op);
692
-
} else {
693
-
ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR,
694
-
NULL, 0);
695
-
}
696
-
697
-
if (ret)
698
-
dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
699
-
}
700
-
701
-
/**
702
-
* spi_nor_fsr_ready() - Query the Flag Status Register to see if the flash is
703
-
* ready for new commands.
704
-
* @nor: pointer to 'struct spi_nor'.
705
-
*
706
-
* Return: 1 if ready, 0 if not ready, -errno on errors.
707
-
*/
708
-
static int spi_nor_fsr_ready(struct spi_nor *nor)
709
-
{
710
-
int ret = spi_nor_read_fsr(nor, nor->bouncebuf);
711
-
612
+
ret = spi_nor_read_sr(nor, nor->bouncebuf);
712
613
if (ret)
713
614
return ret;
714
615
715
-
if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
716
-
if (nor->bouncebuf[0] & FSR_E_ERR)
717
-
dev_err(nor->dev, "Erase operation failed.\n");
718
-
else
719
-
dev_err(nor->dev, "Program operation failed.\n");
720
-
721
-
if (nor->bouncebuf[0] & FSR_PT_ERR)
722
-
dev_err(nor->dev,
723
-
"Attempted to modify a protected sector.\n");
724
-
725
-
spi_nor_clear_fsr(nor);
726
-
727
-
/*
728
-
* WEL bit remains set to one when an erase or page program
729
-
* error occurs. Issue a Write Disable command to protect
730
-
* against inadvertent writes that can possibly corrupt the
731
-
* contents of the memory.
732
-
*/
733
-
ret = spi_nor_write_disable(nor);
734
-
if (ret)
735
-
return ret;
736
-
737
-
return -EIO;
738
-
}
739
-
740
-
return !!(nor->bouncebuf[0] & FSR_READY);
616
+
return !(nor->bouncebuf[0] & SR_WIP);
741
617
}
742
618
743
619
/**
···
580
792
*/
581
793
static int spi_nor_ready(struct spi_nor *nor)
582
794
{
583
-
int sr, fsr;
795
+
/* Flashes might override the standard routine. */
796
+
if (nor->params->ready)
797
+
return nor->params->ready(nor);
584
798
585
-
if (nor->flags & SNOR_F_READY_XSR_RDY)
586
-
sr = spi_nor_xsr_ready(nor);
587
-
else
588
-
sr = spi_nor_sr_ready(nor);
589
-
if (sr < 0)
590
-
return sr;
591
-
fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
592
-
if (fsr < 0)
593
-
return fsr;
594
-
return sr && fsr;
799
+
return spi_nor_sr_ready(nor);
595
800
}
596
801
597
802
/**
···
2313
2532
{
2314
2533
int ret;
2315
2534
2316
-
if (nor->params->setup) {
2535
+
if (nor->params->setup)
2317
2536
ret = nor->params->setup(nor, hwcaps);
2318
-
if (ret)
2319
-
return ret;
2320
-
}
2537
+
else
2538
+
ret = spi_nor_default_setup(nor, hwcaps);
2539
+
if (ret)
2540
+
return ret;
2321
2541
2322
2542
return spi_nor_set_addr_width(nor);
2323
2543
}
···
2448
2666
2449
2667
if (flags & NO_CHIP_ERASE)
2450
2668
nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
2451
-
2452
-
if (flags & USE_CLSR)
2453
-
nor->flags |= SNOR_F_USE_CLSR;
2454
-
2455
-
if (flags & USE_FSR)
2456
-
nor->flags |= SNOR_F_USE_FSR;
2457
-
2458
-
/*
2459
-
* Make sure the XSR_RDY flag is set before calling
2460
-
* spi_nor_wait_till_ready(). Xilinx S3AN share MFR
2461
-
* with Atmel SPI NOR.
2462
-
*/
2463
-
if (flags & SPI_NOR_XSR_RDY)
2464
-
nor->flags |= SNOR_F_READY_XSR_RDY;
2465
2669
}
2466
2670
2467
2671
/**
···
2554
2786
2555
2787
params->quad_enable = spi_nor_sr2_bit1_quad_enable;
2556
2788
params->set_4byte_addr_mode = spansion_set_4byte_addr_mode;
2557
-
params->setup = spi_nor_default_setup;
2558
2789
params->otp.org = &info->otp_org;
2559
2790
2560
2791
/* Default to 16-bit Write Status (01h) Command */
···
2948
3181
mtd->flags = MTD_CAP_NORFLASH;
2949
3182
if (nor->info->flags & SPI_NOR_NO_ERASE)
2950
3183
mtd->flags |= MTD_NO_ERASE;
3184
+
else
3185
+
mtd->_erase = spi_nor_erase;
2951
3186
mtd->writesize = nor->params->writesize;
2952
3187
mtd->writebufsize = nor->params->page_size;
2953
3188
mtd->size = nor->params->size;
2954
-
mtd->_erase = spi_nor_erase;
2955
3189
mtd->_read = spi_nor_read;
2956
3190
/* Might be already set by some SST flashes. */
2957
3191
if (!mtd->_write)
+28
-42
drivers/mtd/spi-nor/core.h
+28
-42
drivers/mtd/spi-nor/core.h
···
12
12
#define SPI_NOR_MAX_ID_LEN 6
13
13
14
14
enum spi_nor_option_flags {
15
-
SNOR_F_USE_FSR = BIT(0),
16
-
SNOR_F_HAS_SR_TB = BIT(1),
17
-
SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
18
-
SNOR_F_READY_XSR_RDY = BIT(3),
19
-
SNOR_F_USE_CLSR = BIT(4),
20
-
SNOR_F_BROKEN_RESET = BIT(5),
21
-
SNOR_F_4B_OPCODES = BIT(6),
22
-
SNOR_F_HAS_4BAIT = BIT(7),
23
-
SNOR_F_HAS_LOCK = BIT(8),
24
-
SNOR_F_HAS_16BIT_SR = BIT(9),
25
-
SNOR_F_NO_READ_CR = BIT(10),
26
-
SNOR_F_HAS_SR_TB_BIT6 = BIT(11),
27
-
SNOR_F_HAS_4BIT_BP = BIT(12),
28
-
SNOR_F_HAS_SR_BP3_BIT6 = BIT(13),
29
-
SNOR_F_IO_MODE_EN_VOLATILE = BIT(14),
30
-
SNOR_F_SOFT_RESET = BIT(15),
31
-
SNOR_F_SWP_IS_VOLATILE = BIT(16),
15
+
SNOR_F_HAS_SR_TB = BIT(0),
16
+
SNOR_F_NO_OP_CHIP_ERASE = BIT(1),
17
+
SNOR_F_BROKEN_RESET = BIT(2),
18
+
SNOR_F_4B_OPCODES = BIT(3),
19
+
SNOR_F_HAS_4BAIT = BIT(4),
20
+
SNOR_F_HAS_LOCK = BIT(5),
21
+
SNOR_F_HAS_16BIT_SR = BIT(6),
22
+
SNOR_F_NO_READ_CR = BIT(7),
23
+
SNOR_F_HAS_SR_TB_BIT6 = BIT(8),
24
+
SNOR_F_HAS_4BIT_BP = BIT(9),
25
+
SNOR_F_HAS_SR_BP3_BIT6 = BIT(10),
26
+
SNOR_F_IO_MODE_EN_VOLATILE = BIT(11),
27
+
SNOR_F_SOFT_RESET = BIT(12),
28
+
SNOR_F_SWP_IS_VOLATILE = BIT(13),
32
29
};
33
30
34
31
struct spi_nor_read_command {
···
254
257
* @convert_addr: converts an absolute address into something the flash
255
258
* will understand. Particularly useful when pagesize is
256
259
* not a power-of-2.
257
-
* @setup: configures the SPI NOR memory. Useful for SPI NOR
258
-
* flashes that have peculiarities to the SPI NOR standard
259
-
* e.g. different opcodes, specific address calculation,
260
-
* page size, etc.
260
+
* @setup: (optional) configures the SPI NOR memory. Useful for
261
+
* SPI NOR flashes that have peculiarities to the SPI NOR
262
+
* standard e.g. different opcodes, specific address
263
+
* calculation, page size, etc.
264
+
* @ready: (optional) flashes might use a different mechanism
265
+
* than reading the status register to indicate they
266
+
* are ready for a new command
261
267
* @locking_ops: SPI NOR locking methods.
262
268
*/
263
269
struct spi_nor_flash_parameter {
···
282
282
int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
283
283
u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
284
284
int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
285
+
int (*ready)(struct spi_nor *nor);
285
286
286
287
const struct spi_nor_locking_ops *locking_ops;
287
288
};
···
346
345
* SPI_NOR_NO_ERASE: no erase command needed.
347
346
* NO_CHIP_ERASE: chip does not support chip erase.
348
347
* SPI_NOR_NO_FR: can't do fastread.
349
-
* USE_CLSR: use CLSR command.
350
-
* USE_FSR: use flag status register
351
-
* SPI_NOR_XSR_RDY: S3AN flashes have specific opcode to read the
352
-
* status register.
353
348
*
354
349
* @no_sfdp_flags: flags that indicate support that can be discovered via SFDP.
355
350
* Used when SFDP tables are not defined in the flash. These
···
396
399
#define SPI_NOR_NO_ERASE BIT(6)
397
400
#define NO_CHIP_ERASE BIT(7)
398
401
#define SPI_NOR_NO_FR BIT(8)
399
-
#define USE_CLSR BIT(9)
400
-
#define USE_FSR BIT(10)
401
-
#define SPI_NOR_XSR_RDY BIT(11)
402
402
403
403
u8 no_sfdp_flags;
404
404
#define SPI_NOR_SKIP_SFDP BIT(0)
···
451
457
.page_size = (_page_size), \
452
458
.addr_width = (_addr_width), \
453
459
.flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR, \
454
-
455
-
#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
456
-
.id = { \
457
-
((_jedec_id) >> 16) & 0xff, \
458
-
((_jedec_id) >> 8) & 0xff, \
459
-
(_jedec_id) & 0xff \
460
-
}, \
461
-
.id_len = 3, \
462
-
.sector_size = (8*_page_size), \
463
-
.n_sectors = (_n_sectors), \
464
-
.page_size = _page_size, \
465
-
.addr_width = 3, \
466
-
.flags = SPI_NOR_NO_FR | SPI_NOR_XSR_RDY,
467
460
468
461
#define OTP_INFO(_len, _n_regions, _base, _offset) \
469
462
.otp_org = { \
···
535
554
int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor);
536
555
int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor);
537
556
int spi_nor_read_sr(struct spi_nor *nor, u8 *sr);
557
+
int spi_nor_sr_ready(struct spi_nor *nor);
538
558
int spi_nor_read_cr(struct spi_nor *nor, u8 *cr);
539
559
int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len);
540
560
int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1);
541
561
int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr);
542
562
543
-
int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr);
544
563
ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
545
564
u8 *buf);
546
565
ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
···
579
598
void spi_nor_try_unlock_all(struct spi_nor *nor);
580
599
void spi_nor_set_mtd_locking_ops(struct spi_nor *nor);
581
600
void spi_nor_set_mtd_otp_ops(struct spi_nor *nor);
601
+
602
+
int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,
603
+
u8 *buf, size_t len);
604
+
int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
605
+
const u8 *buf, size_t len);
582
606
583
607
static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
584
608
{
+3
-3
drivers/mtd/spi-nor/eon.c
+3
-3
drivers/mtd/spi-nor/eon.c
···
8
8
9
9
#include "core.h"
10
10
11
-
static const struct flash_info eon_parts[] = {
11
+
static const struct flash_info eon_nor_parts[] = {
12
12
/* EON -- en25xxx */
13
13
{ "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64)
14
14
NO_SFDP_FLAGS(SECT_4K) },
···
32
32
33
33
const struct spi_nor_manufacturer spi_nor_eon = {
34
34
.name = "eon",
35
-
.parts = eon_parts,
36
-
.nparts = ARRAY_SIZE(eon_parts),
35
+
.parts = eon_nor_parts,
36
+
.nparts = ARRAY_SIZE(eon_nor_parts),
37
37
};
+3
-3
drivers/mtd/spi-nor/esmt.c
+3
-3
drivers/mtd/spi-nor/esmt.c
···
8
8
9
9
#include "core.h"
10
10
11
-
static const struct flash_info esmt_parts[] = {
11
+
static const struct flash_info esmt_nor_parts[] = {
12
12
/* ESMT */
13
13
{ "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64)
14
14
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
···
23
23
24
24
const struct spi_nor_manufacturer spi_nor_esmt = {
25
25
.name = "esmt",
26
-
.parts = esmt_parts,
27
-
.nparts = ARRAY_SIZE(esmt_parts),
26
+
.parts = esmt_nor_parts,
27
+
.nparts = ARRAY_SIZE(esmt_nor_parts),
28
28
};
+3
-3
drivers/mtd/spi-nor/everspin.c
+3
-3
drivers/mtd/spi-nor/everspin.c
···
8
8
9
9
#include "core.h"
10
10
11
-
static const struct flash_info everspin_parts[] = {
11
+
static const struct flash_info everspin_nor_parts[] = {
12
12
/* Everspin */
13
13
{ "mr25h128", CAT25_INFO(16 * 1024, 1, 256, 2) },
14
14
{ "mr25h256", CAT25_INFO(32 * 1024, 1, 256, 2) },
···
18
18
19
19
const struct spi_nor_manufacturer spi_nor_everspin = {
20
20
.name = "everspin",
21
-
.parts = everspin_parts,
22
-
.nparts = ARRAY_SIZE(everspin_parts),
21
+
.parts = everspin_nor_parts,
22
+
.nparts = ARRAY_SIZE(everspin_nor_parts),
23
23
};
+3
-3
drivers/mtd/spi-nor/fujitsu.c
+3
-3
drivers/mtd/spi-nor/fujitsu.c
···
8
8
9
9
#include "core.h"
10
10
11
-
static const struct flash_info fujitsu_parts[] = {
11
+
static const struct flash_info fujitsu_nor_parts[] = {
12
12
/* Fujitsu */
13
13
{ "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1)
14
14
FLAGS(SPI_NOR_NO_ERASE) },
···
16
16
17
17
const struct spi_nor_manufacturer spi_nor_fujitsu = {
18
18
.name = "fujitsu",
19
-
.parts = fujitsu_parts,
20
-
.nparts = ARRAY_SIZE(fujitsu_parts),
19
+
.parts = fujitsu_nor_parts,
20
+
.nparts = ARRAY_SIZE(fujitsu_nor_parts),
21
21
};
+3
-3
drivers/mtd/spi-nor/gigadevice.c
+3
-3
drivers/mtd/spi-nor/gigadevice.c
···
23
23
.default_init = gd25q256_default_init,
24
24
};
25
25
26
-
static const struct flash_info gigadevice_parts[] = {
26
+
static const struct flash_info gigadevice_nor_parts[] = {
27
27
{ "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32)
28
28
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
29
29
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
···
61
61
62
62
const struct spi_nor_manufacturer spi_nor_gigadevice = {
63
63
.name = "gigadevice",
64
-
.parts = gigadevice_parts,
65
-
.nparts = ARRAY_SIZE(gigadevice_parts),
64
+
.parts = gigadevice_nor_parts,
65
+
.nparts = ARRAY_SIZE(gigadevice_nor_parts),
66
66
};
+3
-3
drivers/mtd/spi-nor/intel.c
+3
-3
drivers/mtd/spi-nor/intel.c
···
8
8
9
9
#include "core.h"
10
10
11
-
static const struct flash_info intel_parts[] = {
11
+
static const struct flash_info intel_nor_parts[] = {
12
12
/* Intel/Numonyx -- xxxs33b */
13
13
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32)
14
14
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) },
···
20
20
21
21
const struct spi_nor_manufacturer spi_nor_intel = {
22
22
.name = "intel",
23
-
.parts = intel_parts,
24
-
.nparts = ARRAY_SIZE(intel_parts),
23
+
.parts = intel_nor_parts,
24
+
.nparts = ARRAY_SIZE(intel_nor_parts),
25
25
};
+5
-5
drivers/mtd/spi-nor/issi.c
+5
-5
drivers/mtd/spi-nor/issi.c
···
29
29
.post_bfpt = is25lp256_post_bfpt_fixups,
30
30
};
31
31
32
-
static const struct flash_info issi_parts[] = {
32
+
static const struct flash_info issi_nor_parts[] = {
33
33
/* ISSI */
34
34
{ "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2)
35
35
NO_SFDP_FLAGS(SECT_4K) },
···
69
69
NO_SFDP_FLAGS(SECT_4K) },
70
70
};
71
71
72
-
static void issi_default_init(struct spi_nor *nor)
72
+
static void issi_nor_default_init(struct spi_nor *nor)
73
73
{
74
74
nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
75
75
}
76
76
77
77
static const struct spi_nor_fixups issi_fixups = {
78
-
.default_init = issi_default_init,
78
+
.default_init = issi_nor_default_init,
79
79
};
80
80
81
81
const struct spi_nor_manufacturer spi_nor_issi = {
82
82
.name = "issi",
83
-
.parts = issi_parts,
84
-
.nparts = ARRAY_SIZE(issi_parts),
83
+
.parts = issi_nor_parts,
84
+
.nparts = ARRAY_SIZE(issi_nor_parts),
85
85
.fixups = &issi_fixups,
86
86
};
+7
-7
drivers/mtd/spi-nor/macronix.c
+7
-7
drivers/mtd/spi-nor/macronix.c
···
32
32
.post_bfpt = mx25l25635_post_bfpt_fixups,
33
33
};
34
34
35
-
static const struct flash_info macronix_parts[] = {
35
+
static const struct flash_info macronix_nor_parts[] = {
36
36
/* Macronix */
37
37
{ "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1)
38
38
NO_SFDP_FLAGS(SECT_4K) },
···
102
102
FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
103
103
};
104
104
105
-
static void macronix_default_init(struct spi_nor *nor)
105
+
static void macronix_nor_default_init(struct spi_nor *nor)
106
106
{
107
107
nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
108
108
nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
109
109
}
110
110
111
-
static const struct spi_nor_fixups macronix_fixups = {
112
-
.default_init = macronix_default_init,
111
+
static const struct spi_nor_fixups macronix_nor_fixups = {
112
+
.default_init = macronix_nor_default_init,
113
113
};
114
114
115
115
const struct spi_nor_manufacturer spi_nor_macronix = {
116
116
.name = "macronix",
117
-
.parts = macronix_parts,
118
-
.nparts = ARRAY_SIZE(macronix_parts),
119
-
.fixups = ¯onix_fixups,
117
+
.parts = macronix_nor_parts,
118
+
.nparts = ARRAY_SIZE(macronix_nor_parts),
119
+
.fixups = ¯onix_nor_fixups,
120
120
};
+210
-49
drivers/mtd/spi-nor/micron-st.c
+210
-49
drivers/mtd/spi-nor/micron-st.c
···
8
8
9
9
#include "core.h"
10
10
11
+
/* flash_info mfr_flag. Used to read proprietary FSR register. */
12
+
#define USE_FSR BIT(0)
13
+
14
+
#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
15
+
#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
11
16
#define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
12
17
#define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */
13
18
#define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */
···
22
17
#define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR. */
23
18
#define SPINOR_MT_EXSPI 0xff /* Enable Extended SPI (default) */
24
19
25
-
static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor, bool enable)
20
+
/* Flag Status Register bits */
21
+
#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
22
+
#define FSR_E_ERR BIT(5) /* Erase operation status */
23
+
#define FSR_P_ERR BIT(4) /* Program operation status */
24
+
#define FSR_PT_ERR BIT(1) /* Protection error bit */
25
+
26
+
static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
26
27
{
27
28
struct spi_mem_op op;
28
29
u8 *buf = nor->bouncebuf;
···
113
102
114
103
static void mt35xu512aba_default_init(struct spi_nor *nor)
115
104
{
116
-
nor->params->octal_dtr_enable = spi_nor_micron_octal_dtr_enable;
105
+
nor->params->octal_dtr_enable = micron_st_nor_octal_dtr_enable;
117
106
}
118
107
119
108
static void mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor)
···
141
130
.post_sfdp = mt35xu512aba_post_sfdp_fixup,
142
131
};
143
132
144
-
static const struct flash_info micron_parts[] = {
133
+
static const struct flash_info micron_nor_parts[] = {
145
134
{ "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512)
146
-
FLAGS(USE_FSR)
147
135
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ |
148
136
SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP)
149
137
FIXUP_FLAGS(SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE)
150
-
.fixups = &mt35xu512aba_fixups},
138
+
MFR_FLAGS(USE_FSR)
139
+
.fixups = &mt35xu512aba_fixups
140
+
},
151
141
{ "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048)
152
-
FLAGS(USE_FSR)
153
142
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ)
154
-
FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
143
+
FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
144
+
MFR_FLAGS(USE_FSR)
145
+
},
155
146
};
156
147
157
-
static const struct flash_info st_parts[] = {
148
+
static const struct flash_info st_nor_parts[] = {
158
149
{ "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32)
159
150
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
160
151
{ "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64)
···
169
156
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
170
157
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256)
171
158
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
172
-
SPI_NOR_BP3_SR_BIT6 | USE_FSR)
173
-
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
159
+
SPI_NOR_BP3_SR_BIT6)
160
+
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
161
+
MFR_FLAGS(USE_FSR)
162
+
},
174
163
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256)
175
164
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
176
-
SPI_NOR_BP3_SR_BIT6 | USE_FSR)
177
-
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
165
+
SPI_NOR_BP3_SR_BIT6)
166
+
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
167
+
MFR_FLAGS(USE_FSR)
168
+
},
178
169
{ "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512)
179
-
FLAGS(USE_FSR)
180
170
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
181
-
FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
171
+
FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
172
+
MFR_FLAGS(USE_FSR)
173
+
},
182
174
{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512)
183
-
FLAGS(USE_FSR)
184
175
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
185
-
SPI_NOR_QUAD_READ) },
176
+
SPI_NOR_QUAD_READ)
177
+
MFR_FLAGS(USE_FSR)
178
+
},
186
179
{ "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512)
187
-
FLAGS(USE_FSR)
188
180
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
189
-
FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
181
+
FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
182
+
MFR_FLAGS(USE_FSR)
183
+
},
190
184
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512)
191
-
FLAGS(USE_FSR)
192
-
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
185
+
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
186
+
MFR_FLAGS(USE_FSR)
187
+
},
193
188
{ "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024)
194
-
FLAGS(USE_FSR)
195
189
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
196
-
FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
190
+
FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
191
+
MFR_FLAGS(USE_FSR)
192
+
},
197
193
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024)
198
194
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
199
-
SPI_NOR_BP3_SR_BIT6 | USE_FSR)
200
-
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
195
+
SPI_NOR_BP3_SR_BIT6)
196
+
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
197
+
MFR_FLAGS(USE_FSR)
198
+
},
201
199
{ "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024)
202
-
FLAGS(USE_FSR)
203
200
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
204
-
FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
201
+
FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
202
+
MFR_FLAGS(USE_FSR)
203
+
},
205
204
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024)
206
205
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
207
-
SPI_NOR_BP3_SR_BIT6 | USE_FSR)
208
-
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
206
+
SPI_NOR_BP3_SR_BIT6)
207
+
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
208
+
MFR_FLAGS(USE_FSR)
209
+
},
209
210
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048)
210
211
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
211
-
SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE | USE_FSR)
212
-
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
212
+
SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE)
213
+
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
214
+
MFR_FLAGS(USE_FSR)
215
+
},
213
216
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048)
214
-
FLAGS(NO_CHIP_ERASE | USE_FSR)
215
-
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
217
+
FLAGS(NO_CHIP_ERASE)
218
+
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
219
+
MFR_FLAGS(USE_FSR)
220
+
},
216
221
{ "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096)
217
-
FLAGS(NO_CHIP_ERASE | USE_FSR)
218
-
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) },
222
+
FLAGS(NO_CHIP_ERASE)
223
+
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
224
+
MFR_FLAGS(USE_FSR)
225
+
},
219
226
{ "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096)
220
-
FLAGS(NO_CHIP_ERASE | USE_FSR)
227
+
FLAGS(NO_CHIP_ERASE)
221
228
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
222
-
SPI_NOR_QUAD_READ) },
229
+
SPI_NOR_QUAD_READ)
230
+
MFR_FLAGS(USE_FSR)
231
+
},
223
232
224
233
{ "m25p05", INFO(0x202010, 0, 32 * 1024, 2) },
225
234
{ "m25p10", INFO(0x202011, 0, 32 * 1024, 4) },
···
285
250
};
286
251
287
252
/**
288
-
* st_micron_set_4byte_addr_mode() - Set 4-byte address mode for ST and Micron
289
-
* flashes.
253
+
* micron_st_nor_set_4byte_addr_mode() - Set 4-byte address mode for ST and
254
+
* Micron flashes.
290
255
* @nor: pointer to 'struct spi_nor'.
291
256
* @enable: true to enter the 4-byte address mode, false to exit the 4-byte
292
257
* address mode.
293
258
*
294
259
* Return: 0 on success, -errno otherwise.
295
260
*/
296
-
static int st_micron_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
261
+
static int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
297
262
{
298
263
int ret;
299
264
···
308
273
return spi_nor_write_disable(nor);
309
274
}
310
275
311
-
static void micron_st_default_init(struct spi_nor *nor)
276
+
/**
277
+
* micron_st_nor_read_fsr() - Read the Flag Status Register.
278
+
* @nor: pointer to 'struct spi_nor'
279
+
* @fsr: pointer to a DMA-able buffer where the value of the
280
+
* Flag Status Register will be written. Should be at least 2
281
+
* bytes.
282
+
*
283
+
* Return: 0 on success, -errno otherwise.
284
+
*/
285
+
static int micron_st_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
286
+
{
287
+
int ret;
288
+
289
+
if (nor->spimem) {
290
+
struct spi_mem_op op =
291
+
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0),
292
+
SPI_MEM_OP_NO_ADDR,
293
+
SPI_MEM_OP_NO_DUMMY,
294
+
SPI_MEM_OP_DATA_IN(1, fsr, 0));
295
+
296
+
if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
297
+
op.addr.nbytes = nor->params->rdsr_addr_nbytes;
298
+
op.dummy.nbytes = nor->params->rdsr_dummy;
299
+
/*
300
+
* We don't want to read only one byte in DTR mode. So,
301
+
* read 2 and then discard the second byte.
302
+
*/
303
+
op.data.nbytes = 2;
304
+
}
305
+
306
+
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
307
+
308
+
ret = spi_mem_exec_op(nor->spimem, &op);
309
+
} else {
310
+
ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr,
311
+
1);
312
+
}
313
+
314
+
if (ret)
315
+
dev_dbg(nor->dev, "error %d reading FSR\n", ret);
316
+
317
+
return ret;
318
+
}
319
+
320
+
/**
321
+
* micron_st_nor_clear_fsr() - Clear the Flag Status Register.
322
+
* @nor: pointer to 'struct spi_nor'.
323
+
*/
324
+
static void micron_st_nor_clear_fsr(struct spi_nor *nor)
325
+
{
326
+
int ret;
327
+
328
+
if (nor->spimem) {
329
+
struct spi_mem_op op =
330
+
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0),
331
+
SPI_MEM_OP_NO_ADDR,
332
+
SPI_MEM_OP_NO_DUMMY,
333
+
SPI_MEM_OP_NO_DATA);
334
+
335
+
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
336
+
337
+
ret = spi_mem_exec_op(nor->spimem, &op);
338
+
} else {
339
+
ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR,
340
+
NULL, 0);
341
+
}
342
+
343
+
if (ret)
344
+
dev_dbg(nor->dev, "error %d clearing FSR\n", ret);
345
+
}
346
+
347
+
/**
348
+
* micron_st_nor_ready() - Query the Status Register as well as the Flag Status
349
+
* Register to see if the flash is ready for new commands. If there are any
350
+
* errors in the FSR clear them.
351
+
* @nor: pointer to 'struct spi_nor'.
352
+
*
353
+
* Return: 1 if ready, 0 if not ready, -errno on errors.
354
+
*/
355
+
static int micron_st_nor_ready(struct spi_nor *nor)
356
+
{
357
+
int sr_ready, ret;
358
+
359
+
sr_ready = spi_nor_sr_ready(nor);
360
+
if (sr_ready < 0)
361
+
return sr_ready;
362
+
363
+
ret = micron_st_nor_read_fsr(nor, nor->bouncebuf);
364
+
if (ret)
365
+
return ret;
366
+
367
+
if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) {
368
+
if (nor->bouncebuf[0] & FSR_E_ERR)
369
+
dev_err(nor->dev, "Erase operation failed.\n");
370
+
else
371
+
dev_err(nor->dev, "Program operation failed.\n");
372
+
373
+
if (nor->bouncebuf[0] & FSR_PT_ERR)
374
+
dev_err(nor->dev,
375
+
"Attempted to modify a protected sector.\n");
376
+
377
+
micron_st_nor_clear_fsr(nor);
378
+
379
+
/*
380
+
* WEL bit remains set to one when an erase or page program
381
+
* error occurs. Issue a Write Disable command to protect
382
+
* against inadvertent writes that can possibly corrupt the
383
+
* contents of the memory.
384
+
*/
385
+
ret = spi_nor_write_disable(nor);
386
+
if (ret)
387
+
return ret;
388
+
389
+
return -EIO;
390
+
}
391
+
392
+
return sr_ready && !!(nor->bouncebuf[0] & FSR_READY);
393
+
}
394
+
395
+
static void micron_st_nor_default_init(struct spi_nor *nor)
312
396
{
313
397
nor->flags |= SNOR_F_HAS_LOCK;
314
398
nor->flags &= ~SNOR_F_HAS_16BIT_SR;
315
399
nor->params->quad_enable = NULL;
316
-
nor->params->set_4byte_addr_mode = st_micron_set_4byte_addr_mode;
400
+
nor->params->set_4byte_addr_mode = micron_st_nor_set_4byte_addr_mode;
317
401
}
318
402
319
-
static const struct spi_nor_fixups micron_st_fixups = {
320
-
.default_init = micron_st_default_init,
403
+
static void micron_st_nor_late_init(struct spi_nor *nor)
404
+
{
405
+
if (nor->info->mfr_flags & USE_FSR)
406
+
nor->params->ready = micron_st_nor_ready;
407
+
}
408
+
409
+
static const struct spi_nor_fixups micron_st_nor_fixups = {
410
+
.default_init = micron_st_nor_default_init,
411
+
.late_init = micron_st_nor_late_init,
321
412
};
322
413
323
414
const struct spi_nor_manufacturer spi_nor_micron = {
324
415
.name = "micron",
325
-
.parts = micron_parts,
326
-
.nparts = ARRAY_SIZE(micron_parts),
327
-
.fixups = µn_st_fixups,
416
+
.parts = micron_nor_parts,
417
+
.nparts = ARRAY_SIZE(micron_nor_parts),
418
+
.fixups = µn_st_nor_fixups,
328
419
};
329
420
330
421
const struct spi_nor_manufacturer spi_nor_st = {
331
422
.name = "st",
332
-
.parts = st_parts,
333
-
.nparts = ARRAY_SIZE(st_parts),
334
-
.fixups = µn_st_fixups,
423
+
.parts = st_nor_parts,
424
+
.nparts = ARRAY_SIZE(st_nor_parts),
425
+
.fixups = µn_st_nor_fixups,
335
426
};
+127
-45
drivers/mtd/spi-nor/spansion.c
+127
-45
drivers/mtd/spi-nor/spansion.c
···
8
8
9
9
#include "core.h"
10
10
11
+
/* flash_info mfr_flag. Used to clear sticky prorietary SR bits. */
12
+
#define USE_CLSR BIT(0)
13
+
14
+
#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
11
15
#define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
12
16
#define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
13
17
#define SPINOR_REG_CYPRESS_CFR2V 0x00800003
···
24
20
#define SPINOR_OP_CYPRESS_RD_FAST 0xee
25
21
26
22
/**
27
-
* spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
23
+
* cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
28
24
* @nor: pointer to a 'struct spi_nor'
29
25
* @enable: whether to enable or disable Octal DTR
30
26
*
···
33
29
*
34
30
* Return: 0 on success, -errno otherwise.
35
31
*/
36
-
static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable)
32
+
static int cypress_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
37
33
{
38
34
struct spi_mem_op op;
39
35
u8 *buf = nor->bouncebuf;
···
120
116
121
117
static void s28hs512t_default_init(struct spi_nor *nor)
122
118
{
123
-
nor->params->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable;
119
+
nor->params->octal_dtr_enable = cypress_nor_octal_dtr_enable;
124
120
nor->params->writesize = 16;
125
121
}
126
122
···
187
183
};
188
184
189
185
static int
190
-
s25fs_s_post_bfpt_fixups(struct spi_nor *nor,
191
-
const struct sfdp_parameter_header *bfpt_header,
192
-
const struct sfdp_bfpt *bfpt)
186
+
s25fs_s_nor_post_bfpt_fixups(struct spi_nor *nor,
187
+
const struct sfdp_parameter_header *bfpt_header,
188
+
const struct sfdp_bfpt *bfpt)
193
189
{
194
190
/*
195
191
* The S25FS-S chip family reports 512-byte pages in BFPT but
···
202
198
return 0;
203
199
}
204
200
205
-
static const struct spi_nor_fixups s25fs_s_fixups = {
206
-
.post_bfpt = s25fs_s_post_bfpt_fixups,
201
+
static const struct spi_nor_fixups s25fs_s_nor_fixups = {
202
+
.post_bfpt = s25fs_s_nor_post_bfpt_fixups,
207
203
};
208
204
209
-
static const struct flash_info spansion_parts[] = {
205
+
static const struct flash_info spansion_nor_parts[] = {
210
206
/* Spansion/Cypress -- single (large) sector size only, at least
211
207
* for the chips listed here (without boot sectors).
212
208
*/
···
215
211
{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128)
216
212
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
217
213
{ "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64)
218
-
FLAGS(USE_CLSR)
219
-
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
214
+
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
215
+
MFR_FLAGS(USE_CLSR)
216
+
},
220
217
{ "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256)
221
-
FLAGS(USE_CLSR)
222
-
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
218
+
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
219
+
MFR_FLAGS(USE_CLSR)
220
+
},
223
221
{ "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128)
224
-
FLAGS(USE_CLSR)
225
222
NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ |
226
-
SPI_NOR_QUAD_READ) },
223
+
SPI_NOR_QUAD_READ)
224
+
MFR_FLAGS(USE_CLSR)
225
+
},
227
226
{ "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512)
228
-
FLAGS(USE_CLSR)
229
-
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
227
+
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
228
+
MFR_FLAGS(USE_CLSR)
229
+
},
230
230
{ "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256)
231
-
FLAGS(SPI_NOR_HAS_LOCK | USE_CLSR)
232
-
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
231
+
FLAGS(SPI_NOR_HAS_LOCK)
232
+
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
233
+
MFR_FLAGS(USE_CLSR)
234
+
},
233
235
{ "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256)
234
-
FLAGS(USE_CLSR)
235
236
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
236
-
.fixups = &s25fs_s_fixups, },
237
+
MFR_FLAGS(USE_CLSR)
238
+
.fixups = &s25fs_s_nor_fixups, },
237
239
{ "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128)
238
-
FLAGS(USE_CLSR)
239
-
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
240
-
{ "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512)
241
-
FLAGS(USE_CLSR)
242
-
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
243
-
{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256)
244
-
FLAGS(USE_CLSR)
245
240
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
246
-
.fixups = &s25fs_s_fixups, },
241
+
MFR_FLAGS(USE_CLSR)
242
+
},
243
+
{ "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512)
244
+
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
245
+
MFR_FLAGS(USE_CLSR)
246
+
},
247
+
{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256)
248
+
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
249
+
MFR_FLAGS(USE_CLSR)
250
+
.fixups = &s25fs_s_nor_fixups, },
247
251
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64) },
248
252
{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256) },
249
253
{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64)
250
-
FLAGS(USE_CLSR)
251
-
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
254
+
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
255
+
MFR_FLAGS(USE_CLSR)
256
+
},
252
257
{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256)
253
-
FLAGS(USE_CLSR)
254
-
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
258
+
NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
259
+
MFR_FLAGS(USE_CLSR)
260
+
},
255
261
{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8) },
256
262
{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16) },
257
263
{ "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32) },
···
308
294
},
309
295
};
310
296
311
-
static void spansion_late_init(struct spi_nor *nor)
297
+
/**
298
+
* spansion_nor_clear_sr() - Clear the Status Register.
299
+
* @nor: pointer to 'struct spi_nor'.
300
+
*/
301
+
static void spansion_nor_clear_sr(struct spi_nor *nor)
312
302
{
313
-
if (nor->params->size <= SZ_16M)
314
-
return;
303
+
int ret;
315
304
316
-
nor->flags |= SNOR_F_4B_OPCODES;
317
-
/* No small sector erase for 4-byte command set */
318
-
nor->erase_opcode = SPINOR_OP_SE;
319
-
nor->mtd.erasesize = nor->info->sector_size;
305
+
if (nor->spimem) {
306
+
struct spi_mem_op op =
307
+
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0),
308
+
SPI_MEM_OP_NO_ADDR,
309
+
SPI_MEM_OP_NO_DUMMY,
310
+
SPI_MEM_OP_NO_DATA);
311
+
312
+
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
313
+
314
+
ret = spi_mem_exec_op(nor->spimem, &op);
315
+
} else {
316
+
ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR,
317
+
NULL, 0);
318
+
}
319
+
320
+
if (ret)
321
+
dev_dbg(nor->dev, "error %d clearing SR\n", ret);
320
322
}
321
323
322
-
static const struct spi_nor_fixups spansion_fixups = {
323
-
.late_init = spansion_late_init,
324
+
/**
325
+
* spansion_nor_sr_ready_and_clear() - Query the Status Register to see if the
326
+
* flash is ready for new commands and clear it if there are any errors.
327
+
* @nor: pointer to 'struct spi_nor'.
328
+
*
329
+
* Return: 1 if ready, 0 if not ready, -errno on errors.
330
+
*/
331
+
static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
332
+
{
333
+
int ret;
334
+
335
+
ret = spi_nor_read_sr(nor, nor->bouncebuf);
336
+
if (ret)
337
+
return ret;
338
+
339
+
if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
340
+
if (nor->bouncebuf[0] & SR_E_ERR)
341
+
dev_err(nor->dev, "Erase Error occurred\n");
342
+
else
343
+
dev_err(nor->dev, "Programming Error occurred\n");
344
+
345
+
spansion_nor_clear_sr(nor);
346
+
347
+
/*
348
+
* WEL bit remains set to one when an erase or page program
349
+
* error occurs. Issue a Write Disable command to protect
350
+
* against inadvertent writes that can possibly corrupt the
351
+
* contents of the memory.
352
+
*/
353
+
ret = spi_nor_write_disable(nor);
354
+
if (ret)
355
+
return ret;
356
+
357
+
return -EIO;
358
+
}
359
+
360
+
return !(nor->bouncebuf[0] & SR_WIP);
361
+
}
362
+
363
+
static void spansion_nor_late_init(struct spi_nor *nor)
364
+
{
365
+
if (nor->params->size > SZ_16M) {
366
+
nor->flags |= SNOR_F_4B_OPCODES;
367
+
/* No small sector erase for 4-byte command set */
368
+
nor->erase_opcode = SPINOR_OP_SE;
369
+
nor->mtd.erasesize = nor->info->sector_size;
370
+
}
371
+
372
+
if (nor->info->mfr_flags & USE_CLSR)
373
+
nor->params->ready = spansion_nor_sr_ready_and_clear;
374
+
}
375
+
376
+
static const struct spi_nor_fixups spansion_nor_fixups = {
377
+
.late_init = spansion_nor_late_init,
324
378
};
325
379
326
380
const struct spi_nor_manufacturer spi_nor_spansion = {
327
381
.name = "spansion",
328
-
.parts = spansion_parts,
329
-
.nparts = ARRAY_SIZE(spansion_parts),
330
-
.fixups = &spansion_fixups,
382
+
.parts = spansion_nor_parts,
383
+
.nparts = ARRAY_SIZE(spansion_nor_parts),
384
+
.fixups = &spansion_nor_fixups,
331
385
};
+22
-22
drivers/mtd/spi-nor/sst.c
+22
-22
drivers/mtd/spi-nor/sst.c
···
13
13
14
14
#define SST26VF_CR_BPNV BIT(3)
15
15
16
-
static int sst26vf_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
16
+
static int sst26vf_nor_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
17
17
{
18
18
return -EOPNOTSUPP;
19
19
}
20
20
21
-
static int sst26vf_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
21
+
static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
22
22
{
23
23
int ret;
24
24
···
38
38
return spi_nor_global_block_unlock(nor);
39
39
}
40
40
41
-
static int sst26vf_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
41
+
static int sst26vf_nor_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
42
42
{
43
43
return -EOPNOTSUPP;
44
44
}
45
45
46
-
static const struct spi_nor_locking_ops sst26vf_locking_ops = {
47
-
.lock = sst26vf_lock,
48
-
.unlock = sst26vf_unlock,
49
-
.is_locked = sst26vf_is_locked,
46
+
static const struct spi_nor_locking_ops sst26vf_nor_locking_ops = {
47
+
.lock = sst26vf_nor_lock,
48
+
.unlock = sst26vf_nor_unlock,
49
+
.is_locked = sst26vf_nor_is_locked,
50
50
};
51
51
52
-
static void sst26vf_late_init(struct spi_nor *nor)
52
+
static void sst26vf_nor_late_init(struct spi_nor *nor)
53
53
{
54
-
nor->params->locking_ops = &sst26vf_locking_ops;
54
+
nor->params->locking_ops = &sst26vf_nor_locking_ops;
55
55
}
56
56
57
-
static const struct spi_nor_fixups sst26vf_fixups = {
58
-
.late_init = sst26vf_late_init,
57
+
static const struct spi_nor_fixups sst26vf_nor_fixups = {
58
+
.late_init = sst26vf_nor_late_init,
59
59
};
60
60
61
-
static const struct flash_info sst_parts[] = {
61
+
static const struct flash_info sst_nor_parts[] = {
62
62
/* SST -- large erase sizes are "overlays", "sectors" are 4K */
63
63
{ "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8)
64
64
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
···
114
114
{ "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128)
115
115
FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE)
116
116
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
117
-
.fixups = &sst26vf_fixups },
117
+
.fixups = &sst26vf_nor_fixups },
118
118
};
119
119
120
-
static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
121
-
size_t *retlen, const u_char *buf)
120
+
static int sst_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
121
+
size_t *retlen, const u_char *buf)
122
122
{
123
123
struct spi_nor *nor = mtd_to_spi_nor(mtd);
124
124
size_t actual = 0;
···
203
203
return ret;
204
204
}
205
205
206
-
static void sst_late_init(struct spi_nor *nor)
206
+
static void sst_nor_late_init(struct spi_nor *nor)
207
207
{
208
208
if (nor->info->mfr_flags & SST_WRITE)
209
-
nor->mtd._write = sst_write;
209
+
nor->mtd._write = sst_nor_write;
210
210
}
211
211
212
-
static const struct spi_nor_fixups sst_fixups = {
213
-
.late_init = sst_late_init,
212
+
static const struct spi_nor_fixups sst_nor_fixups = {
213
+
.late_init = sst_nor_late_init,
214
214
};
215
215
216
216
const struct spi_nor_manufacturer spi_nor_sst = {
217
217
.name = "sst",
218
-
.parts = sst_parts,
219
-
.nparts = ARRAY_SIZE(sst_parts),
220
-
.fixups = &sst_fixups,
218
+
.parts = sst_nor_parts,
219
+
.nparts = ARRAY_SIZE(sst_nor_parts),
220
+
.fixups = &sst_nor_fixups,
221
221
};
+15
-14
drivers/mtd/spi-nor/winbond.c
+15
-14
drivers/mtd/spi-nor/winbond.c
···
32
32
.post_bfpt = w25q256_post_bfpt_fixups,
33
33
};
34
34
35
-
static const struct flash_info winbond_parts[] = {
35
+
static const struct flash_info winbond_nor_parts[] = {
36
36
/* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
37
37
{ "w25x05", INFO(0xef3010, 0, 64 * 1024, 1)
38
38
NO_SFDP_FLAGS(SECT_4K) },
···
130
130
};
131
131
132
132
/**
133
-
* winbond_set_4byte_addr_mode() - Set 4-byte address mode for Winbond flashes.
133
+
* winbond_nor_set_4byte_addr_mode() - Set 4-byte address mode for Winbond
134
+
* flashes.
134
135
* @nor: pointer to 'struct spi_nor'.
135
136
* @enable: true to enter the 4-byte address mode, false to exit the 4-byte
136
137
* address mode.
137
138
*
138
139
* Return: 0 on success, -errno otherwise.
139
140
*/
140
-
static int winbond_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
141
+
static int winbond_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
141
142
{
142
143
int ret;
143
144
···
162
161
return spi_nor_write_disable(nor);
163
162
}
164
163
165
-
static const struct spi_nor_otp_ops winbond_otp_ops = {
164
+
static const struct spi_nor_otp_ops winbond_nor_otp_ops = {
166
165
.read = spi_nor_otp_read_secr,
167
166
.write = spi_nor_otp_write_secr,
168
167
.erase = spi_nor_otp_erase_secr,
···
170
169
.is_locked = spi_nor_otp_is_locked_sr2,
171
170
};
172
171
173
-
static void winbond_default_init(struct spi_nor *nor)
172
+
static void winbond_nor_default_init(struct spi_nor *nor)
174
173
{
175
-
nor->params->set_4byte_addr_mode = winbond_set_4byte_addr_mode;
174
+
nor->params->set_4byte_addr_mode = winbond_nor_set_4byte_addr_mode;
176
175
}
177
176
178
-
static void winbond_late_init(struct spi_nor *nor)
177
+
static void winbond_nor_late_init(struct spi_nor *nor)
179
178
{
180
179
if (nor->params->otp.org->n_regions)
181
-
nor->params->otp.ops = &winbond_otp_ops;
180
+
nor->params->otp.ops = &winbond_nor_otp_ops;
182
181
}
183
182
184
-
static const struct spi_nor_fixups winbond_fixups = {
185
-
.default_init = winbond_default_init,
186
-
.late_init = winbond_late_init,
183
+
static const struct spi_nor_fixups winbond_nor_fixups = {
184
+
.default_init = winbond_nor_default_init,
185
+
.late_init = winbond_nor_late_init,
187
186
};
188
187
189
188
const struct spi_nor_manufacturer spi_nor_winbond = {
190
189
.name = "winbond",
191
-
.parts = winbond_parts,
192
-
.nparts = ARRAY_SIZE(winbond_parts),
193
-
.fixups = &winbond_fixups,
190
+
.parts = winbond_nor_parts,
191
+
.nparts = ARRAY_SIZE(winbond_nor_parts),
192
+
.fixups = &winbond_nor_fixups,
194
193
};
+85
-12
drivers/mtd/spi-nor/xilinx.c
+85
-12
drivers/mtd/spi-nor/xilinx.c
···
8
8
9
9
#include "core.h"
10
10
11
-
static const struct flash_info xilinx_parts[] = {
11
+
#define XILINX_OP_SE 0x50 /* Sector erase */
12
+
#define XILINX_OP_PP 0x82 /* Page program */
13
+
#define XILINX_OP_RDSR 0xd7 /* Read status register */
14
+
15
+
#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
16
+
#define XSR_RDY BIT(7) /* Ready */
17
+
18
+
#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
19
+
.id = { \
20
+
((_jedec_id) >> 16) & 0xff, \
21
+
((_jedec_id) >> 8) & 0xff, \
22
+
(_jedec_id) & 0xff \
23
+
}, \
24
+
.id_len = 3, \
25
+
.sector_size = (8 * (_page_size)), \
26
+
.n_sectors = (_n_sectors), \
27
+
.page_size = (_page_size), \
28
+
.addr_width = 3, \
29
+
.flags = SPI_NOR_NO_FR
30
+
31
+
/* Xilinx S3AN share MFR with Atmel SPI NOR */
32
+
static const struct flash_info xilinx_nor_parts[] = {
12
33
/* Xilinx S3AN Internal Flash */
13
34
{ "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
14
35
{ "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
···
47
26
* Addr can safely be unsigned int, the biggest S3AN device is smaller than
48
27
* 4 MiB.
49
28
*/
50
-
static u32 s3an_convert_addr(struct spi_nor *nor, u32 addr)
29
+
static u32 s3an_nor_convert_addr(struct spi_nor *nor, u32 addr)
51
30
{
52
31
u32 page_size = nor->params->page_size;
53
32
u32 offset, page;
···
59
38
return page | offset;
60
39
}
61
40
41
+
/**
42
+
* xilinx_nor_read_sr() - Read the Status Register on S3AN flashes.
43
+
* @nor: pointer to 'struct spi_nor'.
44
+
* @sr: pointer to a DMA-able buffer where the value of the
45
+
* Status Register will be written.
46
+
*
47
+
* Return: 0 on success, -errno otherwise.
48
+
*/
49
+
static int xilinx_nor_read_sr(struct spi_nor *nor, u8 *sr)
50
+
{
51
+
int ret;
52
+
53
+
if (nor->spimem) {
54
+
struct spi_mem_op op =
55
+
SPI_MEM_OP(SPI_MEM_OP_CMD(XILINX_OP_RDSR, 0),
56
+
SPI_MEM_OP_NO_ADDR,
57
+
SPI_MEM_OP_NO_DUMMY,
58
+
SPI_MEM_OP_DATA_IN(1, sr, 0));
59
+
60
+
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
61
+
62
+
ret = spi_mem_exec_op(nor->spimem, &op);
63
+
} else {
64
+
ret = spi_nor_controller_ops_read_reg(nor, XILINX_OP_RDSR, sr,
65
+
1);
66
+
}
67
+
68
+
if (ret)
69
+
dev_dbg(nor->dev, "error %d reading SR\n", ret);
70
+
71
+
return ret;
72
+
}
73
+
74
+
/**
75
+
* xilinx_nor_sr_ready() - Query the Status Register of the S3AN flash to see
76
+
* if the flash is ready for new commands.
77
+
* @nor: pointer to 'struct spi_nor'.
78
+
*
79
+
* Return: 1 if ready, 0 if not ready, -errno on errors.
80
+
*/
81
+
static int xilinx_nor_sr_ready(struct spi_nor *nor)
82
+
{
83
+
int ret;
84
+
85
+
ret = xilinx_nor_read_sr(nor, nor->bouncebuf);
86
+
if (ret)
87
+
return ret;
88
+
89
+
return !!(nor->bouncebuf[0] & XSR_RDY);
90
+
}
91
+
62
92
static int xilinx_nor_setup(struct spi_nor *nor,
63
93
const struct spi_nor_hwcaps *hwcaps)
64
94
{
65
95
u32 page_size;
66
96
int ret;
67
97
68
-
ret = spi_nor_xread_sr(nor, nor->bouncebuf);
98
+
ret = xilinx_nor_read_sr(nor, nor->bouncebuf);
69
99
if (ret)
70
100
return ret;
71
101
72
-
nor->erase_opcode = SPINOR_OP_XSE;
73
-
nor->program_opcode = SPINOR_OP_XPP;
102
+
nor->erase_opcode = XILINX_OP_SE;
103
+
nor->program_opcode = XILINX_OP_PP;
74
104
nor->read_opcode = SPINOR_OP_READ;
75
105
nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
76
106
···
145
73
nor->mtd.erasesize = 8 * page_size;
146
74
} else {
147
75
/* Flash in Default addressing mode */
148
-
nor->params->convert_addr = s3an_convert_addr;
76
+
nor->params->convert_addr = s3an_nor_convert_addr;
149
77
nor->mtd.erasesize = nor->info->sector_size;
150
78
}
151
79
152
80
return 0;
153
81
}
154
82
155
-
static void xilinx_late_init(struct spi_nor *nor)
83
+
static void xilinx_nor_late_init(struct spi_nor *nor)
156
84
{
157
85
nor->params->setup = xilinx_nor_setup;
86
+
nor->params->ready = xilinx_nor_sr_ready;
158
87
}
159
88
160
-
static const struct spi_nor_fixups xilinx_fixups = {
161
-
.late_init = xilinx_late_init,
89
+
static const struct spi_nor_fixups xilinx_nor_fixups = {
90
+
.late_init = xilinx_nor_late_init,
162
91
};
163
92
164
93
const struct spi_nor_manufacturer spi_nor_xilinx = {
165
94
.name = "xilinx",
166
-
.parts = xilinx_parts,
167
-
.nparts = ARRAY_SIZE(xilinx_parts),
168
-
.fixups = &xilinx_fixups,
95
+
.parts = xilinx_nor_parts,
96
+
.nparts = ARRAY_SIZE(xilinx_nor_parts),
97
+
.fixups = &xilinx_nor_fixups,
169
98
};
+3
-3
drivers/mtd/spi-nor/xmc.c
+3
-3
drivers/mtd/spi-nor/xmc.c
···
8
8
9
9
#include "core.h"
10
10
11
-
static const struct flash_info xmc_parts[] = {
11
+
static const struct flash_info xmc_nor_parts[] = {
12
12
/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
13
13
{ "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128)
14
14
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
···
20
20
21
21
const struct spi_nor_manufacturer spi_nor_xmc = {
22
22
.name = "xmc",
23
-
.parts = xmc_parts,
24
-
.nparts = ARRAY_SIZE(xmc_parts),
23
+
.parts = xmc_nor_parts,
24
+
.nparts = ARRAY_SIZE(xmc_nor_parts),
25
25
};
+5
-6
drivers/mtd/tests/speedtest.c
+5
-6
drivers/mtd/tests/speedtest.c
···
160
160
161
161
static long calc_speed(void)
162
162
{
163
-
uint64_t k;
164
-
long ms;
163
+
uint64_t k, us;
165
164
166
-
ms = ktime_ms_delta(finish, start);
167
-
if (ms == 0)
165
+
us = ktime_us_delta(finish, start);
166
+
if (us == 0)
168
167
return 0;
169
-
k = (uint64_t)goodebcnt * (mtd->erasesize / 1024) * 1000;
170
-
do_div(k, ms);
168
+
k = (uint64_t)goodebcnt * (mtd->erasesize / 1024) * 1000000;
169
+
do_div(k, us);
171
170
return k;
172
171
}
173
172
+1
drivers/spi/Kconfig
+1
drivers/spi/Kconfig
+6
-4
drivers/spi/spi-cadence-quadspi.c
+6
-4
drivers/spi/spi-cadence-quadspi.c
···
1441
1441
if (!(all_true || all_false))
1442
1442
return false;
1443
1443
1444
-
if (all_true)
1445
-
return spi_mem_dtr_supports_op(mem, op);
1446
-
else
1447
-
return spi_mem_default_supports_op(mem, op);
1444
+
return spi_mem_default_supports_op(mem, op);
1448
1445
}
1449
1446
1450
1447
static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
···
1592
1595
.supports_op = cqspi_supports_mem_op,
1593
1596
};
1594
1597
1598
+
static const struct spi_controller_mem_caps cqspi_mem_caps = {
1599
+
.dtr = true,
1600
+
};
1601
+
1595
1602
static int cqspi_setup_flash(struct cqspi_st *cqspi)
1596
1603
{
1597
1604
struct platform_device *pdev = cqspi->pdev;
···
1653
1652
}
1654
1653
master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
1655
1654
master->mem_ops = &cqspi_mem_ops;
1655
+
master->mem_caps = &cqspi_mem_caps;
1656
1656
master->dev.of_node = pdev->dev.of_node;
1657
1657
1658
1658
cqspi = spi_master_get_devdata(master);
+18
-14
drivers/spi/spi-mem.c
+18
-14
drivers/spi/spi-mem.c
···
160
160
return true;
161
161
}
162
162
163
-
bool spi_mem_dtr_supports_op(struct spi_mem *mem,
164
-
const struct spi_mem_op *op)
165
-
{
166
-
if (op->cmd.nbytes != 2)
167
-
return false;
168
-
169
-
return spi_mem_check_buswidth(mem, op);
170
-
}
171
-
EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op);
172
-
173
163
bool spi_mem_default_supports_op(struct spi_mem *mem,
174
164
const struct spi_mem_op *op)
175
165
{
176
-
if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
177
-
return false;
166
+
struct spi_controller *ctlr = mem->spi->controller;
167
+
bool op_is_dtr =
168
+
op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr;
178
169
179
-
if (op->cmd.nbytes != 1)
180
-
return false;
170
+
if (op_is_dtr) {
171
+
if (!spi_mem_controller_is_capable(ctlr, dtr))
172
+
return false;
173
+
174
+
if (op->cmd.nbytes != 2)
175
+
return false;
176
+
} else {
177
+
if (op->cmd.nbytes != 1)
178
+
return false;
179
+
}
180
+
181
+
if (op->data.ecc) {
182
+
if (!spi_mem_controller_is_capable(ctlr, ecc))
183
+
return false;
184
+
}
181
185
182
186
return spi_mem_check_buswidth(mem, op);
183
187
}
+280
-60
drivers/spi/spi-mxic.c
+280
-60
drivers/spi/spi-mxic.c
···
12
12
#include <linux/io.h>
13
13
#include <linux/iopoll.h>
14
14
#include <linux/module.h>
15
+
#include <linux/mtd/nand.h>
16
+
#include <linux/mtd/nand-ecc-mxic.h>
15
17
#include <linux/platform_device.h>
16
18
#include <linux/pm_runtime.h>
17
19
#include <linux/spi/spi.h>
···
169
167
#define HW_TEST(x) (0xe0 + ((x) * 4))
170
168
171
169
struct mxic_spi {
170
+
struct device *dev;
172
171
struct clk *ps_clk;
173
172
struct clk *send_clk;
174
173
struct clk *send_dly_clk;
175
174
void __iomem *regs;
176
175
u32 cur_speed_hz;
176
+
struct {
177
+
void __iomem *map;
178
+
dma_addr_t dma;
179
+
size_t size;
180
+
} linear;
181
+
182
+
struct {
183
+
bool use_pipelined_conf;
184
+
struct nand_ecc_engine *pipelined_engine;
185
+
void *ctx;
186
+
} ecc;
177
187
};
178
188
179
189
static int mxic_spi_clk_enable(struct mxic_spi *mxic)
···
294
280
mxic->regs + HC_CFG);
295
281
}
296
282
283
+
static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags)
284
+
{
285
+
int nio = 1;
286
+
287
+
if (spi->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL))
288
+
nio = 8;
289
+
else if (spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
290
+
nio = 4;
291
+
else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
292
+
nio = 2;
293
+
294
+
return flags | HC_CFG_NIO(nio) |
295
+
HC_CFG_TYPE(spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
296
+
HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1);
297
+
}
298
+
299
+
static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op,
300
+
unsigned int data_len)
301
+
{
302
+
u32 cfg = OP_CMD_BYTES(op->cmd.nbytes) |
303
+
OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) |
304
+
(op->cmd.dtr ? OP_CMD_DDR : 0);
305
+
306
+
if (op->addr.nbytes)
307
+
cfg |= OP_ADDR_BYTES(op->addr.nbytes) |
308
+
OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) |
309
+
(op->addr.dtr ? OP_ADDR_DDR : 0);
310
+
311
+
if (op->dummy.nbytes)
312
+
cfg |= OP_DUMMY_CYC(op->dummy.nbytes);
313
+
314
+
/* Direct mapping data.nbytes field is not populated */
315
+
if (data_len) {
316
+
cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) |
317
+
(op->data.dtr ? OP_DATA_DDR : 0);
318
+
if (op->data.dir == SPI_MEM_DATA_IN) {
319
+
cfg |= OP_READ;
320
+
if (op->data.dtr)
321
+
cfg |= OP_DQS_EN;
322
+
}
323
+
}
324
+
325
+
return cfg;
326
+
}
327
+
297
328
static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
298
329
void *rxbuf, unsigned int len)
299
330
{
···
363
304
364
305
writel(data, mxic->regs + TXD(nbytes % 4));
365
306
307
+
ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
308
+
sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
309
+
if (ret)
310
+
return ret;
311
+
312
+
ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
313
+
sts & INT_RX_NOT_EMPTY, 0,
314
+
USEC_PER_SEC);
315
+
if (ret)
316
+
return ret;
317
+
318
+
data = readl(mxic->regs + RXD);
366
319
if (rxbuf) {
367
-
ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
368
-
sts & INT_TX_EMPTY, 0,
369
-
USEC_PER_SEC);
370
-
if (ret)
371
-
return ret;
372
-
373
-
ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
374
-
sts & INT_RX_NOT_EMPTY, 0,
375
-
USEC_PER_SEC);
376
-
if (ret)
377
-
return ret;
378
-
379
-
data = readl(mxic->regs + RXD);
380
320
data >>= (8 * (4 - nbytes));
381
321
memcpy(rxbuf + pos, &data, nbytes);
382
-
WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
383
-
} else {
384
-
readl(mxic->regs + RXD);
385
322
}
386
323
WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
387
324
···
387
332
return 0;
388
333
}
389
334
335
+
static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
336
+
u64 offs, size_t len, void *buf)
337
+
{
338
+
struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master);
339
+
int ret;
340
+
u32 sts;
341
+
342
+
if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
343
+
return -EINVAL;
344
+
345
+
writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);
346
+
347
+
writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
348
+
mxic->regs + LRD_CFG);
349
+
writel(desc->info.offset + offs, mxic->regs + LRD_ADDR);
350
+
len = min_t(size_t, len, mxic->linear.size);
351
+
writel(len, mxic->regs + LRD_RANGE);
352
+
writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
353
+
LMODE_SLV_ACT(desc->mem->spi->chip_select) |
354
+
LMODE_EN,
355
+
mxic->regs + LRD_CTRL);
356
+
357
+
if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) {
358
+
ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine,
359
+
NAND_PAGE_READ,
360
+
mxic->linear.dma + offs);
361
+
if (ret)
362
+
return ret;
363
+
} else {
364
+
memcpy_fromio(buf, mxic->linear.map, len);
365
+
}
366
+
367
+
writel(INT_LRD_DIS, mxic->regs + INT_STS);
368
+
writel(0, mxic->regs + LRD_CTRL);
369
+
370
+
ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
371
+
sts & INT_LRD_DIS, 0, USEC_PER_SEC);
372
+
if (ret)
373
+
return ret;
374
+
375
+
return len;
376
+
}
377
+
378
+
static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc,
379
+
u64 offs, size_t len,
380
+
const void *buf)
381
+
{
382
+
struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master);
383
+
u32 sts;
384
+
int ret;
385
+
386
+
if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
387
+
return -EINVAL;
388
+
389
+
writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);
390
+
391
+
writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
392
+
mxic->regs + LWR_CFG);
393
+
writel(desc->info.offset + offs, mxic->regs + LWR_ADDR);
394
+
len = min_t(size_t, len, mxic->linear.size);
395
+
writel(len, mxic->regs + LWR_RANGE);
396
+
writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
397
+
LMODE_SLV_ACT(desc->mem->spi->chip_select) |
398
+
LMODE_EN,
399
+
mxic->regs + LWR_CTRL);
400
+
401
+
if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) {
402
+
ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine,
403
+
NAND_PAGE_WRITE,
404
+
mxic->linear.dma + offs);
405
+
if (ret)
406
+
return ret;
407
+
} else {
408
+
memcpy_toio(mxic->linear.map, buf, len);
409
+
}
410
+
411
+
writel(INT_LWR_DIS, mxic->regs + INT_STS);
412
+
writel(0, mxic->regs + LWR_CTRL);
413
+
414
+
ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
415
+
sts & INT_LWR_DIS, 0, USEC_PER_SEC);
416
+
if (ret)
417
+
return ret;
418
+
419
+
return len;
420
+
}
421
+
390
422
static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
391
423
const struct spi_mem_op *op)
392
424
{
393
-
bool all_false;
394
-
395
425
if (op->data.buswidth > 8 || op->addr.buswidth > 8 ||
396
426
op->dummy.buswidth > 8 || op->cmd.buswidth > 8)
397
427
return false;
···
488
348
if (op->addr.nbytes > 7)
489
349
return false;
490
350
491
-
all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
492
-
!op->data.dtr;
351
+
return spi_mem_default_supports_op(mem, op);
352
+
}
493
353
494
-
if (all_false)
495
-
return spi_mem_default_supports_op(mem, op);
496
-
else
497
-
return spi_mem_dtr_supports_op(mem, op);
354
+
static int mxic_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc)
355
+
{
356
+
struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master);
357
+
358
+
if (!mxic->linear.map)
359
+
return -EINVAL;
360
+
361
+
if (desc->info.offset + desc->info.length > U32_MAX)
362
+
return -EINVAL;
363
+
364
+
if (!mxic_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
365
+
return -EOPNOTSUPP;
366
+
367
+
return 0;
498
368
}
499
369
500
370
static int mxic_spi_mem_exec_op(struct spi_mem *mem,
501
371
const struct spi_mem_op *op)
502
372
{
503
373
struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master);
504
-
int nio = 1, i, ret;
505
-
u32 ss_ctrl;
374
+
int i, ret;
506
375
u8 addr[8], cmd[2];
507
376
508
377
ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
509
378
if (ret)
510
379
return ret;
511
380
512
-
if (mem->spi->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL))
513
-
nio = 8;
514
-
else if (mem->spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
515
-
nio = 4;
516
-
else if (mem->spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
517
-
nio = 2;
518
-
519
-
writel(HC_CFG_NIO(nio) |
520
-
HC_CFG_TYPE(mem->spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
521
-
HC_CFG_SLV_ACT(mem->spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1) |
522
-
HC_CFG_MAN_CS_EN,
381
+
writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN),
523
382
mxic->regs + HC_CFG);
383
+
524
384
writel(HC_EN_BIT, mxic->regs + HC_EN);
525
385
526
-
ss_ctrl = OP_CMD_BYTES(op->cmd.nbytes) |
527
-
OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) |
528
-
(op->cmd.dtr ? OP_CMD_DDR : 0);
529
-
530
-
if (op->addr.nbytes)
531
-
ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) |
532
-
OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) |
533
-
(op->addr.dtr ? OP_ADDR_DDR : 0);
534
-
535
-
if (op->dummy.nbytes)
536
-
ss_ctrl |= OP_DUMMY_CYC(op->dummy.nbytes);
537
-
538
-
if (op->data.nbytes) {
539
-
ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) |
540
-
(op->data.dtr ? OP_DATA_DDR : 0);
541
-
if (op->data.dir == SPI_MEM_DATA_IN) {
542
-
ss_ctrl |= OP_READ;
543
-
if (op->data.dtr)
544
-
ss_ctrl |= OP_DQS_EN;
545
-
}
546
-
}
547
-
548
-
writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select));
386
+
writel(mxic_spi_mem_prep_op_cfg(op, op->data.nbytes),
387
+
mxic->regs + SS_CTRL(mem->spi->chip_select));
549
388
550
389
writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
551
390
mxic->regs + HC_CFG);
···
565
446
static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
566
447
.supports_op = mxic_spi_mem_supports_op,
567
448
.exec_op = mxic_spi_mem_exec_op,
449
+
.dirmap_create = mxic_spi_mem_dirmap_create,
450
+
.dirmap_read = mxic_spi_mem_dirmap_read,
451
+
.dirmap_write = mxic_spi_mem_dirmap_write,
452
+
};
453
+
454
+
static const struct spi_controller_mem_caps mxic_spi_mem_caps = {
455
+
.dtr = true,
456
+
.ecc = true,
568
457
};
569
458
570
459
static void mxic_spi_set_cs(struct spi_device *spi, bool lvl)
···
637
510
return 0;
638
511
}
639
512
513
+
/* ECC wrapper */
514
+
static int mxic_spi_mem_ecc_init_ctx(struct nand_device *nand)
515
+
{
516
+
struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
517
+
struct mxic_spi *mxic = nand->ecc.engine->priv;
518
+
519
+
mxic->ecc.use_pipelined_conf = true;
520
+
521
+
return ops->init_ctx(nand);
522
+
}
523
+
524
+
static void mxic_spi_mem_ecc_cleanup_ctx(struct nand_device *nand)
525
+
{
526
+
struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
527
+
struct mxic_spi *mxic = nand->ecc.engine->priv;
528
+
529
+
mxic->ecc.use_pipelined_conf = false;
530
+
531
+
ops->cleanup_ctx(nand);
532
+
}
533
+
534
+
static int mxic_spi_mem_ecc_prepare_io_req(struct nand_device *nand,
535
+
struct nand_page_io_req *req)
536
+
{
537
+
struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
538
+
539
+
return ops->prepare_io_req(nand, req);
540
+
}
541
+
542
+
static int mxic_spi_mem_ecc_finish_io_req(struct nand_device *nand,
543
+
struct nand_page_io_req *req)
544
+
{
545
+
struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
546
+
547
+
return ops->finish_io_req(nand, req);
548
+
}
549
+
550
+
static struct nand_ecc_engine_ops mxic_spi_mem_ecc_engine_pipelined_ops = {
551
+
.init_ctx = mxic_spi_mem_ecc_init_ctx,
552
+
.cleanup_ctx = mxic_spi_mem_ecc_cleanup_ctx,
553
+
.prepare_io_req = mxic_spi_mem_ecc_prepare_io_req,
554
+
.finish_io_req = mxic_spi_mem_ecc_finish_io_req,
555
+
};
556
+
557
+
static void mxic_spi_mem_ecc_remove(struct mxic_spi *mxic)
558
+
{
559
+
if (mxic->ecc.pipelined_engine) {
560
+
mxic_ecc_put_pipelined_engine(mxic->ecc.pipelined_engine);
561
+
nand_ecc_unregister_on_host_hw_engine(mxic->ecc.pipelined_engine);
562
+
}
563
+
}
564
+
565
+
static int mxic_spi_mem_ecc_probe(struct platform_device *pdev,
566
+
struct mxic_spi *mxic)
567
+
{
568
+
struct nand_ecc_engine *eng;
569
+
570
+
if (!mxic_ecc_get_pipelined_ops())
571
+
return -EOPNOTSUPP;
572
+
573
+
eng = mxic_ecc_get_pipelined_engine(pdev);
574
+
if (IS_ERR(eng))
575
+
return PTR_ERR(eng);
576
+
577
+
eng->dev = &pdev->dev;
578
+
eng->integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
579
+
eng->ops = &mxic_spi_mem_ecc_engine_pipelined_ops;
580
+
eng->priv = mxic;
581
+
mxic->ecc.pipelined_engine = eng;
582
+
nand_ecc_register_on_host_hw_engine(eng);
583
+
584
+
return 0;
585
+
}
586
+
640
587
static int __maybe_unused mxic_spi_runtime_suspend(struct device *dev)
641
588
{
642
589
struct spi_master *master = dev_get_drvdata(dev);
···
756
555
platform_set_drvdata(pdev, master);
757
556
758
557
mxic = spi_master_get_devdata(master);
558
+
mxic->dev = &pdev->dev;
759
559
760
560
master->dev.of_node = pdev->dev.of_node;
761
561
···
777
575
if (IS_ERR(mxic->regs))
778
576
return PTR_ERR(mxic->regs);
779
577
578
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
579
+
mxic->linear.map = devm_ioremap_resource(&pdev->dev, res);
580
+
if (!IS_ERR(mxic->linear.map)) {
581
+
mxic->linear.dma = res->start;
582
+
mxic->linear.size = resource_size(res);
583
+
} else {
584
+
mxic->linear.map = NULL;
585
+
}
586
+
780
587
pm_runtime_enable(&pdev->dev);
781
588
master->auto_runtime_pm = true;
782
589
783
590
master->num_chipselect = 1;
784
591
master->mem_ops = &mxic_spi_mem_ops;
592
+
master->mem_caps = &mxic_spi_mem_caps;
785
593
786
594
master->set_cs = mxic_spi_set_cs;
787
595
master->transfer_one = mxic_spi_transfer_one;
···
802
590
SPI_RX_OCTAL | SPI_TX_OCTAL;
803
591
804
592
mxic_spi_hw_init(mxic);
593
+
594
+
ret = mxic_spi_mem_ecc_probe(pdev, mxic);
595
+
if (ret == -EPROBE_DEFER) {
596
+
pm_runtime_disable(&pdev->dev);
597
+
return ret;
598
+
}
805
599
806
600
ret = spi_register_master(master);
807
601
if (ret) {
···
821
603
static int mxic_spi_remove(struct platform_device *pdev)
822
604
{
823
605
struct spi_master *master = platform_get_drvdata(pdev);
606
+
struct mxic_spi *mxic = spi_master_get_devdata(master);
824
607
825
608
pm_runtime_disable(&pdev->dev);
609
+
mxic_spi_mem_ecc_remove(mxic);
826
610
spi_unregister_master(master);
827
611
828
612
return 0;
+5
include/linux/bcma/bcma_driver_chipcommon.h
+5
include/linux/bcma/bcma_driver_chipcommon.h
···
3
3
#define LINUX_BCMA_DRIVER_CC_H_
4
4
5
5
#include <linux/platform_device.h>
6
+
#include <linux/platform_data/brcmnand.h>
6
7
#include <linux/gpio.h>
7
8
8
9
/** ChipCommon core registers. **/
···
600
599
601
600
#ifdef CONFIG_BCMA_NFLASH
602
601
struct bcma_nflash {
602
+
/* Must be the fist member for the brcmnand driver to
603
+
* de-reference that structure.
604
+
*/
605
+
struct brcmnand_platform_data brcmnand_info;
603
606
bool present;
604
607
bool boot; /* This is the flash the SoC boots from */
605
608
};
+6
-5
include/linux/mtd/mtd.h
+6
-5
include/linux/mtd/mtd.h
···
188
188
*/
189
189
struct mtd_debug_info {
190
190
struct dentry *dfs_dir;
191
-
192
-
const char *partname;
193
-
const char *partid;
194
191
};
195
192
196
193
/**
···
708
711
709
712
unsigned mtd_mmap_capabilities(struct mtd_info *mtd);
710
713
711
-
extern char *mtd_expert_analysis_warning;
712
-
extern bool mtd_expert_analysis_mode;
714
+
#ifdef CONFIG_DEBUG_FS
715
+
bool mtd_check_expert_analysis_mode(void);
716
+
#else
717
+
static inline bool mtd_check_expert_analysis_mode(void) { return false; }
718
+
#endif
719
+
713
720
714
721
#endif /* __MTD_MTD_H__ */
+49
include/linux/mtd/nand-ecc-mxic.h
+49
include/linux/mtd/nand-ecc-mxic.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright © 2019 Macronix
4
+
* Author: Miquèl Raynal <miquel.raynal@bootlin.com>
5
+
*
6
+
* Header for the Macronix external ECC engine.
7
+
*/
8
+
9
+
#ifndef __MTD_NAND_ECC_MXIC_H__
10
+
#define __MTD_NAND_ECC_MXIC_H__
11
+
12
+
#include <linux/platform_device.h>
13
+
#include <linux/device.h>
14
+
15
+
struct mxic_ecc_engine;
16
+
17
+
#if IS_ENABLED(CONFIG_MTD_NAND_ECC_MXIC) && IS_REACHABLE(CONFIG_MTD_NAND_CORE)
18
+
19
+
struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void);
20
+
struct nand_ecc_engine *mxic_ecc_get_pipelined_engine(struct platform_device *spi_pdev);
21
+
void mxic_ecc_put_pipelined_engine(struct nand_ecc_engine *eng);
22
+
int mxic_ecc_process_data_pipelined(struct nand_ecc_engine *eng,
23
+
unsigned int direction, dma_addr_t dirmap);
24
+
25
+
#else /* !CONFIG_MTD_NAND_ECC_MXIC */
26
+
27
+
static inline struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void)
28
+
{
29
+
return NULL;
30
+
}
31
+
32
+
static inline struct nand_ecc_engine *
33
+
mxic_ecc_get_pipelined_engine(struct platform_device *spi_pdev)
34
+
{
35
+
return ERR_PTR(-EOPNOTSUPP);
36
+
}
37
+
38
+
static inline void mxic_ecc_put_pipelined_engine(struct nand_ecc_engine *eng) {}
39
+
40
+
static inline int mxic_ecc_process_data_pipelined(struct nand_ecc_engine *eng,
41
+
unsigned int direction,
42
+
dma_addr_t dirmap)
43
+
{
44
+
return -EOPNOTSUPP;
45
+
}
46
+
47
+
#endif /* CONFIG_MTD_NAND_ECC_MXIC */
48
+
49
+
#endif /* __MTD_NAND_ECC_MXIC_H__ */
+49
include/linux/mtd/nand.h
+49
include/linux/mtd/nand.h
···
264
264
};
265
265
266
266
/**
267
+
* enum nand_ecc_engine_integration - How the NAND ECC engine is integrated
268
+
* @NAND_ECC_ENGINE_INTEGRATION_INVALID: Invalid value
269
+
* @NAND_ECC_ENGINE_INTEGRATION_PIPELINED: Pipelined engine, performs on-the-fly
270
+
* correction, does not need to copy
271
+
* data around
272
+
* @NAND_ECC_ENGINE_INTEGRATION_EXTERNAL: External engine, needs to bring the
273
+
* data into its own area before use
274
+
*/
275
+
enum nand_ecc_engine_integration {
276
+
NAND_ECC_ENGINE_INTEGRATION_INVALID,
277
+
NAND_ECC_ENGINE_INTEGRATION_PIPELINED,
278
+
NAND_ECC_ENGINE_INTEGRATION_EXTERNAL,
279
+
};
280
+
281
+
/**
267
282
* struct nand_ecc_engine - ECC engine abstraction for NAND devices
283
+
* @dev: Host device
284
+
* @node: Private field for registration time
268
285
* @ops: ECC engine operations
286
+
* @integration: How the engine is integrated with the host
287
+
* (only relevant on %NAND_ECC_ENGINE_TYPE_ON_HOST engines)
288
+
* @priv: Private data
269
289
*/
270
290
struct nand_ecc_engine {
291
+
struct device *dev;
292
+
struct list_head node;
271
293
struct nand_ecc_engine_ops *ops;
294
+
enum nand_ecc_engine_integration integration;
295
+
void *priv;
272
296
};
273
297
274
298
void of_get_nand_ecc_user_config(struct nand_device *nand);
···
303
279
int nand_ecc_finish_io_req(struct nand_device *nand,
304
280
struct nand_page_io_req *req);
305
281
bool nand_ecc_is_strong_enough(struct nand_device *nand);
282
+
283
+
#if IS_REACHABLE(CONFIG_MTD_NAND_CORE)
284
+
int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine);
285
+
int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine);
286
+
#else
287
+
static inline int
288
+
nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine)
289
+
{
290
+
return -ENOTSUPP;
291
+
}
292
+
static inline int
293
+
nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine)
294
+
{
295
+
return -ENOTSUPP;
296
+
}
297
+
#endif
298
+
306
299
struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand);
307
300
struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);
301
+
struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand);
302
+
void nand_ecc_put_on_host_hw_engine(struct nand_device *nand);
303
+
struct device *nand_ecc_get_engine_dev(struct device *host);
308
304
309
305
#if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)
310
306
struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);
···
1005
961
/* ECC related functions */
1006
962
int nanddev_ecc_engine_init(struct nand_device *nand);
1007
963
void nanddev_ecc_engine_cleanup(struct nand_device *nand);
964
+
965
+
static inline void *nand_to_ecc_ctx(struct nand_device *nand)
966
+
{
967
+
return nand->ecc.ctx.priv;
968
+
}
1008
969
1009
970
/* BBT related functions */
1010
971
enum nand_bbt_block_status {
+2
include/linux/mtd/rawnand.h
+2
include/linux/mtd/rawnand.h
···
1240
1240
* @lock: Lock protecting the suspended field. Also used to serialize accesses
1241
1241
* to the NAND device
1242
1242
* @suspended: Set to 1 when the device is suspended, 0 when it's not
1243
+
* @resume_wq: wait queue to sleep if rawnand is in suspended state.
1243
1244
* @cur_cs: Currently selected target. -1 means no target selected, otherwise we
1244
1245
* should always have cur_cs >= 0 && cur_cs < nanddev_ntargets().
1245
1246
* NAND Controller drivers should not modify this value, but they're
···
1295
1294
/* Internals */
1296
1295
struct mutex lock;
1297
1296
unsigned int suspended : 1;
1297
+
wait_queue_head_t resume_wq;
1298
1298
int cur_cs;
1299
1299
int read_retries;
1300
1300
struct nand_secure_region *secure_regions;
-18
include/linux/mtd/spi-nor.h
-18
include/linux/mtd/spi-nor.h
···
47
47
#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
48
48
#define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
49
49
#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
50
-
#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
51
-
#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
52
50
#define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
53
51
#define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
54
52
#define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
···
84
86
#define SPINOR_OP_BP 0x02 /* Byte program */
85
87
#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
86
88
87
-
/* Used for S3AN flashes only */
88
-
#define SPINOR_OP_XSE 0x50 /* Sector erase */
89
-
#define SPINOR_OP_XPP 0x82 /* Page program */
90
-
#define SPINOR_OP_XRDSR 0xd7 /* Read status register */
91
-
92
-
#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
93
-
#define XSR_RDY BIT(7) /* Ready */
94
-
95
-
96
89
/* Used for Macronix and Winbond flashes. */
97
90
#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
98
91
#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
99
92
100
93
/* Used for Spansion flashes only. */
101
94
#define SPINOR_OP_BRWR 0x17 /* Bank register write */
102
-
#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
103
95
104
96
/* Used for Micron flashes only. */
105
97
#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
···
122
134
123
135
/* Enhanced Volatile Configuration Register bits */
124
136
#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
125
-
126
-
/* Flag Status Register bits */
127
-
#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
128
-
#define FSR_E_ERR BIT(5) /* Erase operation status */
129
-
#define FSR_P_ERR BIT(4) /* Program operation status */
130
-
#define FSR_PT_ERR BIT(1) /* Protection error bit */
131
137
132
138
/* Status Register 2 bits. */
133
139
#define SR2_QUAD_EN_BIT1 BIT(1)
+2
include/linux/mtd/spinand.h
+2
include/linux/mtd/spinand.h
+12
include/linux/platform_data/brcmnand.h
+12
include/linux/platform_data/brcmnand.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
#ifndef BRCMNAND_PLAT_DATA_H
3
+
#define BRCMNAND_PLAT_DATA_H
4
+
5
+
struct brcmnand_platform_data {
6
+
int chip_select;
7
+
const char * const *part_probe_types;
8
+
unsigned int ecc_stepsize;
9
+
unsigned int ecc_strength;
10
+
};
11
+
12
+
#endif /* BRCMNAND_PLAT_DATA_H */
+15
-11
include/linux/spi/spi-mem.h
+15
-11
include/linux/spi/spi-mem.h
···
89
89
* @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
90
90
* @data.buswidth: number of IO lanes used to send/receive the data
91
91
* @data.dtr: whether the data should be sent in DTR mode or not
92
+
* @data.ecc: whether error correction is required or not
92
93
* @data.dir: direction of the transfer
93
94
* @data.nbytes: number of data bytes to send/receive. Can be zero if the
94
95
* operation does not involve transferring data
···
120
119
struct {
121
120
u8 buswidth;
122
121
u8 dtr : 1;
122
+
u8 ecc : 1;
123
123
enum spi_mem_data_dir dir;
124
124
unsigned int nbytes;
125
125
union {
···
288
286
};
289
287
290
288
/**
289
+
* struct spi_controller_mem_caps - SPI memory controller capabilities
290
+
* @dtr: Supports DTR operations
291
+
* @ecc: Supports operations with error correction
292
+
*/
293
+
struct spi_controller_mem_caps {
294
+
bool dtr;
295
+
bool ecc;
296
+
};
297
+
298
+
#define spi_mem_controller_is_capable(ctlr, cap) \
299
+
((ctlr)->mem_caps && (ctlr)->mem_caps->cap)
300
+
301
+
/**
291
302
* struct spi_mem_driver - SPI memory driver
292
303
* @spidrv: inherit from a SPI driver
293
304
* @probe: probe a SPI memory. Usually where detection/initialization takes
···
334
319
335
320
bool spi_mem_default_supports_op(struct spi_mem *mem,
336
321
const struct spi_mem_op *op);
337
-
338
-
bool spi_mem_dtr_supports_op(struct spi_mem *mem,
339
-
const struct spi_mem_op *op);
340
-
341
322
#else
342
323
static inline int
343
324
spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
···
353
342
static inline
354
343
bool spi_mem_default_supports_op(struct spi_mem *mem,
355
344
const struct spi_mem_op *op)
356
-
{
357
-
return false;
358
-
}
359
-
360
-
static inline
361
-
bool spi_mem_dtr_supports_op(struct spi_mem *mem,
362
-
const struct spi_mem_op *op)
363
345
{
364
346
return false;
365
347
}
+3
include/linux/spi/spi.h
+3
include/linux/spi/spi.h
···
24
24
struct spi_controller;
25
25
struct spi_transfer;
26
26
struct spi_controller_mem_ops;
27
+
struct spi_controller_mem_caps;
27
28
28
29
/*
29
30
* INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
···
414
413
* @mem_ops: optimized/dedicated operations for interactions with SPI memory.
415
414
* This field is optional and should only be implemented if the
416
415
* controller has native support for memory like operations.
416
+
* @mem_caps: controller capabilities for the handling of memory operations.
417
417
* @unprepare_message: undo any work done by prepare_message().
418
418
* @slave_abort: abort the ongoing transfer request on an SPI slave controller
419
419
* @cs_gpiods: Array of GPIO descs to use as chip select lines; one per CS
···
634
632
635
633
/* Optimized handlers for SPI memory-like operations. */
636
634
const struct spi_controller_mem_ops *mem_ops;
635
+
const struct spi_controller_mem_caps *mem_caps;
637
636
638
637
/* gpio chip select */
639
638
struct gpio_desc **cs_gpiods;