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phy: phy-snps-eusb2: refactor reference clock init

Instead of matching frequencies with a switch and case, introduce
a table-based lookup. This improves readability, reduces redundancy,
and makes it easier to extend support for additional frequencies in
the future.

Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250504144527.1723980-9-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Ivaylo Ivanov and committed by
Vinod Koul e36a5d1e aba7a966

+32 -29
+32 -29
drivers/phy/phy-snps-eusb2.c
··· 192 192 FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0)); 193 193 } 194 194 195 + struct snps_eusb2_ref_clk { 196 + unsigned long freq; 197 + u32 fsel_val; 198 + u32 div_7_0_val; 199 + u32 div_11_8_val; 200 + }; 201 + 202 + static const struct snps_eusb2_ref_clk qcom_eusb2_ref_clk[] = { 203 + { 19200000, FSEL_19_2_MHZ_VAL, DIV_7_0_19_2_MHZ_VAL, DIV_11_8_19_2_MHZ_VAL }, 204 + { 38400000, FSEL_38_4_MHZ_VAL, DIV_7_0_38_4_MHZ_VAL, DIV_11_8_38_4_MHZ_VAL }, 205 + }; 206 + 195 207 static int qcom_eusb2_ref_clk_init(struct snps_eusb2_hsphy *phy) 196 208 { 209 + const struct snps_eusb2_ref_clk *config = NULL; 197 210 unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); 198 211 199 - switch (ref_clk_freq) { 200 - case 19200000: 201 - snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL_COMMON0, 202 - FSEL_MASK, 203 - FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL)); 212 + for (int i = 0; i < ARRAY_SIZE(qcom_eusb2_ref_clk); i++) { 213 + if (qcom_eusb2_ref_clk[i].freq == ref_clk_freq) { 214 + config = &qcom_eusb2_ref_clk[i]; 215 + break; 216 + } 217 + } 204 218 205 - snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_2, 206 - PHY_CFG_PLL_FB_DIV_7_0_MASK, 207 - DIV_7_0_19_2_MHZ_VAL); 208 - 209 - snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_3, 210 - PHY_CFG_PLL_FB_DIV_11_8_MASK, 211 - DIV_11_8_19_2_MHZ_VAL); 212 - break; 213 - 214 - case 38400000: 215 - snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL_COMMON0, 216 - FSEL_MASK, 217 - FIELD_PREP(FSEL_MASK, FSEL_38_4_MHZ_VAL)); 218 - 219 - snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_2, 220 - PHY_CFG_PLL_FB_DIV_7_0_MASK, 221 - DIV_7_0_38_4_MHZ_VAL); 222 - 223 - snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_3, 224 - PHY_CFG_PLL_FB_DIV_11_8_MASK, 225 - DIV_11_8_38_4_MHZ_VAL); 226 - break; 227 - 228 - default: 219 + if (!config) { 229 220 dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq); 230 221 return -EINVAL; 231 222 } 223 + 224 + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL_COMMON0, 225 + FSEL_MASK, 226 + FIELD_PREP(FSEL_MASK, config->fsel_val)); 227 + 228 + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_2, 229 + PHY_CFG_PLL_FB_DIV_7_0_MASK, 230 + config->div_7_0_val); 231 + 232 + snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_3, 233 + PHY_CFG_PLL_FB_DIV_11_8_MASK, 234 + config->div_11_8_val); 232 235 233 236 snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_3, 234 237 PHY_CFG_PLL_REF_DIV, PLL_REF_DIV_VAL);