tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amd/pm: Add gpuboard temperature metrics support

Add gpuboard temperature metrics support via system metrics table for
smu_v15_0_8

v3: Use per sensor attr id (Lijo)

v4: Use s16 for temp, remove cast, use separate function to fill
gpuboard temperature metrics data (Lijo)

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Asad Kamal and committed by
Alex Deucher e3b96f5b 1415503d

+278
+35
drivers/gpu/drm/amd/include/kgd_pp_interface.h
··· 590 590 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_MID, 591 591 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_AID, 592 592 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_XCD, 593 + AMDGPU_METRICS_ATTR_ID_LABEL_VERSION, 594 + AMDGPU_METRICS_ATTR_ID_NODE_ID, 595 + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_RETIMER, 596 + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_IBC, 597 + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_IBC_2, 598 + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_VDD18_VR, 599 + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_04_HBM_B_VR, 600 + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_04_HBM_D_VR, 601 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_SOCIO_A, 602 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_SOCIO_C, 603 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_X0, 604 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_X1, 605 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_HBM_B, 606 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_HBM_D, 607 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_04_HBM_B, 608 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_04_HBM_D, 609 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_HBM_B, 610 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_HBM_D, 611 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_HBM_B, 612 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_HBM_D, 613 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_11_GTA_A, 614 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_11_GTA_C, 615 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075_GTA_A, 616 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075_GTA_C, 617 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_UCIE, 618 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAA, 619 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_A, 620 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_C, 621 + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075, 593 622 AMDGPU_METRICS_ATTR_ID_MAX, 594 623 }; 595 624 ··· 1869 1840 AMDGPU_XGMI_LINK_ACTIVE = 1, 1870 1841 /* Status not available */ 1871 1842 AMDGPU_XGMI_LINK_NA = 2, 1843 + }; 1844 + 1845 + struct amdgpu_gpuboard_temp_metrics_v1_1 { 1846 + struct metrics_table_header common_header; 1847 + int attr_count; 1848 + struct gpu_metrics_attr metrics_attrs[]; 1872 1849 }; 1873 1850 1874 1851 #endif
+172
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
··· 171 171 TAB_MAP(I2C_COMMANDS), 172 172 }; 173 173 174 + static size_t smu_v15_0_8_get_system_metrics_size(void) 175 + { 176 + return sizeof(SystemMetricsTable_t); 177 + } 178 + 174 179 static int smu_v15_0_8_tables_init(struct smu_context *smu) 175 180 { 181 + struct smu_v15_0_8_gpuboard_temp_metrics *gpuboard_temp_metrics; 176 182 struct smu_table_context *smu_table = &smu->smu_table; 177 183 int ret, gpu_metrcs_size = sizeof(MetricsTable_t); 178 184 struct smu_table *tables = smu_table->tables; ··· 192 186 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, 193 187 gpu_metrcs_size, 194 188 PAGE_SIZE, 189 + AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT); 190 + SMU_TABLE_INIT(tables, SMU_TABLE_PMFW_SYSTEM_METRICS, 191 + smu_v15_0_8_get_system_metrics_size(), PAGE_SIZE, 195 192 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT); 196 193 197 194 metrics_table = kzalloc(gpu_metrcs_size, GFP_KERNEL); ··· 216 207 gpu_metrics = (struct smu_v15_0_8_gpu_metrics *)smu_driver_table_ptr(smu, 217 208 SMU_DRIVER_TABLE_GPU_METRICS); 218 209 smu_v15_0_8_gpu_metrics_init(gpu_metrics, 1, 9); 210 + 211 + ret = smu_table_cache_init(smu, SMU_TABLE_PMFW_SYSTEM_METRICS, 212 + smu_v15_0_8_get_system_metrics_size(), 5); 213 + 214 + if (ret) 215 + return ret; 216 + 217 + /* Initialize GPU board temperature metrics */ 218 + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS, 219 + sizeof(*gpuboard_temp_metrics), 50); 220 + if (ret) { 221 + smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); 222 + return ret; 223 + } 224 + gpuboard_temp_metrics = (struct smu_v15_0_8_gpuboard_temp_metrics *) 225 + smu_driver_table_ptr(smu, 226 + SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); 227 + smu_v15_0_8_gpuboard_temp_metrics_init(gpuboard_temp_metrics, 1, 1); 228 + 219 229 smu_table->metrics_table = no_free_ptr(metrics_table); 220 230 smu_table->driver_pptable = no_free_ptr(driver_pptable); 221 231 ··· 280 252 { 281 253 struct smu_table_context *smu_table = &smu->smu_table; 282 254 255 + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); 256 + smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); 283 257 mutex_destroy(&smu_table->metrics_lock); 284 258 285 259 return 0; ··· 515 485 } 516 486 517 487 return ret; 488 + } 489 + 490 + static int smu_v15_0_8_get_system_metrics_table(struct smu_context *smu) 491 + { 492 + struct smu_table_context *smu_table = &smu->smu_table; 493 + struct smu_table *table = &smu_table->driver_table; 494 + struct smu_table *tables = smu_table->tables; 495 + struct smu_table *sys_table; 496 + int ret; 497 + 498 + sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; 499 + if (smu_table_cache_is_valid(sys_table)) 500 + return 0; 501 + 502 + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSystemMetricsTable, NULL); 503 + if (ret) { 504 + dev_info(smu->adev->dev, 505 + "Failed to export system metrics table!\n"); 506 + return ret; 507 + } 508 + 509 + amdgpu_hdp_invalidate(smu->adev, NULL); 510 + smu_table_cache_update_time(sys_table, jiffies); 511 + memcpy(sys_table->cache.buffer, table->cpu_addr, 512 + sizeof(SystemMetricsTable_t)); 513 + 514 + return 0; 518 515 } 519 516 520 517 static int smu_v15_0_8_read_sensor(struct smu_context *smu, ··· 1349 1292 return ret; 1350 1293 } 1351 1294 1295 + static bool smu_v15_0_8_is_temp_metrics_supported(struct smu_context *smu, 1296 + enum smu_temp_metric_type type) 1297 + { 1298 + switch (type) { 1299 + case SMU_TEMP_METRIC_GPUBOARD: 1300 + return true; 1301 + default: 1302 + return false; 1303 + } 1304 + } 1305 + 1306 + static void smu_v15_0_8_fill_gpuboard_temp_metrics( 1307 + struct smu_v15_0_8_gpuboard_temp_metrics *gpuboard_temp_metrics, 1308 + const SystemMetricsTable_t *metrics) 1309 + { 1310 + gpuboard_temp_metrics->accumulation_counter = metrics->AccumulationCounter; 1311 + gpuboard_temp_metrics->label_version = metrics->LabelVersion; 1312 + gpuboard_temp_metrics->node_id = metrics->NodeIdentifier; 1313 + 1314 + gpuboard_temp_metrics->node_temp_retimer = 1315 + metrics->NodeTemperatures[NODE_TEMP_RETIMER]; 1316 + gpuboard_temp_metrics->node_temp_ibc = 1317 + metrics->NodeTemperatures[NODE_TEMP_IBC_TEMP]; 1318 + gpuboard_temp_metrics->node_temp_ibc_2 = 1319 + metrics->NodeTemperatures[NODE_TEMP_IBC_2_TEMP]; 1320 + gpuboard_temp_metrics->node_temp_vdd18_vr = 1321 + metrics->NodeTemperatures[NODE_TEMP_VDD18_VR_TEMP]; 1322 + gpuboard_temp_metrics->node_temp_04_hbm_b_vr = 1323 + metrics->NodeTemperatures[NODE_TEMP_04_HBM_B_VR_TEMP]; 1324 + gpuboard_temp_metrics->node_temp_04_hbm_d_vr = 1325 + metrics->NodeTemperatures[NODE_TEMP_04_HBM_D_VR_TEMP]; 1326 + 1327 + gpuboard_temp_metrics->vr_temp_vddcr_socio_a = 1328 + metrics->VrTemperatures[SVI_PLANE_VDDCR_SOCIO_A_TEMP]; 1329 + gpuboard_temp_metrics->vr_temp_vddcr_socio_c = 1330 + metrics->VrTemperatures[SVI_PLANE_VDDCR_SOCIO_C_TEMP]; 1331 + gpuboard_temp_metrics->vr_temp_vddcr_x0 = 1332 + metrics->VrTemperatures[SVI_PLANE_VDDCR_X0_TEMP]; 1333 + gpuboard_temp_metrics->vr_temp_vddcr_x1 = 1334 + metrics->VrTemperatures[SVI_PLANE_VDDCR_X1_TEMP]; 1335 + gpuboard_temp_metrics->vr_temp_vddio_hbm_b = 1336 + metrics->VrTemperatures[SVI_PLANE_VDDIO_HBM_B_TEMP]; 1337 + gpuboard_temp_metrics->vr_temp_vddio_hbm_d = 1338 + metrics->VrTemperatures[SVI_PLANE_VDDIO_HBM_D_TEMP]; 1339 + gpuboard_temp_metrics->vr_temp_vddio_04_hbm_b = 1340 + metrics->VrTemperatures[SVI_PLANE_VDDIO_04_HBM_B_TEMP]; 1341 + gpuboard_temp_metrics->vr_temp_vddio_04_hbm_d = 1342 + metrics->VrTemperatures[SVI_PLANE_VDDIO_04_HBM_D_TEMP]; 1343 + gpuboard_temp_metrics->vr_temp_vddcr_hbm_b = 1344 + metrics->VrTemperatures[SVI_PLANE_VDDCR_HBM_B_TEMP]; 1345 + gpuboard_temp_metrics->vr_temp_vddcr_hbm_d = 1346 + metrics->VrTemperatures[SVI_PLANE_VDDCR_HBM_D_TEMP]; 1347 + gpuboard_temp_metrics->vr_temp_vddcr_075_hbm_b = 1348 + metrics->VrTemperatures[SVI_PLANE_VDDCR_075_HBM_B_TEMP]; 1349 + gpuboard_temp_metrics->vr_temp_vddcr_075_hbm_d = 1350 + metrics->VrTemperatures[SVI_PLANE_VDDCR_075_HBM_D_TEMP]; 1351 + gpuboard_temp_metrics->vr_temp_vddio_11_gta_a = 1352 + metrics->VrTemperatures[SVI_PLANE_VDDIO_11_GTA_A_TEMP]; 1353 + gpuboard_temp_metrics->vr_temp_vddio_11_gta_c = 1354 + metrics->VrTemperatures[SVI_PLANE_VDDIO_11_GTA_C_TEMP]; 1355 + gpuboard_temp_metrics->vr_temp_vddan_075_gta_a = 1356 + metrics->VrTemperatures[SVI_PLANE_VDDAN_075_GTA_A_TEMP]; 1357 + gpuboard_temp_metrics->vr_temp_vddan_075_gta_c = 1358 + metrics->VrTemperatures[SVI_PLANE_VDDAN_075_GTA_C_TEMP]; 1359 + gpuboard_temp_metrics->vr_temp_vddcr_075_ucie = 1360 + metrics->VrTemperatures[SVI_PLANE_VDDCR_075_UCIE_TEMP]; 1361 + gpuboard_temp_metrics->vr_temp_vddio_065_ucieaa = 1362 + metrics->VrTemperatures[SVI_PLANE_VDDIO_065_UCIEAA_TEMP]; 1363 + gpuboard_temp_metrics->vr_temp_vddio_065_ucieam_a = 1364 + metrics->VrTemperatures[SVI_PLANE_VDDIO_065_UCIEAM_A_TEMP]; 1365 + gpuboard_temp_metrics->vr_temp_vddio_065_ucieam_c = 1366 + metrics->VrTemperatures[SVI_PLANE_VDDIO_065_UCIEAM_C_TEMP]; 1367 + gpuboard_temp_metrics->vr_temp_vddan_075 = 1368 + metrics->VrTemperatures[SVI_PLANE_VDDAN_075_TEMP]; 1369 + } 1370 + 1371 + static ssize_t smu_v15_0_8_get_temp_metrics(struct smu_context *smu, 1372 + enum smu_temp_metric_type type, 1373 + void *table) 1374 + { 1375 + struct smu_v15_0_8_gpuboard_temp_metrics *gpuboard_temp_metrics; 1376 + struct smu_table_context *smu_table = &smu->smu_table; 1377 + struct smu_table *tables = smu_table->tables; 1378 + enum smu_driver_table_id table_id; 1379 + SystemMetricsTable_t *metrics; 1380 + struct smu_table *sys_table; 1381 + ssize_t size; 1382 + int ret; 1383 + 1384 + table_id = SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS; 1385 + gpuboard_temp_metrics = 1386 + (struct smu_v15_0_8_gpuboard_temp_metrics *) 1387 + smu_driver_table_ptr(smu, table_id); 1388 + size = sizeof(*gpuboard_temp_metrics); 1389 + 1390 + ret = smu_v15_0_8_get_system_metrics_table(smu); 1391 + if (ret) 1392 + return ret; 1393 + 1394 + sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; 1395 + metrics = (SystemMetricsTable_t *)sys_table->cache.buffer; 1396 + smu_driver_table_update_cache_time(smu, table_id); 1397 + 1398 + smu_v15_0_8_fill_gpuboard_temp_metrics(gpuboard_temp_metrics, 1399 + metrics); 1400 + memcpy(table, gpuboard_temp_metrics, size); 1401 + return size; 1402 + } 1403 + 1352 1404 static ssize_t smu_v15_0_8_get_gpu_metrics(struct smu_context *smu, void **table) 1353 1405 { 1354 1406 struct smu_table_context *smu_table = &smu->smu_table; ··· 2120 1954 ctl->message_map = message_map; 2121 1955 } 2122 1956 1957 + static const struct smu_temp_funcs smu_v15_0_8_temp_funcs = { 1958 + .temp_metrics_is_supported = smu_v15_0_8_is_temp_metrics_supported, 1959 + .get_temp_metrics = smu_v15_0_8_get_temp_metrics, 1960 + }; 1961 + 2123 1962 void smu_v15_0_8_set_ppt_funcs(struct smu_context *smu) 2124 1963 { 2125 1964 smu->ppt_funcs = &smu_v15_0_8_ppt_funcs; ··· 2132 1961 smu->feature_map = smu_v15_0_8_feature_mask_map; 2133 1962 smu->table_map = smu_v15_0_8_table_map; 2134 1963 smu_v15_0_8_init_msg_ctl(smu, smu_v15_0_8_message_map); 1964 + smu->smu_temp.temp_funcs = &smu_v15_0_8_temp_funcs; 2135 1965 smu->smc_driver_if_version = SMU15_DRIVER_IF_VERSION_SMU_V15_0_8; 2136 1966 }
+71
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h
··· 180 180 SMU_15_0_8_MAX_XCC); 181 181 182 182 DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_gpu_metrics, SMU_15_0_8_METRICS_FIELDS); 183 + 184 + /* Maximum temperature sensor counts for system metrics */ 185 + #define SMU_15_0_8_MAX_NODE_TEMP_ENTRIES 12 186 + #define SMU_15_0_8_MAX_VR_TEMP_ENTRIES 22 187 + 188 + /* SMUv 15.0.8 GPU board temperature metrics */ 189 + #define SMU_15_0_8_GPUBOARD_TEMP_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ 190 + SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ 191 + SMU_MTYPE(U64), accumulation_counter); \ 192 + SMU_SCALAR(SMU_MATTR(LABEL_VERSION), SMU_MUNIT(NONE), \ 193 + SMU_MTYPE(U16), label_version); \ 194 + SMU_SCALAR(SMU_MATTR(NODE_ID), SMU_MUNIT(NONE), \ 195 + SMU_MTYPE(U16), node_id); \ 196 + SMU_SCALAR(SMU_MATTR(NODE_TEMP_RETIMER), SMU_MUNIT(TEMP_1), \ 197 + SMU_MTYPE(S16), node_temp_retimer); \ 198 + SMU_SCALAR(SMU_MATTR(NODE_TEMP_IBC), SMU_MUNIT(TEMP_1), \ 199 + SMU_MTYPE(S16), node_temp_ibc); \ 200 + SMU_SCALAR(SMU_MATTR(NODE_TEMP_IBC_2), SMU_MUNIT(TEMP_1), \ 201 + SMU_MTYPE(S16), node_temp_ibc_2); \ 202 + SMU_SCALAR(SMU_MATTR(NODE_TEMP_VDD18_VR), SMU_MUNIT(TEMP_1), \ 203 + SMU_MTYPE(S16), node_temp_vdd18_vr); \ 204 + SMU_SCALAR(SMU_MATTR(NODE_TEMP_04_HBM_B_VR), SMU_MUNIT(TEMP_1), \ 205 + SMU_MTYPE(S16), node_temp_04_hbm_b_vr); \ 206 + SMU_SCALAR(SMU_MATTR(NODE_TEMP_04_HBM_D_VR), SMU_MUNIT(TEMP_1), \ 207 + SMU_MTYPE(S16), node_temp_04_hbm_d_vr); \ 208 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_SOCIO_A), SMU_MUNIT(TEMP_1), \ 209 + SMU_MTYPE(S16), vr_temp_vddcr_socio_a); \ 210 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_SOCIO_C), SMU_MUNIT(TEMP_1), \ 211 + SMU_MTYPE(S16), vr_temp_vddcr_socio_c); \ 212 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_X0), SMU_MUNIT(TEMP_1), \ 213 + SMU_MTYPE(S16), vr_temp_vddcr_x0); \ 214 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_X1), SMU_MUNIT(TEMP_1), \ 215 + SMU_MTYPE(S16), vr_temp_vddcr_x1); \ 216 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_HBM_B), SMU_MUNIT(TEMP_1), \ 217 + SMU_MTYPE(S16), vr_temp_vddio_hbm_b); \ 218 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_HBM_D), SMU_MUNIT(TEMP_1), \ 219 + SMU_MTYPE(S16), vr_temp_vddio_hbm_d); \ 220 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_04_HBM_B), SMU_MUNIT(TEMP_1), \ 221 + SMU_MTYPE(S16), vr_temp_vddio_04_hbm_b); \ 222 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_04_HBM_D), SMU_MUNIT(TEMP_1), \ 223 + SMU_MTYPE(S16), vr_temp_vddio_04_hbm_d); \ 224 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_HBM_B), SMU_MUNIT(TEMP_1), \ 225 + SMU_MTYPE(S16), vr_temp_vddcr_hbm_b); \ 226 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_HBM_D), SMU_MUNIT(TEMP_1), \ 227 + SMU_MTYPE(S16), vr_temp_vddcr_hbm_d); \ 228 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_075_HBM_B), SMU_MUNIT(TEMP_1), \ 229 + SMU_MTYPE(S16), vr_temp_vddcr_075_hbm_b); \ 230 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_075_HBM_D), SMU_MUNIT(TEMP_1), \ 231 + SMU_MTYPE(S16), vr_temp_vddcr_075_hbm_d); \ 232 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_11_GTA_A), SMU_MUNIT(TEMP_1), \ 233 + SMU_MTYPE(S16), vr_temp_vddio_11_gta_a); \ 234 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_11_GTA_C), SMU_MUNIT(TEMP_1), \ 235 + SMU_MTYPE(S16), vr_temp_vddio_11_gta_c); \ 236 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDAN_075_GTA_A), SMU_MUNIT(TEMP_1), \ 237 + SMU_MTYPE(S16), vr_temp_vddan_075_gta_a); \ 238 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDAN_075_GTA_C), SMU_MUNIT(TEMP_1), \ 239 + SMU_MTYPE(S16), vr_temp_vddan_075_gta_c); \ 240 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_075_UCIE), SMU_MUNIT(TEMP_1), \ 241 + SMU_MTYPE(S16), vr_temp_vddcr_075_ucie); \ 242 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_065_UCIEAA), SMU_MUNIT(TEMP_1), \ 243 + SMU_MTYPE(S16), vr_temp_vddio_065_ucieaa); \ 244 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_065_UCIEAM_A), SMU_MUNIT(TEMP_1), \ 245 + SMU_MTYPE(S16), vr_temp_vddio_065_ucieam_a); \ 246 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_065_UCIEAM_C), SMU_MUNIT(TEMP_1), \ 247 + SMU_MTYPE(S16), vr_temp_vddio_065_ucieam_c); \ 248 + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDAN_075), SMU_MUNIT(TEMP_1), \ 249 + SMU_MTYPE(S16), vr_temp_vddan_075); 250 + 251 + DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_gpuboard_temp_metrics, 252 + SMU_15_0_8_GPUBOARD_TEMP_METRICS_FIELDS); 253 + 183 254 #endif 184 255 #endif