tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/amdgpu: introduce amdgpu_sdma_set_vm_pte_scheds

All sdma versions used the same logic, so add a helper and move the
common code to a single place.

---
v2: pass amdgpu_vm_pte_funcs as well
v3: drop all the *_set_vm_pte_funcs one liners
v5: rebased
---

Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Pierre-Eric Pelloux-Prayer and committed by
Alex Deucher e3dc7976 91ff83b5

+113 -249
+2
drivers/gpu/drm/amd/amdgpu/amdgpu.h
··· 1536 1536 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1537 1537 ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); 1538 1538 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); 1539 + void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, 1540 + const struct amdgpu_vm_pte_funcs *vm_pte_funcs); 1539 1541 1540 1542 /* atpx handler */ 1541 1543 #if defined(CONFIG_VGA_SWITCHEROO)
+17
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
··· 3210 3210 task_info->process_name, task_info->tgid, 3211 3211 task_info->task.comm, task_info->task.pid); 3212 3212 } 3213 + 3214 + void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, 3215 + const struct amdgpu_vm_pte_funcs *vm_pte_funcs) 3216 + { 3217 + struct drm_gpu_scheduler *sched; 3218 + int i; 3219 + 3220 + for (i = 0; i < adev->sdma.num_instances; i++) { 3221 + if (adev->sdma.has_page_queue) 3222 + sched = &adev->sdma.instance[i].page.sched; 3223 + else 3224 + sched = &adev->sdma.instance[i].ring.sched; 3225 + adev->vm_manager.vm_pte_scheds[i] = sched; 3226 + } 3227 + adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 3228 + adev->vm_manager.vm_pte_funcs = vm_pte_funcs; 3229 + }
+9 -22
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
··· 53 53 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); 54 54 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); 55 55 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); 56 - static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev); 57 56 static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block); 58 57 59 58 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev); ··· 918 919 } 919 920 } 920 921 922 + static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { 923 + .copy_pte_num_dw = 7, 924 + .copy_pte = cik_sdma_vm_copy_pte, 925 + 926 + .write_pte = cik_sdma_vm_write_pte, 927 + .set_pte_pde = cik_sdma_vm_set_pte_pde, 928 + }; 929 + 921 930 static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block) 922 931 { 923 932 struct amdgpu_device *adev = ip_block->adev; ··· 940 933 cik_sdma_set_ring_funcs(adev); 941 934 cik_sdma_set_irq_funcs(adev); 942 935 cik_sdma_set_buffer_funcs(adev); 943 - cik_sdma_set_vm_pte_funcs(adev); 936 + amdgpu_sdma_set_vm_pte_scheds(adev, &cik_sdma_vm_pte_funcs); 944 937 945 938 return 0; 946 939 } ··· 1342 1335 { 1343 1336 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs; 1344 1337 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1345 - } 1346 - 1347 - static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { 1348 - .copy_pte_num_dw = 7, 1349 - .copy_pte = cik_sdma_vm_copy_pte, 1350 - 1351 - .write_pte = cik_sdma_vm_write_pte, 1352 - .set_pte_pde = cik_sdma_vm_set_pte_pde, 1353 - }; 1354 - 1355 - static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) 1356 - { 1357 - unsigned i; 1358 - 1359 - adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; 1360 - for (i = 0; i < adev->sdma.num_instances; i++) { 1361 - adev->vm_manager.vm_pte_scheds[i] = 1362 - &adev->sdma.instance[i].ring.sched; 1363 - } 1364 - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1365 1338 } 1366 1339 1367 1340 const struct amdgpu_ip_block_version cik_sdma_ip_block =
+9 -22
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
··· 51 51 52 52 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev); 53 53 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev); 54 - static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev); 55 54 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); 56 55 57 56 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin"); ··· 808 809 amdgpu_ring_write(ring, val); 809 810 } 810 811 812 + static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { 813 + .copy_pte_num_dw = 7, 814 + .copy_pte = sdma_v2_4_vm_copy_pte, 815 + 816 + .write_pte = sdma_v2_4_vm_write_pte, 817 + .set_pte_pde = sdma_v2_4_vm_set_pte_pde, 818 + }; 819 + 811 820 static int sdma_v2_4_early_init(struct amdgpu_ip_block *ip_block) 812 821 { 813 822 struct amdgpu_device *adev = ip_block->adev; ··· 829 822 830 823 sdma_v2_4_set_ring_funcs(adev); 831 824 sdma_v2_4_set_buffer_funcs(adev); 832 - sdma_v2_4_set_vm_pte_funcs(adev); 825 + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v2_4_vm_pte_funcs); 833 826 sdma_v2_4_set_irq_funcs(adev); 834 827 835 828 return 0; ··· 1237 1230 { 1238 1231 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs; 1239 1232 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1240 - } 1241 - 1242 - static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { 1243 - .copy_pte_num_dw = 7, 1244 - .copy_pte = sdma_v2_4_vm_copy_pte, 1245 - 1246 - .write_pte = sdma_v2_4_vm_write_pte, 1247 - .set_pte_pde = sdma_v2_4_vm_set_pte_pde, 1248 - }; 1249 - 1250 - static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) 1251 - { 1252 - unsigned i; 1253 - 1254 - adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; 1255 - for (i = 0; i < adev->sdma.num_instances; i++) { 1256 - adev->vm_manager.vm_pte_scheds[i] = 1257 - &adev->sdma.instance[i].ring.sched; 1258 - } 1259 - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1260 1233 } 1261 1234 1262 1235 const struct amdgpu_ip_block_version sdma_v2_4_ip_block = {
+9 -22
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
··· 51 51 52 52 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); 53 53 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); 54 - static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); 55 54 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); 56 55 57 56 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); ··· 1081 1082 amdgpu_ring_write(ring, val); 1082 1083 } 1083 1084 1085 + static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1086 + .copy_pte_num_dw = 7, 1087 + .copy_pte = sdma_v3_0_vm_copy_pte, 1088 + 1089 + .write_pte = sdma_v3_0_vm_write_pte, 1090 + .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1091 + }; 1092 + 1084 1093 static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block) 1085 1094 { 1086 1095 struct amdgpu_device *adev = ip_block->adev; ··· 1109 1102 1110 1103 sdma_v3_0_set_ring_funcs(adev); 1111 1104 sdma_v3_0_set_buffer_funcs(adev); 1112 - sdma_v3_0_set_vm_pte_funcs(adev); 1105 + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v3_0_vm_pte_funcs); 1113 1106 sdma_v3_0_set_irq_funcs(adev); 1114 1107 1115 1108 return 0; ··· 1679 1672 { 1680 1673 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; 1681 1674 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1682 - } 1683 - 1684 - static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1685 - .copy_pte_num_dw = 7, 1686 - .copy_pte = sdma_v3_0_vm_copy_pte, 1687 - 1688 - .write_pte = sdma_v3_0_vm_write_pte, 1689 - .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1690 - }; 1691 - 1692 - static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1693 - { 1694 - unsigned i; 1695 - 1696 - adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; 1697 - for (i = 0; i < adev->sdma.num_instances; i++) { 1698 - adev->vm_manager.vm_pte_scheds[i] = 1699 - &adev->sdma.instance[i].ring.sched; 1700 - } 1701 - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1702 1675 } 1703 1676 1704 1677 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
+9 -26
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
··· 129 129 130 130 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 131 131 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 132 - static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 133 132 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 134 133 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev); 135 134 ··· 1750 1751 } 1751 1752 } 1752 1753 1754 + static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 1755 + .copy_pte_num_dw = 7, 1756 + .copy_pte = sdma_v4_0_vm_copy_pte, 1757 + 1758 + .write_pte = sdma_v4_0_vm_write_pte, 1759 + .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 1760 + }; 1761 + 1753 1762 static int sdma_v4_0_early_init(struct amdgpu_ip_block *ip_block) 1754 1763 { 1755 1764 struct amdgpu_device *adev = ip_block->adev; ··· 1776 1769 1777 1770 sdma_v4_0_set_ring_funcs(adev); 1778 1771 sdma_v4_0_set_buffer_funcs(adev); 1779 - sdma_v4_0_set_vm_pte_funcs(adev); 1772 + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_0_vm_pte_funcs); 1780 1773 sdma_v4_0_set_irq_funcs(adev); 1781 1774 sdma_v4_0_set_ras_funcs(adev); 1782 1775 ··· 2620 2613 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2621 2614 else 2622 2615 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2623 - } 2624 - 2625 - static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 2626 - .copy_pte_num_dw = 7, 2627 - .copy_pte = sdma_v4_0_vm_copy_pte, 2628 - 2629 - .write_pte = sdma_v4_0_vm_write_pte, 2630 - .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 2631 - }; 2632 - 2633 - static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2634 - { 2635 - struct drm_gpu_scheduler *sched; 2636 - unsigned i; 2637 - 2638 - adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 2639 - for (i = 0; i < adev->sdma.num_instances; i++) { 2640 - if (adev->sdma.has_page_queue) 2641 - sched = &adev->sdma.instance[i].page.sched; 2642 - else 2643 - sched = &adev->sdma.instance[i].ring.sched; 2644 - adev->vm_manager.vm_pte_scheds[i] = sched; 2645 - } 2646 - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2647 2616 } 2648 2617 2649 2618 static void sdma_v4_0_get_ras_error_count(uint32_t value,
+9 -26
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
··· 104 104 105 105 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); 106 106 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); 107 - static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev); 108 107 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); 109 108 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); 110 109 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev); ··· 1346 1347 .soft_reset_kernel_queue = &sdma_v4_4_2_soft_reset_engine, 1347 1348 }; 1348 1349 1350 + static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 1351 + .copy_pte_num_dw = 7, 1352 + .copy_pte = sdma_v4_4_2_vm_copy_pte, 1353 + 1354 + .write_pte = sdma_v4_4_2_vm_write_pte, 1355 + .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 1356 + }; 1357 + 1349 1358 static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) 1350 1359 { 1351 1360 struct amdgpu_device *adev = ip_block->adev; ··· 1369 1362 1370 1363 sdma_v4_4_2_set_ring_funcs(adev); 1371 1364 sdma_v4_4_2_set_buffer_funcs(adev); 1372 - sdma_v4_4_2_set_vm_pte_funcs(adev); 1365 + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_4_2_vm_pte_funcs); 1373 1366 sdma_v4_4_2_set_irq_funcs(adev); 1374 1367 sdma_v4_4_2_set_ras_funcs(adev); 1375 1368 return 0; ··· 2321 2314 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; 2322 2315 else 2323 2316 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2324 - } 2325 - 2326 - static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { 2327 - .copy_pte_num_dw = 7, 2328 - .copy_pte = sdma_v4_4_2_vm_copy_pte, 2329 - 2330 - .write_pte = sdma_v4_4_2_vm_write_pte, 2331 - .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, 2332 - }; 2333 - 2334 - static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev) 2335 - { 2336 - struct drm_gpu_scheduler *sched; 2337 - unsigned i; 2338 - 2339 - adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs; 2340 - for (i = 0; i < adev->sdma.num_instances; i++) { 2341 - if (adev->sdma.has_page_queue) 2342 - sched = &adev->sdma.instance[i].page.sched; 2343 - else 2344 - sched = &adev->sdma.instance[i].ring.sched; 2345 - adev->vm_manager.vm_pte_scheds[i] = sched; 2346 - } 2347 - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2348 2317 } 2349 2318 2350 2319 /**
+8 -23
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
··· 110 110 111 111 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev); 112 112 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev); 113 - static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev); 114 113 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev); 115 114 static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring); 116 115 static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring); ··· 1356 1357 .soft_reset_kernel_queue = &sdma_v5_0_soft_reset_engine, 1357 1358 }; 1358 1359 1360 + static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { 1361 + .copy_pte_num_dw = 7, 1362 + .copy_pte = sdma_v5_0_vm_copy_pte, 1363 + .write_pte = sdma_v5_0_vm_write_pte, 1364 + .set_pte_pde = sdma_v5_0_vm_set_pte_pde, 1365 + }; 1366 + 1359 1367 static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block) 1360 1368 { 1361 1369 struct amdgpu_device *adev = ip_block->adev; ··· 1374 1368 1375 1369 sdma_v5_0_set_ring_funcs(adev); 1376 1370 sdma_v5_0_set_buffer_funcs(adev); 1377 - sdma_v5_0_set_vm_pte_funcs(adev); 1371 + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_0_vm_pte_funcs); 1378 1372 sdma_v5_0_set_irq_funcs(adev); 1379 1373 sdma_v5_0_set_mqd_funcs(adev); 1380 1374 ··· 2055 2049 if (adev->mman.buffer_funcs == NULL) { 2056 2050 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs; 2057 2051 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2058 - } 2059 - } 2060 - 2061 - static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { 2062 - .copy_pte_num_dw = 7, 2063 - .copy_pte = sdma_v5_0_vm_copy_pte, 2064 - .write_pte = sdma_v5_0_vm_write_pte, 2065 - .set_pte_pde = sdma_v5_0_vm_set_pte_pde, 2066 - }; 2067 - 2068 - static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev) 2069 - { 2070 - unsigned i; 2071 - 2072 - if (adev->vm_manager.vm_pte_funcs == NULL) { 2073 - adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; 2074 - for (i = 0; i < adev->sdma.num_instances; i++) { 2075 - adev->vm_manager.vm_pte_scheds[i] = 2076 - &adev->sdma.instance[i].ring.sched; 2077 - } 2078 - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2079 2052 } 2080 2053 } 2081 2054
+8 -23
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
··· 111 111 112 112 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); 113 113 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); 114 - static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); 115 114 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); 116 115 static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring); 117 116 static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring); ··· 1247 1248 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1248 1249 } 1249 1250 1251 + static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { 1252 + .copy_pte_num_dw = 7, 1253 + .copy_pte = sdma_v5_2_vm_copy_pte, 1254 + .write_pte = sdma_v5_2_vm_write_pte, 1255 + .set_pte_pde = sdma_v5_2_vm_set_pte_pde, 1256 + }; 1257 + 1250 1258 static int sdma_v5_2_early_init(struct amdgpu_ip_block *ip_block) 1251 1259 { 1252 1260 struct amdgpu_device *adev = ip_block->adev; ··· 1265 1259 1266 1260 sdma_v5_2_set_ring_funcs(adev); 1267 1261 sdma_v5_2_set_buffer_funcs(adev); 1268 - sdma_v5_2_set_vm_pte_funcs(adev); 1262 + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_2_vm_pte_funcs); 1269 1263 sdma_v5_2_set_irq_funcs(adev); 1270 1264 sdma_v5_2_set_mqd_funcs(adev); 1271 1265 ··· 2059 2053 if (adev->mman.buffer_funcs == NULL) { 2060 2054 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; 2061 2055 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 2062 - } 2063 - } 2064 - 2065 - static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { 2066 - .copy_pte_num_dw = 7, 2067 - .copy_pte = sdma_v5_2_vm_copy_pte, 2068 - .write_pte = sdma_v5_2_vm_write_pte, 2069 - .set_pte_pde = sdma_v5_2_vm_set_pte_pde, 2070 - }; 2071 - 2072 - static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) 2073 - { 2074 - unsigned i; 2075 - 2076 - if (adev->vm_manager.vm_pte_funcs == NULL) { 2077 - adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; 2078 - for (i = 0; i < adev->sdma.num_instances; i++) { 2079 - adev->vm_manager.vm_pte_scheds[i] = 2080 - &adev->sdma.instance[i].ring.sched; 2081 - } 2082 - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 2083 2056 } 2084 2057 } 2085 2058
+8 -21
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
··· 120 120 121 121 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev); 122 122 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev); 123 - static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev); 124 123 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev); 125 124 static int sdma_v6_0_start(struct amdgpu_device *adev); 126 125 ··· 1279 1280 csa_info->alignment = SDMA6_CSA_ALIGNMENT; 1280 1281 } 1281 1282 1283 + static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { 1284 + .copy_pte_num_dw = 7, 1285 + .copy_pte = sdma_v6_0_vm_copy_pte, 1286 + .write_pte = sdma_v6_0_vm_write_pte, 1287 + .set_pte_pde = sdma_v6_0_vm_set_pte_pde, 1288 + }; 1289 + 1282 1290 static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block) 1283 1291 { 1284 1292 struct amdgpu_device *adev = ip_block->adev; ··· 1314 1308 1315 1309 sdma_v6_0_set_ring_funcs(adev); 1316 1310 sdma_v6_0_set_buffer_funcs(adev); 1317 - sdma_v6_0_set_vm_pte_funcs(adev); 1311 + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v6_0_vm_pte_funcs); 1318 1312 sdma_v6_0_set_irq_funcs(adev); 1319 1313 sdma_v6_0_set_mqd_funcs(adev); 1320 1314 sdma_v6_0_set_ras_funcs(adev); ··· 1897 1891 { 1898 1892 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs; 1899 1893 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1900 - } 1901 - 1902 - static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { 1903 - .copy_pte_num_dw = 7, 1904 - .copy_pte = sdma_v6_0_vm_copy_pte, 1905 - .write_pte = sdma_v6_0_vm_write_pte, 1906 - .set_pte_pde = sdma_v6_0_vm_set_pte_pde, 1907 - }; 1908 - 1909 - static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1910 - { 1911 - unsigned i; 1912 - 1913 - adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs; 1914 - for (i = 0; i < adev->sdma.num_instances; i++) { 1915 - adev->vm_manager.vm_pte_scheds[i] = 1916 - &adev->sdma.instance[i].ring.sched; 1917 - } 1918 - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1919 1894 } 1920 1895 1921 1896 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = {
+8 -21
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
··· 119 119 120 120 static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev); 121 121 static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev); 122 - static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev); 123 122 static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev); 124 123 static int sdma_v7_0_start(struct amdgpu_device *adev); 125 124 ··· 1263 1264 csa_info->alignment = SDMA7_CSA_ALIGNMENT; 1264 1265 } 1265 1266 1267 + static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = { 1268 + .copy_pte_num_dw = 8, 1269 + .copy_pte = sdma_v7_0_vm_copy_pte, 1270 + .write_pte = sdma_v7_0_vm_write_pte, 1271 + .set_pte_pde = sdma_v7_0_vm_set_pte_pde, 1272 + }; 1273 + 1266 1274 static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block) 1267 1275 { 1268 1276 struct amdgpu_device *adev = ip_block->adev; ··· 1300 1294 1301 1295 sdma_v7_0_set_ring_funcs(adev); 1302 1296 sdma_v7_0_set_buffer_funcs(adev); 1303 - sdma_v7_0_set_vm_pte_funcs(adev); 1297 + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v7_0_vm_pte_funcs); 1304 1298 sdma_v7_0_set_irq_funcs(adev); 1305 1299 sdma_v7_0_set_mqd_funcs(adev); 1306 1300 adev->sdma.get_csa_info = &sdma_v7_0_get_csa_info; ··· 1847 1841 { 1848 1842 adev->mman.buffer_funcs = &sdma_v7_0_buffer_funcs; 1849 1843 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1850 - } 1851 - 1852 - static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = { 1853 - .copy_pte_num_dw = 8, 1854 - .copy_pte = sdma_v7_0_vm_copy_pte, 1855 - .write_pte = sdma_v7_0_vm_write_pte, 1856 - .set_pte_pde = sdma_v7_0_vm_set_pte_pde, 1857 - }; 1858 - 1859 - static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1860 - { 1861 - unsigned i; 1862 - 1863 - adev->vm_manager.vm_pte_funcs = &sdma_v7_0_vm_pte_funcs; 1864 - for (i = 0; i < adev->sdma.num_instances; i++) { 1865 - adev->vm_manager.vm_pte_scheds[i] = 1866 - &adev->sdma.instance[i].ring.sched; 1867 - } 1868 - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1869 1844 } 1870 1845 1871 1846 const struct amdgpu_ip_block_version sdma_v7_0_ip_block = {
+8 -21
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
··· 110 110 111 111 static void sdma_v7_1_set_ring_funcs(struct amdgpu_device *adev); 112 112 static void sdma_v7_1_set_buffer_funcs(struct amdgpu_device *adev); 113 - static void sdma_v7_1_set_vm_pte_funcs(struct amdgpu_device *adev); 114 113 static void sdma_v7_1_set_irq_funcs(struct amdgpu_device *adev); 115 114 static int sdma_v7_1_inst_start(struct amdgpu_device *adev, 116 115 uint32_t inst_mask); ··· 1247 1248 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1248 1249 } 1249 1250 1251 + static const struct amdgpu_vm_pte_funcs sdma_v7_1_vm_pte_funcs = { 1252 + .copy_pte_num_dw = 8, 1253 + .copy_pte = sdma_v7_1_vm_copy_pte, 1254 + .write_pte = sdma_v7_1_vm_write_pte, 1255 + .set_pte_pde = sdma_v7_1_vm_set_pte_pde, 1256 + }; 1257 + 1250 1258 static int sdma_v7_1_early_init(struct amdgpu_ip_block *ip_block) 1251 1259 { 1252 1260 struct amdgpu_device *adev = ip_block->adev; ··· 1267 1261 1268 1262 sdma_v7_1_set_ring_funcs(adev); 1269 1263 sdma_v7_1_set_buffer_funcs(adev); 1270 - sdma_v7_1_set_vm_pte_funcs(adev); 1264 + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v7_1_vm_pte_funcs); 1271 1265 sdma_v7_1_set_irq_funcs(adev); 1272 1266 sdma_v7_1_set_mqd_funcs(adev); 1273 1267 ··· 1757 1751 { 1758 1752 adev->mman.buffer_funcs = &sdma_v7_1_buffer_funcs; 1759 1753 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1760 - } 1761 - 1762 - static const struct amdgpu_vm_pte_funcs sdma_v7_1_vm_pte_funcs = { 1763 - .copy_pte_num_dw = 8, 1764 - .copy_pte = sdma_v7_1_vm_copy_pte, 1765 - .write_pte = sdma_v7_1_vm_write_pte, 1766 - .set_pte_pde = sdma_v7_1_vm_set_pte_pde, 1767 - }; 1768 - 1769 - static void sdma_v7_1_set_vm_pte_funcs(struct amdgpu_device *adev) 1770 - { 1771 - unsigned i; 1772 - 1773 - adev->vm_manager.vm_pte_funcs = &sdma_v7_1_vm_pte_funcs; 1774 - for (i = 0; i < adev->sdma.num_instances; i++) { 1775 - adev->vm_manager.vm_pte_scheds[i] = 1776 - &adev->sdma.instance[i].ring.sched; 1777 - } 1778 - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1779 1754 } 1780 1755 1781 1756 const struct amdgpu_ip_block_version sdma_v7_1_ip_block = {
+9 -22
drivers/gpu/drm/amd/amdgpu/si_dma.c
··· 37 37 38 38 static void si_dma_set_ring_funcs(struct amdgpu_device *adev); 39 39 static void si_dma_set_buffer_funcs(struct amdgpu_device *adev); 40 - static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev); 41 40 static void si_dma_set_irq_funcs(struct amdgpu_device *adev); 42 41 43 42 /** ··· 472 473 amdgpu_ring_write(ring, val); 473 474 } 474 475 476 + static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = { 477 + .copy_pte_num_dw = 5, 478 + .copy_pte = si_dma_vm_copy_pte, 479 + 480 + .write_pte = si_dma_vm_write_pte, 481 + .set_pte_pde = si_dma_vm_set_pte_pde, 482 + }; 483 + 475 484 static int si_dma_early_init(struct amdgpu_ip_block *ip_block) 476 485 { 477 486 struct amdgpu_device *adev = ip_block->adev; ··· 488 481 489 482 si_dma_set_ring_funcs(adev); 490 483 si_dma_set_buffer_funcs(adev); 491 - si_dma_set_vm_pte_funcs(adev); 484 + amdgpu_sdma_set_vm_pte_scheds(adev, &si_dma_vm_pte_funcs); 492 485 si_dma_set_irq_funcs(adev); 493 486 494 487 return 0; ··· 835 828 { 836 829 adev->mman.buffer_funcs = &si_dma_buffer_funcs; 837 830 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 838 - } 839 - 840 - static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = { 841 - .copy_pte_num_dw = 5, 842 - .copy_pte = si_dma_vm_copy_pte, 843 - 844 - .write_pte = si_dma_vm_write_pte, 845 - .set_pte_pde = si_dma_vm_set_pte_pde, 846 - }; 847 - 848 - static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev) 849 - { 850 - unsigned i; 851 - 852 - adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs; 853 - for (i = 0; i < adev->sdma.num_instances; i++) { 854 - adev->vm_manager.vm_pte_scheds[i] = 855 - &adev->sdma.instance[i].ring.sched; 856 - } 857 - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 858 831 } 859 832 860 833 const struct amdgpu_ip_block_version si_dma_ip_block =