Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018
Add support for the global clock controller found on IPQ5018
based devices.
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Co-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/1690533192-22220-3-git-send-email-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Sricharan Ramabadhran
and committed by
Bjorn Andersson
e3fdbef1
2f6be35d
+3733
+8
drivers/clk/qcom/Kconfig
+8
drivers/clk/qcom/Kconfig
···
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Say Y if you want to use peripheral devices such as UART, SPI,
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i2c, USB, SD/eMMC, etc.
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+
config IPQ_GCC_5018
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tristate "IPQ5018 Global Clock Controller"
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depends on ARM64 || COMPILE_TEST
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help
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Support for global clock controller on ipq5018 devices.
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Say Y if you want to use peripheral devices such as UART, SPI,
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i2c, USB, SD/eMMC, etc.
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+
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config IPQ_GCC_5332
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tristate "IPQ5332 Global Clock Controller"
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depends on ARM64 || COMPILE_TEST
+1
drivers/clk/qcom/Makefile
+1
drivers/clk/qcom/Makefile
···
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obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
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obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
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obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
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+
obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o
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obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
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obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
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obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
+3724
drivers/clk/qcom/gcc-ipq5018.c
+3724
drivers/clk/qcom/gcc-ipq5018.c
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+
/*
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* Copyright (c) 2023, The Linux Foundation. All rights reserved.
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+
*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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+
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#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
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#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
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+
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "clk-regmap-phy-mux.h"
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#include "reset.h"
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+
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/* Need to match the order of clocks in DT binding */
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enum {
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DT_XO,
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DT_SLEEP_CLK,
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DT_PCIE20_PHY0_PIPE_CLK,
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DT_PCIE20_PHY1_PIPE_CLK,
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DT_USB3_PHY0_CC_PIPE_CLK,
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DT_GEPHY_RX_CLK,
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DT_GEPHY_TX_CLK,
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DT_UNIPHY_RX_CLK,
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DT_UNIPHY_TX_CLK,
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};
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+
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enum {
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P_XO,
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P_CORE_PI_SLEEP_CLK,
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P_PCIE20_PHY0_PIPE,
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P_PCIE20_PHY1_PIPE,
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P_USB3PHY_0_PIPE,
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P_GEPHY_RX,
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P_GEPHY_TX,
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P_UNIPHY_RX,
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P_UNIPHY_TX,
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P_GPLL0,
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P_GPLL0_DIV2,
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P_GPLL2,
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P_GPLL4,
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P_UBI32_PLL,
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};
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+
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static const struct clk_parent_data gcc_xo_data[] = {
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{ .index = DT_XO },
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};
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+
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static const struct clk_parent_data gcc_sleep_clk_data[] = {
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{ .index = DT_SLEEP_CLK },
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};
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+
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static struct clk_alpha_pll gpll0_main = {
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.offset = 0x21000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.enable_reg = 0x0b000,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data) {
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.name = "gpll0_main",
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.parent_data = gcc_xo_data,
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.num_parents = ARRAY_SIZE(gcc_xo_data),
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.ops = &clk_alpha_pll_stromer_ops,
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},
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},
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};
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+
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static struct clk_alpha_pll gpll2_main = {
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.offset = 0x4a000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.enable_reg = 0x0b000,
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.enable_mask = BIT(2),
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.hw.init = &(struct clk_init_data) {
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.name = "gpll2_main",
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.parent_data = gcc_xo_data,
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.num_parents = ARRAY_SIZE(gcc_xo_data),
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.ops = &clk_alpha_pll_stromer_ops,
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},
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},
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};
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+
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static struct clk_alpha_pll gpll4_main = {
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.offset = 0x24000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.enable_reg = 0x0b000,
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.enable_mask = BIT(5),
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.hw.init = &(struct clk_init_data) {
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.name = "gpll4_main",
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.parent_data = gcc_xo_data,
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.num_parents = ARRAY_SIZE(gcc_xo_data),
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.ops = &clk_alpha_pll_stromer_ops,
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},
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},
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};
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+
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static struct clk_alpha_pll ubi32_pll_main = {
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.offset = 0x25000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.clkr = {
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.enable_reg = 0x0b000,
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.enable_mask = BIT(6),
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.hw.init = &(struct clk_init_data) {
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+
.name = "ubi32_pll_main",
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.parent_data = gcc_xo_data,
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.num_parents = ARRAY_SIZE(gcc_xo_data),
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.ops = &clk_alpha_pll_stromer_ops,
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},
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},
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};
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+
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static struct clk_alpha_pll_postdiv gpll0 = {
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.offset = 0x21000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "gpll0",
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.parent_hws = (const struct clk_hw *[]) {
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&gpll0_main.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_ro_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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+
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static struct clk_alpha_pll_postdiv gpll2 = {
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.offset = 0x4a000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "gpll2",
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.parent_hws = (const struct clk_hw *[]) {
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&gpll2_main.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_ro_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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+
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static struct clk_alpha_pll_postdiv gpll4 = {
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.offset = 0x24000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "gpll4",
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+
.parent_hws = (const struct clk_hw *[]) {
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&gpll4_main.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_ro_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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+
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static struct clk_alpha_pll_postdiv ubi32_pll = {
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.offset = 0x25000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.width = 4,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "ubi32_pll",
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.parent_hws = (const struct clk_hw *[]) {
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&ubi32_pll_main.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_postdiv_ro_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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+
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static struct clk_fixed_factor gpll0_out_main_div2 = {
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.mult = 1,
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.div = 2,
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.hw.init = &(struct clk_init_data) {
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.name = "gpll0_out_main_div2",
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.parent_hws = (const struct clk_hw *[]) {
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&gpll0_main.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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+
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static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
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{ .index = DT_XO },
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{ .hw = &gpll0.clkr.hw },
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{ .hw = &gpll0_out_main_div2.hw },
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};
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+
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static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
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{ P_XO, 0 },
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{ P_GPLL0, 1 },
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{ P_GPLL0_DIV2, 4 },
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+
};
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+
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static const struct clk_parent_data gcc_xo_gpll0[] = {
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{ .index = DT_XO },
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{ .hw = &gpll0.clkr.hw },
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};
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+
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static const struct parent_map gcc_xo_gpll0_map[] = {
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{ P_XO, 0 },
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{ P_GPLL0, 1 },
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};
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+
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static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
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{ .index = DT_XO },
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{ .hw = &gpll0_out_main_div2.hw },
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{ .hw = &gpll0.clkr.hw },
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};
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+
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static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
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{ P_XO, 0 },
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{ P_GPLL0_DIV2, 2 },
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{ P_GPLL0, 1 },
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};
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+
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static const struct clk_parent_data gcc_xo_ubi32_gpll0[] = {
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{ .index = DT_XO },
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{ .hw = &ubi32_pll.clkr.hw },
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{ .hw = &gpll0.clkr.hw },
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};
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+
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static const struct parent_map gcc_xo_ubi32_gpll0_map[] = {
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{ P_XO, 0 },
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{ P_UBI32_PLL, 1 },
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{ P_GPLL0, 2 },
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};
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+
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static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
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{ .index = DT_XO },
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{ .hw = &gpll0.clkr.hw },
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{ .hw = &gpll2.clkr.hw },
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};
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+
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static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
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{ P_XO, 0 },
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{ P_GPLL0, 1 },
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{ P_GPLL2, 2 },
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};
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+
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static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4[] = {
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{ .index = DT_XO },
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{ .hw = &gpll0.clkr.hw },
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{ .hw = &gpll2.clkr.hw },
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{ .hw = &gpll4.clkr.hw },
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};
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+
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static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
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{ P_XO, 0 },
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{ P_GPLL0, 1 },
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{ P_GPLL2, 2 },
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{ P_GPLL4, 3 },
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};
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+
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static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
267
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{ .index = DT_XO },
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{ .hw = &gpll0.clkr.hw },
269
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{ .hw = &gpll4.clkr.hw },
270
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};
271
+
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static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
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{ P_XO, 0 },
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{ P_GPLL0, 1 },
275
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{ P_GPLL4, 2 },
276
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};
277
+
278
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static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
279
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{ .index = DT_XO },
280
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{ .hw = &gpll0.clkr.hw },
281
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{ .index = DT_SLEEP_CLK },
282
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};
283
+
284
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static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
285
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{ P_XO, 0 },
286
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{ P_GPLL0, 2 },
287
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{ P_CORE_PI_SLEEP_CLK, 6 },
288
+
};
289
+
290
+
static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk[] = {
291
+
{ .index = DT_XO },
292
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{ .hw = &gpll0.clkr.hw },
293
+
{ .hw = &gpll0_out_main_div2.hw },
294
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{ .index = DT_SLEEP_CLK },
295
+
};
296
+
297
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static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map[] = {
298
+
{ P_XO, 0 },
299
+
{ P_GPLL0, 1 },
300
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{ P_GPLL0_DIV2, 4 },
301
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{ P_CORE_PI_SLEEP_CLK, 6 },
302
+
};
303
+
304
+
static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
305
+
{ .index = DT_XO },
306
+
{ .hw = &gpll0.clkr.hw },
307
+
{ .hw = &gpll2.clkr.hw },
308
+
{ .hw = &gpll0_out_main_div2.hw },
309
+
};
310
+
311
+
static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
312
+
{ P_XO, 0 },
313
+
{ P_GPLL0, 1 },
314
+
{ P_GPLL2, 2 },
315
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{ P_GPLL0_DIV2, 4 },
316
+
};
317
+
318
+
static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
319
+
{ .index = DT_XO },
320
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{ .hw = &gpll4.clkr.hw },
321
+
{ .hw = &gpll0.clkr.hw },
322
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{ .hw = &gpll0_out_main_div2.hw },
323
+
};
324
+
325
+
static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1[] = {
326
+
{ P_XO, 0 },
327
+
{ P_GPLL4, 1 },
328
+
{ P_GPLL0, 2 },
329
+
{ P_GPLL0_DIV2, 4 },
330
+
};
331
+
332
+
static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2[] = {
333
+
{ P_XO, 0 },
334
+
{ P_GPLL4, 1 },
335
+
{ P_GPLL0, 3 },
336
+
{ P_GPLL0_DIV2, 4 },
337
+
};
338
+
339
+
static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = {
340
+
{ .index = DT_XO },
341
+
{ .index = DT_GEPHY_RX_CLK },
342
+
{ .index = DT_GEPHY_TX_CLK },
343
+
{ .hw = &ubi32_pll.clkr.hw },
344
+
{ .hw = &gpll0.clkr.hw },
345
+
};
346
+
347
+
static const struct parent_map gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map[] = {
348
+
{ P_XO, 0 },
349
+
{ P_GEPHY_RX, 1 },
350
+
{ P_GEPHY_TX, 2 },
351
+
{ P_UBI32_PLL, 3 },
352
+
{ P_GPLL0, 4 },
353
+
};
354
+
355
+
static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = {
356
+
{ .index = DT_XO },
357
+
{ .index = DT_GEPHY_TX_CLK },
358
+
{ .index = DT_GEPHY_RX_CLK },
359
+
{ .hw = &ubi32_pll.clkr.hw },
360
+
{ .hw = &gpll0.clkr.hw },
361
+
};
362
+
363
+
static const struct parent_map gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map[] = {
364
+
{ P_XO, 0 },
365
+
{ P_GEPHY_TX, 1 },
366
+
{ P_GEPHY_RX, 2 },
367
+
{ P_UBI32_PLL, 3 },
368
+
{ P_GPLL0, 4 },
369
+
};
370
+
371
+
static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {
372
+
{ .index = DT_XO },
373
+
{ .index = DT_UNIPHY_RX_CLK },
374
+
{ .index = DT_UNIPHY_TX_CLK },
375
+
{ .hw = &ubi32_pll.clkr.hw },
376
+
{ .hw = &gpll0.clkr.hw },
377
+
};
378
+
379
+
static const struct parent_map gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map[] = {
380
+
{ P_XO, 0 },
381
+
{ P_UNIPHY_RX, 1 },
382
+
{ P_UNIPHY_TX, 2 },
383
+
{ P_UBI32_PLL, 3 },
384
+
{ P_GPLL0, 4 },
385
+
};
386
+
387
+
static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {
388
+
{ .index = DT_XO },
389
+
{ .index = DT_UNIPHY_TX_CLK },
390
+
{ .index = DT_UNIPHY_RX_CLK },
391
+
{ .hw = &ubi32_pll.clkr.hw },
392
+
{ .hw = &gpll0.clkr.hw },
393
+
};
394
+
395
+
static const struct parent_map gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map[] = {
396
+
{ P_XO, 0 },
397
+
{ P_UNIPHY_TX, 1 },
398
+
{ P_UNIPHY_RX, 2 },
399
+
{ P_UBI32_PLL, 3 },
400
+
{ P_GPLL0, 4 },
401
+
};
402
+
403
+
static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
404
+
{ .index = DT_PCIE20_PHY0_PIPE_CLK },
405
+
{ .index = DT_XO },
406
+
};
407
+
408
+
static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
409
+
{ P_PCIE20_PHY0_PIPE, 0 },
410
+
{ P_XO, 2 },
411
+
};
412
+
413
+
static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
414
+
{ .index = DT_PCIE20_PHY1_PIPE_CLK },
415
+
{ .index = DT_XO },
416
+
};
417
+
418
+
static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
419
+
{ P_PCIE20_PHY1_PIPE, 0 },
420
+
{ P_XO, 2 },
421
+
};
422
+
423
+
static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
424
+
{ .index = DT_USB3_PHY0_CC_PIPE_CLK },
425
+
{ .index = DT_XO },
426
+
};
427
+
428
+
static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
429
+
{ P_USB3PHY_0_PIPE, 0 },
430
+
{ P_XO, 2 },
431
+
};
432
+
433
+
static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
434
+
F(24000000, P_XO, 1, 0, 0),
435
+
F(100000000, P_GPLL0, 8, 0, 0),
436
+
{ }
437
+
};
438
+
439
+
static struct clk_rcg2 adss_pwm_clk_src = {
440
+
.cmd_rcgr = 0x1f008,
441
+
.freq_tbl = ftbl_adss_pwm_clk_src,
442
+
.hid_width = 5,
443
+
.parent_map = gcc_xo_gpll0_map,
444
+
.clkr.hw.init = &(struct clk_init_data) {
445
+
.name = "adss_pwm_clk_src",
446
+
.parent_data = gcc_xo_gpll0,
447
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
448
+
.ops = &clk_rcg2_ops,
449
+
},
450
+
};
451
+
452
+
static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
453
+
F(50000000, P_GPLL0, 16, 0, 0),
454
+
{ }
455
+
};
456
+
457
+
static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
458
+
.cmd_rcgr = 0x0200c,
459
+
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
460
+
.hid_width = 5,
461
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
462
+
.clkr.hw.init = &(struct clk_init_data) {
463
+
.name = "blsp1_qup1_i2c_apps_clk_src",
464
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
465
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
466
+
.ops = &clk_rcg2_ops,
467
+
},
468
+
};
469
+
470
+
static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
471
+
.cmd_rcgr = 0x03000,
472
+
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
473
+
.hid_width = 5,
474
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
475
+
.clkr.hw.init = &(struct clk_init_data) {
476
+
.name = "blsp1_qup2_i2c_apps_clk_src",
477
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
478
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
479
+
.ops = &clk_rcg2_ops,
480
+
},
481
+
};
482
+
483
+
static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
484
+
.cmd_rcgr = 0x04000,
485
+
.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
486
+
.hid_width = 5,
487
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
488
+
.clkr.hw.init = &(struct clk_init_data) {
489
+
.name = "blsp1_qup3_i2c_apps_clk_src",
490
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
491
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
492
+
.ops = &clk_rcg2_ops,
493
+
},
494
+
};
495
+
496
+
static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
497
+
F(960000, P_XO, 10, 2, 5),
498
+
F(4800000, P_XO, 5, 0, 0),
499
+
F(9600000, P_XO, 2, 4, 5),
500
+
F(16000000, P_GPLL0, 10, 1, 5),
501
+
F(24000000, P_XO, 1, 0, 0),
502
+
F(50000000, P_GPLL0, 16, 0, 0),
503
+
{ }
504
+
};
505
+
506
+
static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
507
+
.cmd_rcgr = 0x02024,
508
+
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
509
+
.mnd_width = 8,
510
+
.hid_width = 5,
511
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
512
+
.clkr.hw.init = &(struct clk_init_data) {
513
+
.name = "blsp1_qup1_spi_apps_clk_src",
514
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
515
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
516
+
.ops = &clk_rcg2_ops,
517
+
},
518
+
};
519
+
520
+
static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
521
+
.cmd_rcgr = 0x03014,
522
+
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
523
+
.mnd_width = 8,
524
+
.hid_width = 5,
525
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
526
+
.clkr.hw.init = &(struct clk_init_data) {
527
+
.name = "blsp1_qup2_spi_apps_clk_src",
528
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
529
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
530
+
.ops = &clk_rcg2_ops,
531
+
},
532
+
};
533
+
534
+
static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
535
+
.cmd_rcgr = 0x04014,
536
+
.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
537
+
.mnd_width = 8,
538
+
.hid_width = 5,
539
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
540
+
.clkr.hw.init = &(struct clk_init_data) {
541
+
.name = "blsp1_qup3_spi_apps_clk_src",
542
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
543
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
544
+
.ops = &clk_rcg2_ops,
545
+
},
546
+
};
547
+
548
+
static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
549
+
F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
550
+
F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
551
+
F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
552
+
F(24000000, P_XO, 1, 0, 0),
553
+
F(25000000, P_GPLL0, 16, 1, 2),
554
+
F(40000000, P_GPLL0, 1, 1, 20),
555
+
F(46400000, P_GPLL0, 1, 29, 500),
556
+
F(48000000, P_GPLL0, 1, 3, 50),
557
+
F(51200000, P_GPLL0, 1, 8, 125),
558
+
F(56000000, P_GPLL0, 1, 7, 100),
559
+
F(58982400, P_GPLL0, 1, 1152, 15625),
560
+
F(60000000, P_GPLL0, 1, 3, 40),
561
+
F(64000000, P_GPLL0, 10, 4, 5),
562
+
{ }
563
+
};
564
+
565
+
static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
566
+
.cmd_rcgr = 0x02044,
567
+
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
568
+
.mnd_width = 16,
569
+
.hid_width = 5,
570
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
571
+
.clkr.hw.init = &(struct clk_init_data) {
572
+
.name = "blsp1_uart1_apps_clk_src",
573
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
574
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
575
+
.ops = &clk_rcg2_ops,
576
+
},
577
+
};
578
+
579
+
static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
580
+
.cmd_rcgr = 0x03034,
581
+
.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
582
+
.mnd_width = 16,
583
+
.hid_width = 5,
584
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
585
+
.clkr.hw.init = &(struct clk_init_data) {
586
+
.name = "blsp1_uart2_apps_clk_src",
587
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
588
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
589
+
.ops = &clk_rcg2_ops,
590
+
},
591
+
};
592
+
593
+
static const struct freq_tbl ftbl_crypto_clk_src[] = {
594
+
F(160000000, P_GPLL0, 5, 0, 0),
595
+
{ }
596
+
};
597
+
598
+
static struct clk_rcg2 crypto_clk_src = {
599
+
.cmd_rcgr = 0x16004,
600
+
.freq_tbl = ftbl_crypto_clk_src,
601
+
.hid_width = 5,
602
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
603
+
.clkr.hw.init = &(struct clk_init_data) {
604
+
.name = "crypto_clk_src",
605
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
606
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
607
+
.ops = &clk_rcg2_ops,
608
+
},
609
+
};
610
+
611
+
static const struct freq_tbl ftbl_gmac0_tx_clk_src[] = {
612
+
F(2500000, P_GEPHY_TX, 5, 0, 0),
613
+
F(24000000, P_XO, 1, 0, 0),
614
+
F(25000000, P_GEPHY_TX, 5, 0, 0),
615
+
F(125000000, P_GEPHY_TX, 1, 0, 0),
616
+
{ }
617
+
};
618
+
619
+
static struct clk_rcg2 gmac0_rx_clk_src = {
620
+
.cmd_rcgr = 0x68020,
621
+
.parent_map = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map,
622
+
.hid_width = 5,
623
+
.freq_tbl = ftbl_gmac0_tx_clk_src,
624
+
.clkr.hw.init = &(struct clk_init_data) {
625
+
.name = "gmac0_rx_clk_src",
626
+
.parent_data = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0,
627
+
.num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0),
628
+
.ops = &clk_rcg2_ops,
629
+
},
630
+
};
631
+
632
+
static struct clk_regmap_div gmac0_rx_div_clk_src = {
633
+
.reg = 0x68420,
634
+
.shift = 0,
635
+
.width = 4,
636
+
.clkr = {
637
+
.hw.init = &(struct clk_init_data) {
638
+
.name = "gmac0_rx_div_clk_src",
639
+
.parent_hws = (const struct clk_hw *[]) {
640
+
&gmac0_rx_clk_src.clkr.hw,
641
+
},
642
+
.num_parents = 1,
643
+
.ops = &clk_regmap_div_ops,
644
+
.flags = CLK_SET_RATE_PARENT,
645
+
},
646
+
},
647
+
};
648
+
649
+
static struct clk_rcg2 gmac0_tx_clk_src = {
650
+
.cmd_rcgr = 0x68028,
651
+
.parent_map = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map,
652
+
.hid_width = 5,
653
+
.freq_tbl = ftbl_gmac0_tx_clk_src,
654
+
.clkr.hw.init = &(struct clk_init_data) {
655
+
.name = "gmac0_tx_clk_src",
656
+
.parent_data = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0,
657
+
.num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0),
658
+
.ops = &clk_rcg2_ops,
659
+
},
660
+
};
661
+
662
+
static struct clk_regmap_div gmac0_tx_div_clk_src = {
663
+
.reg = 0x68424,
664
+
.shift = 0,
665
+
.width = 4,
666
+
.clkr = {
667
+
.hw.init = &(struct clk_init_data) {
668
+
.name = "gmac0_tx_div_clk_src",
669
+
.parent_hws = (const struct clk_hw *[]) {
670
+
&gmac0_tx_clk_src.clkr.hw,
671
+
},
672
+
.num_parents = 1,
673
+
.ops = &clk_regmap_div_ops,
674
+
.flags = CLK_SET_RATE_PARENT,
675
+
},
676
+
},
677
+
};
678
+
679
+
static const struct freq_tbl ftbl_gmac1_rx_clk_src[] = {
680
+
F(2500000, P_UNIPHY_RX, 12.5, 0, 0),
681
+
F(24000000, P_XO, 1, 0, 0),
682
+
F(25000000, P_UNIPHY_RX, 2.5, 0, 0),
683
+
F(125000000, P_UNIPHY_RX, 2.5, 0, 0),
684
+
F(125000000, P_UNIPHY_RX, 1, 0, 0),
685
+
F(312500000, P_UNIPHY_RX, 1, 0, 0),
686
+
{ }
687
+
};
688
+
689
+
static struct clk_rcg2 gmac1_rx_clk_src = {
690
+
.cmd_rcgr = 0x68030,
691
+
.parent_map = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map,
692
+
.hid_width = 5,
693
+
.freq_tbl = ftbl_gmac1_rx_clk_src,
694
+
.clkr.hw.init = &(struct clk_init_data) {
695
+
.name = "gmac1_rx_clk_src",
696
+
.parent_data = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0,
697
+
.num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0),
698
+
.ops = &clk_rcg2_ops,
699
+
},
700
+
};
701
+
702
+
static struct clk_regmap_div gmac1_rx_div_clk_src = {
703
+
.reg = 0x68430,
704
+
.shift = 0,
705
+
.width = 4,
706
+
.clkr = {
707
+
.hw.init = &(struct clk_init_data) {
708
+
.name = "gmac1_rx_div_clk_src",
709
+
.parent_hws = (const struct clk_hw *[]) {
710
+
&gmac1_rx_clk_src.clkr.hw,
711
+
},
712
+
.num_parents = 1,
713
+
.ops = &clk_regmap_div_ops,
714
+
.flags = CLK_SET_RATE_PARENT,
715
+
},
716
+
},
717
+
};
718
+
719
+
static const struct freq_tbl ftbl_gmac1_tx_clk_src[] = {
720
+
F(2500000, P_UNIPHY_TX, 12.5, 0, 0),
721
+
F(24000000, P_XO, 1, 0, 0),
722
+
F(25000000, P_UNIPHY_TX, 2.5, 0, 0),
723
+
F(125000000, P_UNIPHY_TX, 2.5, 0, 0),
724
+
F(125000000, P_UNIPHY_TX, 1, 0, 0),
725
+
F(312500000, P_UNIPHY_TX, 1, 0, 0),
726
+
{ }
727
+
};
728
+
729
+
static struct clk_rcg2 gmac1_tx_clk_src = {
730
+
.cmd_rcgr = 0x68038,
731
+
.parent_map = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map,
732
+
.hid_width = 5,
733
+
.freq_tbl = ftbl_gmac1_tx_clk_src,
734
+
.clkr.hw.init = &(struct clk_init_data) {
735
+
.name = "gmac1_tx_clk_src",
736
+
.parent_data = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0,
737
+
.num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0),
738
+
.ops = &clk_rcg2_ops,
739
+
},
740
+
};
741
+
742
+
static struct clk_regmap_div gmac1_tx_div_clk_src = {
743
+
.reg = 0x68434,
744
+
.shift = 0,
745
+
.width = 4,
746
+
.clkr = {
747
+
.hw.init = &(struct clk_init_data) {
748
+
.name = "gmac1_tx_div_clk_src",
749
+
.parent_hws = (const struct clk_hw *[]) {
750
+
&gmac1_tx_clk_src.clkr.hw,
751
+
},
752
+
.num_parents = 1,
753
+
.ops = &clk_regmap_div_ops,
754
+
.flags = CLK_SET_RATE_PARENT,
755
+
},
756
+
},
757
+
};
758
+
759
+
static const struct freq_tbl ftbl_gmac_clk_src[] = {
760
+
F(240000000, P_GPLL4, 5, 0, 0),
761
+
{ }
762
+
};
763
+
764
+
static struct clk_rcg2 gmac_clk_src = {
765
+
.cmd_rcgr = 0x68080,
766
+
.parent_map = gcc_xo_gpll0_gpll4_map,
767
+
.hid_width = 5,
768
+
.freq_tbl = ftbl_gmac_clk_src,
769
+
.clkr.hw.init = &(struct clk_init_data) {
770
+
.name = "gmac_clk_src",
771
+
.parent_data = gcc_xo_gpll0_gpll4,
772
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
773
+
.ops = &clk_rcg2_ops,
774
+
},
775
+
};
776
+
777
+
static const struct freq_tbl ftbl_gp_clk_src[] = {
778
+
F(200000000, P_GPLL0, 4, 0, 0),
779
+
{ }
780
+
};
781
+
782
+
static struct clk_rcg2 gp1_clk_src = {
783
+
.cmd_rcgr = 0x08004,
784
+
.freq_tbl = ftbl_gp_clk_src,
785
+
.mnd_width = 8,
786
+
.hid_width = 5,
787
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
788
+
.clkr.hw.init = &(struct clk_init_data) {
789
+
.name = "gp1_clk_src",
790
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
791
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
792
+
.ops = &clk_rcg2_ops,
793
+
},
794
+
};
795
+
796
+
static struct clk_rcg2 gp2_clk_src = {
797
+
.cmd_rcgr = 0x09004,
798
+
.freq_tbl = ftbl_gp_clk_src,
799
+
.mnd_width = 8,
800
+
.hid_width = 5,
801
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
802
+
.clkr.hw.init = &(struct clk_init_data) {
803
+
.name = "gp2_clk_src",
804
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
805
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
806
+
.ops = &clk_rcg2_ops,
807
+
},
808
+
};
809
+
810
+
static struct clk_rcg2 gp3_clk_src = {
811
+
.cmd_rcgr = 0x0a004,
812
+
.freq_tbl = ftbl_gp_clk_src,
813
+
.mnd_width = 8,
814
+
.hid_width = 5,
815
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
816
+
.clkr.hw.init = &(struct clk_init_data) {
817
+
.name = "gp3_clk_src",
818
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
819
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
820
+
.ops = &clk_rcg2_ops,
821
+
},
822
+
};
823
+
824
+
static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
825
+
F(133333334, P_GPLL0, 6, 0, 0),
826
+
{ }
827
+
};
828
+
829
+
struct clk_rcg2 lpass_axim_clk_src = {
830
+
.cmd_rcgr = 0x2e028,
831
+
.freq_tbl = ftbl_lpass_axim_clk_src,
832
+
.hid_width = 5,
833
+
.parent_map = gcc_xo_gpll0_map,
834
+
.clkr.hw.init = &(struct clk_init_data) {
835
+
.name = "lpass_axim_clk_src",
836
+
.parent_data = gcc_xo_gpll0,
837
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
838
+
.ops = &clk_rcg2_ops,
839
+
},
840
+
};
841
+
842
+
static const struct freq_tbl ftbl_lpass_sway_clk_src[] = {
843
+
F(66666667, P_GPLL0, 12, 0, 0),
844
+
{ }
845
+
};
846
+
847
+
struct clk_rcg2 lpass_sway_clk_src = {
848
+
.cmd_rcgr = 0x2e040,
849
+
.freq_tbl = ftbl_lpass_sway_clk_src,
850
+
.hid_width = 5,
851
+
.parent_map = gcc_xo_gpll0_map,
852
+
.clkr.hw.init = &(struct clk_init_data) {
853
+
.name = "lpass_sway_clk_src",
854
+
.parent_data = gcc_xo_gpll0,
855
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
856
+
.ops = &clk_rcg2_ops,
857
+
},
858
+
};
859
+
860
+
static const struct freq_tbl ftbl_pcie0_aux_clk_src[] = {
861
+
F(2000000, P_XO, 12, 0, 0),
862
+
};
863
+
864
+
static struct clk_rcg2 pcie0_aux_clk_src = {
865
+
.cmd_rcgr = 0x75020,
866
+
.freq_tbl = ftbl_pcie0_aux_clk_src,
867
+
.mnd_width = 16,
868
+
.hid_width = 5,
869
+
.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
870
+
.clkr.hw.init = &(struct clk_init_data) {
871
+
.name = "pcie0_aux_clk_src",
872
+
.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
873
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
874
+
.ops = &clk_rcg2_ops,
875
+
},
876
+
};
877
+
878
+
static const struct freq_tbl ftbl_pcie0_axi_clk_src[] = {
879
+
F(240000000, P_GPLL4, 5, 0, 0),
880
+
{ }
881
+
};
882
+
883
+
static struct clk_rcg2 pcie0_axi_clk_src = {
884
+
.cmd_rcgr = 0x75050,
885
+
.freq_tbl = ftbl_pcie0_axi_clk_src,
886
+
.hid_width = 5,
887
+
.parent_map = gcc_xo_gpll0_gpll4_map,
888
+
.clkr.hw.init = &(struct clk_init_data) {
889
+
.name = "pcie0_axi_clk_src",
890
+
.parent_data = gcc_xo_gpll0_gpll4,
891
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
892
+
.ops = &clk_rcg2_ops,
893
+
},
894
+
};
895
+
896
+
static struct clk_rcg2 pcie1_aux_clk_src = {
897
+
.cmd_rcgr = 0x76020,
898
+
.freq_tbl = ftbl_pcie0_aux_clk_src,
899
+
.mnd_width = 16,
900
+
.hid_width = 5,
901
+
.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
902
+
.clkr.hw.init = &(struct clk_init_data) {
903
+
.name = "pcie1_aux_clk_src",
904
+
.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
905
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
906
+
.ops = &clk_rcg2_ops,
907
+
},
908
+
};
909
+
910
+
static struct clk_rcg2 pcie1_axi_clk_src = {
911
+
.cmd_rcgr = 0x76050,
912
+
.freq_tbl = ftbl_gp_clk_src,
913
+
.hid_width = 5,
914
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
915
+
.clkr.hw.init = &(struct clk_init_data) {
916
+
.name = "pcie1_axi_clk_src",
917
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
918
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
919
+
.ops = &clk_rcg2_ops,
920
+
},
921
+
};
922
+
923
+
static struct clk_regmap_mux pcie0_pipe_clk_src = {
924
+
.reg = 0x7501c,
925
+
.shift = 8,
926
+
.width = 2,
927
+
.parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
928
+
.clkr = {
929
+
.hw.init = &(struct clk_init_data) {
930
+
.name = "pcie0_pipe_clk_src",
931
+
.parent_data = gcc_pcie20_phy0_pipe_clk_xo,
932
+
.num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
933
+
.ops = &clk_regmap_mux_closest_ops,
934
+
.flags = CLK_SET_RATE_PARENT,
935
+
},
936
+
},
937
+
};
938
+
939
+
static struct clk_regmap_mux pcie1_pipe_clk_src = {
940
+
.reg = 0x7601c,
941
+
.shift = 8,
942
+
.width = 2,
943
+
.parent_map = gcc_pcie20_phy1_pipe_clk_xo_map, .clkr = {
944
+
.hw.init = &(struct clk_init_data) {
945
+
.name = "pcie1_pipe_clk_src",
946
+
.parent_data = gcc_pcie20_phy1_pipe_clk_xo,
947
+
.num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
948
+
.ops = &clk_regmap_mux_closest_ops,
949
+
.flags = CLK_SET_RATE_PARENT,
950
+
},
951
+
},
952
+
};
953
+
954
+
static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
955
+
F(100000000, P_GPLL0, 8, 0, 0),
956
+
{ }
957
+
};
958
+
959
+
static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
960
+
.cmd_rcgr = 0x27000,
961
+
.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
962
+
.hid_width = 5,
963
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
964
+
.clkr.hw.init = &(struct clk_init_data) {
965
+
.name = "pcnoc_bfdcd_clk_src",
966
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
967
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
968
+
.ops = &clk_rcg2_ops,
969
+
},
970
+
};
971
+
972
+
static struct clk_fixed_factor pcnoc_clk_src = {
973
+
.mult = 1,
974
+
.div = 1,
975
+
.hw.init = &(struct clk_init_data) {
976
+
.name = "pcnoc_clk_src",
977
+
.parent_hws = (const struct clk_hw *[]) {
978
+
&pcnoc_bfdcd_clk_src.clkr.hw,
979
+
},
980
+
.num_parents = 1,
981
+
.ops = &clk_fixed_factor_ops,
982
+
.flags = CLK_SET_RATE_PARENT,
983
+
},
984
+
};
985
+
986
+
static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
987
+
F(240000000, P_GPLL4, 5, 0, 0),
988
+
{ }
989
+
};
990
+
991
+
static struct clk_rcg2 qdss_at_clk_src = {
992
+
.cmd_rcgr = 0x2900c,
993
+
.freq_tbl = ftbl_qdss_at_clk_src,
994
+
.hid_width = 5,
995
+
.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
996
+
.clkr.hw.init = &(struct clk_init_data) {
997
+
.name = "qdss_at_clk_src",
998
+
.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
999
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1000
+
.ops = &clk_rcg2_ops,
1001
+
},
1002
+
};
1003
+
1004
+
static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
1005
+
F(200000000, P_GPLL0, 4, 0, 0),
1006
+
{ }
1007
+
};
1008
+
1009
+
static struct clk_rcg2 qdss_stm_clk_src = {
1010
+
.cmd_rcgr = 0x2902c,
1011
+
.freq_tbl = ftbl_qdss_stm_clk_src,
1012
+
.hid_width = 5,
1013
+
.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1014
+
.clkr.hw.init = &(struct clk_init_data) {
1015
+
.name = "qdss_stm_clk_src",
1016
+
.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1017
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
1018
+
.ops = &clk_rcg2_ops,
1019
+
},
1020
+
};
1021
+
1022
+
static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
1023
+
F(266666667, P_GPLL0, 3, 0, 0),
1024
+
{ }
1025
+
};
1026
+
1027
+
static struct clk_rcg2 qdss_traceclkin_clk_src = {
1028
+
.cmd_rcgr = 0x29048,
1029
+
.freq_tbl = ftbl_qdss_traceclkin_clk_src,
1030
+
.hid_width = 5,
1031
+
.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
1032
+
.clkr.hw.init = &(struct clk_init_data) {
1033
+
.name = "qdss_traceclkin_clk_src",
1034
+
.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1035
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1036
+
.ops = &clk_rcg2_ops,
1037
+
},
1038
+
};
1039
+
1040
+
static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
1041
+
F(600000000, P_GPLL4, 2, 0, 0),
1042
+
{ }
1043
+
};
1044
+
1045
+
static struct clk_rcg2 qdss_tsctr_clk_src = {
1046
+
.cmd_rcgr = 0x29064,
1047
+
.freq_tbl = ftbl_qdss_tsctr_clk_src,
1048
+
.hid_width = 5,
1049
+
.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
1050
+
.clkr.hw.init = &(struct clk_init_data) {
1051
+
.name = "qdss_tsctr_clk_src",
1052
+
.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1053
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1054
+
.ops = &clk_rcg2_ops,
1055
+
},
1056
+
};
1057
+
1058
+
static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
1059
+
.mult = 1,
1060
+
.div = 2,
1061
+
.hw.init = &(struct clk_init_data) {
1062
+
.name = "qdss_tsctr_div2_clk_src",
1063
+
.parent_hws = (const struct clk_hw *[]) {
1064
+
&qdss_tsctr_clk_src.clkr.hw,
1065
+
},
1066
+
.num_parents = 1,
1067
+
.flags = CLK_SET_RATE_PARENT,
1068
+
.ops = &clk_fixed_factor_ops,
1069
+
},
1070
+
};
1071
+
1072
+
static struct clk_fixed_factor qdss_dap_sync_clk_src = {
1073
+
.mult = 1,
1074
+
.div = 4,
1075
+
.hw.init = &(struct clk_init_data) {
1076
+
.name = "qdss_dap_sync_clk_src",
1077
+
.parent_hws = (const struct clk_hw *[]) {
1078
+
&qdss_tsctr_clk_src.clkr.hw,
1079
+
},
1080
+
.num_parents = 1,
1081
+
.ops = &clk_fixed_factor_ops,
1082
+
},
1083
+
};
1084
+
1085
+
static struct clk_fixed_factor eud_at_clk_src = {
1086
+
.mult = 1,
1087
+
.div = 6,
1088
+
.hw.init = &(struct clk_init_data) {
1089
+
.name = "eud_at_clk_src",
1090
+
.parent_hws = (const struct clk_hw *[]) {
1091
+
&qdss_at_clk_src.clkr.hw,
1092
+
},
1093
+
.num_parents = 1,
1094
+
.ops = &clk_fixed_factor_ops,
1095
+
.flags = CLK_SET_RATE_PARENT,
1096
+
},
1097
+
};
1098
+
1099
+
static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
1100
+
F(24000000, P_XO, 1, 0, 0),
1101
+
F(100000000, P_GPLL0, 8, 0, 0),
1102
+
F(200000000, P_GPLL0, 4, 0, 0),
1103
+
F(320000000, P_GPLL0, 2.5, 0, 0),
1104
+
};
1105
+
1106
+
static struct clk_rcg2 qpic_io_macro_clk_src = {
1107
+
.cmd_rcgr = 0x57010,
1108
+
.freq_tbl = ftbl_qpic_io_macro_clk_src,
1109
+
.hid_width = 5,
1110
+
.parent_map = gcc_xo_gpll0_gpll2_map,
1111
+
.clkr.hw.init = &(struct clk_init_data) {
1112
+
.name = "qpic_io_macro_clk_src",
1113
+
.parent_data = gcc_xo_gpll0_gpll2,
1114
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
1115
+
.ops = &clk_rcg2_ops,
1116
+
},
1117
+
};
1118
+
1119
+
static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
1120
+
F(143713, P_XO, 1, 1, 167),
1121
+
F(400000, P_XO, 1, 1, 60),
1122
+
F(24000000, P_XO, 1, 0, 0),
1123
+
F(48000000, P_GPLL2, 12, 1, 2),
1124
+
F(96000000, P_GPLL2, 12, 0, 0),
1125
+
F(177777778, P_GPLL0, 1, 2, 9),
1126
+
F(192000000, P_GPLL2, 6, 0, 0),
1127
+
F(200000000, P_GPLL0, 4, 0, 0),
1128
+
{ }
1129
+
};
1130
+
1131
+
static struct clk_rcg2 sdcc1_apps_clk_src = {
1132
+
.cmd_rcgr = 0x42004,
1133
+
.freq_tbl = ftbl_sdcc1_apps_clk_src,
1134
+
.mnd_width = 8,
1135
+
.hid_width = 5,
1136
+
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1137
+
.clkr.hw.init = &(struct clk_init_data) {
1138
+
.name = "sdcc1_apps_clk_src",
1139
+
.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1140
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
1141
+
.ops = &clk_rcg2_floor_ops,
1142
+
},
1143
+
};
1144
+
1145
+
static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1146
+
F(266666667, P_GPLL0, 3, 0, 0),
1147
+
{ }
1148
+
};
1149
+
1150
+
static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1151
+
.cmd_rcgr = 0x26004,
1152
+
.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1153
+
.hid_width = 5,
1154
+
.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1155
+
.clkr.hw.init = &(struct clk_init_data) {
1156
+
.name = "system_noc_bfdcd_clk_src",
1157
+
.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1158
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
1159
+
.ops = &clk_rcg2_ops,
1160
+
},
1161
+
};
1162
+
1163
+
static struct clk_fixed_factor system_noc_clk_src = {
1164
+
.mult = 1,
1165
+
.div = 1,
1166
+
.hw.init = &(struct clk_init_data) {
1167
+
.name = "system_noc_clk_src",
1168
+
.parent_hws = (const struct clk_hw *[]) {
1169
+
&system_noc_bfdcd_clk_src.clkr.hw,
1170
+
},
1171
+
.num_parents = 1,
1172
+
.ops = &clk_fixed_factor_ops,
1173
+
.flags = CLK_SET_RATE_PARENT,
1174
+
},
1175
+
};
1176
+
1177
+
static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
1178
+
F(400000000, P_GPLL0, 2, 0, 0),
1179
+
{ }
1180
+
};
1181
+
1182
+
static struct clk_rcg2 ubi0_axi_clk_src = {
1183
+
.cmd_rcgr = 0x68088,
1184
+
.freq_tbl = ftbl_apss_axi_clk_src,
1185
+
.hid_width = 5,
1186
+
.parent_map = gcc_xo_gpll0_gpll2_map,
1187
+
.clkr.hw.init = &(struct clk_init_data) {
1188
+
.name = "ubi0_axi_clk_src",
1189
+
.parent_data = gcc_xo_gpll0_gpll2,
1190
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
1191
+
.ops = &clk_rcg2_ops,
1192
+
.flags = CLK_SET_RATE_PARENT,
1193
+
},
1194
+
};
1195
+
1196
+
static const struct freq_tbl ftbl_ubi0_core_clk_src[] = {
1197
+
F(850000000, P_UBI32_PLL, 1, 0, 0),
1198
+
F(1000000000, P_UBI32_PLL, 1, 0, 0),
1199
+
};
1200
+
1201
+
static struct clk_rcg2 ubi0_core_clk_src = {
1202
+
.cmd_rcgr = 0x68100,
1203
+
.freq_tbl = ftbl_ubi0_core_clk_src,
1204
+
.hid_width = 5,
1205
+
.parent_map = gcc_xo_ubi32_gpll0_map,
1206
+
.clkr.hw.init = &(struct clk_init_data) {
1207
+
.name = "ubi0_core_clk_src",
1208
+
.parent_data = gcc_xo_ubi32_gpll0,
1209
+
.num_parents = ARRAY_SIZE(gcc_xo_ubi32_gpll0),
1210
+
.ops = &clk_rcg2_ops,
1211
+
.flags = CLK_SET_RATE_PARENT,
1212
+
},
1213
+
};
1214
+
1215
+
static struct clk_rcg2 usb0_aux_clk_src = {
1216
+
.cmd_rcgr = 0x3e05c,
1217
+
.freq_tbl = ftbl_pcie0_aux_clk_src,
1218
+
.mnd_width = 16,
1219
+
.hid_width = 5,
1220
+
.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1221
+
.clkr.hw.init = &(struct clk_init_data) {
1222
+
.name = "usb0_aux_clk_src",
1223
+
.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1224
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
1225
+
.ops = &clk_rcg2_ops,
1226
+
},
1227
+
};
1228
+
1229
+
static const struct freq_tbl ftbl_usb0_lfps_clk_src[] = {
1230
+
F(25000000, P_GPLL0, 16, 1, 2),
1231
+
{ }
1232
+
};
1233
+
1234
+
static struct clk_rcg2 usb0_lfps_clk_src = {
1235
+
.cmd_rcgr = 0x3e090,
1236
+
.freq_tbl = ftbl_usb0_lfps_clk_src,
1237
+
.mnd_width = 8,
1238
+
.hid_width = 5,
1239
+
.parent_map = gcc_xo_gpll0_map,
1240
+
.clkr.hw.init = &(struct clk_init_data) {
1241
+
.name = "usb0_lfps_clk_src",
1242
+
.parent_data = gcc_xo_gpll0,
1243
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1244
+
.ops = &clk_rcg2_ops,
1245
+
},
1246
+
};
1247
+
1248
+
static struct clk_rcg2 usb0_master_clk_src = {
1249
+
.cmd_rcgr = 0x3e00c,
1250
+
.freq_tbl = ftbl_gp_clk_src,
1251
+
.mnd_width = 8,
1252
+
.hid_width = 5,
1253
+
.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1254
+
.clkr.hw.init = &(struct clk_init_data) {
1255
+
.name = "usb0_master_clk_src",
1256
+
.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
1257
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
1258
+
.ops = &clk_rcg2_ops,
1259
+
},
1260
+
};
1261
+
1262
+
static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
1263
+
F(60000000, P_GPLL4, 10, 1, 2),
1264
+
{ }
1265
+
};
1266
+
1267
+
static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1268
+
.cmd_rcgr = 0x3e020,
1269
+
.freq_tbl = ftbl_usb0_mock_utmi_clk_src,
1270
+
.mnd_width = 8,
1271
+
.hid_width = 5,
1272
+
.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2,
1273
+
.clkr.hw.init = &(struct clk_init_data) {
1274
+
.name = "usb0_mock_utmi_clk_src",
1275
+
.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1276
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1277
+
.ops = &clk_rcg2_ops,
1278
+
},
1279
+
};
1280
+
1281
+
static struct clk_regmap_mux usb0_pipe_clk_src = {
1282
+
.reg = 0x3e048,
1283
+
.shift = 8,
1284
+
.width = 2,
1285
+
.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1286
+
.clkr = {
1287
+
.hw.init = &(struct clk_init_data) {
1288
+
.name = "usb0_pipe_clk_src",
1289
+
.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
1290
+
.num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
1291
+
.ops = &clk_regmap_mux_closest_ops,
1292
+
.flags = CLK_SET_RATE_PARENT,
1293
+
},
1294
+
},
1295
+
};
1296
+
1297
+
static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
1298
+
F(400000000, P_GPLL0, 2, 0, 0),
1299
+
{ }
1300
+
};
1301
+
1302
+
static struct clk_rcg2 q6_axi_clk_src = {
1303
+
.cmd_rcgr = 0x59120,
1304
+
.freq_tbl = ftbl_q6_axi_clk_src,
1305
+
.hid_width = 5,
1306
+
.parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
1307
+
.clkr.hw.init = &(struct clk_init_data) {
1308
+
.name = "q6_axi_clk_src",
1309
+
.parent_data = gcc_xo_gpll0_gpll2_gpll4,
1310
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4),
1311
+
.ops = &clk_rcg2_ops,
1312
+
},
1313
+
};
1314
+
1315
+
static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
1316
+
F(133333333, P_GPLL0, 6, 0, 0),
1317
+
{ }
1318
+
};
1319
+
1320
+
static struct clk_rcg2 wcss_ahb_clk_src = {
1321
+
.cmd_rcgr = 0x59020,
1322
+
.freq_tbl = ftbl_wcss_ahb_clk_src,
1323
+
.hid_width = 5,
1324
+
.parent_map = gcc_xo_gpll0_map,
1325
+
.clkr.hw.init = &(struct clk_init_data) {
1326
+
.name = "wcss_ahb_clk_src",
1327
+
.parent_data = gcc_xo_gpll0,
1328
+
.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1329
+
.ops = &clk_rcg2_ops,
1330
+
},
1331
+
};
1332
+
1333
+
static struct clk_branch gcc_sleep_clk_src = {
1334
+
.halt_reg = 0x30000,
1335
+
.clkr = {
1336
+
.enable_reg = 0x30000,
1337
+
.enable_mask = BIT(1),
1338
+
.hw.init = &(struct clk_init_data) {
1339
+
.name = "gcc_sleep_clk_src",
1340
+
.parent_data = gcc_sleep_clk_data,
1341
+
.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
1342
+
.ops = &clk_branch2_ops,
1343
+
},
1344
+
},
1345
+
};
1346
+
1347
+
static struct clk_branch gcc_xo_clk_src = {
1348
+
.halt_reg = 0x30018,
1349
+
.clkr = {
1350
+
.enable_reg = 0x30018,
1351
+
.enable_mask = BIT(1),
1352
+
.hw.init = &(struct clk_init_data) {
1353
+
.name = "gcc_xo_clk_src",
1354
+
.parent_data = gcc_xo_data,
1355
+
.num_parents = ARRAY_SIZE(gcc_xo_data),
1356
+
.flags = CLK_SET_RATE_PARENT,
1357
+
.ops = &clk_branch2_ops,
1358
+
},
1359
+
},
1360
+
};
1361
+
1362
+
static struct clk_branch gcc_xo_clk = {
1363
+
.halt_reg = 0x30030,
1364
+
.clkr = {
1365
+
.enable_reg = 0x30030,
1366
+
.enable_mask = BIT(0),
1367
+
.hw.init = &(struct clk_init_data) {
1368
+
.name = "gcc_xo_clk",
1369
+
.parent_hws = (const struct clk_hw *[]) {
1370
+
&gcc_xo_clk_src.clkr.hw,
1371
+
},
1372
+
.num_parents = 1,
1373
+
.flags = CLK_SET_RATE_PARENT,
1374
+
.ops = &clk_branch2_ops,
1375
+
},
1376
+
},
1377
+
};
1378
+
1379
+
static struct clk_branch gcc_adss_pwm_clk = {
1380
+
.halt_reg = 0x1f020,
1381
+
.clkr = {
1382
+
.enable_reg = 0x1f020,
1383
+
.enable_mask = BIT(0),
1384
+
.hw.init = &(struct clk_init_data) {
1385
+
.name = "gcc_adss_pwm_clk",
1386
+
.parent_hws = (const struct clk_hw *[]) {
1387
+
&adss_pwm_clk_src.clkr.hw,
1388
+
},
1389
+
.num_parents = 1,
1390
+
.flags = CLK_SET_RATE_PARENT,
1391
+
.ops = &clk_branch2_ops,
1392
+
},
1393
+
},
1394
+
};
1395
+
1396
+
static struct clk_branch gcc_blsp1_ahb_clk = {
1397
+
.halt_reg = 0x01008,
1398
+
.halt_check = BRANCH_HALT_VOTED,
1399
+
.clkr = {
1400
+
.enable_reg = 0x0b004,
1401
+
.enable_mask = BIT(10),
1402
+
.hw.init = &(struct clk_init_data) {
1403
+
.name = "gcc_blsp1_ahb_clk",
1404
+
.parent_hws = (const struct clk_hw *[]) {
1405
+
&pcnoc_clk_src.hw,
1406
+
},
1407
+
.num_parents = 1,
1408
+
.flags = CLK_SET_RATE_PARENT,
1409
+
.ops = &clk_branch2_ops,
1410
+
},
1411
+
},
1412
+
};
1413
+
1414
+
static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1415
+
.halt_reg = 0x02008,
1416
+
.clkr = {
1417
+
.enable_reg = 0x02008,
1418
+
.enable_mask = BIT(0),
1419
+
.hw.init = &(struct clk_init_data) {
1420
+
.name = "gcc_blsp1_qup1_i2c_apps_clk",
1421
+
.parent_hws = (const struct clk_hw *[]) {
1422
+
&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1423
+
},
1424
+
.num_parents = 1,
1425
+
.flags = CLK_SET_RATE_PARENT,
1426
+
.ops = &clk_branch2_ops,
1427
+
},
1428
+
},
1429
+
};
1430
+
1431
+
static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1432
+
.halt_reg = 0x02004,
1433
+
.clkr = {
1434
+
.enable_reg = 0x02004,
1435
+
.enable_mask = BIT(0),
1436
+
.hw.init = &(struct clk_init_data) {
1437
+
.name = "gcc_blsp1_qup1_spi_apps_clk",
1438
+
.parent_hws = (const struct clk_hw *[]) {
1439
+
&blsp1_qup1_spi_apps_clk_src.clkr.hw,
1440
+
},
1441
+
.num_parents = 1,
1442
+
.flags = CLK_SET_RATE_PARENT,
1443
+
.ops = &clk_branch2_ops,
1444
+
},
1445
+
},
1446
+
};
1447
+
1448
+
static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1449
+
.halt_reg = 0x03010,
1450
+
.clkr = {
1451
+
.enable_reg = 0x03010,
1452
+
.enable_mask = BIT(0),
1453
+
.hw.init = &(struct clk_init_data) {
1454
+
.name = "gcc_blsp1_qup2_i2c_apps_clk",
1455
+
.parent_hws = (const struct clk_hw *[]) {
1456
+
&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1457
+
},
1458
+
.num_parents = 1,
1459
+
.flags = CLK_SET_RATE_PARENT,
1460
+
.ops = &clk_branch2_ops,
1461
+
},
1462
+
},
1463
+
};
1464
+
1465
+
static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1466
+
.halt_reg = 0x0300c,
1467
+
.clkr = {
1468
+
.enable_reg = 0x0300c,
1469
+
.enable_mask = BIT(0),
1470
+
.hw.init = &(struct clk_init_data) {
1471
+
.name = "gcc_blsp1_qup2_spi_apps_clk",
1472
+
.parent_hws = (const struct clk_hw *[]) {
1473
+
&blsp1_qup2_spi_apps_clk_src.clkr.hw,
1474
+
},
1475
+
.num_parents = 1,
1476
+
.flags = CLK_SET_RATE_PARENT,
1477
+
.ops = &clk_branch2_ops,
1478
+
},
1479
+
},
1480
+
};
1481
+
1482
+
static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1483
+
.halt_reg = 0x04010,
1484
+
.clkr = {
1485
+
.enable_reg = 0x04010,
1486
+
.enable_mask = BIT(0),
1487
+
.hw.init = &(struct clk_init_data) {
1488
+
.name = "gcc_blsp1_qup3_i2c_apps_clk",
1489
+
.parent_hws = (const struct clk_hw *[]) {
1490
+
&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1491
+
},
1492
+
.num_parents = 1,
1493
+
.flags = CLK_SET_RATE_PARENT,
1494
+
.ops = &clk_branch2_ops,
1495
+
},
1496
+
},
1497
+
};
1498
+
1499
+
static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1500
+
.halt_reg = 0x0400c,
1501
+
.clkr = {
1502
+
.enable_reg = 0x0400c,
1503
+
.enable_mask = BIT(0),
1504
+
.hw.init = &(struct clk_init_data) {
1505
+
.name = "gcc_blsp1_qup3_spi_apps_clk",
1506
+
.parent_hws = (const struct clk_hw *[]) {
1507
+
&blsp1_qup3_spi_apps_clk_src.clkr.hw,
1508
+
},
1509
+
.num_parents = 1,
1510
+
.flags = CLK_SET_RATE_PARENT,
1511
+
.ops = &clk_branch2_ops,
1512
+
},
1513
+
},
1514
+
};
1515
+
1516
+
static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1517
+
.halt_reg = 0x0203c,
1518
+
.clkr = {
1519
+
.enable_reg = 0x0203c,
1520
+
.enable_mask = BIT(0),
1521
+
.hw.init = &(struct clk_init_data) {
1522
+
.name = "gcc_blsp1_uart1_apps_clk",
1523
+
.parent_hws = (const struct clk_hw *[]) {
1524
+
&blsp1_uart1_apps_clk_src.clkr.hw,
1525
+
},
1526
+
.num_parents = 1,
1527
+
.flags = CLK_SET_RATE_PARENT,
1528
+
.ops = &clk_branch2_ops,
1529
+
},
1530
+
},
1531
+
};
1532
+
1533
+
static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1534
+
.halt_reg = 0x0302c,
1535
+
.clkr = {
1536
+
.enable_reg = 0x0302c,
1537
+
.enable_mask = BIT(0),
1538
+
.hw.init = &(struct clk_init_data) {
1539
+
.name = "gcc_blsp1_uart2_apps_clk",
1540
+
.parent_hws = (const struct clk_hw *[]) {
1541
+
&blsp1_uart2_apps_clk_src.clkr.hw,
1542
+
},
1543
+
.num_parents = 1,
1544
+
.flags = CLK_SET_RATE_PARENT,
1545
+
.ops = &clk_branch2_ops,
1546
+
},
1547
+
},
1548
+
};
1549
+
1550
+
static struct clk_branch gcc_btss_lpo_clk = {
1551
+
.halt_reg = 0x1c004,
1552
+
.clkr = {
1553
+
.enable_reg = 0x1c004,
1554
+
.enable_mask = BIT(0),
1555
+
.hw.init = &(struct clk_init_data) {
1556
+
.name = "gcc_btss_lpo_clk",
1557
+
.ops = &clk_branch2_ops,
1558
+
},
1559
+
},
1560
+
};
1561
+
1562
+
static struct clk_branch gcc_cmn_blk_ahb_clk = {
1563
+
.halt_reg = 0x56308,
1564
+
.clkr = {
1565
+
.enable_reg = 0x56308,
1566
+
.enable_mask = BIT(0),
1567
+
.hw.init = &(struct clk_init_data) {
1568
+
.name = "gcc_cmn_blk_ahb_clk",
1569
+
.parent_hws = (const struct clk_hw *[]) {
1570
+
&pcnoc_clk_src.hw,
1571
+
},
1572
+
.num_parents = 1,
1573
+
.flags = CLK_SET_RATE_PARENT,
1574
+
.ops = &clk_branch2_ops,
1575
+
},
1576
+
},
1577
+
};
1578
+
1579
+
static struct clk_branch gcc_cmn_blk_sys_clk = {
1580
+
.halt_reg = 0x5630c,
1581
+
.clkr = {
1582
+
.enable_reg = 0x5630c,
1583
+
.enable_mask = BIT(0),
1584
+
.hw.init = &(struct clk_init_data) {
1585
+
.name = "gcc_cmn_blk_sys_clk",
1586
+
.parent_hws = (const struct clk_hw *[]) {
1587
+
&gcc_xo_clk_src.clkr.hw,
1588
+
},
1589
+
.num_parents = 1,
1590
+
.flags = CLK_SET_RATE_PARENT,
1591
+
.ops = &clk_branch2_ops,
1592
+
},
1593
+
},
1594
+
};
1595
+
1596
+
static struct clk_branch gcc_crypto_ahb_clk = {
1597
+
.halt_reg = 0x16024,
1598
+
.halt_check = BRANCH_HALT_VOTED,
1599
+
.clkr = {
1600
+
.enable_reg = 0x0b004,
1601
+
.enable_mask = BIT(0),
1602
+
.hw.init = &(struct clk_init_data) {
1603
+
.name = "gcc_crypto_ahb_clk",
1604
+
.parent_hws = (const struct clk_hw *[]) {
1605
+
&pcnoc_clk_src.hw,
1606
+
},
1607
+
.num_parents = 1,
1608
+
.flags = CLK_SET_RATE_PARENT,
1609
+
.ops = &clk_branch2_ops,
1610
+
},
1611
+
},
1612
+
};
1613
+
1614
+
static struct clk_branch gcc_crypto_axi_clk = {
1615
+
.halt_reg = 0x16020,
1616
+
.halt_check = BRANCH_HALT_VOTED,
1617
+
.clkr = {
1618
+
.enable_reg = 0x0b004,
1619
+
.enable_mask = BIT(1),
1620
+
.hw.init = &(struct clk_init_data) {
1621
+
.name = "gcc_crypto_axi_clk",
1622
+
.parent_hws = (const struct clk_hw *[]) {
1623
+
&pcnoc_clk_src.hw,
1624
+
},
1625
+
.num_parents = 1,
1626
+
.flags = CLK_SET_RATE_PARENT,
1627
+
.ops = &clk_branch2_ops,
1628
+
},
1629
+
},
1630
+
};
1631
+
1632
+
static struct clk_branch gcc_crypto_clk = {
1633
+
.halt_reg = 0x1601c,
1634
+
.halt_check = BRANCH_HALT_VOTED,
1635
+
.clkr = {
1636
+
.enable_reg = 0x0b004,
1637
+
.enable_mask = BIT(2),
1638
+
.hw.init = &(struct clk_init_data) {
1639
+
.name = "gcc_crypto_clk",
1640
+
.parent_hws = (const struct clk_hw *[]) {
1641
+
&crypto_clk_src.clkr.hw,
1642
+
},
1643
+
.num_parents = 1,
1644
+
.flags = CLK_SET_RATE_PARENT,
1645
+
.ops = &clk_branch2_ops,
1646
+
},
1647
+
},
1648
+
};
1649
+
1650
+
static struct clk_branch gcc_dcc_clk = {
1651
+
.halt_reg = 0x77004,
1652
+
.clkr = {
1653
+
.enable_reg = 0x77004,
1654
+
.enable_mask = BIT(0),
1655
+
.hw.init = &(struct clk_init_data) {
1656
+
.name = "gcc_dcc_clk",
1657
+
.parent_hws = (const struct clk_hw *[]) {
1658
+
&pcnoc_clk_src.hw,
1659
+
},
1660
+
.num_parents = 1,
1661
+
.flags = CLK_SET_RATE_PARENT,
1662
+
.ops = &clk_branch2_ops,
1663
+
},
1664
+
},
1665
+
};
1666
+
1667
+
static struct clk_branch gcc_gephy_rx_clk = {
1668
+
.halt_reg = 0x56010,
1669
+
.halt_check = BRANCH_HALT_DELAY,
1670
+
.clkr = {
1671
+
.enable_reg = 0x56010,
1672
+
.enable_mask = BIT(0),
1673
+
.hw.init = &(struct clk_init_data) {
1674
+
.name = "gcc_gephy_rx_clk",
1675
+
.parent_hws = (const struct clk_hw *[]) {
1676
+
&gmac0_rx_div_clk_src.clkr.hw,
1677
+
},
1678
+
.num_parents = 1,
1679
+
.ops = &clk_branch2_ops,
1680
+
.flags = CLK_SET_RATE_PARENT,
1681
+
},
1682
+
},
1683
+
};
1684
+
1685
+
static struct clk_branch gcc_gephy_tx_clk = {
1686
+
.halt_reg = 0x56014,
1687
+
.halt_check = BRANCH_HALT_DELAY,
1688
+
.clkr = {
1689
+
.enable_reg = 0x56014,
1690
+
.enable_mask = BIT(0),
1691
+
.hw.init = &(struct clk_init_data) {
1692
+
.name = "gcc_gephy_tx_clk",
1693
+
.parent_hws = (const struct clk_hw *[]) {
1694
+
&gmac0_tx_div_clk_src.clkr.hw,
1695
+
},
1696
+
.num_parents = 1,
1697
+
.ops = &clk_branch2_ops,
1698
+
.flags = CLK_SET_RATE_PARENT,
1699
+
},
1700
+
},
1701
+
};
1702
+
1703
+
static struct clk_branch gcc_gmac0_cfg_clk = {
1704
+
.halt_reg = 0x68304,
1705
+
.clkr = {
1706
+
.enable_reg = 0x68304,
1707
+
.enable_mask = BIT(0),
1708
+
.hw.init = &(struct clk_init_data) {
1709
+
.name = "gcc_gmac0_cfg_clk",
1710
+
.parent_hws = (const struct clk_hw *[]) {
1711
+
&gmac_clk_src.clkr.hw,
1712
+
},
1713
+
.num_parents = 1,
1714
+
.flags = CLK_SET_RATE_PARENT,
1715
+
.ops = &clk_branch2_ops,
1716
+
},
1717
+
},
1718
+
};
1719
+
1720
+
static struct clk_branch gcc_gmac0_ptp_clk = {
1721
+
.halt_reg = 0x68300,
1722
+
.clkr = {
1723
+
.enable_reg = 0x68300,
1724
+
.enable_mask = BIT(0),
1725
+
.hw.init = &(struct clk_init_data) {
1726
+
.name = "gcc_gmac0_ptp_clk",
1727
+
.parent_hws = (const struct clk_hw *[]) {
1728
+
&gmac_clk_src.clkr.hw,
1729
+
},
1730
+
.num_parents = 1,
1731
+
.flags = CLK_SET_RATE_PARENT,
1732
+
.ops = &clk_branch2_ops,
1733
+
},
1734
+
},
1735
+
};
1736
+
1737
+
static struct clk_branch gcc_gmac0_rx_clk = {
1738
+
.halt_reg = 0x68240,
1739
+
.clkr = {
1740
+
.enable_reg = 0x68240,
1741
+
.enable_mask = BIT(0),
1742
+
.hw.init = &(struct clk_init_data) {
1743
+
.name = "gcc_gmac0_rx_clk",
1744
+
.parent_hws = (const struct clk_hw *[]) {
1745
+
&gmac0_rx_div_clk_src.clkr.hw,
1746
+
},
1747
+
.num_parents = 1,
1748
+
.ops = &clk_branch2_ops,
1749
+
.flags = CLK_SET_RATE_PARENT,
1750
+
},
1751
+
},
1752
+
};
1753
+
1754
+
static struct clk_branch gcc_gmac0_sys_clk = {
1755
+
.halt_reg = 0x68190,
1756
+
.halt_check = BRANCH_HALT_DELAY,
1757
+
.halt_bit = 31,
1758
+
.clkr = {
1759
+
.enable_reg = 0x683190,
1760
+
.enable_mask = BIT(0),
1761
+
.hw.init = &(struct clk_init_data) {
1762
+
.name = "gcc_gmac0_sys_clk",
1763
+
.parent_hws = (const struct clk_hw *[]) {
1764
+
&gmac_clk_src.clkr.hw,
1765
+
},
1766
+
.num_parents = 1,
1767
+
.flags = CLK_SET_RATE_PARENT,
1768
+
.ops = &clk_branch2_ops,
1769
+
},
1770
+
},
1771
+
};
1772
+
1773
+
static struct clk_branch gcc_gmac0_tx_clk = {
1774
+
.halt_reg = 0x68244,
1775
+
.clkr = {
1776
+
.enable_reg = 0x68244,
1777
+
.enable_mask = BIT(0),
1778
+
.hw.init = &(struct clk_init_data) {
1779
+
.name = "gcc_gmac0_tx_clk",
1780
+
.parent_hws = (const struct clk_hw *[]) {
1781
+
&gmac0_tx_div_clk_src.clkr.hw,
1782
+
},
1783
+
.num_parents = 1,
1784
+
.ops = &clk_branch2_ops,
1785
+
.flags = CLK_SET_RATE_PARENT,
1786
+
},
1787
+
},
1788
+
};
1789
+
1790
+
static struct clk_branch gcc_gmac1_cfg_clk = {
1791
+
.halt_reg = 0x68324,
1792
+
.clkr = {
1793
+
.enable_reg = 0x68324,
1794
+
.enable_mask = BIT(0),
1795
+
.hw.init = &(struct clk_init_data) {
1796
+
.name = "gcc_gmac1_cfg_clk",
1797
+
.parent_hws = (const struct clk_hw *[]) {
1798
+
&gmac_clk_src.clkr.hw,
1799
+
},
1800
+
.num_parents = 1,
1801
+
.flags = CLK_SET_RATE_PARENT,
1802
+
.ops = &clk_branch2_ops,
1803
+
},
1804
+
},
1805
+
};
1806
+
1807
+
static struct clk_branch gcc_gmac1_ptp_clk = {
1808
+
.halt_reg = 0x68320,
1809
+
.clkr = {
1810
+
.enable_reg = 0x68320,
1811
+
.enable_mask = BIT(0),
1812
+
.hw.init = &(struct clk_init_data) {
1813
+
.name = "gcc_gmac1_ptp_clk",
1814
+
.parent_hws = (const struct clk_hw *[]) {
1815
+
&gmac_clk_src.clkr.hw,
1816
+
},
1817
+
.num_parents = 1,
1818
+
.flags = CLK_SET_RATE_PARENT,
1819
+
.ops = &clk_branch2_ops,
1820
+
},
1821
+
},
1822
+
};
1823
+
1824
+
static struct clk_branch gcc_gmac1_rx_clk = {
1825
+
.halt_reg = 0x68248,
1826
+
.clkr = {
1827
+
.enable_reg = 0x68248,
1828
+
.enable_mask = BIT(0),
1829
+
.hw.init = &(struct clk_init_data) {
1830
+
.name = "gcc_gmac1_rx_clk",
1831
+
.parent_hws = (const struct clk_hw *[]) {
1832
+
&gmac1_rx_div_clk_src.clkr.hw,
1833
+
},
1834
+
.num_parents = 1,
1835
+
.ops = &clk_branch2_ops,
1836
+
.flags = CLK_SET_RATE_PARENT,
1837
+
},
1838
+
},
1839
+
};
1840
+
1841
+
static struct clk_branch gcc_gmac1_sys_clk = {
1842
+
.halt_reg = 0x68310,
1843
+
.clkr = {
1844
+
.enable_reg = 0x68310,
1845
+
.enable_mask = BIT(0),
1846
+
.hw.init = &(struct clk_init_data) {
1847
+
.name = "gcc_gmac1_sys_clk",
1848
+
.parent_hws = (const struct clk_hw *[]) {
1849
+
&gmac_clk_src.clkr.hw,
1850
+
},
1851
+
.num_parents = 1,
1852
+
.flags = CLK_SET_RATE_PARENT,
1853
+
.ops = &clk_branch2_ops,
1854
+
},
1855
+
},
1856
+
};
1857
+
1858
+
static struct clk_branch gcc_gmac1_tx_clk = {
1859
+
.halt_reg = 0x6824c,
1860
+
.clkr = {
1861
+
.enable_reg = 0x6824c,
1862
+
.enable_mask = BIT(0),
1863
+
.hw.init = &(struct clk_init_data) {
1864
+
.name = "gcc_gmac1_tx_clk",
1865
+
.parent_hws = (const struct clk_hw *[]) {
1866
+
&gmac1_tx_div_clk_src.clkr.hw,
1867
+
},
1868
+
.num_parents = 1,
1869
+
.ops = &clk_branch2_ops,
1870
+
.flags = CLK_SET_RATE_PARENT,
1871
+
},
1872
+
},
1873
+
};
1874
+
1875
+
static struct clk_branch gcc_gp1_clk = {
1876
+
.halt_reg = 0x08000,
1877
+
.clkr = {
1878
+
.enable_reg = 0x08000,
1879
+
.enable_mask = BIT(0),
1880
+
.hw.init = &(struct clk_init_data) {
1881
+
.name = "gcc_gp1_clk",
1882
+
.parent_hws = (const struct clk_hw *[]) {
1883
+
&gp1_clk_src.clkr.hw,
1884
+
},
1885
+
.num_parents = 1,
1886
+
.flags = CLK_SET_RATE_PARENT,
1887
+
.ops = &clk_branch2_ops,
1888
+
},
1889
+
},
1890
+
};
1891
+
1892
+
static struct clk_branch gcc_gp2_clk = {
1893
+
.halt_reg = 0x09000,
1894
+
.clkr = {
1895
+
.enable_reg = 0x09000,
1896
+
.enable_mask = BIT(0),
1897
+
.hw.init = &(struct clk_init_data) {
1898
+
.name = "gcc_gp2_clk",
1899
+
.parent_hws = (const struct clk_hw *[]) {
1900
+
&gp2_clk_src.clkr.hw,
1901
+
},
1902
+
.num_parents = 1,
1903
+
.flags = CLK_SET_RATE_PARENT,
1904
+
.ops = &clk_branch2_ops,
1905
+
},
1906
+
},
1907
+
};
1908
+
1909
+
static struct clk_branch gcc_gp3_clk = {
1910
+
.halt_reg = 0x0a000,
1911
+
.clkr = {
1912
+
.enable_reg = 0x0a000,
1913
+
.enable_mask = BIT(0),
1914
+
.hw.init = &(struct clk_init_data) {
1915
+
.name = "gcc_gp3_clk",
1916
+
.parent_hws = (const struct clk_hw *[]) {
1917
+
&gp3_clk_src.clkr.hw,
1918
+
},
1919
+
.num_parents = 1,
1920
+
.flags = CLK_SET_RATE_PARENT,
1921
+
.ops = &clk_branch2_ops,
1922
+
},
1923
+
},
1924
+
};
1925
+
1926
+
static struct clk_branch gcc_lpass_core_axim_clk = {
1927
+
.halt_reg = 0x2e048,
1928
+
.halt_check = BRANCH_VOTED,
1929
+
.clkr = {
1930
+
.enable_reg = 0x2e048,
1931
+
.enable_mask = BIT(0),
1932
+
.hw.init = &(struct clk_init_data) {
1933
+
.name = "gcc_lpass_core_axim_clk",
1934
+
.parent_hws = (const struct clk_hw *[]) {
1935
+
&lpass_axim_clk_src.clkr.hw,
1936
+
},
1937
+
.num_parents = 1,
1938
+
.flags = CLK_SET_RATE_PARENT,
1939
+
.ops = &clk_branch2_ops,
1940
+
},
1941
+
},
1942
+
};
1943
+
1944
+
static struct clk_branch gcc_lpass_sway_clk = {
1945
+
.halt_reg = 0x2e04c,
1946
+
.clkr = {
1947
+
.enable_reg = 0x2e04c,
1948
+
.enable_mask = BIT(0),
1949
+
.hw.init = &(struct clk_init_data) {
1950
+
.name = "gcc_lpass_sway_clk",
1951
+
.parent_hws = (const struct clk_hw *[]) {
1952
+
&lpass_sway_clk_src.clkr.hw,
1953
+
},
1954
+
.num_parents = 1,
1955
+
.flags = CLK_SET_RATE_PARENT,
1956
+
.ops = &clk_branch2_ops,
1957
+
},
1958
+
},
1959
+
};
1960
+
1961
+
static struct clk_branch gcc_mdio0_ahb_clk = {
1962
+
.halt_reg = 0x58004,
1963
+
.clkr = {
1964
+
.enable_reg = 0x58004,
1965
+
.enable_mask = BIT(0),
1966
+
.hw.init = &(struct clk_init_data) {
1967
+
.name = "gcc_mdioi0_ahb_clk",
1968
+
.parent_hws = (const struct clk_hw *[]) {
1969
+
&pcnoc_clk_src.hw,
1970
+
},
1971
+
.num_parents = 1,
1972
+
.flags = CLK_SET_RATE_PARENT,
1973
+
.ops = &clk_branch2_ops,
1974
+
},
1975
+
},
1976
+
};
1977
+
1978
+
static struct clk_branch gcc_mdio1_ahb_clk = {
1979
+
.halt_reg = 0x58014,
1980
+
.clkr = {
1981
+
.enable_reg = 0x58014,
1982
+
.enable_mask = BIT(0),
1983
+
.hw.init = &(struct clk_init_data) {
1984
+
.name = "gcc_mdio1_ahb_clk",
1985
+
.parent_hws = (const struct clk_hw *[]) {
1986
+
&pcnoc_clk_src.hw,
1987
+
},
1988
+
.num_parents = 1,
1989
+
.flags = CLK_SET_RATE_PARENT,
1990
+
.ops = &clk_branch2_ops,
1991
+
},
1992
+
},
1993
+
};
1994
+
1995
+
static struct clk_branch gcc_pcie0_ahb_clk = {
1996
+
.halt_reg = 0x75010,
1997
+
.clkr = {
1998
+
.enable_reg = 0x75010,
1999
+
.enable_mask = BIT(0),
2000
+
.hw.init = &(struct clk_init_data) {
2001
+
.name = "gcc_pcie0_ahb_clk",
2002
+
.parent_hws = (const struct clk_hw *[]) {
2003
+
&pcnoc_clk_src.hw,
2004
+
},
2005
+
.num_parents = 1,
2006
+
.flags = CLK_SET_RATE_PARENT,
2007
+
.ops = &clk_branch2_ops,
2008
+
},
2009
+
},
2010
+
};
2011
+
2012
+
static struct clk_branch gcc_pcie0_aux_clk = {
2013
+
.halt_reg = 0x75014,
2014
+
.clkr = {
2015
+
.enable_reg = 0x75014,
2016
+
.enable_mask = BIT(0),
2017
+
.hw.init = &(struct clk_init_data) {
2018
+
.name = "gcc_pcie0_aux_clk",
2019
+
.parent_hws = (const struct clk_hw *[]) {
2020
+
&pcie0_aux_clk_src.clkr.hw,
2021
+
},
2022
+
.num_parents = 1,
2023
+
.flags = CLK_SET_RATE_PARENT,
2024
+
.ops = &clk_branch2_ops,
2025
+
},
2026
+
},
2027
+
};
2028
+
2029
+
static struct clk_branch gcc_pcie0_axi_m_clk = {
2030
+
.halt_reg = 0x75008,
2031
+
.clkr = {
2032
+
.enable_reg = 0x75008,
2033
+
.enable_mask = BIT(0),
2034
+
.hw.init = &(struct clk_init_data) {
2035
+
.name = "gcc_pcie0_axi_m_clk",
2036
+
.parent_hws = (const struct clk_hw *[]) {
2037
+
&pcie0_axi_clk_src.clkr.hw,
2038
+
},
2039
+
.num_parents = 1,
2040
+
.flags = CLK_SET_RATE_PARENT,
2041
+
.ops = &clk_branch2_ops,
2042
+
},
2043
+
},
2044
+
};
2045
+
2046
+
static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
2047
+
.halt_reg = 0x75048,
2048
+
.clkr = {
2049
+
.enable_reg = 0x75048,
2050
+
.enable_mask = BIT(0),
2051
+
.hw.init = &(struct clk_init_data) {
2052
+
.name = "gcc_pcie0_axi_s_bridge_clk",
2053
+
.parent_hws = (const struct clk_hw *[]) {
2054
+
&pcie0_axi_clk_src.clkr.hw,
2055
+
},
2056
+
.num_parents = 1,
2057
+
.flags = CLK_SET_RATE_PARENT,
2058
+
.ops = &clk_branch2_ops,
2059
+
},
2060
+
},
2061
+
};
2062
+
2063
+
static struct clk_branch gcc_pcie0_axi_s_clk = {
2064
+
.halt_reg = 0x7500c,
2065
+
.clkr = {
2066
+
.enable_reg = 0x7500c,
2067
+
.enable_mask = BIT(0),
2068
+
.hw.init = &(struct clk_init_data) {
2069
+
.name = "gcc_pcie0_axi_s_clk",
2070
+
.parent_hws = (const struct clk_hw *[]) {
2071
+
&pcie0_axi_clk_src.clkr.hw,
2072
+
},
2073
+
.num_parents = 1,
2074
+
.flags = CLK_SET_RATE_PARENT,
2075
+
.ops = &clk_branch2_ops,
2076
+
},
2077
+
},
2078
+
};
2079
+
2080
+
static struct clk_branch gcc_pcie0_pipe_clk = {
2081
+
.halt_reg = 0x75018,
2082
+
.halt_check = BRANCH_HALT_DELAY,
2083
+
.halt_bit = 31,
2084
+
.clkr = {
2085
+
.enable_reg = 0x75018,
2086
+
.enable_mask = BIT(0),
2087
+
.hw.init = &(struct clk_init_data) {
2088
+
.name = "gcc_pcie0_pipe_clk",
2089
+
.parent_hws = (const struct clk_hw *[]) {
2090
+
&pcie0_pipe_clk_src.clkr.hw,
2091
+
},
2092
+
.num_parents = 1,
2093
+
.flags = CLK_SET_RATE_PARENT,
2094
+
.ops = &clk_branch2_ops,
2095
+
},
2096
+
},
2097
+
};
2098
+
2099
+
static struct clk_branch gcc_pcie1_ahb_clk = {
2100
+
.halt_reg = 0x76010,
2101
+
.clkr = {
2102
+
.enable_reg = 0x76010,
2103
+
.enable_mask = BIT(0),
2104
+
.hw.init = &(struct clk_init_data) {
2105
+
.name = "gcc_pcie1_ahb_clk",
2106
+
.parent_hws = (const struct clk_hw *[]) {
2107
+
&pcnoc_clk_src.hw,
2108
+
},
2109
+
.num_parents = 1,
2110
+
.flags = CLK_SET_RATE_PARENT,
2111
+
.ops = &clk_branch2_ops,
2112
+
},
2113
+
},
2114
+
};
2115
+
2116
+
static struct clk_branch gcc_pcie1_aux_clk = {
2117
+
.halt_reg = 0x76014,
2118
+
.clkr = {
2119
+
.enable_reg = 0x76014,
2120
+
.enable_mask = BIT(0),
2121
+
.hw.init = &(struct clk_init_data) {
2122
+
.name = "gcc_pcie1_aux_clk",
2123
+
.parent_hws = (const struct clk_hw *[]) {
2124
+
&pcie1_aux_clk_src.clkr.hw,
2125
+
},
2126
+
.num_parents = 1,
2127
+
.flags = CLK_SET_RATE_PARENT,
2128
+
.ops = &clk_branch2_ops,
2129
+
},
2130
+
},
2131
+
};
2132
+
2133
+
static struct clk_branch gcc_pcie1_axi_m_clk = {
2134
+
.halt_reg = 0x76008,
2135
+
.clkr = {
2136
+
.enable_reg = 0x76008,
2137
+
.enable_mask = BIT(0),
2138
+
.hw.init = &(struct clk_init_data) {
2139
+
.name = "gcc_pcie1_axi_m_clk",
2140
+
.parent_hws = (const struct clk_hw *[]) {
2141
+
&pcie1_axi_clk_src.clkr.hw,
2142
+
},
2143
+
.num_parents = 1,
2144
+
.flags = CLK_SET_RATE_PARENT,
2145
+
.ops = &clk_branch2_ops,
2146
+
},
2147
+
},
2148
+
};
2149
+
2150
+
static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
2151
+
.halt_reg = 0x76048,
2152
+
.clkr = {
2153
+
.enable_reg = 0x76048,
2154
+
.enable_mask = BIT(0),
2155
+
.hw.init = &(struct clk_init_data) {
2156
+
.name = "gcc_pcie1_axi_s_bridge_clk",
2157
+
.parent_hws = (const struct clk_hw *[]) {
2158
+
&pcie1_axi_clk_src.clkr.hw,
2159
+
},
2160
+
.num_parents = 1,
2161
+
.flags = CLK_SET_RATE_PARENT,
2162
+
.ops = &clk_branch2_ops,
2163
+
},
2164
+
},
2165
+
};
2166
+
2167
+
static struct clk_branch gcc_pcie1_axi_s_clk = {
2168
+
.halt_reg = 0x7600c,
2169
+
.clkr = {
2170
+
.enable_reg = 0x7600c,
2171
+
.enable_mask = BIT(0),
2172
+
.hw.init = &(struct clk_init_data) {
2173
+
.name = "gcc_pcie1_axi_s_clk",
2174
+
.parent_hws = (const struct clk_hw *[]) {
2175
+
&pcie1_axi_clk_src.clkr.hw,
2176
+
},
2177
+
.num_parents = 1,
2178
+
.flags = CLK_SET_RATE_PARENT,
2179
+
.ops = &clk_branch2_ops,
2180
+
},
2181
+
},
2182
+
};
2183
+
2184
+
static struct clk_branch gcc_pcie1_pipe_clk = {
2185
+
.halt_reg = 8,
2186
+
.halt_check = BRANCH_HALT_DELAY,
2187
+
.halt_bit = 31,
2188
+
.clkr = {
2189
+
.enable_reg = 0x76018,
2190
+
.enable_mask = BIT(0),
2191
+
.hw.init = &(struct clk_init_data) {
2192
+
.name = "gcc_pcie1_pipe_clk",
2193
+
.parent_hws = (const struct clk_hw *[]) {
2194
+
&pcie1_pipe_clk_src.clkr.hw,
2195
+
},
2196
+
.num_parents = 1,
2197
+
.flags = CLK_SET_RATE_PARENT,
2198
+
.ops = &clk_branch2_ops,
2199
+
},
2200
+
},
2201
+
};
2202
+
2203
+
static struct clk_branch gcc_prng_ahb_clk = {
2204
+
.halt_reg = 0x13004,
2205
+
.halt_check = BRANCH_HALT_VOTED,
2206
+
.clkr = {
2207
+
.enable_reg = 0x0b004,
2208
+
.enable_mask = BIT(8),
2209
+
.hw.init = &(struct clk_init_data) {
2210
+
.name = "gcc_prng_ahb_clk",
2211
+
.parent_hws = (const struct clk_hw *[]) {
2212
+
&pcnoc_clk_src.hw,
2213
+
},
2214
+
.num_parents = 1,
2215
+
.flags = CLK_SET_RATE_PARENT,
2216
+
.ops = &clk_branch2_ops,
2217
+
},
2218
+
},
2219
+
};
2220
+
2221
+
static struct clk_branch gcc_q6_ahb_clk = {
2222
+
.halt_reg = 0x59138,
2223
+
.clkr = {
2224
+
.enable_reg = 0x59138,
2225
+
.enable_mask = BIT(0),
2226
+
.hw.init = &(struct clk_init_data) {
2227
+
.name = "gcc_q6_ahb_clk",
2228
+
.parent_hws = (const struct clk_hw *[]) {
2229
+
&wcss_ahb_clk_src.clkr.hw,
2230
+
},
2231
+
.num_parents = 1,
2232
+
.flags = CLK_SET_RATE_PARENT,
2233
+
.ops = &clk_branch2_ops,
2234
+
},
2235
+
},
2236
+
};
2237
+
2238
+
static struct clk_branch gcc_q6_ahb_s_clk = {
2239
+
.halt_reg = 0x5914c,
2240
+
.clkr = {
2241
+
.enable_reg = 0x5914c,
2242
+
.enable_mask = BIT(0),
2243
+
.hw.init = &(struct clk_init_data) {
2244
+
.name = "gcc_q6_ahb_s_clk",
2245
+
.parent_hws = (const struct clk_hw *[]) {
2246
+
&wcss_ahb_clk_src.clkr.hw,
2247
+
},
2248
+
.num_parents = 1,
2249
+
.flags = CLK_SET_RATE_PARENT,
2250
+
.ops = &clk_branch2_ops,
2251
+
},
2252
+
},
2253
+
};
2254
+
2255
+
static struct clk_branch gcc_q6_axim_clk = {
2256
+
.halt_reg = 0x5913c,
2257
+
.clkr = {
2258
+
.enable_reg = 0x5913c,
2259
+
.enable_mask = BIT(0),
2260
+
.hw.init = &(struct clk_init_data) {
2261
+
.name = "gcc_q6_axim_clk",
2262
+
.parent_hws = (const struct clk_hw *[]) {
2263
+
&q6_axi_clk_src.clkr.hw,
2264
+
},
2265
+
.num_parents = 1,
2266
+
.flags = CLK_SET_RATE_PARENT,
2267
+
.ops = &clk_branch2_ops,
2268
+
},
2269
+
},
2270
+
};
2271
+
2272
+
static struct clk_branch gcc_q6_axim2_clk = {
2273
+
.halt_reg = 0x59150,
2274
+
.clkr = {
2275
+
.enable_reg = 0x59150,
2276
+
.enable_mask = BIT(0),
2277
+
.hw.init = &(struct clk_init_data) {
2278
+
.name = "gcc_q6_axim2_clk",
2279
+
.parent_hws = (const struct clk_hw *[]) {
2280
+
&q6_axi_clk_src.clkr.hw,
2281
+
},
2282
+
.num_parents = 1,
2283
+
.flags = CLK_SET_RATE_PARENT,
2284
+
.ops = &clk_branch2_ops,
2285
+
},
2286
+
},
2287
+
};
2288
+
2289
+
static struct clk_branch gcc_q6_axis_clk = {
2290
+
.halt_reg = 0x59154,
2291
+
.clkr = {
2292
+
.enable_reg = 0x59154,
2293
+
.enable_mask = BIT(0),
2294
+
.hw.init = &(struct clk_init_data) {
2295
+
.name = "gcc_q6_axis_clk",
2296
+
.parent_hws = (const struct clk_hw *[]) {
2297
+
&system_noc_clk_src.hw,
2298
+
},
2299
+
.num_parents = 1,
2300
+
.flags = CLK_SET_RATE_PARENT,
2301
+
.ops = &clk_branch2_ops,
2302
+
},
2303
+
},
2304
+
};
2305
+
2306
+
static struct clk_branch gcc_q6_tsctr_1to2_clk = {
2307
+
.halt_reg = 0x59148,
2308
+
.clkr = {
2309
+
.enable_reg = 0x59148,
2310
+
.enable_mask = BIT(0),
2311
+
.hw.init = &(struct clk_init_data) {
2312
+
.name = "gcc_q6_tsctr_1to2_clk",
2313
+
.parent_hws = (const struct clk_hw *[]) {
2314
+
&qdss_tsctr_div2_clk_src.hw,
2315
+
},
2316
+
.num_parents = 1,
2317
+
.flags = CLK_SET_RATE_PARENT,
2318
+
.ops = &clk_branch2_ops,
2319
+
},
2320
+
},
2321
+
};
2322
+
2323
+
static struct clk_branch gcc_q6ss_atbm_clk = {
2324
+
.halt_reg = 0x59144,
2325
+
.clkr = {
2326
+
.enable_reg = 0x59144,
2327
+
.enable_mask = BIT(0),
2328
+
.hw.init = &(struct clk_init_data) {
2329
+
.name = "gcc_q6ss_atbm_clk",
2330
+
.parent_hws = (const struct clk_hw *[]) {
2331
+
&qdss_at_clk_src.clkr.hw,
2332
+
},
2333
+
.num_parents = 1,
2334
+
.flags = CLK_SET_RATE_PARENT,
2335
+
.ops = &clk_branch2_ops,
2336
+
},
2337
+
},
2338
+
};
2339
+
2340
+
static struct clk_branch gcc_q6ss_pclkdbg_clk = {
2341
+
.halt_reg = 0x59140,
2342
+
.clkr = {
2343
+
.enable_reg = 0x59140,
2344
+
.enable_mask = BIT(0),
2345
+
.hw.init = &(struct clk_init_data) {
2346
+
.name = "gcc_q6ss_pclkdbg_clk",
2347
+
.parent_hws = (const struct clk_hw *[]) {
2348
+
&qdss_dap_sync_clk_src.hw,
2349
+
},
2350
+
.num_parents = 1,
2351
+
.flags = CLK_SET_RATE_PARENT,
2352
+
.ops = &clk_branch2_ops,
2353
+
},
2354
+
},
2355
+
};
2356
+
2357
+
static struct clk_branch gcc_q6ss_trig_clk = {
2358
+
.halt_reg = 0x59128,
2359
+
.clkr = {
2360
+
.enable_reg = 0x59128,
2361
+
.enable_mask = BIT(0),
2362
+
.hw.init = &(struct clk_init_data) {
2363
+
.name = "gcc_q6ss_trig_clk",
2364
+
.parent_hws = (const struct clk_hw *[]) {
2365
+
&qdss_dap_sync_clk_src.hw,
2366
+
},
2367
+
.num_parents = 1,
2368
+
.flags = CLK_SET_RATE_PARENT,
2369
+
.ops = &clk_branch2_ops,
2370
+
},
2371
+
},
2372
+
};
2373
+
2374
+
static struct clk_branch gcc_qdss_at_clk = {
2375
+
.halt_reg = 0x29024,
2376
+
.clkr = {
2377
+
.enable_reg = 0x29024,
2378
+
.enable_mask = BIT(0),
2379
+
.hw.init = &(struct clk_init_data) {
2380
+
.name = "gcc_qdss_at_clk",
2381
+
.parent_hws = (const struct clk_hw *[]) {
2382
+
&qdss_at_clk_src.clkr.hw,
2383
+
},
2384
+
.num_parents = 1,
2385
+
.flags = CLK_SET_RATE_PARENT,
2386
+
.ops = &clk_branch2_ops,
2387
+
},
2388
+
},
2389
+
};
2390
+
2391
+
static struct clk_branch gcc_qdss_dap_clk = {
2392
+
.halt_reg = 0x29084,
2393
+
.clkr = {
2394
+
.enable_reg = 0x29084,
2395
+
.enable_mask = BIT(0),
2396
+
.hw.init = &(struct clk_init_data) {
2397
+
.name = "gcc_qdss_dap_clk",
2398
+
.parent_hws = (const struct clk_hw *[]) {
2399
+
&qdss_tsctr_clk_src.clkr.hw,
2400
+
},
2401
+
.num_parents = 1,
2402
+
.flags = CLK_SET_RATE_PARENT,
2403
+
.ops = &clk_branch2_ops,
2404
+
},
2405
+
},
2406
+
};
2407
+
2408
+
static struct clk_branch gcc_qdss_cfg_ahb_clk = {
2409
+
.halt_reg = 0x29008,
2410
+
.clkr = {
2411
+
.enable_reg = 0x29008,
2412
+
.enable_mask = BIT(0),
2413
+
.hw.init = &(struct clk_init_data) {
2414
+
.name = "gcc_qdss_cfg_ahb_clk",
2415
+
.parent_hws = (const struct clk_hw *[]) {
2416
+
&pcnoc_clk_src.hw,
2417
+
},
2418
+
.num_parents = 1,
2419
+
.flags = CLK_SET_RATE_PARENT,
2420
+
.ops = &clk_branch2_ops,
2421
+
},
2422
+
},
2423
+
};
2424
+
2425
+
static struct clk_branch gcc_qdss_dap_ahb_clk = {
2426
+
.halt_reg = 0x29004,
2427
+
.clkr = {
2428
+
.enable_reg = 0x29004,
2429
+
.enable_mask = BIT(0),
2430
+
.hw.init = &(struct clk_init_data) {
2431
+
.name = "gcc_qdss_dap_ahb_clk",
2432
+
.parent_hws = (const struct clk_hw *[]) {
2433
+
&pcnoc_clk_src.hw,
2434
+
},
2435
+
.num_parents = 1,
2436
+
.flags = CLK_SET_RATE_PARENT,
2437
+
.ops = &clk_branch2_ops,
2438
+
},
2439
+
},
2440
+
};
2441
+
2442
+
static struct clk_branch gcc_qdss_etr_usb_clk = {
2443
+
.halt_reg = 0x29028,
2444
+
.clkr = {
2445
+
.enable_reg = 0x29028,
2446
+
.enable_mask = BIT(0),
2447
+
.hw.init = &(struct clk_init_data) {
2448
+
.name = "gcc_qdss_etr_usb_clk",
2449
+
.parent_hws = (const struct clk_hw *[]) {
2450
+
&system_noc_clk_src.hw,
2451
+
},
2452
+
.num_parents = 1,
2453
+
.flags = CLK_SET_RATE_PARENT,
2454
+
.ops = &clk_branch2_ops,
2455
+
},
2456
+
},
2457
+
};
2458
+
2459
+
static struct clk_branch gcc_qdss_eud_at_clk = {
2460
+
.halt_reg = 0x29020,
2461
+
.clkr = {
2462
+
.enable_reg = 0x29020,
2463
+
.enable_mask = BIT(0),
2464
+
.hw.init = &(struct clk_init_data) {
2465
+
.name = "gcc_qdss_eud_at_clk",
2466
+
.parent_hws = (const struct clk_hw *[]) {
2467
+
&eud_at_clk_src.hw,
2468
+
},
2469
+
.num_parents = 1,
2470
+
.flags = CLK_SET_RATE_PARENT,
2471
+
.ops = &clk_branch2_ops,
2472
+
},
2473
+
},
2474
+
};
2475
+
2476
+
static struct clk_branch gcc_qdss_stm_clk = {
2477
+
.halt_reg = 0x29044,
2478
+
.clkr = {
2479
+
.enable_reg = 0x29044,
2480
+
.enable_mask = BIT(0),
2481
+
.hw.init = &(struct clk_init_data) {
2482
+
.name = "gcc_qdss_stm_clk",
2483
+
.parent_hws = (const struct clk_hw *[]) {
2484
+
&qdss_stm_clk_src.clkr.hw,
2485
+
},
2486
+
.num_parents = 1,
2487
+
.flags = CLK_SET_RATE_PARENT,
2488
+
.ops = &clk_branch2_ops,
2489
+
},
2490
+
},
2491
+
};
2492
+
2493
+
static struct clk_branch gcc_qdss_traceclkin_clk = {
2494
+
.halt_reg = 0x29060,
2495
+
.clkr = {
2496
+
.enable_reg = 0x29060,
2497
+
.enable_mask = BIT(0),
2498
+
.hw.init = &(struct clk_init_data) {
2499
+
.name = "gcc_qdss_traceclkin_clk",
2500
+
.parent_hws = (const struct clk_hw *[]) {
2501
+
&qdss_traceclkin_clk_src.clkr.hw,
2502
+
},
2503
+
.num_parents = 1,
2504
+
.flags = CLK_SET_RATE_PARENT,
2505
+
.ops = &clk_branch2_ops,
2506
+
},
2507
+
},
2508
+
};
2509
+
2510
+
static struct clk_branch gcc_qdss_tsctr_div8_clk = {
2511
+
.halt_reg = 0x2908c,
2512
+
.clkr = {
2513
+
.enable_reg = 0x2908c,
2514
+
.enable_mask = BIT(0),
2515
+
.hw.init = &(struct clk_init_data) {
2516
+
.name = "gcc_qdss_tsctr_div8_clk",
2517
+
.parent_hws = (const struct clk_hw *[]) {
2518
+
&qdss_tsctr_clk_src.clkr.hw,
2519
+
},
2520
+
.num_parents = 1,
2521
+
.flags = CLK_SET_RATE_PARENT,
2522
+
.ops = &clk_branch2_ops,
2523
+
},
2524
+
},
2525
+
};
2526
+
2527
+
static struct clk_branch gcc_qpic_ahb_clk = {
2528
+
.halt_reg = 0x57024,
2529
+
.clkr = {
2530
+
.enable_reg = 0x57024,
2531
+
.enable_mask = BIT(0),
2532
+
.hw.init = &(struct clk_init_data) {
2533
+
.name = "gcc_qpic_ahb_clk",
2534
+
.parent_hws = (const struct clk_hw *[]) {
2535
+
&pcnoc_clk_src.hw,
2536
+
},
2537
+
.num_parents = 1,
2538
+
.flags = CLK_SET_RATE_PARENT,
2539
+
.ops = &clk_branch2_ops,
2540
+
},
2541
+
},
2542
+
};
2543
+
2544
+
static struct clk_branch gcc_qpic_clk = {
2545
+
.halt_reg = 0x57020,
2546
+
.clkr = {
2547
+
.enable_reg = 0x57020,
2548
+
.enable_mask = BIT(0),
2549
+
.hw.init = &(struct clk_init_data) {
2550
+
.name = "gcc_qpic_clk",
2551
+
.parent_hws = (const struct clk_hw *[]) {
2552
+
&pcnoc_clk_src.hw,
2553
+
},
2554
+
.num_parents = 1,
2555
+
.flags = CLK_SET_RATE_PARENT,
2556
+
.ops = &clk_branch2_ops,
2557
+
},
2558
+
},
2559
+
};
2560
+
2561
+
static struct clk_branch gcc_qpic_io_macro_clk = {
2562
+
.halt_reg = 0x5701c,
2563
+
.clkr = {
2564
+
.enable_reg = 0x5701c,
2565
+
.enable_mask = BIT(0),
2566
+
.hw.init = &(struct clk_init_data) {
2567
+
.name = "gcc_qpic_io_macro_clk",
2568
+
.parent_hws = (const struct clk_hw *[]) {
2569
+
&qpic_io_macro_clk_src.clkr.hw,
2570
+
},
2571
+
.num_parents = 1,
2572
+
.flags = CLK_SET_RATE_PARENT,
2573
+
.ops = &clk_branch2_ops,
2574
+
},
2575
+
},
2576
+
};
2577
+
2578
+
static struct clk_branch gcc_sdcc1_ahb_clk = {
2579
+
.halt_reg = 0x4201c,
2580
+
.clkr = {
2581
+
.enable_reg = 0x4201c,
2582
+
.enable_mask = BIT(0),
2583
+
.hw.init = &(struct clk_init_data) {
2584
+
.name = "gcc_sdcc1_ahb_clk",
2585
+
.parent_hws = (const struct clk_hw *[]) {
2586
+
&pcnoc_clk_src.hw,
2587
+
},
2588
+
.num_parents = 1,
2589
+
.flags = CLK_SET_RATE_PARENT,
2590
+
.ops = &clk_branch2_ops,
2591
+
},
2592
+
},
2593
+
};
2594
+
2595
+
static struct clk_branch gcc_sdcc1_apps_clk = {
2596
+
.halt_reg = 0x42018,
2597
+
.clkr = {
2598
+
.enable_reg = 0x42018,
2599
+
.enable_mask = BIT(0),
2600
+
.hw.init = &(struct clk_init_data) {
2601
+
.name = "gcc_sdcc1_apps_clk",
2602
+
.parent_hws = (const struct clk_hw *[]) {
2603
+
&sdcc1_apps_clk_src.clkr.hw,
2604
+
},
2605
+
.num_parents = 1,
2606
+
.flags = CLK_SET_RATE_PARENT,
2607
+
.ops = &clk_branch2_ops,
2608
+
},
2609
+
},
2610
+
};
2611
+
2612
+
static struct clk_branch gcc_snoc_gmac0_ahb_clk = {
2613
+
.halt_reg = 0x260a0,
2614
+
.clkr = {
2615
+
.enable_reg = 0x260a0,
2616
+
.enable_mask = BIT(0),
2617
+
.hw.init = &(struct clk_init_data) {
2618
+
.name = "gcc_snoc_gmac0_ahb_clk",
2619
+
.parent_hws = (const struct clk_hw *[]) {
2620
+
&gmac_clk_src.clkr.hw,
2621
+
},
2622
+
.num_parents = 1,
2623
+
.flags = CLK_SET_RATE_PARENT,
2624
+
.ops = &clk_branch2_ops,
2625
+
},
2626
+
},
2627
+
};
2628
+
2629
+
static struct clk_branch gcc_snoc_gmac0_axi_clk = {
2630
+
.halt_reg = 0x26084,
2631
+
.clkr = {
2632
+
.enable_reg = 0x26084,
2633
+
.enable_mask = BIT(0),
2634
+
.hw.init = &(struct clk_init_data) {
2635
+
.name = "gcc_snoc_gmac0_axi_clk",
2636
+
.parent_hws = (const struct clk_hw *[]) {
2637
+
&gmac_clk_src.clkr.hw,
2638
+
},
2639
+
.num_parents = 1,
2640
+
.flags = CLK_SET_RATE_PARENT,
2641
+
.ops = &clk_branch2_ops,
2642
+
},
2643
+
},
2644
+
};
2645
+
2646
+
static struct clk_branch gcc_snoc_gmac1_ahb_clk = {
2647
+
.halt_reg = 0x260a4,
2648
+
.clkr = {
2649
+
.enable_reg = 0x260a4,
2650
+
.enable_mask = BIT(0),
2651
+
.hw.init = &(struct clk_init_data) {
2652
+
.name = "gcc_snoc_gmac1_ahb_clk",
2653
+
.parent_hws = (const struct clk_hw *[]) {
2654
+
&gmac_clk_src.clkr.hw,
2655
+
},
2656
+
.num_parents = 1,
2657
+
.flags = CLK_SET_RATE_PARENT,
2658
+
.ops = &clk_branch2_ops,
2659
+
},
2660
+
},
2661
+
};
2662
+
2663
+
static struct clk_branch gcc_snoc_gmac1_axi_clk = {
2664
+
.halt_reg = 0x26088,
2665
+
.clkr = {
2666
+
.enable_reg = 0x26088,
2667
+
.enable_mask = BIT(0),
2668
+
.hw.init = &(struct clk_init_data) {
2669
+
.name = "gcc_snoc_gmac1_axi_clk",
2670
+
.parent_hws = (const struct clk_hw *[]) {
2671
+
&gmac_clk_src.clkr.hw,
2672
+
},
2673
+
.num_parents = 1,
2674
+
.flags = CLK_SET_RATE_PARENT,
2675
+
.ops = &clk_branch2_ops,
2676
+
},
2677
+
},
2678
+
};
2679
+
2680
+
static struct clk_branch gcc_snoc_lpass_axim_clk = {
2681
+
.halt_reg = 0x26074,
2682
+
.clkr = {
2683
+
.enable_reg = 0x26074,
2684
+
.enable_mask = BIT(0),
2685
+
.hw.init = &(struct clk_init_data) {
2686
+
.name = "gcc_snoc_lpass_axim_clk",
2687
+
.parent_hws = (const struct clk_hw *[]) {
2688
+
&lpass_axim_clk_src.clkr.hw,
2689
+
},
2690
+
.num_parents = 1,
2691
+
.flags = CLK_SET_RATE_PARENT,
2692
+
.ops = &clk_branch2_ops,
2693
+
},
2694
+
},
2695
+
};
2696
+
2697
+
static struct clk_branch gcc_snoc_lpass_sway_clk = {
2698
+
.halt_reg = 0x26078,
2699
+
.clkr = {
2700
+
.enable_reg = 0x26078,
2701
+
.enable_mask = BIT(0),
2702
+
.hw.init = &(struct clk_init_data) {
2703
+
.name = "gcc_snoc_lpass_sway_clk",
2704
+
.parent_hws = (const struct clk_hw *[]) {
2705
+
&lpass_sway_clk_src.clkr.hw,
2706
+
},
2707
+
.num_parents = 1,
2708
+
.flags = CLK_SET_RATE_PARENT,
2709
+
.ops = &clk_branch2_ops,
2710
+
},
2711
+
},
2712
+
};
2713
+
2714
+
static struct clk_branch gcc_snoc_ubi0_axi_clk = {
2715
+
.halt_reg = 0x26094,
2716
+
.clkr = {
2717
+
.enable_reg = 0x26094,
2718
+
.enable_mask = BIT(0),
2719
+
.hw.init = &(struct clk_init_data) {
2720
+
.name = "gcc_snoc_ubi0_axi_clk",
2721
+
.parent_hws = (const struct clk_hw *[]) {
2722
+
&ubi0_axi_clk_src.clkr.hw,
2723
+
},
2724
+
.num_parents = 1,
2725
+
.flags = CLK_SET_RATE_PARENT,
2726
+
.ops = &clk_branch2_ops,
2727
+
},
2728
+
},
2729
+
};
2730
+
2731
+
static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
2732
+
.halt_reg = 0x26048,
2733
+
.clkr = {
2734
+
.enable_reg = 0x26048,
2735
+
.enable_mask = BIT(0),
2736
+
.hw.init = &(struct clk_init_data) {
2737
+
.name = "gcc_sys_noc_pcie0_axi_clk",
2738
+
.parent_hws = (const struct clk_hw *[]) {
2739
+
&pcie0_axi_clk_src.clkr.hw,
2740
+
},
2741
+
.num_parents = 1,
2742
+
.flags = CLK_SET_RATE_PARENT,
2743
+
.ops = &clk_branch2_ops,
2744
+
},
2745
+
},
2746
+
};
2747
+
2748
+
static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
2749
+
.halt_reg = 0x2604c,
2750
+
.clkr = {
2751
+
.enable_reg = 0x2604c,
2752
+
.enable_mask = BIT(0),
2753
+
.hw.init = &(struct clk_init_data) {
2754
+
.name = "gcc_sys_noc_pcie1_axi_clk",
2755
+
.parent_hws = (const struct clk_hw *[]) {
2756
+
&pcie1_axi_clk_src.clkr.hw,
2757
+
},
2758
+
.num_parents = 1,
2759
+
.flags = CLK_SET_RATE_PARENT,
2760
+
.ops = &clk_branch2_ops,
2761
+
},
2762
+
},
2763
+
};
2764
+
2765
+
static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
2766
+
.halt_reg = 0x26024,
2767
+
.clkr = {
2768
+
.enable_reg = 0x26024,
2769
+
.enable_mask = BIT(0),
2770
+
.hw.init = &(struct clk_init_data) {
2771
+
.name = "gcc_sys_noc_qdss_stm_axi_clk",
2772
+
.parent_hws = (const struct clk_hw *[]) {
2773
+
&qdss_stm_clk_src.clkr.hw,
2774
+
},
2775
+
.num_parents = 1,
2776
+
.flags = CLK_SET_RATE_PARENT,
2777
+
.ops = &clk_branch2_ops,
2778
+
},
2779
+
},
2780
+
};
2781
+
2782
+
static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
2783
+
.halt_reg = 0x26040,
2784
+
.clkr = {
2785
+
.enable_reg = 0x26040,
2786
+
.enable_mask = BIT(0),
2787
+
.hw.init = &(struct clk_init_data) {
2788
+
.name = "gcc_sys_noc_usb0_axi_clk",
2789
+
.parent_hws = (const struct clk_hw *[]) {
2790
+
&usb0_master_clk_src.clkr.hw,
2791
+
},
2792
+
.num_parents = 1,
2793
+
.flags = CLK_SET_RATE_PARENT,
2794
+
.ops = &clk_branch2_ops,
2795
+
},
2796
+
},
2797
+
};
2798
+
2799
+
static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
2800
+
.halt_reg = 0x26034,
2801
+
.clkr = {
2802
+
.enable_reg = 0x26034,
2803
+
.enable_mask = BIT(0),
2804
+
.hw.init = &(struct clk_init_data) {
2805
+
.name = "gcc_sys_noc_wcss_ahb_clk",
2806
+
.parent_hws = (const struct clk_hw *[]) {
2807
+
&wcss_ahb_clk_src.clkr.hw,
2808
+
},
2809
+
.num_parents = 1,
2810
+
.flags = CLK_SET_RATE_PARENT,
2811
+
.ops = &clk_branch2_ops,
2812
+
},
2813
+
},
2814
+
};
2815
+
2816
+
static struct clk_branch gcc_ubi0_axi_clk = {
2817
+
.halt_reg = 0x68200,
2818
+
.halt_check = BRANCH_HALT_DELAY,
2819
+
.clkr = {
2820
+
.enable_reg = 0x68200,
2821
+
.enable_mask = BIT(0),
2822
+
.hw.init = &(struct clk_init_data) {
2823
+
.name = "gcc_ubi0_axi_clk",
2824
+
.parent_hws = (const struct clk_hw *[]) {
2825
+
&ubi0_axi_clk_src.clkr.hw,
2826
+
},
2827
+
.num_parents = 1,
2828
+
.flags = CLK_SET_RATE_PARENT,
2829
+
.ops = &clk_branch2_ops,
2830
+
},
2831
+
},
2832
+
};
2833
+
2834
+
static struct clk_branch gcc_ubi0_cfg_clk = {
2835
+
.halt_reg = 0x68160,
2836
+
.halt_check = BRANCH_HALT_DELAY,
2837
+
.clkr = {
2838
+
.enable_reg = 0x68160,
2839
+
.enable_mask = BIT(0),
2840
+
.hw.init = &(struct clk_init_data) {
2841
+
.name = "gcc_ubi0_cfg_clk",
2842
+
.parent_hws = (const struct clk_hw *[]) {
2843
+
&pcnoc_clk_src.hw,
2844
+
},
2845
+
.num_parents = 1,
2846
+
.flags = CLK_SET_RATE_PARENT,
2847
+
.ops = &clk_branch2_ops,
2848
+
},
2849
+
},
2850
+
};
2851
+
2852
+
static struct clk_branch gcc_ubi0_dbg_clk = {
2853
+
.halt_reg = 0x68214,
2854
+
.halt_check = BRANCH_HALT_DELAY,
2855
+
.clkr = {
2856
+
.enable_reg = 0x68214,
2857
+
.enable_mask = BIT(0),
2858
+
.hw.init = &(struct clk_init_data) {
2859
+
.name = "gcc_ubi0_dbg_clk",
2860
+
.parent_hws = (const struct clk_hw *[]) {
2861
+
&qdss_tsctr_clk_src.clkr.hw,
2862
+
},
2863
+
.num_parents = 1,
2864
+
.flags = CLK_SET_RATE_PARENT,
2865
+
.ops = &clk_branch2_ops,
2866
+
},
2867
+
},
2868
+
};
2869
+
2870
+
static struct clk_branch gcc_ubi0_core_clk = {
2871
+
.halt_reg = 0x68210,
2872
+
.halt_check = BRANCH_HALT_DELAY,
2873
+
.clkr = {
2874
+
.enable_reg = 0x68210,
2875
+
.enable_mask = BIT(0),
2876
+
.hw.init = &(struct clk_init_data) {
2877
+
.name = "gcc_ubi0_core_clk",
2878
+
.parent_hws = (const struct clk_hw *[]) {
2879
+
&ubi0_core_clk_src.clkr.hw,
2880
+
},
2881
+
.num_parents = 1,
2882
+
.flags = CLK_SET_RATE_PARENT,
2883
+
.ops = &clk_branch2_ops,
2884
+
},
2885
+
},
2886
+
};
2887
+
2888
+
static struct clk_branch gcc_ubi0_nc_axi_clk = {
2889
+
.halt_reg = 0x68204,
2890
+
.halt_check = BRANCH_HALT_DELAY,
2891
+
.clkr = {
2892
+
.enable_reg = 0x68204,
2893
+
.enable_mask = BIT(0),
2894
+
.hw.init = &(struct clk_init_data) {
2895
+
.name = "gcc_ubi0_nc_axi_clk",
2896
+
.parent_hws = (const struct clk_hw *[]) {
2897
+
&system_noc_clk_src.hw,
2898
+
},
2899
+
.num_parents = 1,
2900
+
.flags = CLK_SET_RATE_PARENT,
2901
+
.ops = &clk_branch2_ops,
2902
+
},
2903
+
},
2904
+
};
2905
+
2906
+
static struct clk_branch gcc_ubi0_utcm_clk = {
2907
+
.halt_reg = 0x68208,
2908
+
.halt_check = BRANCH_HALT_DELAY,
2909
+
.clkr = {
2910
+
.enable_reg = 0x68208,
2911
+
.enable_mask = BIT(0),
2912
+
.hw.init = &(struct clk_init_data) {
2913
+
.name = "gcc_ubi0_utcm_clk",
2914
+
.parent_hws = (const struct clk_hw *[]) {
2915
+
&system_noc_clk_src.hw,
2916
+
},
2917
+
.num_parents = 1,
2918
+
.flags = CLK_SET_RATE_PARENT,
2919
+
.ops = &clk_branch2_ops,
2920
+
},
2921
+
},
2922
+
};
2923
+
2924
+
static struct clk_branch gcc_uniphy_ahb_clk = {
2925
+
.halt_reg = 0x56108,
2926
+
.clkr = {
2927
+
.enable_reg = 0x56108,
2928
+
.enable_mask = BIT(0),
2929
+
.hw.init = &(struct clk_init_data) {
2930
+
.name = "gcc_uniphy_ahb_clk",
2931
+
.parent_hws = (const struct clk_hw *[]) {
2932
+
&pcnoc_clk_src.hw,
2933
+
},
2934
+
.num_parents = 1,
2935
+
.flags = CLK_SET_RATE_PARENT,
2936
+
.ops = &clk_branch2_ops,
2937
+
},
2938
+
},
2939
+
};
2940
+
2941
+
static struct clk_branch gcc_uniphy_rx_clk = {
2942
+
.halt_reg = 0x56110,
2943
+
.clkr = {
2944
+
.enable_reg = 0x56110,
2945
+
.enable_mask = BIT(0),
2946
+
.hw.init = &(struct clk_init_data) {
2947
+
.name = "gcc_uniphy_rx_clk",
2948
+
.parent_hws = (const struct clk_hw *[]) {
2949
+
&gmac1_rx_div_clk_src.clkr.hw,
2950
+
},
2951
+
.num_parents = 1,
2952
+
.ops = &clk_branch2_ops,
2953
+
.flags = CLK_SET_RATE_PARENT,
2954
+
},
2955
+
},
2956
+
};
2957
+
2958
+
static struct clk_branch gcc_uniphy_tx_clk = {
2959
+
.halt_reg = 0x56114,
2960
+
.clkr = {
2961
+
.enable_reg = 0x56114,
2962
+
.enable_mask = BIT(0),
2963
+
.hw.init = &(struct clk_init_data) {
2964
+
.name = "gcc_uniphy_tx_clk",
2965
+
.parent_hws = (const struct clk_hw *[]) {
2966
+
&gmac1_tx_div_clk_src.clkr.hw,
2967
+
},
2968
+
.num_parents = 1,
2969
+
.ops = &clk_branch2_ops,
2970
+
.flags = CLK_SET_RATE_PARENT,
2971
+
},
2972
+
},
2973
+
};
2974
+
2975
+
static struct clk_branch gcc_uniphy_sys_clk = {
2976
+
.halt_reg = 0x5610c,
2977
+
.clkr = {
2978
+
.enable_reg = 0x5610c,
2979
+
.enable_mask = BIT(0),
2980
+
.hw.init = &(struct clk_init_data) {
2981
+
.name = "gcc_uniphy_sys_clk",
2982
+
.parent_hws = (const struct clk_hw *[]) {
2983
+
&gcc_xo_clk_src.clkr.hw,
2984
+
},
2985
+
.num_parents = 1,
2986
+
.flags = CLK_SET_RATE_PARENT,
2987
+
.ops = &clk_branch2_ops,
2988
+
},
2989
+
},
2990
+
};
2991
+
2992
+
static struct clk_branch gcc_usb0_aux_clk = {
2993
+
.halt_reg = 0x3e044,
2994
+
.clkr = {
2995
+
.enable_reg = 0x3e044,
2996
+
.enable_mask = BIT(0),
2997
+
.hw.init = &(struct clk_init_data) {
2998
+
.name = "gcc_usb0_aux_clk",
2999
+
.parent_hws = (const struct clk_hw *[]) {
3000
+
&usb0_aux_clk_src.clkr.hw,
3001
+
},
3002
+
.num_parents = 1,
3003
+
.flags = CLK_SET_RATE_PARENT,
3004
+
.ops = &clk_branch2_ops,
3005
+
},
3006
+
},
3007
+
};
3008
+
3009
+
static struct clk_branch gcc_usb0_eud_at_clk = {
3010
+
.halt_reg = 0x3e04c,
3011
+
.halt_check = BRANCH_HALT_VOTED,
3012
+
.clkr = {
3013
+
.enable_reg = 0x3e04c,
3014
+
.enable_mask = BIT(0),
3015
+
.hw.init = &(struct clk_init_data) {
3016
+
.name = "gcc_usb0_eud_at_clk",
3017
+
.parent_hws = (const struct clk_hw *[]) {
3018
+
&eud_at_clk_src.hw,
3019
+
},
3020
+
.num_parents = 1,
3021
+
.flags = CLK_SET_RATE_PARENT,
3022
+
.ops = &clk_branch2_ops,
3023
+
},
3024
+
},
3025
+
};
3026
+
3027
+
static struct clk_branch gcc_usb0_lfps_clk = {
3028
+
.halt_reg = 0x3e050,
3029
+
.clkr = {
3030
+
.enable_reg = 0x3e050,
3031
+
.enable_mask = BIT(0),
3032
+
.hw.init = &(struct clk_init_data) {
3033
+
.name = "gcc_usb0_lfps_clk",
3034
+
.parent_hws = (const struct clk_hw *[]) {
3035
+
&usb0_lfps_clk_src.clkr.hw,
3036
+
},
3037
+
.num_parents = 1,
3038
+
.flags = CLK_SET_RATE_PARENT,
3039
+
.ops = &clk_branch2_ops,
3040
+
},
3041
+
},
3042
+
};
3043
+
3044
+
static struct clk_branch gcc_usb0_master_clk = {
3045
+
.halt_reg = 0x3e000,
3046
+
.clkr = {
3047
+
.enable_reg = 0x3e000,
3048
+
.enable_mask = BIT(0),
3049
+
.hw.init = &(struct clk_init_data) {
3050
+
.name = "gcc_usb0_master_clk",
3051
+
.parent_hws = (const struct clk_hw *[]) {
3052
+
&usb0_master_clk_src.clkr.hw,
3053
+
},
3054
+
.num_parents = 1,
3055
+
.flags = CLK_SET_RATE_PARENT,
3056
+
.ops = &clk_branch2_ops,
3057
+
},
3058
+
},
3059
+
};
3060
+
3061
+
static struct clk_branch gcc_usb0_mock_utmi_clk = {
3062
+
.halt_reg = 0x3e008,
3063
+
.clkr = {
3064
+
.enable_reg = 0x3e008,
3065
+
.enable_mask = BIT(0),
3066
+
.hw.init = &(struct clk_init_data) {
3067
+
.name = "gcc_usb0_mock_utmi_clk",
3068
+
.parent_hws = (const struct clk_hw *[]) {
3069
+
&usb0_mock_utmi_clk_src.clkr.hw,
3070
+
},
3071
+
.num_parents = 1,
3072
+
.flags = CLK_SET_RATE_PARENT,
3073
+
.ops = &clk_branch2_ops,
3074
+
},
3075
+
},
3076
+
};
3077
+
3078
+
static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
3079
+
.halt_reg = 0x3e080,
3080
+
.clkr = {
3081
+
.enable_reg = 0x3e080,
3082
+
.enable_mask = BIT(0),
3083
+
.hw.init = &(struct clk_init_data) {
3084
+
.name = "gcc_usb0_phy_cfg_ahb_clk",
3085
+
.parent_hws = (const struct clk_hw *[]) {
3086
+
&pcnoc_clk_src.hw,
3087
+
},
3088
+
.num_parents = 1,
3089
+
.flags = CLK_SET_RATE_PARENT,
3090
+
.ops = &clk_branch2_ops,
3091
+
},
3092
+
},
3093
+
};
3094
+
3095
+
static struct clk_branch gcc_usb0_sleep_clk = {
3096
+
.halt_reg = 0x3e004,
3097
+
.clkr = {
3098
+
.enable_reg = 0x3e004,
3099
+
.enable_mask = BIT(0),
3100
+
.hw.init = &(struct clk_init_data) {
3101
+
.name = "gcc_usb0_sleep_clk",
3102
+
.parent_hws = (const struct clk_hw *[]) {
3103
+
&gcc_sleep_clk_src.clkr.hw,
3104
+
},
3105
+
.num_parents = 1,
3106
+
.flags = CLK_SET_RATE_PARENT,
3107
+
.ops = &clk_branch2_ops,
3108
+
},
3109
+
},
3110
+
};
3111
+
3112
+
static struct clk_branch gcc_usb0_pipe_clk = {
3113
+
.halt_reg = 0x3e040,
3114
+
.halt_check = BRANCH_HALT_DELAY,
3115
+
.clkr = {
3116
+
.enable_reg = 0x3e040,
3117
+
.enable_mask = BIT(0),
3118
+
.hw.init = &(struct clk_init_data) {
3119
+
.name = "gcc_usb0_pipe_clk",
3120
+
.parent_hws = (const struct clk_hw *[]) {
3121
+
&usb0_pipe_clk_src.clkr.hw,
3122
+
},
3123
+
.num_parents = 1,
3124
+
.flags = CLK_SET_RATE_PARENT,
3125
+
.ops = &clk_branch2_ops,
3126
+
},
3127
+
},
3128
+
};
3129
+
3130
+
static struct clk_branch gcc_wcss_acmt_clk = {
3131
+
.halt_reg = 0x59064,
3132
+
.clkr = {
3133
+
.enable_reg = 0x59064,
3134
+
.enable_mask = BIT(0),
3135
+
.hw.init = &(struct clk_init_data) {
3136
+
.name = "gcc_wcss_acmt_clk",
3137
+
.parent_hws = (const struct clk_hw *[]) {
3138
+
&wcss_ahb_clk_src.clkr.hw,
3139
+
},
3140
+
.num_parents = 1,
3141
+
.flags = CLK_SET_RATE_PARENT,
3142
+
.ops = &clk_branch2_ops,
3143
+
},
3144
+
},
3145
+
};
3146
+
3147
+
static struct clk_branch gcc_wcss_ahb_s_clk = {
3148
+
.halt_reg = 0x59034,
3149
+
.clkr = {
3150
+
.enable_reg = 0x59034,
3151
+
.enable_mask = BIT(0),
3152
+
.hw.init = &(struct clk_init_data) {
3153
+
.name = "gcc_wcss_ahb_s_clk",
3154
+
.parent_hws = (const struct clk_hw *[]) {
3155
+
&wcss_ahb_clk_src.clkr.hw,
3156
+
},
3157
+
.num_parents = 1,
3158
+
.flags = CLK_SET_RATE_PARENT,
3159
+
.ops = &clk_branch2_ops,
3160
+
},
3161
+
},
3162
+
};
3163
+
3164
+
static struct clk_branch gcc_wcss_axi_m_clk = {
3165
+
.halt_reg = 0x5903c,
3166
+
.clkr = {
3167
+
.enable_reg = 0x5903c,
3168
+
.enable_mask = BIT(0),
3169
+
.hw.init = &(struct clk_init_data) {
3170
+
.name = "gcc_wcss_axi_m_clk",
3171
+
.parent_hws = (const struct clk_hw *[]) {
3172
+
&system_noc_clk_src.hw,
3173
+
},
3174
+
.num_parents = 1,
3175
+
.flags = CLK_SET_RATE_PARENT,
3176
+
.ops = &clk_branch2_ops,
3177
+
},
3178
+
},
3179
+
};
3180
+
3181
+
static struct clk_branch gcc_wcss_axi_s_clk = {
3182
+
.halt_reg = 0x59068,
3183
+
.clkr = {
3184
+
.enable_reg = 0x59068,
3185
+
.enable_mask = BIT(0),
3186
+
.hw.init = &(struct clk_init_data) {
3187
+
.name = "gcc_wi_s_clk",
3188
+
.parent_hws = (const struct clk_hw *[]) {
3189
+
&system_noc_clk_src.hw,
3190
+
},
3191
+
.num_parents = 1,
3192
+
.flags = CLK_SET_RATE_PARENT,
3193
+
.ops = &clk_branch2_ops,
3194
+
},
3195
+
},
3196
+
};
3197
+
3198
+
static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {
3199
+
.halt_reg = 0x59050,
3200
+
.clkr = {
3201
+
.enable_reg = 0x59050,
3202
+
.enable_mask = BIT(0),
3203
+
.hw.init = &(struct clk_init_data) {
3204
+
.name = "gcc_wcss_dbg_ifc_apb_bdg_clk",
3205
+
.parent_hws = (const struct clk_hw *[]) {
3206
+
&qdss_dap_sync_clk_src.hw,
3207
+
},
3208
+
.num_parents = 1,
3209
+
.flags = CLK_SET_RATE_PARENT,
3210
+
.ops = &clk_branch2_ops,
3211
+
},
3212
+
},
3213
+
};
3214
+
3215
+
static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
3216
+
.halt_reg = 0x59040,
3217
+
.clkr = {
3218
+
.enable_reg = 0x59040,
3219
+
.enable_mask = BIT(0),
3220
+
.hw.init = &(struct clk_init_data) {
3221
+
.name = "gcc_wcss_dbg_ifc_apb_clk",
3222
+
.parent_hws = (const struct clk_hw *[]) {
3223
+
&qdss_dap_sync_clk_src.hw,
3224
+
},
3225
+
.num_parents = 1,
3226
+
.flags = CLK_SET_RATE_PARENT,
3227
+
.ops = &clk_branch2_ops,
3228
+
},
3229
+
},
3230
+
};
3231
+
3232
+
static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {
3233
+
.halt_reg = 0x59054,
3234
+
.clkr = {
3235
+
.enable_reg = 0x59054,
3236
+
.enable_mask = BIT(0),
3237
+
.hw.init = &(struct clk_init_data) {
3238
+
.name = "gcc_wcss_dbg_ifc_atb_bdg_clk",
3239
+
.parent_hws = (const struct clk_hw *[]) {
3240
+
&qdss_at_clk_src.clkr.hw,
3241
+
},
3242
+
.num_parents = 1,
3243
+
.flags = CLK_SET_RATE_PARENT,
3244
+
.ops = &clk_branch2_ops,
3245
+
},
3246
+
},
3247
+
};
3248
+
3249
+
static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
3250
+
.halt_reg = 0x59044,
3251
+
.clkr = {
3252
+
.enable_reg = 0x59044,
3253
+
.enable_mask = BIT(0),
3254
+
.hw.init = &(struct clk_init_data) {
3255
+
.name = "gcc_wcss_dbg_ifc_atb_clk",
3256
+
.parent_hws = (const struct clk_hw *[]) {
3257
+
&qdss_at_clk_src.clkr.hw,
3258
+
},
3259
+
.num_parents = 1,
3260
+
.flags = CLK_SET_RATE_PARENT,
3261
+
.ops = &clk_branch2_ops,
3262
+
},
3263
+
},
3264
+
};
3265
+
3266
+
static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = {
3267
+
.halt_reg = 0x59060,
3268
+
.clkr = {
3269
+
.enable_reg = 0x59060,
3270
+
.enable_mask = BIT(0),
3271
+
.hw.init = &(struct clk_init_data) {
3272
+
.name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk",
3273
+
.parent_hws = (const struct clk_hw *[]) {
3274
+
&qdss_dap_sync_clk_src.hw,
3275
+
},
3276
+
.num_parents = 1,
3277
+
.flags = CLK_SET_RATE_PARENT,
3278
+
.ops = &clk_branch2_ops,
3279
+
},
3280
+
},
3281
+
};
3282
+
3283
+
static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
3284
+
.halt_reg = 0x5905c,
3285
+
.clkr = {
3286
+
.enable_reg = 0x5905c,
3287
+
.enable_mask = BIT(0),
3288
+
.hw.init = &(struct clk_init_data) {
3289
+
.name = "gcc_wcss_dbg_ifc_dapbus_clk",
3290
+
.parent_hws = (const struct clk_hw *[]) {
3291
+
&qdss_dap_sync_clk_src.hw,
3292
+
},
3293
+
.num_parents = 1,
3294
+
.flags = CLK_SET_RATE_PARENT,
3295
+
.ops = &clk_branch2_ops,
3296
+
},
3297
+
},
3298
+
};
3299
+
3300
+
static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {
3301
+
.halt_reg = 0x59058,
3302
+
.clkr = {
3303
+
.enable_reg = 0x59058,
3304
+
.enable_mask = BIT(0),
3305
+
.hw.init = &(struct clk_init_data) {
3306
+
.name = "gcc_wcss_dbg_ifc_nts_bdg_clk",
3307
+
.parent_hws = (const struct clk_hw *[]) {
3308
+
&qdss_tsctr_div2_clk_src.hw,
3309
+
},
3310
+
.num_parents = 1,
3311
+
.flags = CLK_SET_RATE_PARENT,
3312
+
.ops = &clk_branch2_ops,
3313
+
},
3314
+
},
3315
+
};
3316
+
3317
+
static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
3318
+
.halt_reg = 0x59048,
3319
+
.clkr = {
3320
+
.enable_reg = 0x59048,
3321
+
.enable_mask = BIT(0),
3322
+
.hw.init = &(struct clk_init_data) {
3323
+
.name = "gcc_wcss_dbg_ifc_nts_clk",
3324
+
.parent_hws = (const struct clk_hw *[]) {
3325
+
&qdss_tsctr_div2_clk_src.hw,
3326
+
},
3327
+
.num_parents = 1,
3328
+
.flags = CLK_SET_RATE_PARENT,
3329
+
.ops = &clk_branch2_ops,
3330
+
},
3331
+
},
3332
+
};
3333
+
3334
+
static struct clk_branch gcc_wcss_ecahb_clk = {
3335
+
.halt_reg = 0x59038,
3336
+
.clkr = {
3337
+
.enable_reg = 0x59038,
3338
+
.enable_mask = BIT(0),
3339
+
.hw.init = &(struct clk_init_data) {
3340
+
.name = "gcc_wcss_ecahb_clk",
3341
+
.parent_hws = (const struct clk_hw *[]) {
3342
+
&wcss_ahb_clk_src.clkr.hw,
3343
+
},
3344
+
.num_parents = 1,
3345
+
.flags = CLK_SET_RATE_PARENT,
3346
+
.ops = &clk_branch2_ops,
3347
+
},
3348
+
},
3349
+
};
3350
+
3351
+
static struct clk_hw *gcc_ipq5018_hws[] = {
3352
+
&gpll0_out_main_div2.hw,
3353
+
&pcnoc_clk_src.hw,
3354
+
&system_noc_clk_src.hw,
3355
+
&qdss_dap_sync_clk_src.hw,
3356
+
&qdss_tsctr_div2_clk_src.hw,
3357
+
&eud_at_clk_src.hw,
3358
+
};
3359
+
3360
+
static const struct alpha_pll_config ubi32_pll_config = {
3361
+
.l = 0x29,
3362
+
.alpha = 0xaaaaaaaa,
3363
+
.alpha_hi = 0xaa,
3364
+
.config_ctl_val = 0x4001075b,
3365
+
.main_output_mask = BIT(0),
3366
+
.aux_output_mask = BIT(1),
3367
+
.alpha_en_mask = BIT(24),
3368
+
.vco_val = 0x1,
3369
+
.vco_mask = GENMASK(21, 20),
3370
+
.test_ctl_val = 0x0,
3371
+
.test_ctl_hi_val = 0x0,
3372
+
};
3373
+
3374
+
static struct clk_regmap *gcc_ipq5018_clks[] = {
3375
+
[GPLL0_MAIN] = &gpll0_main.clkr,
3376
+
[GPLL0] = &gpll0.clkr,
3377
+
[GPLL2_MAIN] = &gpll2_main.clkr,
3378
+
[GPLL2] = &gpll2.clkr,
3379
+
[GPLL4_MAIN] = &gpll4_main.clkr,
3380
+
[GPLL4] = &gpll4.clkr,
3381
+
[UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
3382
+
[UBI32_PLL] = &ubi32_pll.clkr,
3383
+
[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
3384
+
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3385
+
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3386
+
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3387
+
[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3388
+
[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3389
+
[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3390
+
[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3391
+
[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3392
+
[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3393
+
[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
3394
+
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3395
+
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3396
+
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3397
+
[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3398
+
[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3399
+
[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3400
+
[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3401
+
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3402
+
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3403
+
[GCC_BTSS_LPO_CLK] = &gcc_btss_lpo_clk.clkr,
3404
+
[GCC_CMN_BLK_AHB_CLK] = &gcc_cmn_blk_ahb_clk.clkr,
3405
+
[GCC_CMN_BLK_SYS_CLK] = &gcc_cmn_blk_sys_clk.clkr,
3406
+
[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3407
+
[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3408
+
[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3409
+
[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
3410
+
[GCC_GEPHY_RX_CLK] = &gcc_gephy_rx_clk.clkr,
3411
+
[GCC_GEPHY_TX_CLK] = &gcc_gephy_tx_clk.clkr,
3412
+
[GCC_GMAC0_CFG_CLK] = &gcc_gmac0_cfg_clk.clkr,
3413
+
[GCC_GMAC0_PTP_CLK] = &gcc_gmac0_ptp_clk.clkr,
3414
+
[GCC_GMAC0_RX_CLK] = &gcc_gmac0_rx_clk.clkr,
3415
+
[GCC_GMAC0_SYS_CLK] = &gcc_gmac0_sys_clk.clkr,
3416
+
[GCC_GMAC0_TX_CLK] = &gcc_gmac0_tx_clk.clkr,
3417
+
[GCC_GMAC1_CFG_CLK] = &gcc_gmac1_cfg_clk.clkr,
3418
+
[GCC_GMAC1_PTP_CLK] = &gcc_gmac1_ptp_clk.clkr,
3419
+
[GCC_GMAC1_RX_CLK] = &gcc_gmac1_rx_clk.clkr,
3420
+
[GCC_GMAC1_SYS_CLK] = &gcc_gmac1_sys_clk.clkr,
3421
+
[GCC_GMAC1_TX_CLK] = &gcc_gmac1_tx_clk.clkr,
3422
+
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3423
+
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3424
+
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3425
+
[GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
3426
+
[GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
3427
+
[GCC_MDIO0_AHB_CLK] = &gcc_mdio0_ahb_clk.clkr,
3428
+
[GCC_MDIO1_AHB_CLK] = &gcc_mdio1_ahb_clk.clkr,
3429
+
[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
3430
+
[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
3431
+
[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
3432
+
[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
3433
+
[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
3434
+
[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
3435
+
[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
3436
+
[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
3437
+
[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
3438
+
[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
3439
+
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3440
+
[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
3441
+
[GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr,
3442
+
[GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,
3443
+
[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
3444
+
[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
3445
+
[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
3446
+
[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
3447
+
[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
3448
+
[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
3449
+
[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
3450
+
[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
3451
+
[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
3452
+
[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3453
+
[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
3454
+
[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
3455
+
[GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
3456
+
[GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
3457
+
[GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
3458
+
[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
3459
+
[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
3460
+
[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
3461
+
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3462
+
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3463
+
[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3464
+
[GCC_SNOC_GMAC0_AHB_CLK] = &gcc_snoc_gmac0_ahb_clk.clkr,
3465
+
[GCC_SNOC_GMAC0_AXI_CLK] = &gcc_snoc_gmac0_axi_clk.clkr,
3466
+
[GCC_SNOC_GMAC1_AHB_CLK] = &gcc_snoc_gmac1_ahb_clk.clkr,
3467
+
[GCC_SNOC_GMAC1_AXI_CLK] = &gcc_snoc_gmac1_axi_clk.clkr,
3468
+
[GCC_SNOC_LPASS_AXIM_CLK] = &gcc_snoc_lpass_axim_clk.clkr,
3469
+
[GCC_SNOC_LPASS_SWAY_CLK] = &gcc_snoc_lpass_sway_clk.clkr,
3470
+
[GCC_SNOC_UBI0_AXI_CLK] = &gcc_snoc_ubi0_axi_clk.clkr,
3471
+
[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
3472
+
[GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
3473
+
[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
3474
+
[GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
3475
+
[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
3476
+
[GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
3477
+
[GCC_UBI0_CFG_CLK] = &gcc_ubi0_cfg_clk.clkr,
3478
+
[GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
3479
+
[GCC_UBI0_DBG_CLK] = &gcc_ubi0_dbg_clk.clkr,
3480
+
[GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
3481
+
[GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,
3482
+
[GCC_UNIPHY_AHB_CLK] = &gcc_uniphy_ahb_clk.clkr,
3483
+
[GCC_UNIPHY_RX_CLK] = &gcc_uniphy_rx_clk.clkr,
3484
+
[GCC_UNIPHY_SYS_CLK] = &gcc_uniphy_sys_clk.clkr,
3485
+
[GCC_UNIPHY_TX_CLK] = &gcc_uniphy_tx_clk.clkr,
3486
+
[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
3487
+
[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
3488
+
[GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,
3489
+
[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
3490
+
[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
3491
+
[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
3492
+
[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
3493
+
[GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
3494
+
[GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr,
3495
+
[GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr,
3496
+
[GCC_WCSS_AXI_S_CLK] = &gcc_wcss_axi_s_clk.clkr,
3497
+
[GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,
3498
+
[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
3499
+
[GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,
3500
+
[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
3501
+
[GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr,
3502
+
[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
3503
+
[GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,
3504
+
[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
3505
+
[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
3506
+
[GCC_XO_CLK] = &gcc_xo_clk.clkr,
3507
+
[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
3508
+
[GMAC0_RX_CLK_SRC] = &gmac0_rx_clk_src.clkr,
3509
+
[GMAC0_RX_DIV_CLK_SRC] = &gmac0_rx_div_clk_src.clkr,
3510
+
[GMAC0_TX_CLK_SRC] = &gmac0_tx_clk_src.clkr,
3511
+
[GMAC0_TX_DIV_CLK_SRC] = &gmac0_tx_div_clk_src.clkr,
3512
+
[GMAC1_RX_CLK_SRC] = &gmac1_rx_clk_src.clkr,
3513
+
[GMAC1_RX_DIV_CLK_SRC] = &gmac1_rx_div_clk_src.clkr,
3514
+
[GMAC1_TX_CLK_SRC] = &gmac1_tx_clk_src.clkr,
3515
+
[GMAC1_TX_DIV_CLK_SRC] = &gmac1_tx_div_clk_src.clkr,
3516
+
[GMAC_CLK_SRC] = &gmac_clk_src.clkr,
3517
+
[GP1_CLK_SRC] = &gp1_clk_src.clkr,
3518
+
[GP2_CLK_SRC] = &gp2_clk_src.clkr,
3519
+
[GP3_CLK_SRC] = &gp3_clk_src.clkr,
3520
+
[LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
3521
+
[LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
3522
+
[PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
3523
+
[PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
3524
+
[PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
3525
+
[PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
3526
+
[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3527
+
[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
3528
+
[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
3529
+
[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
3530
+
[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
3531
+
[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
3532
+
[QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
3533
+
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3534
+
[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3535
+
[UBI0_AXI_CLK_SRC] = &ubi0_axi_clk_src.clkr,
3536
+
[UBI0_CORE_CLK_SRC] = &ubi0_core_clk_src.clkr,
3537
+
[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
3538
+
[USB0_LFPS_CLK_SRC] = &usb0_lfps_clk_src.clkr,
3539
+
[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
3540
+
[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
3541
+
[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
3542
+
[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
3543
+
[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
3544
+
[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
3545
+
[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
3546
+
[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
3547
+
[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
3548
+
};
3549
+
3550
+
static const struct qcom_reset_map gcc_ipq5018_resets[] = {
3551
+
[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
3552
+
[GCC_BLSP1_BCR] = { 0x01000, 0 },
3553
+
[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
3554
+
[GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
3555
+
[GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
3556
+
[GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
3557
+
[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
3558
+
[GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
3559
+
[GCC_BTSS_BCR] = { 0x1c000, 0 },
3560
+
[GCC_CMN_BLK_BCR] = { 0x56300, 0 },
3561
+
[GCC_CMN_LDO_BCR] = { 0x33000, 0 },
3562
+
[GCC_CE_BCR] = { 0x33014, 0 },
3563
+
[GCC_CRYPTO_BCR] = { 0x16000, 0 },
3564
+
[GCC_DCC_BCR] = { 0x77000, 0 },
3565
+
[GCC_DCD_BCR] = { 0x2a000, 0 },
3566
+
[GCC_DDRSS_BCR] = { 0x1e000, 0 },
3567
+
[GCC_EDPD_BCR] = { 0x3a000, 0 },
3568
+
[GCC_GEPHY_BCR] = { 0x56000, 0 },
3569
+
[GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 },
3570
+
[GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 },
3571
+
[GCC_GEPHY_RX_ARES] = { 0x56004, 2 },
3572
+
[GCC_GEPHY_TX_ARES] = { 0x56004, 3 },
3573
+
[GCC_GMAC0_BCR] = { 0x19000, 0 },
3574
+
[GCC_GMAC0_CFG_ARES] = { 0x68428, 0 },
3575
+
[GCC_GMAC0_SYS_ARES] = { 0x68428, 1 },
3576
+
[GCC_GMAC1_BCR] = { 0x19100, 0 },
3577
+
[GCC_GMAC1_CFG_ARES] = { 0x68438, 0 },
3578
+
[GCC_GMAC1_SYS_ARES] = { 0x68438, 1 },
3579
+
[GCC_IMEM_BCR] = { 0x0e000, 0 },
3580
+
[GCC_LPASS_BCR] = { 0x2e000, 0 },
3581
+
[GCC_MDIO0_BCR] = { 0x58000, 0 },
3582
+
[GCC_MDIO1_BCR] = { 0x58010, 0 },
3583
+
[GCC_MPM_BCR] = { 0x2c000, 0 },
3584
+
[GCC_PCIE0_BCR] = { 0x75004, 0 },
3585
+
[GCC_PCIE0_LINK_DOWN_BCR] = { 0x750a8, 0 },
3586
+
[GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
3587
+
[GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
3588
+
[GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
3589
+
[GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
3590
+
[GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
3591
+
[GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
3592
+
[GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
3593
+
[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
3594
+
[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
3595
+
[GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
3596
+
[GCC_PCIE1_BCR] = { 0x76004, 0 },
3597
+
[GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
3598
+
[GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
3599
+
[GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
3600
+
[GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
3601
+
[GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
3602
+
[GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
3603
+
[GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
3604
+
[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
3605
+
[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
3606
+
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
3607
+
[GCC_PCIE1_AXI_SLAVE_STICKY_ARES] = { 0x76040, 7 },
3608
+
[GCC_PCNOC_BCR] = { 0x27018, 0 },
3609
+
[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
3610
+
[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
3611
+
[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
3612
+
[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
3613
+
[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
3614
+
[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
3615
+
[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
3616
+
[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
3617
+
[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
3618
+
[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
3619
+
[GCC_PCNOC_BUS_TIMEOUT10_BCR] = { 0x48050, 0 },
3620
+
[GCC_PCNOC_BUS_TIMEOUT11_BCR] = { 0x48058, 0 },
3621
+
[GCC_PRNG_BCR] = { 0x13000, 0 },
3622
+
[GCC_Q6SS_DBG_ARES] = { 0x59110, 0 },
3623
+
[GCC_Q6_AHB_S_ARES] = { 0x59110, 1 },
3624
+
[GCC_Q6_AHB_ARES] = { 0x59110, 2 },
3625
+
[GCC_Q6_AXIM2_ARES] = { 0x59110, 3 },
3626
+
[GCC_Q6_AXIM_ARES] = { 0x59110, 4 },
3627
+
[GCC_Q6_AXIS_ARES] = { 0x59158, 0 },
3628
+
[GCC_QDSS_BCR] = { 0x29000, 0 },
3629
+
[GCC_QPIC_BCR] = { 0x57018, 0 },
3630
+
[GCC_QUSB2_0_PHY_BCR] = { 0x41030, 0 },
3631
+
[GCC_SDCC1_BCR] = { 0x42000, 0 },
3632
+
[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
3633
+
[GCC_SPDM_BCR] = { 0x2f000, 0 },
3634
+
[GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
3635
+
[GCC_TCSR_BCR] = { 0x28000, 0 },
3636
+
[GCC_TLMM_BCR] = { 0x34000, 0 },
3637
+
[GCC_UBI0_AXI_ARES] = { 0x680},
3638
+
[GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
3639
+
[GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
3640
+
[GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
3641
+
[GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
3642
+
[GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
3643
+
[GCC_UBI32_BCR] = { 0x19064, 0 },
3644
+
[GCC_UNIPHY_BCR] = { 0x56100, 0 },
3645
+
[GCC_UNIPHY_AHB_ARES] = { 0x56104, 0 },
3646
+
[GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },
3647
+
[GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },
3648
+
[GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },
3649
+
[GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 },
3650
+
[GCC_USB0_BCR] = { 0x3e070, 0 },
3651
+
[GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
3652
+
[GCC_WCSS_BCR] = { 0x18000, 0 },
3653
+
[GCC_WCSS_DBG_ARES] = { 0x59008, 0 },
3654
+
[GCC_WCSS_ECAHB_ARES] = { 0x59008, 1 },
3655
+
[GCC_WCSS_ACMT_ARES] = { 0x59008, 2 },
3656
+
[GCC_WCSS_DBG_BDG_ARES] = { 0x59008, 3 },
3657
+
[GCC_WCSS_AHB_S_ARES] = { 0x59008, 4 },
3658
+
[GCC_WCSS_AXI_M_ARES] = { 0x59008, 5 },
3659
+
[GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
3660
+
[GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
3661
+
[GCC_WCSSAON_RESET] = { 0x59010, 0},
3662
+
[GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
3663
+
};
3664
+
3665
+
static const struct of_device_id gcc_ipq5018_match_table[] = {
3666
+
{ .compatible = "qcom,gcc-ipq5018" },
3667
+
{ }
3668
+
};
3669
+
MODULE_DEVICE_TABLE(of, gcc_ipq5018_match_table);
3670
+
3671
+
static const struct regmap_config gcc_ipq5018_regmap_config = {
3672
+
.reg_bits = 32,
3673
+
.reg_stride = 4,
3674
+
.val_bits = 32,
3675
+
.max_register = 0x7fffc,
3676
+
.fast_io = true,
3677
+
};
3678
+
3679
+
static const struct qcom_cc_desc gcc_ipq5018_desc = {
3680
+
.config = &gcc_ipq5018_regmap_config,
3681
+
.clks = gcc_ipq5018_clks,
3682
+
.num_clks = ARRAY_SIZE(gcc_ipq5018_clks),
3683
+
.resets = gcc_ipq5018_resets,
3684
+
.num_resets = ARRAY_SIZE(gcc_ipq5018_resets),
3685
+
.clk_hws = gcc_ipq5018_hws,
3686
+
.num_clk_hws = ARRAY_SIZE(gcc_ipq5018_hws),
3687
+
};
3688
+
3689
+
static int gcc_ipq5018_probe(struct platform_device *pdev)
3690
+
{
3691
+
struct regmap *regmap;
3692
+
struct qcom_cc_desc ipq5018_desc = gcc_ipq5018_desc;
3693
+
3694
+
regmap = qcom_cc_map(pdev, &ipq5018_desc);
3695
+
if (IS_ERR(regmap))
3696
+
return PTR_ERR(regmap);
3697
+
3698
+
clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
3699
+
3700
+
return qcom_cc_really_probe(pdev, &ipq5018_desc, regmap);
3701
+
}
3702
+
3703
+
static struct platform_driver gcc_ipq5018_driver = {
3704
+
.probe = gcc_ipq5018_probe,
3705
+
.driver = {
3706
+
.name = "qcom,gcc-ipq5018",
3707
+
.of_match_table = gcc_ipq5018_match_table,
3708
+
},
3709
+
};
3710
+
3711
+
static int __init gcc_ipq5018_init(void)
3712
+
{
3713
+
return platform_driver_register(&gcc_ipq5018_driver);
3714
+
}
3715
+
core_initcall(gcc_ipq5018_init);
3716
+
3717
+
static void __exit gcc_ipq5018_exit(void)
3718
+
{
3719
+
platform_driver_unregister(&gcc_ipq5018_driver);
3720
+
}
3721
+
module_exit(gcc_ipq5018_exit);
3722
+
3723
+
MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ5018 Driver");
3724
+
MODULE_LICENSE("GPL");