Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pmdomain-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
Pull pmdomain updates from Ulf Hansson:
"pmdomain core:
- Extend statistics for domain idle states with s2idle data
- Show latency/residency for domain idle states in debugfs
pmdomain providers:
- imx: Add support for optional subnodes for imx93-blk-ctrl
- marvell: Add audio power island for Marvell PXA1908
- mediatek:
- Add legacy support for the MT7622 audio power domain
- Add nvmem provider functionality to the mtk-mfg-pmdomain
- Add support for the MT8189 power domains
- qcom: Add support for the Eliza and Hawi power domains
- sunxi: Add support for the Allwinner A733 power domains
- ti: Handle wakeup constraints for out-of-band wakeups for ti_sci"
* tag 'pmdomain-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm: (32 commits)
pmdomain: qcom: rpmhpd: Add power domains for Hawi SoC
dt-bindings: power: qcom,rpmhpd: Add RPMh power domain for Hawi SoC
pmdomain: qcom: cpr: add COMPILE_TEST support
PM: domains: De-constify fields in struct dev_pm_domain_attach_data
pmdomain: qcom: cpr: simplify main allocation
pmdomain: bcm: bcm2835-power: Replace open-coded polling with readl_poll_timeout_atomic()
pmdomain: sunxi: Add support for A733 to Allwinner PCK600 driver
pmdomain: qcom: rpmhpd: Add Eliza RPMh Power Domains
pmdomain: arm: Add print after a successful probe for SCMI power domains
pmdomain: rockchip: quiet regulator error on -EPROBE_DEFER
pmdomain: mediatek: Add power domain driver for MT8189 SoC
pmdomain: mediatek: Add bus protect control flow for MT8189
pmdomain: core: Extend statistics for domain idle states with s2idle data
pmdomain: core: Show latency/residency for domain idle states in debugfs
pmdomain: core: Restructure domain idle states data for genpd in debugfs
pmdomain: qcom: rpmpd: drop stray semicolon
pmdomain: imx: scu-pd: Fix device_node reference leak during ->probe()
pmdomain: ti: omap_prm: Fix a reference leak on device node
pmdomain: mediatek: scpsys: Add MT7622 Audio power domain to legacy driver
pmdomain: mediatek: Simplify with scoped for each OF child loop
...
+932
-104
+16
-1
Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml
+16
-1
Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml
···
20
20
- allwinner,sun20i-d1-ppu
21
21
- allwinner,sun55i-a523-pck-600
22
22
- allwinner,sun55i-a523-ppu
23
+
- allwinner,sun60i-a733-pck-600
23
24
24
25
reg:
25
26
maxItems: 1
···
39
38
- compatible
40
39
- reg
41
40
- clocks
42
-
- resets
43
41
- '#power-domain-cells'
42
+
43
+
allOf:
44
+
- if:
45
+
properties:
46
+
compatible:
47
+
contains:
48
+
enum:
49
+
- allwinner,sun8i-v853-ppu
50
+
- allwinner,sun20i-d1-ppu
51
+
- allwinner,sun55i-a523-pck-600
52
+
- allwinner,sun55i-a523-ppu
53
+
54
+
then:
55
+
required:
56
+
- resets
44
57
45
58
additionalProperties: false
46
59
+13
Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.yaml
+13
Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.yaml
···
74
74
"#clock-cells":
75
75
const: 1
76
76
77
+
"#nvmem-cell-cells":
78
+
const: 0
79
+
77
80
"#power-domain-cells":
78
81
const: 0
82
+
83
+
shader-present:
84
+
type: object
85
+
86
+
dependencies:
87
+
shader-present: [ "#nvmem-cell-cells" ]
79
88
80
89
required:
81
90
- compatible
···
122
113
"ccf", "fast-dvfs";
123
114
memory-region = <&gpueb_shared_memory>;
124
115
#clock-cells = <1>;
116
+
#nvmem-cell-cells = <0>;
125
117
#power-domain-cells = <0>;
118
+
119
+
shader-present {
120
+
};
126
121
};
+1
Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+1
Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+2
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
+2
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
+1
drivers/pmdomain/arm/scmi_pm_domain.c
+1
drivers/pmdomain/arm/scmi_pm_domain.c
+9
-16
drivers/pmdomain/bcm/bcm2835-power.c
+9
-16
drivers/pmdomain/bcm/bcm2835-power.c
···
215
215
{
216
216
struct bcm2835_power *power = pd->power;
217
217
struct device *dev = power->dev;
218
-
u64 start;
219
218
int ret;
220
219
int inrush;
221
220
bool powok;
221
+
u32 val;
222
222
223
223
/* We don't run this on BCM2711 */
224
224
if (power->rpivid_asb)
···
239
239
(inrush << PM_INRUSH_SHIFT) |
240
240
PM_POWUP);
241
241
242
-
start = ktime_get_ns();
243
-
while (!(powok = !!(PM_READ(pm_reg) & PM_POWOK))) {
244
-
cpu_relax();
245
-
if (ktime_get_ns() - start >= 3000)
246
-
break;
247
-
}
242
+
powok = !readl_poll_timeout_atomic(power->base + pm_reg,
243
+
val, val & PM_POWOK, 0, 3);
248
244
}
249
245
if (!powok) {
250
246
dev_err(dev, "Timeout waiting for %s power OK\n",
···
254
258
255
259
/* Repair memory */
256
260
PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_MEMREP);
257
-
start = ktime_get_ns();
258
-
while (!(PM_READ(pm_reg) & PM_MRDONE)) {
259
-
cpu_relax();
260
-
if (ktime_get_ns() - start >= 1000) {
261
-
dev_err(dev, "Timeout waiting for %s memory repair\n",
262
-
pd->base.name);
263
-
ret = -ETIMEDOUT;
264
-
goto err_disable_ispow;
265
-
}
261
+
if (readl_poll_timeout_atomic(power->base + pm_reg, val,
262
+
val & PM_MRDONE, 0, 1)) {
263
+
dev_err(dev, "Timeout waiting for %s memory repair\n",
264
+
pd->base.name);
265
+
ret = -ETIMEDOUT;
266
+
goto err_disable_ispow;
266
267
}
267
268
268
269
/* Disable functional isolation */
+50
-9
drivers/pmdomain/core.c
+50
-9
drivers/pmdomain/core.c
···
1438
1438
return;
1439
1439
} else {
1440
1440
genpd->states[genpd->state_idx].usage++;
1441
+
1442
+
/*
1443
+
* The ->system_power_down_ok() callback is currently used only
1444
+
* for s2idle. Use it to know when to update the usage counter.
1445
+
*/
1446
+
if (genpd->gov && genpd->gov->system_power_down_ok)
1447
+
genpd->states[genpd->state_idx].usage_s2idle++;
1441
1448
}
1442
1449
1443
1450
genpd->status = GENPD_STATE_OFF;
···
3779
3772
if (ret)
3780
3773
return -ERESTARTSYS;
3781
3774
3782
-
seq_puts(s, "State Time Spent(ms) Usage Rejected Above Below\n");
3775
+
seq_puts(s, "State Time(ms) Usage Rejected Above Below S2idle\n");
3783
3776
3784
3777
for (i = 0; i < genpd->state_count; i++) {
3785
3778
struct genpd_power_state *state = &genpd->states[i];
3786
-
char state_name[15];
3779
+
char state_name[7];
3787
3780
3788
3781
idle_time += state->idle_time;
3789
3782
···
3795
3788
}
3796
3789
}
3797
3790
3798
-
if (!state->name)
3799
-
snprintf(state_name, ARRAY_SIZE(state_name), "S%-13d", i);
3800
-
3791
+
snprintf(state_name, ARRAY_SIZE(state_name), "S%-5d", i);
3801
3792
do_div(idle_time, NSEC_PER_MSEC);
3802
-
seq_printf(s, "%-14s %-14llu %-10llu %-10llu %-10llu %llu\n",
3803
-
state->name ?: state_name, idle_time,
3804
-
state->usage, state->rejected, state->above,
3805
-
state->below);
3793
+
seq_printf(s, "%-6s %-14llu %-10llu %-10llu %-10llu %-10llu %llu\n",
3794
+
state_name, idle_time, state->usage, state->rejected,
3795
+
state->above, state->below, state->usage_s2idle);
3796
+
}
3797
+
3798
+
genpd_unlock(genpd);
3799
+
return ret;
3800
+
}
3801
+
3802
+
static int idle_states_desc_show(struct seq_file *s, void *data)
3803
+
{
3804
+
struct generic_pm_domain *genpd = s->private;
3805
+
unsigned int i;
3806
+
int ret = 0;
3807
+
3808
+
ret = genpd_lock_interruptible(genpd);
3809
+
if (ret)
3810
+
return -ERESTARTSYS;
3811
+
3812
+
seq_puts(s, "State Latency(us) Residency(us) Name\n");
3813
+
3814
+
for (i = 0; i < genpd->state_count; i++) {
3815
+
struct genpd_power_state *state = &genpd->states[i];
3816
+
u64 latency, residency;
3817
+
char state_name[7];
3818
+
3819
+
latency = state->power_off_latency_ns +
3820
+
state->power_on_latency_ns;
3821
+
do_div(latency, NSEC_PER_USEC);
3822
+
3823
+
residency = state->residency_ns;
3824
+
do_div(residency, NSEC_PER_USEC);
3825
+
3826
+
snprintf(state_name, ARRAY_SIZE(state_name), "S%-5d", i);
3827
+
seq_printf(s, "%-6s %-12llu %-14llu %s\n",
3828
+
state_name, latency, residency,
3829
+
state->name ?: "N/A");
3806
3830
}
3807
3831
3808
3832
genpd_unlock(genpd);
···
3929
3891
DEFINE_SHOW_ATTRIBUTE(status);
3930
3892
DEFINE_SHOW_ATTRIBUTE(sub_domains);
3931
3893
DEFINE_SHOW_ATTRIBUTE(idle_states);
3894
+
DEFINE_SHOW_ATTRIBUTE(idle_states_desc);
3932
3895
DEFINE_SHOW_ATTRIBUTE(active_time);
3933
3896
DEFINE_SHOW_ATTRIBUTE(total_idle_time);
3934
3897
DEFINE_SHOW_ATTRIBUTE(devices);
···
3950
3911
d, genpd, &sub_domains_fops);
3951
3912
debugfs_create_file("idle_states", 0444,
3952
3913
d, genpd, &idle_states_fops);
3914
+
debugfs_create_file("idle_states_desc", 0444,
3915
+
d, genpd, &idle_states_desc_fops);
3953
3916
debugfs_create_file("active_time", 0444,
3954
3917
d, genpd, &active_time_fops);
3955
3918
debugfs_create_file("total_idle_time", 0444,
+36
-41
drivers/pmdomain/imx/imx93-blk-ctrl.c
+36
-41
drivers/pmdomain/imx/imx93-blk-ctrl.c
···
7
7
#include <linux/device.h>
8
8
#include <linux/module.h>
9
9
#include <linux/of.h>
10
+
#include <linux/of_platform.h>
10
11
#include <linux/platform_device.h>
11
12
#include <linux/pm_domain.h>
12
13
#include <linux/pm_runtime.h>
···
189
188
return 0;
190
189
}
191
190
191
+
static void imx93_release_genpd_provider(void *data)
192
+
{
193
+
struct device_node *of_node = data;
194
+
195
+
of_genpd_del_provider(of_node);
196
+
}
197
+
198
+
static void imx93_release_pm_genpd(void *data)
199
+
{
200
+
struct generic_pm_domain *genpd = data;
201
+
202
+
pm_genpd_remove(genpd);
203
+
}
204
+
192
205
static struct lock_class_key blk_ctrl_genpd_lock_class;
193
206
194
207
static int imx93_blk_ctrl_probe(struct platform_device *pdev)
···
255
240
bc->num_clks = bc_data->num_clks;
256
241
257
242
ret = devm_clk_bulk_get(dev, bc->num_clks, bc->clks);
258
-
if (ret) {
259
-
dev_err_probe(dev, ret, "failed to get bus clock\n");
260
-
return ret;
261
-
}
243
+
if (ret)
244
+
return dev_err_probe(dev, ret, "failed to get bus clock\n");
262
245
263
246
for (i = 0; i < bc_data->num_domains; i++) {
264
247
const struct imx93_blk_ctrl_domain_data *data = &bc_data->domains[i];
···
271
258
domain->clks[j].id = data->clk_names[j];
272
259
273
260
ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);
274
-
if (ret) {
275
-
dev_err_probe(dev, ret, "failed to get clock\n");
276
-
goto cleanup_pds;
277
-
}
261
+
if (ret)
262
+
return dev_err_probe(dev, ret, "failed to get clock\n");
278
263
279
264
domain->genpd.name = data->name;
280
265
domain->genpd.power_on = imx93_blk_ctrl_power_on;
···
280
269
domain->bc = bc;
281
270
282
271
ret = pm_genpd_init(&domain->genpd, NULL, true);
283
-
if (ret) {
284
-
dev_err_probe(dev, ret, "failed to init power domain\n");
285
-
goto cleanup_pds;
286
-
}
272
+
if (ret)
273
+
return dev_err_probe(dev, ret, "failed to init power domain\n");
287
274
275
+
ret = devm_add_action_or_reset(dev, imx93_release_pm_genpd, &domain->genpd);
276
+
if (ret)
277
+
return dev_err_probe(dev, ret, "failed to add pm_genpd release callback\n");
288
278
/*
289
279
* We use runtime PM to trigger power on/off of the upstream GPC
290
280
* domain, as a strict hierarchical parent/child power domain
···
302
290
bc->onecell_data.domains[i] = &domain->genpd;
303
291
}
304
292
305
-
pm_runtime_enable(dev);
293
+
ret = devm_pm_runtime_enable(dev);
294
+
if (ret)
295
+
return dev_err_probe(dev, ret, "failed to enable pm-runtime\n");
306
296
307
297
ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
308
-
if (ret) {
309
-
dev_err_probe(dev, ret, "failed to add power domain provider\n");
310
-
goto cleanup_pds;
311
-
}
298
+
if (ret)
299
+
return dev_err_probe(dev, ret, "failed to add power domain provider\n");
312
300
313
-
dev_set_drvdata(dev, bc);
301
+
ret = devm_add_action_or_reset(dev, imx93_release_genpd_provider, dev->of_node);
302
+
if (ret)
303
+
return dev_err_probe(dev, ret, "failed to add genpd_provider release callback\n");
304
+
305
+
ret = devm_of_platform_populate(dev);
306
+
if (ret)
307
+
return dev_err_probe(dev, ret, "failed to populate blk-ctrl sub-devices\n");
314
308
315
309
return 0;
316
-
317
-
cleanup_pds:
318
-
for (i--; i >= 0; i--)
319
-
pm_genpd_remove(&bc->domains[i].genpd);
320
-
321
-
return ret;
322
-
}
323
-
324
-
static void imx93_blk_ctrl_remove(struct platform_device *pdev)
325
-
{
326
-
struct imx93_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
327
-
int i;
328
-
329
-
of_genpd_del_provider(pdev->dev.of_node);
330
-
331
-
pm_runtime_disable(&pdev->dev);
332
-
333
-
for (i = 0; i < bc->onecell_data.num_domains; i++) {
334
-
struct imx93_blk_ctrl_domain *domain = &bc->domains[i];
335
-
336
-
pm_genpd_remove(&domain->genpd);
337
-
}
338
310
}
339
311
340
312
static const struct imx93_blk_ctrl_domain_data imx93_media_blk_ctl_domain_data[] = {
···
453
457
454
458
static struct platform_driver imx93_blk_ctrl_driver = {
455
459
.probe = imx93_blk_ctrl_probe,
456
-
.remove = imx93_blk_ctrl_remove,
457
460
.driver = {
458
461
.name = "imx93-blk-ctrl",
459
462
.of_match_table = imx93_blk_ctrl_of_match,
+1
drivers/pmdomain/imx/scu-pd.c
+1
drivers/pmdomain/imx/scu-pd.c
+35
-4
drivers/pmdomain/marvell/pxa1908-power-controller.c
+35
-4
drivers/pmdomain/marvell/pxa1908-power-controller.c
···
24
24
#define APMU_DEBUG 0x88
25
25
#define DSI_PHY_DVM_MASK BIT(31)
26
26
27
+
#define APMU_AUDIO_CLK 0x80
28
+
#define AUDIO_ULCX_ENABLE 0x0d
29
+
27
30
#define POWER_ON_LATENCY_US 300
28
31
#define POWER_OFF_LATENCY_US 20
29
32
#define POWER_POLL_TIMEOUT_US (25 * USEC_PER_MSEC)
30
33
#define POWER_POLL_SLEEP_US 6
31
34
32
-
#define NR_DOMAINS 5
35
+
#define NR_DOMAINS 6
33
36
34
37
#define to_pxa1908_pd(_genpd) container_of(_genpd, struct pxa1908_pd, genpd)
35
38
···
62
59
{
63
60
struct pxa1908_pd_ctrl *ctrl = pd->ctrl;
64
61
65
-
return pd->data.id != PXA1908_POWER_DOMAIN_DSI
66
-
? regmap_test_bits(ctrl->base, APMU_PWR_STATUS_REG, pd->data.pwr_state)
67
-
: regmap_test_bits(ctrl->base, APMU_DEBUG, DSI_PHY_DVM_MASK);
62
+
switch (pd->data.id) {
63
+
case PXA1908_POWER_DOMAIN_AUDIO:
64
+
return regmap_test_bits(ctrl->base, APMU_AUDIO_CLK, AUDIO_ULCX_ENABLE);
65
+
case PXA1908_POWER_DOMAIN_DSI:
66
+
return regmap_test_bits(ctrl->base, APMU_DEBUG, DSI_PHY_DVM_MASK);
67
+
default:
68
+
return regmap_test_bits(ctrl->base, APMU_PWR_STATUS_REG, pd->data.pwr_state);
69
+
}
68
70
}
69
71
70
72
static int pxa1908_pd_power_on(struct generic_pm_domain *genpd)
···
131
123
return regmap_clear_bits(ctrl->base, APMU_DEBUG, DSI_PHY_DVM_MASK);
132
124
}
133
125
126
+
static inline int pxa1908_audio_power_on(struct generic_pm_domain *genpd)
127
+
{
128
+
struct pxa1908_pd *pd = to_pxa1908_pd(genpd);
129
+
struct pxa1908_pd_ctrl *ctrl = pd->ctrl;
130
+
131
+
return regmap_set_bits(ctrl->base, APMU_AUDIO_CLK, AUDIO_ULCX_ENABLE);
132
+
}
133
+
134
+
static inline int pxa1908_audio_power_off(struct generic_pm_domain *genpd)
135
+
{
136
+
struct pxa1908_pd *pd = to_pxa1908_pd(genpd);
137
+
struct pxa1908_pd_ctrl *ctrl = pd->ctrl;
138
+
139
+
return regmap_clear_bits(ctrl->base, APMU_AUDIO_CLK, AUDIO_ULCX_ENABLE);
140
+
}
141
+
134
142
#define DOMAIN(_id, _name, ctrl, mode, state) \
135
143
[_id] = { \
136
144
.data = { \
···
181
157
.data = {
182
158
/* See above. */
183
159
.keep_on = true,
160
+
},
161
+
},
162
+
[PXA1908_POWER_DOMAIN_AUDIO] = {
163
+
.genpd = {
164
+
.name = "audio",
165
+
.power_on = pxa1908_audio_power_on,
166
+
.power_off = pxa1908_audio_power_off,
184
167
},
185
168
},
186
169
};
+485
drivers/pmdomain/mediatek/mt8189-pm-domains.h
+485
drivers/pmdomain/mediatek/mt8189-pm-domains.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Author: Qiqi Wang <qiqi.wang@mediatek.com>
5
+
*/
6
+
7
+
#ifndef __SOC_MEDIATEK_MT8189_PM_DOMAINS_H
8
+
#define __SOC_MEDIATEK_MT8189_PM_DOMAINS_H
9
+
10
+
#include "mtk-pm-domains.h"
11
+
#include <dt-bindings/power/mediatek,mt8189-power.h>
12
+
13
+
/*
14
+
* MT8189 power domain support
15
+
*/
16
+
17
+
#define MT8189_SPM_PWR_STATUS 0x0f40
18
+
#define MT8189_SPM_PWR_STATUS_2ND 0x0f44
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+
#define MT8189_SPM_PWR_STATUS_MSB 0x0f48
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+
#define MT8189_SPM_PWR_STATUS_MSB_2ND 0x0f4c
21
+
#define MT8189_SPM_XPU_PWR_STATUS 0x0f50
22
+
#define MT8189_SPM_XPU_PWR_STATUS_2ND 0x0f54
23
+
24
+
#define MT8189_PROT_EN_EMICFG_GALS_SLP_SET 0x0084
25
+
#define MT8189_PROT_EN_EMICFG_GALS_SLP_CLR 0x0088
26
+
#define MT8189_PROT_EN_EMICFG_GALS_SLP_RDY 0x008c
27
+
#define MT8189_PROT_EN_MMSYS_STA_0_SET 0x0c14
28
+
#define MT8189_PROT_EN_MMSYS_STA_0_CLR 0x0c18
29
+
#define MT8189_PROT_EN_MMSYS_STA_0_RDY 0x0c1c
30
+
#define MT8189_PROT_EN_MMSYS_STA_1_SET 0x0c24
31
+
#define MT8189_PROT_EN_MMSYS_STA_1_CLR 0x0c28
32
+
#define MT8189_PROT_EN_MMSYS_STA_1_RDY 0x0c2c
33
+
#define MT8189_PROT_EN_INFRASYS_STA_0_SET 0x0c44
34
+
#define MT8189_PROT_EN_INFRASYS_STA_0_CLR 0x0c48
35
+
#define MT8189_PROT_EN_INFRASYS_STA_0_RDY 0x0c4c
36
+
#define MT8189_PROT_EN_INFRASYS_STA_1_SET 0x0c54
37
+
#define MT8189_PROT_EN_INFRASYS_STA_1_CLR 0x0c58
38
+
#define MT8189_PROT_EN_INFRASYS_STA_1_RDY 0x0c5c
39
+
#define MT8189_PROT_EN_PERISYS_STA_0_SET 0x0c84
40
+
#define MT8189_PROT_EN_PERISYS_STA_0_CLR 0x0c88
41
+
#define MT8189_PROT_EN_PERISYS_STA_0_RDY 0x0c8c
42
+
#define MT8189_PROT_EN_MCU_STA_0_SET 0x0c94
43
+
#define MT8189_PROT_EN_MCU_STA_0_CLR 0x0c98
44
+
#define MT8189_PROT_EN_MCU_STA_0_RDY 0x0c9c
45
+
#define MT8189_PROT_EN_MD_STA_0_SET 0x0ca4
46
+
#define MT8189_PROT_EN_MD_STA_0_CLR 0x0ca8
47
+
#define MT8189_PROT_EN_MD_STA_0_RDY 0x0cac
48
+
49
+
#define MT8189_PROT_EN_EMISYS_STA_0_MM_INFRA (GENMASK(21, 20))
50
+
#define MT8189_PROT_EN_INFRASYS_STA_0_CONN (BIT(8))
51
+
#define MT8189_PROT_EN_INFRASYS_STA_1_CONN (BIT(12))
52
+
#define MT8189_PROT_EN_INFRASYS_STA_0_MM_INFRA (BIT(16))
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+
#define MT8189_PROT_EN_INFRASYS_STA_1_MM_INFRA (BIT(11))
54
+
#define MT8189_PROT_EN_INFRASYS_STA_1_MFG1 (BIT(20))
55
+
#define MT8189_PROT_EN_MCU_STA_0_CONN (BIT(1))
56
+
#define MT8189_PROT_EN_MCU_STA_0_CONN_2ND (BIT(0))
57
+
#define MT8189_PROT_EN_MD_STA_0_MFG1 (BIT(0) | BIT(2))
58
+
#define MT8189_PROT_EN_MD_STA_0_MFG1_2ND (BIT(4))
59
+
#define MT8189_PROT_EN_MM_INFRA_IGN (BIT(1))
60
+
#define MT8189_PROT_EN_MM_INFRA_2_IGN (BIT(0))
61
+
#define MT8189_PROT_EN_MMSYS_STA_0_CAM_MAIN (GENMASK(31, 30))
62
+
#define MT8189_PROT_EN_MMSYS_STA_1_CAM_MAIN (GENMASK(10, 9))
63
+
#define MT8189_PROT_EN_MMSYS_STA_0_DISP (GENMASK(1, 0))
64
+
#define MT8189_PROT_EN_MMSYS_STA_0_ISP_IMG1 (BIT(3))
65
+
#define MT8189_PROT_EN_MMSYS_STA_1_ISP_IMG1 (BIT(7))
66
+
#define MT8189_PROT_EN_MMSYS_STA_0_ISP_IPE (BIT(2))
67
+
#define MT8189_PROT_EN_MMSYS_STA_1_ISP_IPE (BIT(8))
68
+
#define MT8189_PROT_EN_MMSYS_STA_0_MDP0 (BIT(18))
69
+
#define MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA (GENMASK(3, 2))
70
+
#define MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND (GENMASK(15, 7))
71
+
#define MT8189_PROT_EN_MMSYS_STA_0_VDE0 (BIT(20))
72
+
#define MT8189_PROT_EN_MMSYS_STA_1_VDE0 (BIT(13))
73
+
#define MT8189_PROT_EN_MMSYS_STA_0_VEN0 (BIT(12))
74
+
#define MT8189_PROT_EN_MMSYS_STA_1_VEN0 (BIT(12))
75
+
#define MT8189_PROT_EN_PERISYS_STA_0_AUDIO (BIT(6))
76
+
#define MT8189_PROT_EN_PERISYS_STA_0_SSUSB (BIT(7))
77
+
#define MT8189_PROT_EN_EMICFG_GALS_SLP_MFG1 (GENMASK(5, 4))
78
+
79
+
static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8189[] = {
80
+
BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_SMI
81
+
};
82
+
83
+
static const struct scpsys_domain_data scpsys_domain_data_mt8189[] = {
84
+
[MT8189_POWER_DOMAIN_CONN] = {
85
+
.name = "conn",
86
+
.sta_mask = BIT(1),
87
+
.ctl_offs = 0xe04,
88
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
89
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
90
+
.bp_cfg = {
91
+
BUS_PROT_WR_IGN(INFRA,
92
+
MT8189_PROT_EN_MCU_STA_0_CONN,
93
+
MT8189_PROT_EN_MCU_STA_0_SET,
94
+
MT8189_PROT_EN_MCU_STA_0_CLR,
95
+
MT8189_PROT_EN_MCU_STA_0_RDY),
96
+
BUS_PROT_WR_IGN(INFRA,
97
+
MT8189_PROT_EN_INFRASYS_STA_1_CONN,
98
+
MT8189_PROT_EN_INFRASYS_STA_1_SET,
99
+
MT8189_PROT_EN_INFRASYS_STA_1_CLR,
100
+
MT8189_PROT_EN_INFRASYS_STA_1_RDY),
101
+
BUS_PROT_WR_IGN(INFRA,
102
+
MT8189_PROT_EN_MCU_STA_0_CONN_2ND,
103
+
MT8189_PROT_EN_MCU_STA_0_SET,
104
+
MT8189_PROT_EN_MCU_STA_0_CLR,
105
+
MT8189_PROT_EN_MCU_STA_0_RDY),
106
+
BUS_PROT_WR_IGN(INFRA,
107
+
MT8189_PROT_EN_INFRASYS_STA_0_CONN,
108
+
MT8189_PROT_EN_INFRASYS_STA_0_SET,
109
+
MT8189_PROT_EN_INFRASYS_STA_0_CLR,
110
+
MT8189_PROT_EN_INFRASYS_STA_0_RDY),
111
+
},
112
+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
113
+
},
114
+
[MT8189_POWER_DOMAIN_AUDIO] = {
115
+
.name = "audio",
116
+
.sta_mask = BIT(6),
117
+
.ctl_offs = 0xe18,
118
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
119
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
120
+
.sram_pdn_bits = BIT(8),
121
+
.sram_pdn_ack_bits = BIT(12),
122
+
.bp_cfg = {
123
+
BUS_PROT_WR_IGN(INFRA,
124
+
MT8189_PROT_EN_PERISYS_STA_0_AUDIO,
125
+
MT8189_PROT_EN_PERISYS_STA_0_SET,
126
+
MT8189_PROT_EN_PERISYS_STA_0_CLR,
127
+
MT8189_PROT_EN_PERISYS_STA_0_RDY),
128
+
},
129
+
},
130
+
[MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT] = {
131
+
.name = "adsp-top-dormant",
132
+
.sta_mask = BIT(7),
133
+
.ctl_offs = 0xe1c,
134
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
135
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
136
+
.sram_pdn_bits = BIT(9),
137
+
.sram_pdn_ack_bits = BIT(13),
138
+
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_PDN_INVERTED |
139
+
MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF,
140
+
},
141
+
[MT8189_POWER_DOMAIN_ADSP_INFRA] = {
142
+
.name = "adsp-infra",
143
+
.sta_mask = BIT(8),
144
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
145
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
146
+
.ctl_offs = 0xe20,
147
+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
148
+
},
149
+
[MT8189_POWER_DOMAIN_ADSP_AO] = {
150
+
.name = "adsp-ao",
151
+
.sta_mask = BIT(9),
152
+
.ctl_offs = 0xe24,
153
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
154
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
155
+
},
156
+
[MT8189_POWER_DOMAIN_ISP_IMG1] = {
157
+
.name = "isp-img1",
158
+
.sta_mask = BIT(10),
159
+
.ctl_offs = 0xe28,
160
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
161
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
162
+
.sram_pdn_bits = BIT(8),
163
+
.sram_pdn_ack_bits = BIT(12),
164
+
.bp_cfg = {
165
+
BUS_PROT_WR_IGN(INFRA,
166
+
MT8189_PROT_EN_MMSYS_STA_0_ISP_IMG1,
167
+
MT8189_PROT_EN_MMSYS_STA_0_SET,
168
+
MT8189_PROT_EN_MMSYS_STA_0_CLR,
169
+
MT8189_PROT_EN_MMSYS_STA_0_RDY),
170
+
BUS_PROT_WR_IGN(INFRA,
171
+
MT8189_PROT_EN_MMSYS_STA_1_ISP_IMG1,
172
+
MT8189_PROT_EN_MMSYS_STA_1_SET,
173
+
MT8189_PROT_EN_MMSYS_STA_1_CLR,
174
+
MT8189_PROT_EN_MMSYS_STA_1_RDY),
175
+
},
176
+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
177
+
},
178
+
[MT8189_POWER_DOMAIN_ISP_IMG2] = {
179
+
.name = "isp-img2",
180
+
.sta_mask = BIT(11),
181
+
.ctl_offs = 0xe2c,
182
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
183
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
184
+
.sram_pdn_bits = BIT(8),
185
+
.sram_pdn_ack_bits = BIT(12),
186
+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
187
+
},
188
+
[MT8189_POWER_DOMAIN_ISP_IPE] = {
189
+
.name = "isp-ipe",
190
+
.sta_mask = BIT(12),
191
+
.ctl_offs = 0xe30,
192
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
193
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
194
+
.sram_pdn_bits = BIT(8),
195
+
.sram_pdn_ack_bits = BIT(12),
196
+
.bp_cfg = {
197
+
BUS_PROT_WR_IGN(INFRA,
198
+
MT8189_PROT_EN_MMSYS_STA_0_ISP_IPE,
199
+
MT8189_PROT_EN_MMSYS_STA_0_SET,
200
+
MT8189_PROT_EN_MMSYS_STA_0_CLR,
201
+
MT8189_PROT_EN_MMSYS_STA_0_RDY),
202
+
BUS_PROT_WR_IGN(INFRA,
203
+
MT8189_PROT_EN_MMSYS_STA_1_ISP_IPE,
204
+
MT8189_PROT_EN_MMSYS_STA_1_SET,
205
+
MT8189_PROT_EN_MMSYS_STA_1_CLR,
206
+
MT8189_PROT_EN_MMSYS_STA_1_RDY),
207
+
},
208
+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
209
+
},
210
+
[MT8189_POWER_DOMAIN_VDE0] = {
211
+
.name = "vde0",
212
+
.sta_mask = BIT(14),
213
+
.ctl_offs = 0xe38,
214
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
215
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
216
+
.sram_pdn_bits = BIT(8),
217
+
.sram_pdn_ack_bits = BIT(12),
218
+
.bp_cfg = {
219
+
BUS_PROT_WR_IGN(INFRA,
220
+
MT8189_PROT_EN_MMSYS_STA_0_VDE0,
221
+
MT8189_PROT_EN_MMSYS_STA_0_SET,
222
+
MT8189_PROT_EN_MMSYS_STA_0_CLR,
223
+
MT8189_PROT_EN_MMSYS_STA_0_RDY),
224
+
BUS_PROT_WR_IGN(INFRA,
225
+
MT8189_PROT_EN_MMSYS_STA_1_VDE0,
226
+
MT8189_PROT_EN_MMSYS_STA_1_SET,
227
+
MT8189_PROT_EN_MMSYS_STA_1_CLR,
228
+
MT8189_PROT_EN_MMSYS_STA_1_RDY),
229
+
},
230
+
},
231
+
[MT8189_POWER_DOMAIN_VEN0] = {
232
+
.name = "ven0",
233
+
.sta_mask = BIT(16),
234
+
.ctl_offs = 0xe40,
235
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
236
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
237
+
.sram_pdn_bits = BIT(8),
238
+
.sram_pdn_ack_bits = BIT(12),
239
+
.bp_cfg = {
240
+
BUS_PROT_WR_IGN(INFRA,
241
+
MT8189_PROT_EN_MMSYS_STA_0_VEN0,
242
+
MT8189_PROT_EN_MMSYS_STA_0_SET,
243
+
MT8189_PROT_EN_MMSYS_STA_0_CLR,
244
+
MT8189_PROT_EN_MMSYS_STA_0_RDY),
245
+
BUS_PROT_WR_IGN(INFRA,
246
+
MT8189_PROT_EN_MMSYS_STA_1_VEN0,
247
+
MT8189_PROT_EN_MMSYS_STA_1_SET,
248
+
MT8189_PROT_EN_MMSYS_STA_1_CLR,
249
+
MT8189_PROT_EN_MMSYS_STA_1_RDY),
250
+
},
251
+
},
252
+
[MT8189_POWER_DOMAIN_CAM_MAIN] = {
253
+
.name = "cam-main",
254
+
.sta_mask = BIT(18),
255
+
.ctl_offs = 0xe48,
256
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
257
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
258
+
.sram_pdn_bits = BIT(8),
259
+
.sram_pdn_ack_bits = BIT(12),
260
+
.bp_cfg = {
261
+
BUS_PROT_WR_IGN(INFRA,
262
+
MT8189_PROT_EN_MMSYS_STA_0_CAM_MAIN,
263
+
MT8189_PROT_EN_MMSYS_STA_0_SET,
264
+
MT8189_PROT_EN_MMSYS_STA_0_CLR,
265
+
MT8189_PROT_EN_MMSYS_STA_0_RDY),
266
+
BUS_PROT_WR_IGN(INFRA,
267
+
MT8189_PROT_EN_MMSYS_STA_1_CAM_MAIN,
268
+
MT8189_PROT_EN_MMSYS_STA_1_SET,
269
+
MT8189_PROT_EN_MMSYS_STA_1_CLR,
270
+
MT8189_PROT_EN_MMSYS_STA_1_RDY),
271
+
},
272
+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
273
+
},
274
+
[MT8189_POWER_DOMAIN_CAM_SUBA] = {
275
+
.name = "cam-suba",
276
+
.sta_mask = BIT(20),
277
+
.ctl_offs = 0xe50,
278
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
279
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
280
+
.sram_pdn_bits = BIT(8),
281
+
.sram_pdn_ack_bits = BIT(12),
282
+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
283
+
},
284
+
[MT8189_POWER_DOMAIN_CAM_SUBB] = {
285
+
.name = "cam-subb",
286
+
.sta_mask = BIT(21),
287
+
.ctl_offs = 0xe54,
288
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
289
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
290
+
.sram_pdn_bits = BIT(8),
291
+
.sram_pdn_ack_bits = BIT(12),
292
+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
293
+
},
294
+
[MT8189_POWER_DOMAIN_MDP0] = {
295
+
.name = "mdp0",
296
+
.sta_mask = BIT(26),
297
+
.ctl_offs = 0xe68,
298
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
299
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
300
+
.sram_pdn_bits = BIT(8),
301
+
.sram_pdn_ack_bits = BIT(12),
302
+
.bp_cfg = {
303
+
BUS_PROT_WR_IGN(INFRA,
304
+
MT8189_PROT_EN_MMSYS_STA_0_MDP0,
305
+
MT8189_PROT_EN_MMSYS_STA_0_SET,
306
+
MT8189_PROT_EN_MMSYS_STA_0_CLR,
307
+
MT8189_PROT_EN_MMSYS_STA_0_RDY),
308
+
},
309
+
},
310
+
[MT8189_POWER_DOMAIN_DISP] = {
311
+
.name = "disp",
312
+
.sta_mask = BIT(28),
313
+
.ctl_offs = 0xe70,
314
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
315
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
316
+
.sram_pdn_bits = BIT(8),
317
+
.sram_pdn_ack_bits = BIT(12),
318
+
.bp_cfg = {
319
+
BUS_PROT_WR_IGN(INFRA,
320
+
MT8189_PROT_EN_MMSYS_STA_0_DISP,
321
+
MT8189_PROT_EN_MMSYS_STA_0_SET,
322
+
MT8189_PROT_EN_MMSYS_STA_0_CLR,
323
+
MT8189_PROT_EN_MMSYS_STA_0_RDY),
324
+
},
325
+
},
326
+
[MT8189_POWER_DOMAIN_MM_INFRA] = {
327
+
.name = "mm-infra",
328
+
.sta_mask = BIT(30),
329
+
.ctl_offs = 0xe78,
330
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
331
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
332
+
.sram_pdn_bits = BIT(8),
333
+
.sram_pdn_ack_bits = BIT(12),
334
+
.bp_cfg = {
335
+
BUS_PROT_WR_IGN(INFRA,
336
+
MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA,
337
+
MT8189_PROT_EN_MMSYS_STA_1_SET,
338
+
MT8189_PROT_EN_MMSYS_STA_1_CLR,
339
+
MT8189_PROT_EN_MMSYS_STA_1_RDY),
340
+
BUS_PROT_WR_IGN(INFRA,
341
+
MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND,
342
+
MT8189_PROT_EN_MMSYS_STA_1_SET,
343
+
MT8189_PROT_EN_MMSYS_STA_1_CLR,
344
+
MT8189_PROT_EN_MMSYS_STA_1_RDY),
345
+
BUS_PROT_WR_IGN_SUBCLK(INFRA,
346
+
MT8189_PROT_EN_MM_INFRA_IGN,
347
+
MT8189_PROT_EN_MMSYS_STA_1_SET,
348
+
MT8189_PROT_EN_MMSYS_STA_1_CLR,
349
+
MT8189_PROT_EN_MMSYS_STA_1_RDY),
350
+
BUS_PROT_WR_IGN_SUBCLK(INFRA,
351
+
MT8189_PROT_EN_MM_INFRA_2_IGN,
352
+
MT8189_PROT_EN_MMSYS_STA_1_SET,
353
+
MT8189_PROT_EN_MMSYS_STA_1_CLR,
354
+
MT8189_PROT_EN_MMSYS_STA_1_RDY),
355
+
},
356
+
},
357
+
[MT8189_POWER_DOMAIN_DP_TX] = {
358
+
.name = "dp-tx",
359
+
.sta_mask = BIT(0),
360
+
.ctl_offs = 0xe80,
361
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB,
362
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND,
363
+
.sram_pdn_bits = BIT(8),
364
+
.sram_pdn_ack_bits = BIT(12),
365
+
},
366
+
[MT8189_POWER_DOMAIN_CSI_RX] = {
367
+
.name = "csi-rx",
368
+
.sta_mask = BIT(7),
369
+
.ctl_offs = 0xe9c,
370
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB,
371
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND,
372
+
.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
373
+
},
374
+
[MT8189_POWER_DOMAIN_SSUSB] = {
375
+
.name = "ssusb",
376
+
.sta_mask = BIT(10),
377
+
.ctl_offs = 0xea8,
378
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB,
379
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND,
380
+
.sram_pdn_bits = BIT(8),
381
+
.sram_pdn_ack_bits = BIT(12),
382
+
.bp_cfg = {
383
+
BUS_PROT_WR_IGN(INFRA,
384
+
MT8189_PROT_EN_PERISYS_STA_0_SSUSB,
385
+
MT8189_PROT_EN_PERISYS_STA_0_SET,
386
+
MT8189_PROT_EN_PERISYS_STA_0_CLR,
387
+
MT8189_PROT_EN_PERISYS_STA_0_RDY),
388
+
},
389
+
.caps = MTK_SCPD_ACTIVE_WAKEUP,
390
+
},
391
+
[MT8189_POWER_DOMAIN_MFG0] = {
392
+
.name = "mfg0",
393
+
.sta_mask = BIT(1),
394
+
.ctl_offs = 0xeb4,
395
+
.pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS,
396
+
.pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND,
397
+
.caps = MTK_SCPD_DOMAIN_SUPPLY,
398
+
},
399
+
[MT8189_POWER_DOMAIN_MFG1] = {
400
+
.name = "mfg1",
401
+
.sta_mask = BIT(2),
402
+
.ctl_offs = 0xeb8,
403
+
.pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS,
404
+
.pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND,
405
+
.sram_pdn_bits = BIT(8),
406
+
.sram_pdn_ack_bits = BIT(12),
407
+
.bp_cfg = {
408
+
BUS_PROT_WR_IGN(INFRA,
409
+
MT8189_PROT_EN_INFRASYS_STA_1_MFG1,
410
+
MT8189_PROT_EN_INFRASYS_STA_1_SET,
411
+
MT8189_PROT_EN_INFRASYS_STA_1_CLR,
412
+
MT8189_PROT_EN_INFRASYS_STA_1_RDY),
413
+
BUS_PROT_WR_IGN(INFRA,
414
+
MT8189_PROT_EN_MD_STA_0_MFG1,
415
+
MT8189_PROT_EN_MD_STA_0_SET,
416
+
MT8189_PROT_EN_MD_STA_0_CLR,
417
+
MT8189_PROT_EN_MD_STA_0_RDY),
418
+
BUS_PROT_WR_IGN(INFRA,
419
+
MT8189_PROT_EN_MD_STA_0_MFG1_2ND,
420
+
MT8189_PROT_EN_MD_STA_0_SET,
421
+
MT8189_PROT_EN_MD_STA_0_CLR,
422
+
MT8189_PROT_EN_MD_STA_0_RDY),
423
+
BUS_PROT_WR_IGN(SMI,
424
+
MT8189_PROT_EN_EMICFG_GALS_SLP_MFG1,
425
+
MT8189_PROT_EN_EMICFG_GALS_SLP_SET,
426
+
MT8189_PROT_EN_EMICFG_GALS_SLP_CLR,
427
+
MT8189_PROT_EN_EMICFG_GALS_SLP_RDY),
428
+
},
429
+
.caps = MTK_SCPD_DOMAIN_SUPPLY,
430
+
},
431
+
[MT8189_POWER_DOMAIN_MFG2] = {
432
+
.name = "mfg2",
433
+
.sta_mask = BIT(3),
434
+
.ctl_offs = 0xebc,
435
+
.pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS,
436
+
.pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND,
437
+
.sram_pdn_bits = BIT(8),
438
+
.sram_pdn_ack_bits = BIT(12),
439
+
},
440
+
[MT8189_POWER_DOMAIN_MFG3] = {
441
+
.name = "mfg3",
442
+
.sta_mask = BIT(4),
443
+
.ctl_offs = 0xec0,
444
+
.pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS,
445
+
.pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND,
446
+
.sram_pdn_bits = BIT(8),
447
+
.sram_pdn_ack_bits = BIT(12),
448
+
},
449
+
[MT8189_POWER_DOMAIN_EDP_TX_DORMANT] = {
450
+
.name = "edp-tx-dormant",
451
+
.sta_mask = BIT(12),
452
+
.ctl_offs = 0xf70,
453
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB,
454
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND,
455
+
.sram_pdn_bits = BIT(9),
456
+
.sram_pdn_ack_bits = 0,
457
+
.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_PDN_INVERTED,
458
+
},
459
+
[MT8189_POWER_DOMAIN_PCIE] = {
460
+
.name = "pcie",
461
+
.sta_mask = BIT(13),
462
+
.ctl_offs = 0xf74,
463
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB,
464
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND,
465
+
.sram_pdn_bits = BIT(8),
466
+
.sram_pdn_ack_bits = BIT(12),
467
+
.caps = MTK_SCPD_ACTIVE_WAKEUP,
468
+
},
469
+
[MT8189_POWER_DOMAIN_PCIE_PHY] = {
470
+
.name = "pcie-phy",
471
+
.sta_mask = BIT(14),
472
+
.ctl_offs = 0xf78,
473
+
.pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB,
474
+
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND,
475
+
},
476
+
};
477
+
478
+
static const struct scpsys_soc_data mt8189_scpsys_data = {
479
+
.domains_data = scpsys_domain_data_mt8189,
480
+
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8189),
481
+
.bus_prot_blocks = scpsys_bus_prot_blocks_mt8189,
482
+
.num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt8189),
483
+
};
484
+
485
+
#endif /* __SOC_MEDIATEK_MT8189_PM_DOMAINS_H */
+59
drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c
+59
drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c
···
10
10
#include <linux/clk-provider.h>
11
11
#include <linux/container_of.h>
12
12
#include <linux/iopoll.h>
13
+
#include <linux/nvmem-provider.h>
13
14
#include <linux/mailbox_client.h>
14
15
#include <linux/module.h>
15
16
#include <linux/of.h>
···
873
872
return 0;
874
873
}
875
874
875
+
static int mtk_mfg_read_nvmem(void *priv, unsigned int offset, void *val, size_t bytes)
876
+
{
877
+
struct mtk_mfg *mfg = priv;
878
+
u32 *buf = val;
879
+
880
+
if (bytes != 4)
881
+
return -EINVAL;
882
+
883
+
if (!mfg->shared_mem)
884
+
return -ENODEV;
885
+
886
+
if (offset + bytes >= mfg->shared_mem_size)
887
+
return -EINVAL;
888
+
889
+
*buf = readl(mfg->shared_mem + offset);
890
+
891
+
return 0;
892
+
}
893
+
894
+
static int mtk_mfg_init_nvmem_provider(struct mtk_mfg *mfg)
895
+
{
896
+
struct device *dev = &mfg->pdev->dev;
897
+
struct nvmem_cell_info cell = {};
898
+
struct nvmem_config config = {};
899
+
struct nvmem_device *nvdev;
900
+
int ret;
901
+
902
+
config.reg_read = mtk_mfg_read_nvmem;
903
+
config.dev = dev;
904
+
config.read_only = true;
905
+
config.priv = mfg;
906
+
config.size = 4;
907
+
config.word_size = 4;
908
+
909
+
nvdev = devm_nvmem_register(dev, &config);
910
+
if (IS_ERR(nvdev))
911
+
return dev_err_probe(dev, PTR_ERR(nvdev), "Couldn't register nvmem provider\n");
912
+
913
+
cell.name = "shader-present";
914
+
cell.offset = GF_REG_SHADER_PRESENT;
915
+
cell.bytes = 4;
916
+
cell.np = of_get_child_by_name(dev->of_node, cell.name);
917
+
918
+
ret = nvmem_add_one_cell(nvdev, &cell);
919
+
if (ret) {
920
+
of_node_put(cell.np);
921
+
return dev_err_probe(dev, ret, "Couldn't add cell %s\n", cell.name);
922
+
}
923
+
924
+
/* cell.np purposefully not put as nvmem_add_one_cell does not increase refcount */
925
+
926
+
return 0;
927
+
}
928
+
876
929
static int mtk_mfg_probe(struct platform_device *pdev)
877
930
{
878
931
struct mtk_mfg *mfg;
···
1036
981
}
1037
982
1038
983
ret = mtk_mfg_init_clk_provider(mfg);
984
+
if (ret)
985
+
goto err_power_off;
986
+
987
+
ret = mtk_mfg_init_nvmem_provider(mfg);
1039
988
if (ret)
1040
989
goto err_power_off;
1041
990
+33
-11
drivers/pmdomain/mediatek/mtk-pm-domains.c
+33
-11
drivers/pmdomain/mediatek/mtk-pm-domains.c
···
26
26
#include "mt8183-pm-domains.h"
27
27
#include "mt8186-pm-domains.h"
28
28
#include "mt8188-pm-domains.h"
29
+
#include "mt8189-pm-domains.h"
29
30
#include "mt8192-pm-domains.h"
30
31
#include "mt8195-pm-domains.h"
31
32
#include "mt8196-pm-domains.h"
···
251
250
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
252
251
}
253
252
254
-
static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
253
+
static int scpsys_bus_protect_enable(struct scpsys_domain *pd, u8 flags)
255
254
{
256
255
for (int i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
257
256
const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
···
259
258
260
259
if (!bpd->bus_prot_set_clr_mask)
261
260
break;
261
+
262
+
if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) !=
263
+
(flags & BUS_PROT_IGNORE_SUBCLK))
264
+
continue;
262
265
263
266
if (bpd->flags & BUS_PROT_INVERTED)
264
267
ret = scpsys_bus_protect_clear(pd, bpd);
···
275
270
return 0;
276
271
}
277
272
278
-
static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
273
+
static int scpsys_bus_protect_disable(struct scpsys_domain *pd, u8 flags)
279
274
{
280
275
for (int i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
281
276
const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i];
282
277
int ret;
283
278
284
279
if (!bpd->bus_prot_set_clr_mask)
280
+
continue;
281
+
282
+
if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) !=
283
+
(flags & BUS_PROT_IGNORE_SUBCLK))
285
284
continue;
286
285
287
286
if (bpd->flags & BUS_PROT_INVERTED)
···
642
633
goto err_pwr_ack;
643
634
644
635
/*
636
+
* In MT8189 mminfra power domain, the bus protect policy separates
637
+
* into two parts, one is set before subsys clocks enabled, and another
638
+
* need to enable after subsys clocks enable.
639
+
*/
640
+
ret = scpsys_bus_protect_disable(pd, BUS_PROT_IGNORE_SUBCLK);
641
+
if (ret < 0)
642
+
goto err_pwr_ack;
643
+
644
+
/*
645
645
* In few Mediatek platforms(e.g. MT6779), the bus protect policy is
646
646
* stricter, which leads to bus protect release must be prior to bus
647
647
* access.
···
666
648
if (ret < 0)
667
649
goto err_disable_subsys_clks;
668
650
669
-
ret = scpsys_bus_protect_disable(pd);
651
+
ret = scpsys_bus_protect_disable(pd, 0);
670
652
if (ret < 0)
671
653
goto err_disable_sram;
672
654
···
680
662
return 0;
681
663
682
664
err_enable_bus_protect:
683
-
scpsys_bus_protect_enable(pd);
665
+
scpsys_bus_protect_enable(pd, 0);
684
666
err_disable_sram:
685
667
scpsys_sram_disable(pd);
686
668
err_disable_subsys_clks:
···
701
683
bool tmp;
702
684
int ret;
703
685
704
-
ret = scpsys_bus_protect_enable(pd);
686
+
ret = scpsys_bus_protect_enable(pd, 0);
705
687
if (ret < 0)
706
688
return ret;
707
689
···
714
696
pd->data->ext_buck_iso_mask);
715
697
716
698
clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
699
+
700
+
ret = scpsys_bus_protect_enable(pd, BUS_PROT_IGNORE_SUBCLK);
701
+
if (ret < 0)
702
+
return ret;
717
703
718
704
if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_PWRSEQ))
719
705
scpsys_modem_pwrseq_off(pd);
···
1173
1151
.data = &mt8188_scpsys_data,
1174
1152
},
1175
1153
{
1154
+
.compatible = "mediatek,mt8189-power-controller",
1155
+
.data = &mt8189_scpsys_data,
1156
+
},
1157
+
{
1176
1158
.compatible = "mediatek,mt8192-power-controller",
1177
1159
.data = &mt8192_scpsys_data,
1178
1160
},
···
1208
1182
struct device *dev = &pdev->dev;
1209
1183
struct device_node *np = dev->of_node;
1210
1184
const struct scpsys_soc_data *soc;
1211
-
struct device_node *node;
1212
1185
struct device *parent;
1213
1186
struct scpsys *scpsys;
1214
1187
int num_domains, ret;
···
1251
1226
return ret;
1252
1227
1253
1228
ret = -ENODEV;
1254
-
for_each_available_child_of_node(np, node) {
1229
+
for_each_available_child_of_node_scoped(np, node) {
1255
1230
struct generic_pm_domain *domain;
1256
1231
1257
1232
domain = scpsys_add_one_domain(scpsys, node);
1258
1233
if (IS_ERR(domain)) {
1259
1234
ret = PTR_ERR(domain);
1260
-
of_node_put(node);
1261
1235
goto err_cleanup_domains;
1262
1236
}
1263
1237
1264
1238
ret = scpsys_add_subdomain(scpsys, node);
1265
-
if (ret) {
1266
-
of_node_put(node);
1239
+
if (ret)
1267
1240
goto err_cleanup_domains;
1268
-
}
1269
1241
}
1270
1242
1271
1243
if (ret) {
+5
drivers/pmdomain/mediatek/mtk-pm-domains.h
+5
drivers/pmdomain/mediatek/mtk-pm-domains.h
···
56
56
BUS_PROT_REG_UPDATE = BIT(1),
57
57
BUS_PROT_IGNORE_CLR_ACK = BIT(2),
58
58
BUS_PROT_INVERTED = BIT(3),
59
+
BUS_PROT_IGNORE_SUBCLK = BIT(4),
59
60
};
60
61
61
62
enum scpsys_bus_prot_block {
···
95
94
#define BUS_PROT_UPDATE(_hwip, _mask, _set, _clr, _sta) \
96
95
_BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \
97
96
BUS_PROT_REG_UPDATE)
97
+
98
+
#define BUS_PROT_WR_IGN_SUBCLK(_hwip, _mask, _set, _clr, _sta) \
99
+
_BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \
100
+
BUS_PROT_IGNORE_CLR_ACK | BUS_PROT_IGNORE_SUBCLK)
98
101
99
102
#define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \
100
103
BUS_PROT_UPDATE(INFRA, _mask, \
+10
drivers/pmdomain/mediatek/mtk-scpsys.c
+10
drivers/pmdomain/mediatek/mtk-scpsys.c
···
867
867
.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
868
868
.caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
869
869
},
870
+
[MT7622_POWER_DOMAIN_AUDIO] = {
871
+
.name = "audsys",
872
+
.sta_mask = PWR_STATUS_AUDIO,
873
+
.ctl_offs = SPM_AUDIO_PWR_CON,
874
+
.sram_pdn_bits = GENMASK(11, 8),
875
+
.sram_pdn_ack_bits = GENMASK(15, 12),
876
+
.clk_id = {CLK_NONE},
877
+
.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
878
+
.caps = MTK_SCPD_ACTIVE_WAKEUP,
879
+
},
870
880
};
871
881
872
882
/*
+1
-1
drivers/pmdomain/qcom/Kconfig
+1
-1
drivers/pmdomain/qcom/Kconfig
+5
-8
drivers/pmdomain/qcom/cpr.c
+5
-8
drivers/pmdomain/qcom/cpr.c
···
239
239
u32 gcnt;
240
240
unsigned long flags;
241
241
242
-
struct fuse_corner *fuse_corners;
243
242
struct corner *corners;
244
243
245
244
const struct cpr_desc *desc;
···
246
247
const struct cpr_fuse *cpr_fuses;
247
248
248
249
struct dentry *debugfs;
250
+
251
+
struct fuse_corner fuse_corners[];
249
252
};
250
253
251
254
static bool cpr_is_allowed(struct cpr_drv *drv)
···
1601
1600
if (!data || !data->cpr_desc || !data->acc_desc)
1602
1601
return -EINVAL;
1603
1602
1604
-
drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
1603
+
drv = devm_kzalloc(dev,
1604
+
struct_size(drv, fuse_corners, data->cpr_desc->num_fuse_corners),
1605
+
GFP_KERNEL);
1605
1606
if (!drv)
1606
1607
return -ENOMEM;
1607
1608
drv->dev = dev;
1608
1609
drv->desc = data->cpr_desc;
1609
1610
drv->acc_desc = data->acc_desc;
1610
-
1611
-
drv->fuse_corners = devm_kcalloc(dev, drv->desc->num_fuse_corners,
1612
-
sizeof(*drv->fuse_corners),
1613
-
GFP_KERNEL);
1614
-
if (!drv->fuse_corners)
1615
-
return -ENOMEM;
1616
1611
1617
1612
np = of_parse_phandle(dev->of_node, "acc-syscon", 0);
1618
1613
if (!np)
+58
drivers/pmdomain/qcom/rpmhpd.c
+58
drivers/pmdomain/qcom/rpmhpd.c
···
102
102
.res_name = "cx.lvl",
103
103
};
104
104
105
+
static struct rpmhpd dcx = {
106
+
.pd = { .name = "dcx", },
107
+
.res_name = "dcx.lvl",
108
+
};
109
+
105
110
static struct rpmhpd ebi = {
106
111
.pd = { .name = "ebi", },
107
112
.res_name = "ebi.lvl",
113
+
};
114
+
115
+
static struct rpmhpd gbx = {
116
+
.pd = { .name = "gbx", },
117
+
.res_name = "gbx.lvl",
108
118
};
109
119
110
120
static struct rpmhpd gfx = {
···
225
215
static struct rpmhpd gmxc = {
226
216
.pd = { .name = "gmxc", },
227
217
.res_name = "gmxc.lvl",
218
+
};
219
+
220
+
/* Eliza RPMH powerdomains */
221
+
static struct rpmhpd *eliza_rpmhpds[] = {
222
+
[RPMHPD_CX] = &cx,
223
+
[RPMHPD_CX_AO] = &cx_ao,
224
+
[RPMHPD_EBI] = &ebi,
225
+
[RPMHPD_GFX] = &gfx,
226
+
[RPMHPD_LCX] = &lcx,
227
+
[RPMHPD_LMX] = &lmx,
228
+
[RPMHPD_MSS] = &mss,
229
+
[RPMHPD_MX] = &mx,
230
+
[RPMHPD_MX_AO] = &mx_ao,
231
+
[RPMHPD_NSP] = &nsp,
232
+
};
233
+
234
+
static const struct rpmhpd_desc eliza_desc = {
235
+
.rpmhpds = eliza_rpmhpds,
236
+
.num_pds = ARRAY_SIZE(eliza_rpmhpds),
228
237
};
229
238
230
239
/* Milos RPMH powerdomains */
···
651
622
.num_pds = ARRAY_SIZE(kaanapali_rpmhpds),
652
623
};
653
624
625
+
/* Hawi RPMH powerdomains */
626
+
static struct rpmhpd *hawi_rpmhpds[] = {
627
+
[RPMHPD_CX] = &cx,
628
+
[RPMHPD_CX_AO] = &cx_ao,
629
+
[RPMHPD_DCX] = &dcx,
630
+
[RPMHPD_EBI] = &ebi,
631
+
[RPMHPD_GBX] = &gbx,
632
+
[RPMHPD_GFX] = &gfx,
633
+
[RPMHPD_GMXC] = &gmxc,
634
+
[RPMHPD_LCX] = &lcx,
635
+
[RPMHPD_LMX] = &lmx,
636
+
[RPMHPD_MMCX] = &mmcx,
637
+
[RPMHPD_MMCX_AO] = &mmcx_ao,
638
+
[RPMHPD_MX] = &mx,
639
+
[RPMHPD_MX_AO] = &mx_ao,
640
+
[RPMHPD_MXC] = &mxc,
641
+
[RPMHPD_MXC_AO] = &mxc_ao,
642
+
[RPMHPD_MSS] = &mss,
643
+
[RPMHPD_NSP] = &nsp,
644
+
[RPMHPD_NSP2] = &nsp2,
645
+
};
646
+
647
+
static const struct rpmhpd_desc hawi_desc = {
648
+
.rpmhpds = hawi_rpmhpds,
649
+
.num_pds = ARRAY_SIZE(hawi_rpmhpds),
650
+
};
651
+
654
652
/* QDU1000/QRU1000 RPMH powerdomains */
655
653
static struct rpmhpd *qdu1000_rpmhpds[] = {
656
654
[QDU1000_CX] = &cx,
···
851
795
};
852
796
853
797
static const struct of_device_id rpmhpd_match_table[] = {
798
+
{ .compatible = "qcom,eliza-rpmhpd", .data = &eliza_desc },
854
799
{ .compatible = "qcom,glymur-rpmhpd", .data = &glymur_desc },
800
+
{ .compatible = "qcom,hawi-rpmhpd", .data = &hawi_desc },
855
801
{ .compatible = "qcom,kaanapali-rpmhpd", .data = &kaanapali_desc },
856
802
{ .compatible = "qcom,milos-rpmhpd", .data = &milos_desc },
857
803
{ .compatible = "qcom,qcs615-rpmhpd", .data = &qcs615_desc },
+1
-1
drivers/pmdomain/qcom/rpmpd.c
+1
-1
drivers/pmdomain/qcom/rpmpd.c
+3
-4
drivers/pmdomain/rockchip/pm-domains.c
+3
-4
drivers/pmdomain/rockchip/pm-domains.c
···
705
705
int ret;
706
706
707
707
ret = rockchip_pd_regulator_enable(pd);
708
-
if (ret) {
709
-
dev_err(pd->pmu->dev, "Failed to enable supply: %d\n", ret);
710
-
return ret;
711
-
}
708
+
if (ret)
709
+
return dev_err_probe(pd->pmu->dev, ret,
710
+
"Failed to enable supply: %d\n", ret);
712
711
713
712
ret = rockchip_pd_power(pd, true);
714
713
if (ret)
+31
-4
drivers/pmdomain/sunxi/sun55i-pck600.c
+31
-4
drivers/pmdomain/sunxi/sun55i-pck600.c
···
52
52
u32 logic_power_switch0_delay;
53
53
u32 logic_power_switch1_delay;
54
54
u32 off2on_delay;
55
+
bool has_rst_clk;
55
56
};
56
57
57
58
struct sunxi_pck600_pd {
···
152
151
if (IS_ERR(base))
153
152
return PTR_ERR(base);
154
153
155
-
rst = devm_reset_control_get_exclusive_released(dev, NULL);
156
-
if (IS_ERR(rst))
157
-
return dev_err_probe(dev, PTR_ERR(rst), "failed to get reset control\n");
154
+
if (desc->has_rst_clk) {
155
+
rst = devm_reset_control_get_exclusive_released(dev, NULL);
156
+
if (IS_ERR(rst))
157
+
return dev_err_probe(dev, PTR_ERR(rst), "failed to get reset control\n");
158
+
}
158
159
159
160
clk = devm_clk_get_enabled(dev, NULL);
160
161
if (IS_ERR(clk))
···
209
206
.device_ctrl1_delay = 0xffff,
210
207
.logic_power_switch0_delay = 0x8080808,
211
208
.logic_power_switch1_delay = 0x808,
212
-
.off2on_delay = 0x8
209
+
.off2on_delay = 0x8,
210
+
.has_rst_clk = true,
211
+
};
212
+
213
+
static const char * const sun60i_a733_pck600_pd_names[] = {
214
+
"VI", "DE_SYS", "VE_DEC", "VE_ENC", "NPU",
215
+
"GPU_TOP", "GPU_CORE", "PCIE", "USB2", "VO", "VO1"
216
+
};
217
+
218
+
static const struct sunxi_pck600_desc sun60i_a733_pck600_desc = {
219
+
.pd_names = sun60i_a733_pck600_pd_names,
220
+
.num_domains = ARRAY_SIZE(sun60i_a733_pck600_pd_names),
221
+
.logic_power_switch0_delay_offset = 0xc00,
222
+
.logic_power_switch1_delay_offset = 0xc04,
223
+
.off2on_delay_offset = 0xc10,
224
+
.device_ctrl0_delay = 0x1f1f1f,
225
+
.device_ctrl1_delay = 0x1f1f,
226
+
.logic_power_switch0_delay = 0x8080808,
227
+
.logic_power_switch1_delay = 0x808,
228
+
.off2on_delay = 0x8,
229
+
.has_rst_clk = false,
213
230
};
214
231
215
232
static const struct of_device_id sunxi_pck600_of_match[] = {
216
233
{
217
234
.compatible = "allwinner,sun55i-a523-pck-600",
218
235
.data = &sun55i_a523_pck600_desc,
236
+
},
237
+
{
238
+
.compatible = "allwinner,sun60i-a733-pck-600",
239
+
.data = &sun60i_a733_pck600_desc,
219
240
},
220
241
{}
221
242
};
+1
drivers/pmdomain/ti/omap_prm.c
+1
drivers/pmdomain/ti/omap_prm.c
+3
-2
drivers/pmdomain/ti/ti_sci_pm_domains.c
+3
-2
drivers/pmdomain/ti/ti_sci_pm_domains.c
···
91
91
* If device can wakeup using IO daisy chain wakeups,
92
92
* we do not want to set a constraint.
93
93
*/
94
-
if (dev->power.wakeirq) {
95
-
dev_dbg(dev, "%s: has wake IRQ, not setting constraints\n", __func__);
94
+
if (device_out_band_wakeup(dev)) {
95
+
dev_dbg(dev, "%s: has out of band wakeup, not setting constraints\n", \
96
+
__func__);
96
97
return;
97
98
}
98
99
+18
include/dt-bindings/power/allwinner,sun60i-a733-pck-600.h
+18
include/dt-bindings/power/allwinner,sun60i-a733-pck-600.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
3
+
#ifndef _DT_BINDINGS_POWER_SUN60I_A733_PCK600_H_
4
+
#define _DT_BINDINGS_POWER_SUN60I_A733_PCK600_H_
5
+
6
+
#define PD_VI 0
7
+
#define PD_DE_SYS 1
8
+
#define PD_VE_DEC 2
9
+
#define PD_VE_ENC 3
10
+
#define PD_NPU 4
11
+
#define PD_GPU_TOP 5
12
+
#define PD_GPU_CORE 6
13
+
#define PD_PCIE 7
14
+
#define PD_USB2 8
15
+
#define PD_VO 9
16
+
#define PD_VO1 10
17
+
18
+
#endif /* _DT_BINDINGS_POWER_SUN60I_A733_PCK600_H_ */
+1
include/dt-bindings/power/marvell,pxa1908-power.h
+1
include/dt-bindings/power/marvell,pxa1908-power.h
+38
include/dt-bindings/power/mediatek,mt8189-power.h
+38
include/dt-bindings/power/mediatek,mt8189-power.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2025 MediaTek Inc.
4
+
* Author: Qiqi Wang <qiqi.wang@mediatek.com>
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_POWER_MT8189_POWER_H
8
+
#define _DT_BINDINGS_POWER_MT8189_POWER_H
9
+
10
+
/* SPM */
11
+
#define MT8189_POWER_DOMAIN_CONN 0
12
+
#define MT8189_POWER_DOMAIN_AUDIO 1
13
+
#define MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT 2
14
+
#define MT8189_POWER_DOMAIN_ADSP_INFRA 3
15
+
#define MT8189_POWER_DOMAIN_ADSP_AO 4
16
+
#define MT8189_POWER_DOMAIN_MM_INFRA 5
17
+
#define MT8189_POWER_DOMAIN_ISP_IMG1 6
18
+
#define MT8189_POWER_DOMAIN_ISP_IMG2 7
19
+
#define MT8189_POWER_DOMAIN_ISP_IPE 8
20
+
#define MT8189_POWER_DOMAIN_VDE0 9
21
+
#define MT8189_POWER_DOMAIN_VEN0 10
22
+
#define MT8189_POWER_DOMAIN_CAM_MAIN 11
23
+
#define MT8189_POWER_DOMAIN_CAM_SUBA 12
24
+
#define MT8189_POWER_DOMAIN_CAM_SUBB 13
25
+
#define MT8189_POWER_DOMAIN_MDP0 14
26
+
#define MT8189_POWER_DOMAIN_DISP 15
27
+
#define MT8189_POWER_DOMAIN_DP_TX 16
28
+
#define MT8189_POWER_DOMAIN_CSI_RX 17
29
+
#define MT8189_POWER_DOMAIN_SSUSB 18
30
+
#define MT8189_POWER_DOMAIN_MFG0 19
31
+
#define MT8189_POWER_DOMAIN_MFG1 20
32
+
#define MT8189_POWER_DOMAIN_MFG2 21
33
+
#define MT8189_POWER_DOMAIN_MFG3 22
34
+
#define MT8189_POWER_DOMAIN_EDP_TX_DORMANT 23
35
+
#define MT8189_POWER_DOMAIN_PCIE 24
36
+
#define MT8189_POWER_DOMAIN_PCIE_PHY 25
37
+
38
+
#endif /* _DT_BINDINGS_POWER_MT8189_POWER_H */
+1
include/dt-bindings/power/mt7622-power.h
+1
include/dt-bindings/power/mt7622-power.h
+12
include/dt-bindings/power/qcom,rpmhpd.h
+12
include/dt-bindings/power/qcom,rpmhpd.h
···
28
28
#define RPMHPD_XO 18
29
29
#define RPMHPD_NSP2 19
30
30
#define RPMHPD_GMXC 20
31
+
#define RPMHPD_DCX 21
32
+
#define RPMHPD_GBX 22
31
33
32
34
/* RPMh Power Domain performance levels */
33
35
#define RPMH_REGULATOR_LEVEL_RETENTION 16
34
36
#define RPMH_REGULATOR_LEVEL_MIN_SVS 48
37
+
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D3_0 49
35
38
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D3 50
36
39
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1 51
37
40
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52
38
41
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1 54
42
+
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1_0 55
39
43
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56
44
+
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0_0 59
40
45
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60
41
46
#define RPMH_REGULATOR_LEVEL_LOW_SVS 64
42
47
#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72
···
52
47
#define RPMH_REGULATOR_LEVEL_SVS_L0 144
53
48
#define RPMH_REGULATOR_LEVEL_SVS_L1 192
54
49
#define RPMH_REGULATOR_LEVEL_SVS_L2 224
50
+
#define RPMH_REGULATOR_LEVEL_SVS_L2_0 225
55
51
#define RPMH_REGULATOR_LEVEL_NOM 256
56
52
#define RPMH_REGULATOR_LEVEL_NOM_L0 288
57
53
#define RPMH_REGULATOR_LEVEL_NOM_L1 320
···
60
54
#define RPMH_REGULATOR_LEVEL_TURBO 384
61
55
#define RPMH_REGULATOR_LEVEL_TURBO_L0 400
62
56
#define RPMH_REGULATOR_LEVEL_TURBO_L1 416
57
+
#define RPMH_REGULATOR_LEVEL_TURBO_L1_0 417
58
+
#define RPMH_REGULATOR_LEVEL_TURBO_L1_1 418
59
+
#define RPMH_REGULATOR_LEVEL_TURBO_L1_2 419
63
60
#define RPMH_REGULATOR_LEVEL_TURBO_L2 432
64
61
#define RPMH_REGULATOR_LEVEL_TURBO_L3 448
62
+
#define RPMH_REGULATOR_LEVEL_TURBO_L3_0 449
63
+
#define RPMH_REGULATOR_LEVEL_TURBO_L3_1 450
64
+
#define RPMH_REGULATOR_LEVEL_TURBO_L3_2 451
65
65
#define RPMH_REGULATOR_LEVEL_TURBO_L4 452
66
66
#define RPMH_REGULATOR_LEVEL_TURBO_L5 456
67
67
#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464
+3
-2
include/linux/pm_domain.h
+3
-2
include/linux/pm_domain.h
···
49
49
50
50
struct dev_pm_domain_attach_data {
51
51
const char * const *pd_names;
52
-
const u32 num_pd_names;
53
-
const u32 pd_flags;
52
+
u32 num_pd_names;
53
+
u32 pd_flags;
54
54
};
55
55
56
56
struct dev_pm_domain_list {
···
183
183
u64 rejected;
184
184
u64 above;
185
185
u64 below;
186
+
u64 usage_s2idle;
186
187
struct fwnode_handle *fwnode;
187
188
u64 idle_time;
188
189
void *data;