Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/pm: Modify mode2 msg sequence on aldebaran
v1: During mode2 reset, PCI space is lost after message is sent.
Restore PCI space before waiting for response from firmware.
v2: Move mode2 sequence to aldebaran and update PMFW version.
Handle generic sequence in smu13 without PMFW version check.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Lijo Lazar
and committed by
Alex Deucher
e42569d0
e6c6338f
+61
-11
+52
-1
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+52
-1
drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
···
1432
1432
return sizeof(struct gpu_metrics_v1_1);
1433
1433
}
1434
1434
1435
+
int aldebaran_mode2_reset(struct smu_context *smu)
1436
+
{
1437
+
u32 smu_version;
1438
+
int ret = 0, index;
1439
+
struct amdgpu_device *adev = smu->adev;
1440
+
int timeout = 10;
1441
+
1442
+
smu_cmn_get_smc_version(smu, NULL, &smu_version);
1443
+
1444
+
index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1445
+
SMU_MSG_GfxDeviceDriverReset);
1446
+
1447
+
mutex_lock(&smu->message_lock);
1448
+
if (smu_version >= 0x00441400) {
1449
+
ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);
1450
+
/* This is similar to FLR, wait till max FLR timeout */
1451
+
msleep(100);
1452
+
dev_dbg(smu->adev->dev, "restore config space...\n");
1453
+
/* Restore the config space saved during init */
1454
+
amdgpu_device_load_pci_state(adev->pdev);
1455
+
1456
+
dev_dbg(smu->adev->dev, "wait for reset ack\n");
1457
+
while (ret == -ETIME && timeout) {
1458
+
ret = smu_cmn_wait_for_response(smu);
1459
+
/* Wait a bit more time for getting ACK */
1460
+
if (ret == -ETIME) {
1461
+
--timeout;
1462
+
usleep_range(500, 1000);
1463
+
continue;
1464
+
}
1465
+
1466
+
if (ret != 1) {
1467
+
dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n",
1468
+
SMU_RESET_MODE_2, ret);
1469
+
goto out;
1470
+
}
1471
+
}
1472
+
1473
+
} else {
1474
+
dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",
1475
+
smu_version);
1476
+
}
1477
+
1478
+
if (ret == 1)
1479
+
ret = 0;
1480
+
out:
1481
+
mutex_unlock(&smu->message_lock);
1482
+
1483
+
return ret;
1484
+
}
1485
+
1435
1486
static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
1436
1487
{
1437
1488
#if 0
···
1581
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.mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
1582
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.mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
1583
1532
.mode1_reset = smu_v13_0_mode1_reset,
1584
-
.mode2_reset = smu_v13_0_mode2_reset,
1585
1533
.set_mp1_state = aldebaran_set_mp1_state,
1534
+
.mode2_reset = aldebaran_mode2_reset,
1586
1535
};
1587
1536
1588
1537
void aldebaran_set_ppt_funcs(struct smu_context *smu)
+6
-9
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+6
-9
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
···
1376
1376
1377
1377
int smu_v13_0_mode2_reset(struct smu_context *smu)
1378
1378
{
1379
-
u32 smu_version;
1380
-
int ret = 0;
1381
-
struct amdgpu_device *adev = smu->adev;
1382
-
smu_cmn_get_smc_version(smu, NULL, &smu_version);
1383
-
if (smu_version >= 0x00440700)
1384
-
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
1385
-
else
1386
-
dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n", smu_version);
1387
-
/*TODO: mode2 reset wait time should be shorter, will modify it later*/
1379
+
int ret;
1380
+
1381
+
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
1382
+
SMU_RESET_MODE_2, NULL);
1383
+
/*TODO: mode2 reset wait time should be shorter, add ASIC specific func if required */
1388
1384
if (!ret)
1389
1385
msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
1386
+
1390
1387
return ret;
1391
1388
}
1392
1389
+1
-1
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+1
-1
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
···
76
76
*arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
77
77
}
78
78
79
-
static int smu_cmn_wait_for_response(struct smu_context *smu)
79
+
int smu_cmn_wait_for_response(struct smu_context *smu)
80
80
{
81
81
struct amdgpu_device *adev = smu->adev;
82
82
uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
+2
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+2
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h