Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: renesas: r9a09g047: Add clock and reset entries for USB2
Add clock and reset entries for USB2.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251001212709.579080-10-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
authored by
Tommaso Merciai
and committed by
Geert Uytterhoeven
e43b186d
daa5a9bc
+17
-1
+17
-1
drivers/clk/renesas/r9a09g047-cpg.c
+17
-1
drivers/clk/renesas/r9a09g047-cpg.c
···
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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-
LAST_DT_CORE_CLK = R9A09G047_USB3_0_CLKCORE,
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+
LAST_DT_CORE_CLK = R9A09G047_USB2_0_CLK_CORE1,
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/* External Input Clocks */
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CLK_AUDIO_EXTAL,
···
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CDDIV1_DIVCTL3, dtable_1_8),
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DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
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DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
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+
DEF_FIXED("usb2_0_clk_core0", R9A09G047_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
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+
DEF_FIXED("usb2_0_clk_core1", R9A09G047_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
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DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I,
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CLK_PLLETH_DIV_125_FIX, 1, 1),
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DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
···
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BUS_MSTOP(7, BIT(12))),
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DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
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BUS_MSTOP(7, BIT(14))),
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+
DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
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+
BUS_MSTOP(7, BIT(7))),
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+
DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20,
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+
BUS_MSTOP(7, BIT(8))),
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+
DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
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+
BUS_MSTOP(7, BIT(9))),
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+
DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
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+
BUS_MSTOP(7, BIT(10))),
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+
DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
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+
BUS_MSTOP(7, BIT(11))),
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DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
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BUS_MSTOP(8, BIT(5)), 1),
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DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
···
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DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
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DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
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DEF_RST(10, 10, 4, 27), /* USB3_0_ARESETN */
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+
DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
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+
DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
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+
DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
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+
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
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DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
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DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
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DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */