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drm/amd/pm: optimize logic and remove unnecessary checks in smu v15.0.8

the following two sets of logic are clearly mutually exclusive in
smu_v15_0_8_set_soft_freq_limited_range.
remove unnecessary code logic to keep the code logic clear.

e.g:

if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
return -EINVAL;

if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
...
}

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Yang Wang and committed by
Alex Deucher e4465c04 95e21dff

+28 -34
+28 -34
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
··· 1911 1911 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1912 1912 return -EINVAL; 1913 1913 1914 - if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 1915 - if (min >= max) { 1916 - dev_err(smu->adev->dev, 1917 - "Minimum clk should be less than the maximum allowed clock\n"); 1918 - return -EINVAL; 1919 - } 1920 - 1921 - if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK) { 1922 - if ((min == pstate_table->gfxclk_pstate.curr.min) && 1923 - (max == pstate_table->gfxclk_pstate.curr.max)) 1924 - return 0; 1925 - 1926 - ret = smu_v15_0_8_set_gfx_soft_freq_limited_range(smu, 1927 - min, max); 1928 - if (!ret) { 1929 - pstate_table->gfxclk_pstate.curr.min = min; 1930 - pstate_table->gfxclk_pstate.curr.max = max; 1931 - } 1932 - } 1933 - 1934 - if (clk_type == SMU_UCLK) { 1935 - if (max == pstate_table->uclk_pstate.curr.max) 1936 - return 0; 1937 - 1938 - ret = smu_v15_0_set_soft_freq_limited_range(smu, 1939 - SMU_UCLK, 1940 - 0, max, 1941 - false); 1942 - if (!ret) 1943 - pstate_table->uclk_pstate.curr.max = max; 1944 - } 1945 - 1946 - return ret; 1914 + if (min >= max) { 1915 + dev_err(smu->adev->dev, 1916 + "Minimum clk should be less than the maximum allowed clock\n"); 1917 + return -EINVAL; 1947 1918 } 1948 1919 1949 - return 0; 1920 + if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK) { 1921 + if ((min == pstate_table->gfxclk_pstate.curr.min) && 1922 + (max == pstate_table->gfxclk_pstate.curr.max)) 1923 + return 0; 1924 + 1925 + ret = smu_v15_0_8_set_gfx_soft_freq_limited_range(smu, min, 1926 + max); 1927 + if (!ret) { 1928 + pstate_table->gfxclk_pstate.curr.min = min; 1929 + pstate_table->gfxclk_pstate.curr.max = max; 1930 + } 1931 + } 1932 + 1933 + if (clk_type == SMU_UCLK) { 1934 + if (max == pstate_table->uclk_pstate.curr.max) 1935 + return 0; 1936 + 1937 + ret = smu_v15_0_set_soft_freq_limited_range(smu, SMU_UCLK, 0, 1938 + max, false); 1939 + if (!ret) 1940 + pstate_table->uclk_pstate.curr.max = max; 1941 + } 1942 + 1943 + return ret; 1950 1944 } 1951 1945 1952 1946 static int smu_v15_0_8_od_edit_dpm_table(struct smu_context *smu,