Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Here's a set of patches for (hopefully) -rc1. Some of them are fixes,
but a good number of them also do things such as enable new drivers in
the defconfigs for platforms that have such devices, increases
coverage of the multiplatform defconfig and some DTS changes that
plumbs up some of the devices that now have bindings and driver
support.
The commit dates are recent; we've mostly collected these fixes in the
last few days but I also had to rebuild the branch yesterday to sort
out some internal conflicts which reset the timestamps. The changes
should have been tested by each platform maintainer already (and few
of them have cross-platform impact) so I'm personally not too
concerned by it at this time"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (23 commits)
ARM: multi_v7_defconfig: remove redundant entries and re-enable TI_EDMA
ARM: multi_v7_defconfig: add mvebu drivers
clocksource: kona: Add basic use of external clock
drivers: bus: fix CCI driver kcalloc call parameters swap
ARM: dts: bcm28155-ap: Fix Card Detection GPIO
ARM: multi_v7_defconfig: Select CONFIG_AT803X_PHY
ARM: keystone: config: fix build warning when CONFIG_DMADEVICES is not set
MAINTAINERS: ARM: SiRF: use regex patterns to involve all SiRF drivers
ARM: dts: zynq: Add SDHCI nodes
ARM: hisi: don't select SMP
ARM: tegra: rebuild tegra_defconfig to add DEBUG_FS
ARM: multi_v7: copy most options from tegra_defconfig
ARM: iop32x: fix power off handling for the EM7210 board
ARM: integrator: restore static map on the CP
ARM: msm_defconfig: Enable MSM clock drivers
ARM: dts: msm: Add clock controller nodes and hook into uart
ARM: OMAP4+: move errata initialization to omap4_pm_init_early
ARM: OMAP4460: cpuidle: Extend PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD on cpuidle
ARM: mvebu: fix compilation warning on Armada 370 (i.e. non-SMP)
ARM: shmobile: r8a7790.dtsi: ficx i2c[0-3] clock reference
...
+396
-57
+1
-8
MAINTAINERS
+1
-8
MAINTAINERS
···
868
868
F: drivers/clk/clk-prima2.c
869
869
F: drivers/clocksource/timer-prima2.c
870
870
F: drivers/clocksource/timer-marco.c
871
-
F: drivers/dma/sirf-dma.c
872
-
F: drivers/i2c/busses/i2c-sirf.c
873
-
F: drivers/input/misc/sirfsoc-onkey.c
874
-
F: drivers/irqchip/irq-sirfsoc.c
875
-
F: drivers/mmc/host/sdhci-sirf.c
876
-
F: drivers/pinctrl/sirf/
877
-
F: drivers/rtc/rtc-sirfsoc.c
878
-
F: drivers/spi/spi-sirf.c
871
+
N: [^a-z]sirf
879
872
880
873
ARM/EBSA110 MACHINE SUPPORT
881
874
M: Russell King <linux@arm.linux.org.uk>
+3
-1
arch/arm/boot/dts/bcm28155-ap.dts
+3
-1
arch/arm/boot/dts/bcm28155-ap.dts
···
13
13
14
14
/dts-v1/;
15
15
16
+
#include <dt-bindings/gpio/gpio.h>
17
+
16
18
#include "bcm11351.dtsi"
17
19
18
20
/ {
···
62
60
63
61
sdio4: sdio@3f1b0000 {
64
62
max-frequency = <48000000>;
65
-
cd-gpios = <&gpio 14 0>;
63
+
cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
66
64
status = "okay";
67
65
};
68
66
+11
arch/arm/boot/dts/qcom-msm8660-surf.dts
+11
arch/arm/boot/dts/qcom-msm8660-surf.dts
···
2
2
3
3
/include/ "skeleton.dtsi"
4
4
5
+
#include <dt-bindings/clock/qcom,gcc-msm8660.h>
6
+
5
7
/ {
6
8
model = "Qualcomm MSM8660 SURF";
7
9
compatible = "qcom,msm8660-surf", "qcom,msm8660";
···
39
37
#interrupt-cells = <2>;
40
38
};
41
39
40
+
gcc: clock-controller@900000 {
41
+
compatible = "qcom,gcc-msm8660";
42
+
#clock-cells = <1>;
43
+
#reset-cells = <1>;
44
+
reg = <0x900000 0x4000>;
45
+
};
46
+
42
47
serial@19c40000 {
43
48
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
44
49
reg = <0x19c40000 0x1000>,
45
50
<0x19c00000 0x1000>;
46
51
interrupts = <0 195 0x0>;
52
+
clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
53
+
clock-names = "core", "iface";
47
54
};
48
55
49
56
qcom,ssbi@500000 {
+18
arch/arm/boot/dts/qcom-msm8960-cdp.dts
+18
arch/arm/boot/dts/qcom-msm8960-cdp.dts
···
2
2
3
3
/include/ "skeleton.dtsi"
4
4
5
+
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
6
+
5
7
/ {
6
8
model = "Qualcomm MSM8960 CDP";
7
9
compatible = "qcom,msm8960-cdp", "qcom,msm8960";
···
39
37
reg = <0x800000 0x4000>;
40
38
};
41
39
40
+
gcc: clock-controller@900000 {
41
+
compatible = "qcom,gcc-msm8960";
42
+
#clock-cells = <1>;
43
+
#reset-cells = <1>;
44
+
reg = <0x900000 0x4000>;
45
+
};
46
+
47
+
clock-controller@4000000 {
48
+
compatible = "qcom,mmcc-msm8960";
49
+
reg = <0x4000000 0x1000>;
50
+
#clock-cells = <1>;
51
+
#reset-cells = <1>;
52
+
};
53
+
42
54
serial@16440000 {
43
55
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
44
56
reg = <0x16440000 0x1000>,
45
57
<0x16400000 0x1000>;
46
58
interrupts = <0 154 0x0>;
59
+
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
60
+
clock-names = "core", "iface";
47
61
};
48
62
49
63
qcom,ssbi@500000 {
+24
arch/arm/boot/dts/qcom-msm8974.dtsi
+24
arch/arm/boot/dts/qcom-msm8974.dtsi
···
2
2
3
3
#include "skeleton.dtsi"
4
4
5
+
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
6
+
5
7
/ {
6
8
model = "Qualcomm MSM8974";
7
9
compatible = "qcom,msm8974";
···
94
92
restart@fc4ab000 {
95
93
compatible = "qcom,pshold";
96
94
reg = <0xfc4ab000 0x4>;
95
+
};
96
+
97
+
gcc: clock-controller@fc400000 {
98
+
compatible = "qcom,gcc-msm8974";
99
+
#clock-cells = <1>;
100
+
#reset-cells = <1>;
101
+
reg = <0xfc400000 0x4000>;
102
+
};
103
+
104
+
mmcc: clock-controller@fd8c0000 {
105
+
compatible = "qcom,mmcc-msm8974";
106
+
#clock-cells = <1>;
107
+
#reset-cells = <1>;
108
+
reg = <0xfd8c0000 0x6000>;
109
+
};
110
+
111
+
serial@f991e000 {
112
+
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
113
+
reg = <0xf991e000 0x1000>;
114
+
interrupts = <0 108 0x0>;
115
+
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
116
+
clock-names = "core", "iface";
97
117
};
98
118
};
99
119
};
+4
-4
arch/arm/boot/dts/r8a7790.dtsi
+4
-4
arch/arm/boot/dts/r8a7790.dtsi
···
197
197
reg = <0 0xe6508000 0 0x40>;
198
198
interrupt-parent = <&gic>;
199
199
interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
200
-
clocks = <&mstp3_clks R8A7790_CLK_I2C0>;
200
+
clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
201
201
status = "disabled";
202
202
};
203
203
···
208
208
reg = <0 0xe6518000 0 0x40>;
209
209
interrupt-parent = <&gic>;
210
210
interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
211
-
clocks = <&mstp3_clks R8A7790_CLK_I2C1>;
211
+
clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
212
212
status = "disabled";
213
213
};
214
214
···
219
219
reg = <0 0xe6530000 0 0x40>;
220
220
interrupt-parent = <&gic>;
221
221
interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
222
-
clocks = <&mstp3_clks R8A7790_CLK_I2C2>;
222
+
clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
223
223
status = "disabled";
224
224
};
225
225
···
230
230
reg = <0 0xe6540000 0 0x40>;
231
231
interrupt-parent = <&gic>;
232
232
interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
233
-
clocks = <&mstp3_clks R8A7790_CLK_I2C3>;
233
+
clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
234
234
status = "disabled";
235
235
};
236
236
+20
arch/arm/boot/dts/zynq-7000.dtsi
+20
arch/arm/boot/dts/zynq-7000.dtsi
···
102
102
clock-names = "pclk", "hclk", "tx_clk";
103
103
};
104
104
105
+
sdhci0: ps7-sdhci@e0100000 {
106
+
compatible = "arasan,sdhci-8.9a";
107
+
status = "disabled";
108
+
clock-names = "clk_xin", "clk_ahb";
109
+
clocks = <&clkc 21>, <&clkc 32>;
110
+
interrupt-parent = <&intc>;
111
+
interrupts = <0 24 4>;
112
+
reg = <0xe0100000 0x1000>;
113
+
} ;
114
+
115
+
sdhci1: ps7-sdhci@e0101000 {
116
+
compatible = "arasan,sdhci-8.9a";
117
+
status = "disabled";
118
+
clock-names = "clk_xin", "clk_ahb";
119
+
clocks = <&clkc 22>, <&clkc 33>;
120
+
interrupt-parent = <&intc>;
121
+
interrupts = <0 47 4>;
122
+
reg = <0xe0101000 0x1000>;
123
+
} ;
124
+
105
125
slcr: slcr@f8000000 {
106
126
compatible = "xlnx,zynq-slcr";
107
127
reg = <0xF8000000 0x1000>;
+4
arch/arm/boot/dts/zynq-zc702.dts
+4
arch/arm/boot/dts/zynq-zc702.dts
+4
arch/arm/boot/dts/zynq-zc706.dts
+4
arch/arm/boot/dts/zynq-zc706.dts
+4
arch/arm/boot/dts/zynq-zed.dts
+4
arch/arm/boot/dts/zynq-zed.dts
+1
arch/arm/configs/keystone_defconfig
+1
arch/arm/configs/keystone_defconfig
+4
arch/arm/configs/msm_defconfig
+4
arch/arm/configs/msm_defconfig
+144
-10
arch/arm/configs/multi_v7_defconfig
+144
-10
arch/arm/configs/multi_v7_defconfig
···
1
+
CONFIG_SYSVIPC=y
1
2
CONFIG_IRQ_DOMAIN_DEBUG=y
2
3
CONFIG_NO_HZ=y
3
4
CONFIG_HIGH_RES_TIMERS=y
4
5
CONFIG_BLK_DEV_INITRD=y
6
+
CONFIG_EMBEDDED=y
7
+
CONFIG_MODULES=y
8
+
CONFIG_MODULE_UNLOAD=y
9
+
CONFIG_PARTITION_ADVANCED=y
5
10
CONFIG_ARCH_MVEBU=y
6
11
CONFIG_MACH_ARMADA_370=y
7
12
CONFIG_MACH_ARMADA_XP=y
···
43
38
CONFIG_ARCH_TEGRA_2x_SOC=y
44
39
CONFIG_ARCH_TEGRA_3x_SOC=y
45
40
CONFIG_ARCH_TEGRA_114_SOC=y
46
-
CONFIG_TEGRA_PCI=y
41
+
CONFIG_ARCH_TEGRA_124_SOC=y
47
42
CONFIG_TEGRA_EMC_SCALING_ENABLE=y
48
43
CONFIG_ARCH_U8500=y
49
44
CONFIG_MACH_HREFV60=y
···
54
49
CONFIG_ARCH_VIRT=y
55
50
CONFIG_ARCH_WM8850=y
56
51
CONFIG_ARCH_ZYNQ=y
52
+
CONFIG_TRUSTED_FOUNDATIONS=y
53
+
CONFIG_PCI=y
54
+
CONFIG_PCI_MSI=y
55
+
CONFIG_PCI_MVEBU=y
56
+
CONFIG_PCI_TEGRA=y
57
57
CONFIG_SMP=y
58
58
CONFIG_HIGHPTE=y
59
+
CONFIG_CMA=y
59
60
CONFIG_ARM_APPENDED_DTB=y
60
61
CONFIG_ARM_ATAG_DTB_COMPAT=y
62
+
CONFIG_KEXEC=y
63
+
CONFIG_CPU_FREQ=y
64
+
CONFIG_CPU_FREQ_STAT_DETAILS=y
65
+
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
66
+
CONFIG_CPU_IDLE=y
61
67
CONFIG_NET=y
68
+
CONFIG_PACKET=y
62
69
CONFIG_UNIX=y
63
70
CONFIG_INET=y
64
71
CONFIG_IP_PNP=y
65
72
CONFIG_IP_PNP_DHCP=y
73
+
CONFIG_IP_PNP_BOOTP=y
74
+
CONFIG_IP_PNP_RARP=y
75
+
CONFIG_IPV6_ROUTER_PREF=y
76
+
CONFIG_IPV6_OPTIMISTIC_DAD=y
77
+
CONFIG_INET6_AH=m
78
+
CONFIG_INET6_ESP=m
79
+
CONFIG_INET6_IPCOMP=m
80
+
CONFIG_IPV6_MIP6=m
81
+
CONFIG_IPV6_TUNNEL=m
82
+
CONFIG_IPV6_MULTIPLE_TABLES=y
83
+
CONFIG_CFG80211=m
84
+
CONFIG_MAC80211=m
85
+
CONFIG_RFKILL=y
86
+
CONFIG_RFKILL_INPUT=y
87
+
CONFIG_RFKILL_GPIO=y
66
88
CONFIG_DEVTMPFS=y
67
89
CONFIG_DEVTMPFS_MOUNT=y
90
+
CONFIG_DMA_CMA=y
68
91
CONFIG_OMAP_OCP2SCP=y
92
+
CONFIG_MTD=y
93
+
CONFIG_MTD_M25P80=y
94
+
CONFIG_BLK_DEV_LOOP=y
95
+
CONFIG_ICS932S401=y
96
+
CONFIG_APDS9802ALS=y
97
+
CONFIG_ISL29003=y
69
98
CONFIG_BLK_DEV_SD=y
99
+
CONFIG_BLK_DEV_SR=y
100
+
CONFIG_SCSI_MULTI_LUN=y
70
101
CONFIG_ATA=y
71
102
CONFIG_SATA_AHCI_PLATFORM=y
72
103
CONFIG_SATA_HIGHBANK=y
···
110
69
CONFIG_NETDEVICES=y
111
70
CONFIG_SUN4I_EMAC=y
112
71
CONFIG_NET_CALXEDA_XGMAC=y
72
+
CONFIG_MVNETA=y
113
73
CONFIG_KS8851=y
74
+
CONFIG_R8169=y
114
75
CONFIG_SMSC911X=y
115
76
CONFIG_STMMAC_ETH=y
116
-
CONFIG_ICPLUS_PHY=y
117
-
CONFIG_MDIO_SUN4I=y
118
77
CONFIG_TI_CPSW=y
78
+
CONFIG_AT803X_PHY=y
79
+
CONFIG_MARVELL_PHY=y
80
+
CONFIG_ICPLUS_PHY=y
81
+
CONFIG_USB_PEGASUS=y
82
+
CONFIG_USB_USBNET=y
83
+
CONFIG_USB_NET_SMSC75XX=y
84
+
CONFIG_USB_NET_SMSC95XX=y
85
+
CONFIG_BRCMFMAC=m
86
+
CONFIG_RT2X00=m
87
+
CONFIG_RT2800USB=m
88
+
CONFIG_INPUT_EVDEV=y
89
+
CONFIG_KEYBOARD_GPIO=y
90
+
CONFIG_KEYBOARD_TEGRA=y
119
91
CONFIG_KEYBOARD_SPEAR=y
92
+
CONFIG_KEYBOARD_CROS_EC=y
93
+
CONFIG_MOUSE_PS2_ELANTECH=y
94
+
CONFIG_INPUT_MISC=y
95
+
CONFIG_INPUT_MPU3050=y
120
96
CONFIG_SERIO_AMBAKMI=y
121
97
CONFIG_SERIAL_8250=y
122
98
CONFIG_SERIAL_8250_CONSOLE=y
···
156
98
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
157
99
CONFIG_SERIAL_ST_ASC=y
158
100
CONFIG_SERIAL_ST_ASC_CONSOLE=y
101
+
CONFIG_I2C_CHARDEV=y
102
+
CONFIG_I2C_MUX=y
103
+
CONFIG_I2C_MUX_PINCTRL=y
159
104
CONFIG_I2C_DESIGNWARE_PLATFORM=y
105
+
CONFIG_I2C_MV64XXX=y
160
106
CONFIG_I2C_SIRF=y
161
107
CONFIG_I2C_TEGRA=y
162
108
CONFIG_SPI=y
163
109
CONFIG_SPI_OMAP24XX=y
110
+
CONFIG_SPI_ORION=y
164
111
CONFIG_SPI_PL022=y
165
112
CONFIG_SPI_SIRF=y
166
113
CONFIG_SPI_TEGRA114=y
114
+
CONFIG_SPI_TEGRA20_SFLASH=y
167
115
CONFIG_SPI_TEGRA20_SLINK=y
168
-
CONFIG_PINCTRL_SINGLE=y
116
+
CONFIG_PINCTRL_AS3722=y
117
+
CONFIG_PINCTRL_PALMAS=y
118
+
CONFIG_GPIO_SYSFS=y
169
119
CONFIG_GPIO_GENERIC_PLATFORM=y
120
+
CONFIG_GPIO_PCA953X_IRQ=y
170
121
CONFIG_GPIO_TWL4030=y
171
-
CONFIG_REGULATOR_GPIO=y
122
+
CONFIG_GPIO_PALMAS=y
123
+
CONFIG_GPIO_TPS6586X=y
124
+
CONFIG_GPIO_TPS65910=y
125
+
CONFIG_BATTERY_SBS=y
126
+
CONFIG_CHARGER_TPS65090=y
127
+
CONFIG_POWER_RESET_AS3722=y
128
+
CONFIG_POWER_RESET_GPIO=y
129
+
CONFIG_SENSORS_LM90=y
130
+
CONFIG_THERMAL=y
131
+
CONFIG_ARMADA_THERMAL=y
132
+
CONFIG_MFD_AS3722=y
133
+
CONFIG_MFD_CROS_EC=y
134
+
CONFIG_MFD_CROS_EC_SPI=y
135
+
CONFIG_MFD_MAX8907=y
136
+
CONFIG_MFD_PALMAS=y
137
+
CONFIG_MFD_TPS65090=y
138
+
CONFIG_MFD_TPS6586X=y
139
+
CONFIG_MFD_TPS65910=y
140
+
CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
172
141
CONFIG_REGULATOR_AB8500=y
142
+
CONFIG_REGULATOR_AS3722=y
143
+
CONFIG_REGULATOR_GPIO=y
144
+
CONFIG_REGULATOR_MAX8907=y
145
+
CONFIG_REGULATOR_PALMAS=y
173
146
CONFIG_REGULATOR_TPS51632=y
174
147
CONFIG_REGULATOR_TPS62360=y
148
+
CONFIG_REGULATOR_TPS65090=y
149
+
CONFIG_REGULATOR_TPS6586X=y
150
+
CONFIG_REGULATOR_TPS65910=y
175
151
CONFIG_REGULATOR_TWL4030=y
176
152
CONFIG_REGULATOR_VEXPRESS=y
153
+
CONFIG_MEDIA_SUPPORT=y
154
+
CONFIG_MEDIA_CAMERA_SUPPORT=y
155
+
CONFIG_MEDIA_USB_SUPPORT=y
177
156
CONFIG_DRM=y
178
-
CONFIG_TEGRA_HOST1X=y
179
157
CONFIG_DRM_TEGRA=y
158
+
CONFIG_DRM_PANEL_SIMPLE=y
180
159
CONFIG_FB_ARMCLCD=y
181
160
CONFIG_FB_WM8505=y
182
161
CONFIG_FB_SIMPLE=y
162
+
CONFIG_BACKLIGHT_LCD_SUPPORT=y
163
+
CONFIG_BACKLIGHT_CLASS_DEVICE=y
164
+
CONFIG_BACKLIGHT_PWM=y
165
+
CONFIG_FRAMEBUFFER_CONSOLE=y
166
+
CONFIG_SOUND=y
167
+
CONFIG_SND=y
168
+
CONFIG_SND_SOC=y
169
+
CONFIG_SND_SOC_TEGRA=y
170
+
CONFIG_SND_SOC_TEGRA_RT5640=y
171
+
CONFIG_SND_SOC_TEGRA_WM8753=y
172
+
CONFIG_SND_SOC_TEGRA_WM8903=y
173
+
CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
174
+
CONFIG_SND_SOC_TEGRA_ALC5632=y
175
+
CONFIG_SND_SOC_TEGRA_MAX98090=y
183
176
CONFIG_USB=y
184
177
CONFIG_USB_XHCI_HCD=y
185
178
CONFIG_USB_EHCI_HCD=y
···
241
132
CONFIG_USB_CHIPIDEA=y
242
133
CONFIG_USB_CHIPIDEA_HOST=y
243
134
CONFIG_AB8500_USB=y
244
-
CONFIG_NOP_USB_XCEIV=y
245
-
CONFIG_OMAP_USB2=y
246
135
CONFIG_OMAP_USB3=y
247
136
CONFIG_SAMSUNG_USB2PHY=y
248
137
CONFIG_SAMSUNG_USB3PHY=y
···
251
144
CONFIG_MMC_BLOCK_MINORS=16
252
145
CONFIG_MMC_ARMMMCI=y
253
146
CONFIG_MMC_SDHCI=y
254
-
CONFIG_MMC_SDHCI_PLTFM=y
255
147
CONFIG_MMC_SDHCI_ESDHC_IMX=y
256
148
CONFIG_MMC_SDHCI_TEGRA=y
257
149
CONFIG_MMC_SDHCI_SPEAR=y
258
150
CONFIG_MMC_SDHCI_BCM_KONA=y
259
151
CONFIG_MMC_OMAP=y
260
152
CONFIG_MMC_OMAP_HS=y
153
+
CONFIG_MMC_MVSDIO=y
261
154
CONFIG_EDAC=y
262
155
CONFIG_EDAC_MM_EDAC=y
263
156
CONFIG_EDAC_HIGHBANK_MC=y
264
157
CONFIG_EDAC_HIGHBANK_L2=y
265
158
CONFIG_RTC_CLASS=y
159
+
CONFIG_RTC_DRV_AS3722=y
160
+
CONFIG_RTC_DRV_MAX8907=y
161
+
CONFIG_RTC_DRV_PALMAS=y
266
162
CONFIG_RTC_DRV_TWL4030=y
163
+
CONFIG_RTC_DRV_TPS6586X=y
164
+
CONFIG_RTC_DRV_TPS65910=y
165
+
CONFIG_RTC_DRV_EM3027=y
267
166
CONFIG_RTC_DRV_PL031=y
268
167
CONFIG_RTC_DRV_VT8500=y
168
+
CONFIG_RTC_DRV_MV=y
269
169
CONFIG_RTC_DRV_TEGRA=y
270
170
CONFIG_DMADEVICES=y
271
171
CONFIG_DW_DMAC=y
172
+
CONFIG_MV_XOR=y
272
173
CONFIG_TEGRA20_APB_DMA=y
273
174
CONFIG_STE_DMA40=y
274
175
CONFIG_SIRF_DMA=y
···
286
171
CONFIG_IMX_DMA=y
287
172
CONFIG_MXS_DMA=y
288
173
CONFIG_DMA_OMAP=y
174
+
CONFIG_STAGING=y
175
+
CONFIG_SENSORS_ISL29018=y
176
+
CONFIG_SENSORS_ISL29028=y
177
+
CONFIG_MFD_NVEC=y
178
+
CONFIG_KEYBOARD_NVEC=y
179
+
CONFIG_SERIO_NVEC_PS2=y
180
+
CONFIG_NVEC_POWER=y
181
+
CONFIG_TEGRA_IOMMU_GART=y
182
+
CONFIG_TEGRA_IOMMU_SMMU=y
183
+
CONFIG_MEMORY=y
184
+
CONFIG_IIO=y
185
+
CONFIG_AK8975=y
289
186
CONFIG_PWM=y
187
+
CONFIG_PWM_TEGRA=y
290
188
CONFIG_PWM_VT8500=y
189
+
CONFIG_OMAP_USB2=y
291
190
CONFIG_EXT4_FS=y
191
+
CONFIG_VFAT_FS=y
292
192
CONFIG_TMPFS=y
193
+
CONFIG_SQUASHFS=y
194
+
CONFIG_SQUASHFS_LZO=y
195
+
CONFIG_SQUASHFS_XZ=y
293
196
CONFIG_NFS_FS=y
294
197
CONFIG_NFS_V3_ACL=y
295
198
CONFIG_NFS_V4=y
296
199
CONFIG_ROOT_NFS=y
297
200
CONFIG_PRINTK_TIME=y
298
201
CONFIG_DEBUG_FS=y
299
-
CONFIG_DEBUG_KERNEL=y
202
+
CONFIG_MAGIC_SYSRQ=y
300
203
CONFIG_LOCKUP_DETECTOR=y
204
+
CONFIG_CRYPTO_DEV_TEGRA_AES=y
+3
-8
arch/arm/configs/tegra_defconfig
+3
-8
arch/arm/configs/tegra_defconfig
···
29
29
CONFIG_ARCH_TEGRA_114_SOC=y
30
30
CONFIG_ARCH_TEGRA_124_SOC=y
31
31
CONFIG_TEGRA_EMC_SCALING_ENABLE=y
32
+
CONFIG_TRUSTED_FOUNDATIONS=y
32
33
CONFIG_PCI=y
33
34
CONFIG_PCI_MSI=y
34
35
CONFIG_PCI_TEGRA=y
35
36
CONFIG_PCIEPORTBUS=y
36
-
CONFIG_TRUSTED_FOUNDATIONS=y
37
37
CONFIG_SMP=y
38
38
CONFIG_PREEMPT=y
39
39
CONFIG_AEABI=y
···
125
125
CONFIG_SERIAL_OF_PLATFORM=y
126
126
# CONFIG_HW_RANDOM is not set
127
127
# CONFIG_I2C_COMPAT is not set
128
-
CONFIG_I2C_MUX=y
129
128
CONFIG_I2C_MUX_PINCTRL=y
130
129
CONFIG_I2C_TEGRA=y
131
130
CONFIG_SPI=y
···
168
169
CONFIG_MEDIA_USB_SUPPORT=y
169
170
CONFIG_USB_VIDEO_CLASS=m
170
171
CONFIG_DRM=y
171
-
CONFIG_DRM_PANEL=y
172
-
CONFIG_DRM_PANEL_SIMPLE=y
173
172
CONFIG_DRM_TEGRA=y
173
+
CONFIG_DRM_PANEL_SIMPLE=y
174
174
CONFIG_BACKLIGHT_LCD_SUPPORT=y
175
175
# CONFIG_LCD_CLASS_DEVICE is not set
176
176
CONFIG_BACKLIGHT_CLASS_DEVICE=y
···
204
206
CONFIG_MMC_SDHCI=y
205
207
CONFIG_MMC_SDHCI_PLTFM=y
206
208
CONFIG_MMC_SDHCI_TEGRA=y
207
-
CONFIG_NEW_LEDS=y
208
-
CONFIG_LEDS_CLASS=y
209
209
CONFIG_LEDS_GPIO=y
210
-
CONFIG_LEDS_TRIGGERS=y
211
210
CONFIG_LEDS_TRIGGER_TIMER=y
212
211
CONFIG_LEDS_TRIGGER_ONESHOT=y
213
212
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
···
230
235
CONFIG_SERIO_NVEC_PS2=y
231
236
CONFIG_NVEC_POWER=y
232
237
CONFIG_NVEC_PAZ00=y
233
-
CONFIG_COMMON_CLK_DEBUG=y
234
238
CONFIG_TEGRA_IOMMU_GART=y
235
239
CONFIG_TEGRA_IOMMU_SMMU=y
236
240
CONFIG_MEMORY=y
···
259
265
CONFIG_NLS_ISO8859_1=y
260
266
CONFIG_PRINTK_TIME=y
261
267
CONFIG_DEBUG_INFO=y
268
+
CONFIG_DEBUG_FS=y
262
269
CONFIG_MAGIC_SYSRQ=y
263
270
CONFIG_DEBUG_SLAB=y
264
271
CONFIG_DEBUG_VM=y
-1
arch/arm/mach-hisi/Kconfig
-1
arch/arm/mach-hisi/Kconfig
+6
arch/arm/mach-integrator/integrator_cp.c
+6
arch/arm/mach-integrator/integrator_cp.c
···
64
64
65
65
/*
66
66
* Logical Physical
67
+
* f1000000 10000000 Core module registers
67
68
* f1300000 13000000 Counter/Timer
68
69
* f1400000 14000000 Interrupt controller
69
70
* f1600000 16000000 UART 0
···
76
75
77
76
static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
78
77
{
78
+
.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
79
+
.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
80
+
.length = SZ_4K,
81
+
.type = MT_DEVICE
82
+
}, {
79
83
.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
80
84
.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
81
85
.length = SZ_4K,
+27
-5
arch/arm/mach-iop32x/em7210.c
+27
-5
arch/arm/mach-iop32x/em7210.c
···
23
23
#include <linux/mtd/physmap.h>
24
24
#include <linux/platform_device.h>
25
25
#include <linux/i2c.h>
26
+
#include <linux/gpio.h>
26
27
#include <mach/hardware.h>
27
28
#include <linux/io.h>
28
29
#include <linux/irq.h>
···
177
176
.resource = &em7210_uart_resource,
178
177
};
179
178
179
+
#define EM7210_HARDWARE_POWER 0
180
+
180
181
void em7210_power_off(void)
181
182
{
182
-
*IOP3XX_GPOE &= 0xfe;
183
-
*IOP3XX_GPOD |= 0x01;
183
+
int ret;
184
+
185
+
ret = gpio_direction_output(EM7210_HARDWARE_POWER, 1);
186
+
if (ret)
187
+
pr_crit("could not drive power off GPIO high\n");
184
188
}
189
+
190
+
static int __init em7210_request_gpios(void)
191
+
{
192
+
int ret;
193
+
194
+
if (!machine_is_em7210())
195
+
return 0;
196
+
197
+
ret = gpio_request(EM7210_HARDWARE_POWER, "power");
198
+
if (ret) {
199
+
pr_err("could not request power off GPIO\n");
200
+
return 0;
201
+
}
202
+
203
+
pm_power_off = em7210_power_off;
204
+
205
+
return 0;
206
+
}
207
+
device_initcall(em7210_request_gpios);
185
208
186
209
static void __init em7210_init_machine(void)
187
210
{
···
219
194
220
195
i2c_register_board_info(0, em7210_i2c_devices,
221
196
ARRAY_SIZE(em7210_i2c_devices));
222
-
223
-
224
-
pm_power_off = em7210_power_off;
225
197
}
226
198
227
199
MACHINE_START(EM7210, "Lanner EM7210")
-1
arch/arm/mach-keystone/Kconfig
-1
arch/arm/mach-keystone/Kconfig
+2
-2
arch/arm/mach-kirkwood/pm.c
+2
-2
arch/arm/mach-kirkwood/pm.c
···
18
18
#include <linux/suspend.h>
19
19
#include <linux/io.h>
20
20
#include <mach/bridge-regs.h>
21
+
#include "common.h"
21
22
22
23
static void __iomem *ddr_operation_base;
23
24
···
66
65
.valid = kirkwood_pm_valid_standby,
67
66
};
68
67
69
-
int __init kirkwood_pm_init(void)
68
+
void __init kirkwood_pm_init(void)
70
69
{
71
70
ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4);
72
71
suspend_set_ops(&kirkwood_suspend_ops);
73
-
return 0;
74
72
}
+1
-1
arch/arm/mach-mvebu/mvebu-soc-id.c
+1
-1
arch/arm/mach-mvebu/mvebu-soc-id.c
+7
arch/arm/mach-omap2/common.h
+7
arch/arm/mach-omap2/common.h
···
62
62
63
63
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
64
64
int omap4_pm_init(void);
65
+
int omap4_pm_init_early(void);
65
66
#else
66
67
static inline int omap4_pm_init(void)
68
+
{
69
+
return 0;
70
+
}
71
+
72
+
static inline int omap4_pm_init_early(void)
67
73
{
68
74
return 0;
69
75
}
···
242
236
243
237
extern void __init gic_init_irq(void);
244
238
extern void gic_dist_disable(void);
239
+
extern void gic_dist_enable(void);
245
240
extern bool gic_dist_disabled(void);
246
241
extern void gic_timer_retrigger(void);
247
242
extern void omap_smc1(u32 fn, u32 arg);
+21
-5
arch/arm/mach-omap2/cpuidle44xx.c
+21
-5
arch/arm/mach-omap2/cpuidle44xx.c
···
80
80
int index)
81
81
{
82
82
struct idle_statedata *cx = state_ptr + index;
83
+
u32 mpuss_can_lose_context = 0;
83
84
84
85
/*
85
86
* CPU0 has to wait and stay ON until CPU1 is OFF state.
···
105
104
}
106
105
}
107
106
107
+
mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&
108
+
(cx->mpu_logic_state == PWRDM_POWER_OFF);
109
+
108
110
/*
109
111
* Call idle CPU PM enter notifier chain so that
110
112
* VFP and per CPU interrupt context is saved.
···
122
118
* Call idle CPU cluster PM enter notifier chain
123
119
* to save GIC and wakeupgen context.
124
120
*/
125
-
if ((cx->mpu_state == PWRDM_POWER_RET) &&
126
-
(cx->mpu_logic_state == PWRDM_POWER_OFF))
127
-
cpu_cluster_pm_enter();
121
+
if (mpuss_can_lose_context)
122
+
cpu_cluster_pm_enter();
128
123
}
129
124
130
125
omap4_enter_lowpower(dev->cpu, cx->cpu_state);
···
131
128
132
129
/* Wakeup CPU1 only if it is not offlined */
133
130
if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
131
+
132
+
if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
133
+
mpuss_can_lose_context)
134
+
gic_dist_disable();
135
+
134
136
clkdm_wakeup(cpu_clkdm[1]);
135
137
omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON);
136
138
clkdm_allow_idle(cpu_clkdm[1]);
139
+
140
+
if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
141
+
mpuss_can_lose_context) {
142
+
while (gic_dist_disabled()) {
143
+
udelay(1);
144
+
cpu_relax();
145
+
}
146
+
gic_timer_retrigger();
147
+
}
137
148
}
138
149
139
150
/*
···
160
143
* Call idle CPU cluster PM exit notifier chain
161
144
* to restore GIC and wakeupgen context.
162
145
*/
163
-
if (dev->cpu == 0 && (cx->mpu_state == PWRDM_POWER_RET) &&
164
-
(cx->mpu_logic_state == PWRDM_POWER_OFF))
146
+
if (dev->cpu == 0 && mpuss_can_lose_context)
165
147
cpu_cluster_pm_exit();
166
148
167
149
fail:
+1
arch/arm/mach-omap2/io.c
+1
arch/arm/mach-omap2/io.c
+3
arch/arm/mach-omap2/omap-mpuss-lowpower.c
+3
arch/arm/mach-omap2/omap-mpuss-lowpower.c
···
271
271
else
272
272
omap_pm_ops.finish_suspend(save_state);
273
273
274
+
if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu)
275
+
gic_dist_enable();
276
+
274
277
/*
275
278
* Restore the CPUx power state to ON otherwise CPUx
276
279
* power domain can transitions to programmed low power
+1
-5
arch/arm/mach-omap2/omap-smp.c
+1
-5
arch/arm/mach-omap2/omap-smp.c
···
39
39
40
40
#define OMAP5_CORE_COUNT 0x2
41
41
42
-
u16 pm44xx_errata;
43
-
44
42
/* SCU base address */
45
43
static void __iomem *scu_base;
46
44
···
215
217
if (scu_base)
216
218
scu_enable(scu_base);
217
219
218
-
if (cpu_is_omap446x()) {
220
+
if (cpu_is_omap446x())
219
221
startup_addr = omap4460_secondary_startup;
220
-
pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
221
-
}
222
222
223
223
/*
224
224
* Write the address of secondary startup routine into the
+6
arch/arm/mach-omap2/omap4-common.c
+6
arch/arm/mach-omap2/omap4-common.c
···
127
127
__raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
128
128
}
129
129
130
+
void gic_dist_enable(void)
131
+
{
132
+
if (gic_dist_base_addr)
133
+
__raw_writel(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
134
+
}
135
+
130
136
bool gic_dist_disabled(void)
131
137
{
132
138
return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
+15
arch/arm/mach-omap2/pm44xx.c
+15
arch/arm/mach-omap2/pm44xx.c
···
24
24
#include "powerdomain.h"
25
25
#include "pm.h"
26
26
27
+
u16 pm44xx_errata;
28
+
27
29
struct power_state {
28
30
struct powerdomain *pwrdm;
29
31
u32 next_state;
···
198
196
}
199
197
200
198
return ret;
199
+
}
200
+
201
+
/**
202
+
* omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
203
+
*
204
+
* Initializes basic stuff for power management functionality.
205
+
*/
206
+
int __init omap4_pm_init_early(void)
207
+
{
208
+
if (cpu_is_omap446x())
209
+
pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
210
+
211
+
return 0;
201
212
}
202
213
203
214
/**
+47
arch/arm/plat-orion/irq.c
+47
arch/arm/plat-orion/irq.c
···
15
15
#include <linux/io.h>
16
16
#include <linux/of_address.h>
17
17
#include <linux/of_irq.h>
18
+
#include <asm/exception.h>
18
19
#include <plat/irq.h>
19
20
#include <plat/orion-gpio.h>
21
+
#include <mach/bridge-regs.h>
22
+
23
+
#ifdef CONFIG_MULTI_IRQ_HANDLER
24
+
/*
25
+
* Compiling with both non-DT and DT support enabled, will
26
+
* break asm irq handler used by non-DT boards. Therefore,
27
+
* we provide a C-style irq handler even for non-DT boards,
28
+
* if MULTI_IRQ_HANDLER is set.
29
+
*
30
+
* Notes:
31
+
* - this is prepared for Kirkwood and Dove only, update
32
+
* accordingly if you add Orion5x or MV78x00.
33
+
* - Orion5x uses different macro names and has only one
34
+
* set of CAUSE/MASK registers.
35
+
* - MV78x00 uses the same macro names but has a third
36
+
* set of CAUSE/MASK registers.
37
+
*
38
+
*/
39
+
40
+
static void __iomem *orion_irq_base = IRQ_VIRT_BASE;
41
+
42
+
asmlinkage void
43
+
__exception_irq_entry orion_legacy_handle_irq(struct pt_regs *regs)
44
+
{
45
+
u32 stat;
46
+
47
+
stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_LOW_OFF);
48
+
stat &= readl_relaxed(orion_irq_base + IRQ_MASK_LOW_OFF);
49
+
if (stat) {
50
+
unsigned int hwirq = __fls(stat);
51
+
handle_IRQ(hwirq, regs);
52
+
return;
53
+
}
54
+
stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_HIGH_OFF);
55
+
stat &= readl_relaxed(orion_irq_base + IRQ_MASK_HIGH_OFF);
56
+
if (stat) {
57
+
unsigned int hwirq = 32 + __fls(stat);
58
+
handle_IRQ(hwirq, regs);
59
+
return;
60
+
}
61
+
}
62
+
#endif
20
63
21
64
void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
22
65
{
···
78
35
ct->chip.irq_unmask = irq_gc_mask_set_bit;
79
36
irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
80
37
IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
38
+
39
+
#ifdef CONFIG_MULTI_IRQ_HANDLER
40
+
set_handle_irq(orion_legacy_handle_irq);
41
+
#endif
81
42
}
82
43
83
44
#ifdef CONFIG_OF
+1
-1
drivers/bus/arm-cci.c
+1
-1
drivers/bus/arm-cci.c
+11
-3
drivers/clocksource/bcm_kona_timer.c
+11
-3
drivers/clocksource/bcm_kona_timer.c
···
17
17
#include <linux/jiffies.h>
18
18
#include <linux/clockchips.h>
19
19
#include <linux/types.h>
20
+
#include <linux/clk.h>
20
21
21
22
#include <linux/io.h>
22
23
#include <asm/mach/time.h>
···
102
101
static void __init kona_timers_init(struct device_node *node)
103
102
{
104
103
u32 freq;
104
+
struct clk *external_clk;
105
105
106
-
if (!of_property_read_u32(node, "clock-frequency", &freq))
106
+
external_clk = of_clk_get_by_name(node, NULL);
107
+
108
+
if (!IS_ERR(external_clk)) {
109
+
arch_timer_rate = clk_get_rate(external_clk);
110
+
clk_prepare_enable(external_clk);
111
+
} else if (!of_property_read_u32(node, "clock-frequency", &freq)) {
107
112
arch_timer_rate = freq;
108
-
else
109
-
panic("clock-frequency not set in the .dts file");
113
+
} else {
114
+
panic("unable to determine clock-frequency");
115
+
}
110
116
111
117
/* Setup IRQ numbers */
112
118
timers.tmr_irq = irq_of_parse_and_map(node, 0);
+2
-2
drivers/irqchip/irq-armada-370-xp.c
+2
-2
drivers/irqchip/irq-armada-370-xp.c
···
59
59
#define PCI_MSI_DOORBELL_END (32)
60
60
#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
61
61
62
-
static DEFINE_RAW_SPINLOCK(irq_controller_lock);
63
-
64
62
static void __iomem *per_cpu_int_base;
65
63
static void __iomem *main_int_base;
66
64
static struct irq_domain *armada_370_xp_mpic_domain;
···
237
239
#endif
238
240
239
241
#ifdef CONFIG_SMP
242
+
static DEFINE_RAW_SPINLOCK(irq_controller_lock);
243
+
240
244
static int armada_xp_set_affinity(struct irq_data *d,
241
245
const struct cpumask *mask_val, bool force)
242
246
{