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watchdog: rzg2l_wdt: Fix 'BUG: Invalid wait context'

This patch fixes the issue 'BUG: Invalid wait context' during restart()
callback by using clk_prepare_enable() instead of pm_runtime_get_sync()
for turning on the clocks during restart.

This issue is noticed when testing with renesas_defconfig.

[ 42.213802] reboot: Restarting system
[ 42.217860]
[ 42.219364] =============================
[ 42.223368] [ BUG: Invalid wait context ]
[ 42.227372] 5.17.0-rc5-arm64-renesas-00002-g10393723e35e #522 Not tainted
[ 42.234153] -----------------------------
[ 42.238155] systemd-shutdow/1 is trying to lock:
[ 42.242766] ffff00000a650828 (&genpd->mlock){+.+.}-{3:3}, at: genpd_lock_mtx+0x14/0x20
[ 42.250709] other info that might help us debug this:
[ 42.255753] context-{4:4}
[ 42.258368] 2 locks held by systemd-shutdow/1:
[ 42.262806] #0: ffff80000944e1c8 (system_transition_mutex#2){+.+.}-{3:3}, at: __do_sys_reboot+0xd0/0x250
[ 42.272388] #1: ffff8000094c4e40 (rcu_read_lock){....}-{1:2}, at: atomic_notifier_call_chain+0x0/0x150
[ 42.281795] stack backtrace:
[ 42.284672] CPU: 0 PID: 1 Comm: systemd-shutdow Not tainted 5.17.0-rc5-arm64-renesas-00002-g10393723e35e #522
[ 42.294577] Hardware name: Renesas SMARC EVK based on r9a07g044c2 (DT)
[ 42.301096] Call trace:
[ 42.303538] dump_backtrace+0xcc/0xd8
[ 42.307203] show_stack+0x14/0x30
[ 42.310517] dump_stack_lvl+0x88/0xb0
[ 42.314180] dump_stack+0x14/0x2c
[ 42.317492] __lock_acquire+0x1b24/0x1b50
[ 42.321502] lock_acquire+0x120/0x3a8
[ 42.325162] __mutex_lock+0x84/0x8f8
[ 42.328737] mutex_lock_nested+0x30/0x58
[ 42.332658] genpd_lock_mtx+0x14/0x20
[ 42.336319] genpd_runtime_resume+0xc4/0x228
[ 42.340587] __rpm_callback+0x44/0x170
[ 42.344337] rpm_callback+0x64/0x70
[ 42.347824] rpm_resume+0x4e0/0x6b8
[ 42.351310] __pm_runtime_resume+0x50/0x78
[ 42.355404] rzg2l_wdt_restart+0x28/0x68
[ 42.359329] watchdog_restart_notifier+0x1c/0x30
[ 42.363943] atomic_notifier_call_chain+0x94/0x150
[ 42.368732] do_kernel_restart+0x24/0x30
[ 42.372652] machine_restart+0x44/0x70
[ 42.376399] kernel_restart+0x3c/0x60
[ 42.380058] __do_sys_reboot+0x228/0x250
[ 42.383977] __arm64_sys_reboot+0x20/0x28
[ 42.387983] invoke_syscall+0x40/0xf8

Fixes: 2cbc5cd0b55fa2 ("watchdog: Add Watchdog Timer driver for RZ/G2L")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20220225175320.11041-4-biju.das.jz@bp.renesas.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>

authored by

Biju Das and committed by
Wim Van Sebroeck
e4cf8959 95abafe7

+13 -12
+13 -12
drivers/watchdog/rzg2l_wdt.c
··· 43 43 struct reset_control *rstc; 44 44 unsigned long osc_clk_rate; 45 45 unsigned long delay; 46 + struct clk *pclk; 47 + struct clk *osc_clk; 46 48 }; 47 49 48 50 static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv) ··· 120 118 121 119 /* Reset the module before we modify any register */ 122 120 reset_control_reset(priv->rstc); 123 - pm_runtime_get_sync(wdev->parent); 121 + 122 + clk_prepare_enable(priv->pclk); 123 + clk_prepare_enable(priv->osc_clk); 124 124 125 125 /* smallest counter value to reboot soon */ 126 126 rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(1), WDTSET); ··· 169 165 struct device *dev = &pdev->dev; 170 166 struct rzg2l_wdt_priv *priv; 171 167 unsigned long pclk_rate; 172 - struct clk *wdt_clk; 173 168 int ret; 174 169 175 170 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ··· 180 177 return PTR_ERR(priv->base); 181 178 182 179 /* Get watchdog main clock */ 183 - wdt_clk = clk_get(&pdev->dev, "oscclk"); 184 - if (IS_ERR(wdt_clk)) 185 - return dev_err_probe(&pdev->dev, PTR_ERR(wdt_clk), "no oscclk"); 180 + priv->osc_clk = devm_clk_get(&pdev->dev, "oscclk"); 181 + if (IS_ERR(priv->osc_clk)) 182 + return dev_err_probe(&pdev->dev, PTR_ERR(priv->osc_clk), "no oscclk"); 186 183 187 - priv->osc_clk_rate = clk_get_rate(wdt_clk); 188 - clk_put(wdt_clk); 184 + priv->osc_clk_rate = clk_get_rate(priv->osc_clk); 189 185 if (!priv->osc_clk_rate) 190 186 return dev_err_probe(&pdev->dev, -EINVAL, "oscclk rate is 0"); 191 187 192 188 /* Get Peripheral clock */ 193 - wdt_clk = clk_get(&pdev->dev, "pclk"); 194 - if (IS_ERR(wdt_clk)) 195 - return dev_err_probe(&pdev->dev, PTR_ERR(wdt_clk), "no pclk"); 189 + priv->pclk = devm_clk_get(&pdev->dev, "pclk"); 190 + if (IS_ERR(priv->pclk)) 191 + return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk), "no pclk"); 196 192 197 - pclk_rate = clk_get_rate(wdt_clk); 198 - clk_put(wdt_clk); 193 + pclk_rate = clk_get_rate(priv->pclk); 199 194 if (!pclk_rate) 200 195 return dev_err_probe(&pdev->dev, -EINVAL, "pclk rate is 0"); 201 196