Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2025-11-28' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"Last one for this round hopefully, mostly the usual suspects,
xe/amdgpu, with some single fixes otherwise.
There is one amdgpu HDMI blackscreen bug that came in late in the
cycle, but it was bisected and the revert is in here.
i915:
- Reject async flips when PSR's selective fetch is enabled
xe:
- Fix resource leak in xe_guc_ct_init_noalloc()'s error path
- Fix stack_depot usage without STACKDEPOT_ALWAYS_INIT
- Fix overflow in conversion from clock tics to msec
amdgpu:
- Unified MES fix
- HDMI fix
- Cursor fix
- Bightness fix
- EDID reading improvement
- UserQ fix
- Cyan Skillfish IP discovery fix
bridge:
- sil902x: Fix HDMI detection
imagination:
- Update documentation
sti:
- Fix leaks in probe
vga_switcheroo:
- Avoid race condition during fbcon initialization"
* tag 'drm-fixes-2025-11-28' of https://gitlab.freedesktop.org/drm/kernel:
drm/amdgpu: fix cyan_skillfish2 gpu info fw handling
drm/amdgpu: attach tlb fence to the PTs update
drm/amd/display: Increase EDID read retries
drm/amd/display: Don't change brightness for disabled connectors
drm/amd/display: Check NULL before accessing
Revert "drm/amd/display: Move setup_stream_attribute"
drm/xe: Fix conversion from clock ticks to milliseconds
drm/xe/guc: Fix stack_depot usage
drm/xe/guc: Fix resource leak in xe_guc_ct_init_noalloc()
drm/i915/psr: Reject async flips when selective fetch is enabled
drm, fbcon, vga_switcheroo: Avoid race condition in fbcon setup
drm/amd/amdgpu: reserve vm invalidation engine for uni_mes
drm: sti: fix device leaks at component probe
drm/imagination: Document pvr_device.power member
drm/bridge: sii902x: Fix HDMI detection with DRM_BRIDGE_ATTACH_NO_CONNECTOR
+85
-65
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
···
597
597
/* reserve engine 5 for firmware */
598
598
if (adev->enable_mes)
599
599
vm_inv_engs[i] &= ~(1 << 5);
600
+
/* reserve engine 6 for uni mes */
601
+
if (adev->enable_uni_mes)
602
+
vm_inv_engs[i] &= ~(1 << 6);
600
603
/* reserve mmhub engine 3 for firmware */
601
604
if (adev->enable_umsch_mm)
602
605
vm_inv_engs[i] &= ~(1 << 3);
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
···
1066
1066
}
1067
1067
1068
1068
/* Prepare a TLB flush fence to be attached to PTs */
1069
-
if (!params->unlocked && vm->is_compute_context) {
1069
+
if (!params->unlocked) {
1070
1070
amdgpu_vm_tlb_fence_create(params->adev, vm, fence);
1071
1071
1072
1072
/* Makes sure no PD/PT is freed before the flush */
+15
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+15
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
5052
5052
struct dc_link *link;
5053
5053
u32 brightness;
5054
5054
bool rc, reallow_idle = false;
5055
+
struct drm_connector *connector;
5056
+
5057
+
list_for_each_entry(connector, &dm->ddev->mode_config.connector_list, head) {
5058
+
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5059
+
5060
+
if (aconnector->bl_idx != bl_idx)
5061
+
continue;
5062
+
5063
+
/* if connector is off, save the brightness for next time it's on */
5064
+
if (!aconnector->base.encoder) {
5065
+
dm->brightness[bl_idx] = user_brightness;
5066
+
dm->actual_brightness[bl_idx] = 0;
5067
+
return;
5068
+
}
5069
+
}
5055
5070
5056
5071
amdgpu_dm_update_backlight_caps(dm, bl_idx);
5057
5072
caps = &dm->backlight_caps[bl_idx];
+4
-4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+4
-4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
···
997
997
struct amdgpu_dm_connector *aconnector = link->priv;
998
998
struct drm_connector *connector = &aconnector->base;
999
999
struct i2c_adapter *ddc;
1000
-
int retry = 3;
1001
-
enum dc_edid_status edid_status;
1000
+
int retry = 25;
1001
+
enum dc_edid_status edid_status = EDID_NO_RESPONSE;
1002
1002
const struct drm_edid *drm_edid;
1003
1003
const struct edid *edid;
1004
1004
···
1028
1028
}
1029
1029
1030
1030
if (!drm_edid)
1031
-
return EDID_NO_RESPONSE;
1031
+
continue;
1032
1032
1033
1033
edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()
1034
1034
if (!edid ||
···
1046
1046
&sink->dc_edid,
1047
1047
&sink->edid_caps);
1048
1048
1049
-
} while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
1049
+
} while ((edid_status == EDID_BAD_CHECKSUM || edid_status == EDID_NO_RESPONSE) && --retry > 0);
1050
1050
1051
1051
if (edid_status != EDID_OK)
1052
1052
DRM_ERROR("EDID err: %d, on connector: %s",
+8
-3
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+8
-3
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
···
705
705
{
706
706
uint8_t i;
707
707
bool ret = false;
708
-
struct dc *dc = stream->ctx->dc;
709
-
struct resource_context *res_ctx =
710
-
&dc->current_state->res_ctx;
708
+
struct dc *dc;
709
+
struct resource_context *res_ctx;
710
+
711
+
if (!stream->ctx)
712
+
return false;
713
+
714
+
dc = stream->ctx->dc;
715
+
res_ctx = &dc->current_state->res_ctx;
711
716
712
717
dc_exit_ips_for_hw_access(dc);
713
718
-1
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
-1
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
-2
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
-2
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
-2
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
-2
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+3
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+3
drivers/gpu/drm/amd/display/dc/link/link_dpms.c
···
2458
2458
struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
2459
2459
enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
2460
2460
struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
2461
+
const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
2461
2462
bool apply_edp_fast_boot_optimization =
2462
2463
pipe_ctx->stream->apply_edp_fast_boot_optimization;
2463
2464
···
2502
2501
otg_out_dest = OUT_MUX_DIO;
2503
2502
pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
2504
2503
}
2504
+
2505
+
link_hwss->setup_stream_attribute(pipe_ctx);
2505
2506
2506
2507
pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
2507
2508
-7
drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
-7
drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
···
44
44
struct dc_crtc_timing *crtc_timing,
45
45
bool is_dual_link) {}
46
46
47
-
static void virtual_stream_encoder_lvds_set_stream_attribute(
48
-
struct stream_encoder *enc,
49
-
struct dc_crtc_timing *crtc_timing)
50
-
{}
51
-
52
47
static void virtual_stream_encoder_set_throttled_vcp_size(
53
48
struct stream_encoder *enc,
54
49
struct fixed31_32 avg_time_slots_per_mtp)
···
115
120
virtual_stream_encoder_hdmi_set_stream_attribute,
116
121
.dvi_set_stream_attribute =
117
122
virtual_stream_encoder_dvi_set_stream_attribute,
118
-
.lvds_set_stream_attribute =
119
-
virtual_stream_encoder_lvds_set_stream_attribute,
120
123
.set_throttled_vcp_size =
121
124
virtual_stream_encoder_set_throttled_vcp_size,
122
125
.update_hdmi_info_packets =
+8
-12
drivers/gpu/drm/bridge/sii902x.c
+8
-12
drivers/gpu/drm/bridge/sii902x.c
···
179
179
struct drm_connector connector;
180
180
struct gpio_desc *reset_gpio;
181
181
struct i2c_mux_core *i2cmux;
182
-
bool sink_is_hdmi;
183
182
u32 bus_width;
184
183
185
184
/*
···
314
315
drm_edid_free(drm_edid);
315
316
}
316
317
317
-
sii902x->sink_is_hdmi = connector->display_info.is_hdmi;
318
-
319
318
return num;
320
319
}
321
320
···
339
342
struct drm_atomic_state *state)
340
343
{
341
344
struct sii902x *sii902x = bridge_to_sii902x(bridge);
345
+
struct drm_connector *connector;
346
+
u8 output_mode = SII902X_SYS_CTRL_OUTPUT_DVI;
347
+
348
+
connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
349
+
if (connector && connector->display_info.is_hdmi)
350
+
output_mode = SII902X_SYS_CTRL_OUTPUT_HDMI;
342
351
343
352
mutex_lock(&sii902x->mutex);
344
353
354
+
regmap_update_bits(sii902x->regmap, SII902X_SYS_CTRL_DATA,
355
+
SII902X_SYS_CTRL_OUTPUT_MODE, output_mode);
345
356
regmap_update_bits(sii902x->regmap, SII902X_PWR_STATE_CTRL,
346
357
SII902X_AVI_POWER_STATE_MSK,
347
358
SII902X_AVI_POWER_STATE_D(0));
···
364
359
const struct drm_display_mode *adj)
365
360
{
366
361
struct sii902x *sii902x = bridge_to_sii902x(bridge);
367
-
u8 output_mode = SII902X_SYS_CTRL_OUTPUT_DVI;
368
362
struct regmap *regmap = sii902x->regmap;
369
363
u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
370
364
struct hdmi_avi_infoframe frame;
371
365
u16 pixel_clock_10kHz = adj->clock / 10;
372
366
int ret;
373
-
374
-
if (sii902x->sink_is_hdmi)
375
-
output_mode = SII902X_SYS_CTRL_OUTPUT_HDMI;
376
367
377
368
buf[0] = pixel_clock_10kHz & 0xff;
378
369
buf[1] = pixel_clock_10kHz >> 8;
···
384
383
SII902X_TPI_AVI_INPUT_COLORSPACE_RGB;
385
384
386
385
mutex_lock(&sii902x->mutex);
387
-
388
-
ret = regmap_update_bits(sii902x->regmap, SII902X_SYS_CTRL_DATA,
389
-
SII902X_SYS_CTRL_OUTPUT_MODE, output_mode);
390
-
if (ret)
391
-
goto out;
392
386
393
387
ret = regmap_bulk_write(regmap, SII902X_TPI_VIDEO_DATA, buf, 10);
394
388
if (ret)
-14
drivers/gpu/drm/drm_fb_helper.c
-14
drivers/gpu/drm/drm_fb_helper.c
···
31
31
32
32
#include <linux/console.h>
33
33
#include <linux/export.h>
34
-
#include <linux/pci.h>
35
34
#include <linux/sysrq.h>
36
-
#include <linux/vga_switcheroo.h>
37
35
38
36
#include <drm/drm_atomic.h>
39
37
#include <drm/drm_drv.h>
···
564
566
*/
565
567
void drm_fb_helper_unregister_info(struct drm_fb_helper *fb_helper)
566
568
{
567
-
struct fb_info *info = fb_helper->info;
568
-
struct device *dev = info->device;
569
-
570
-
if (dev_is_pci(dev))
571
-
vga_switcheroo_client_fb_set(to_pci_dev(dev), NULL);
572
569
unregister_framebuffer(fb_helper->info);
573
570
}
574
571
EXPORT_SYMBOL(drm_fb_helper_unregister_info);
···
1625
1632
struct drm_client_dev *client = &fb_helper->client;
1626
1633
struct drm_device *dev = fb_helper->dev;
1627
1634
struct drm_fb_helper_surface_size sizes;
1628
-
struct fb_info *info;
1629
1635
int ret;
1630
1636
1631
1637
if (drm_WARN_ON(dev, !dev->driver->fbdev_probe))
···
1644
1652
return ret;
1645
1653
1646
1654
strcpy(fb_helper->fb->comm, "[fbcon]");
1647
-
1648
-
info = fb_helper->info;
1649
-
1650
-
/* Set the fb info for vgaswitcheroo clients. Does nothing otherwise. */
1651
-
if (dev_is_pci(info->device))
1652
-
vga_switcheroo_client_fb_set(to_pci_dev(info->device), info);
1653
1655
1654
1656
return 0;
1655
1657
}
+8
drivers/gpu/drm/i915/display/intel_display.c
+8
drivers/gpu/drm/i915/display/intel_display.c
···
5964
5964
return -EINVAL;
5965
5965
}
5966
5966
5967
+
/* FIXME: selective fetch should be disabled for async flips */
5968
+
if (new_crtc_state->enable_psr2_sel_fetch) {
5969
+
drm_dbg_kms(display->drm,
5970
+
"[CRTC:%d:%s] async flip disallowed with PSR2 selective fetch\n",
5971
+
crtc->base.base.id, crtc->base.name);
5972
+
return -EINVAL;
5973
+
}
5974
+
5967
5975
for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
5968
5976
new_plane_state, i) {
5969
5977
if (plane->pipe != crtc->pipe)
-6
drivers/gpu/drm/i915/display/intel_psr.c
-6
drivers/gpu/drm/i915/display/intel_psr.c
···
1256
1256
return false;
1257
1257
}
1258
1258
1259
-
if (crtc_state->uapi.async_flip) {
1260
-
drm_dbg_kms(display->drm,
1261
-
"PSR2 sel fetch not enabled, async flip enabled\n");
1262
-
return false;
1263
-
}
1264
-
1265
1259
return crtc_state->enable_psr2_sel_fetch = true;
1266
1260
}
1267
1261
+8
drivers/gpu/drm/imagination/pvr_device.h
+8
drivers/gpu/drm/imagination/pvr_device.h
···
146
146
*/
147
147
struct clk *mem_clk;
148
148
149
+
/**
150
+
* @power: Optional power domain devices.
151
+
*
152
+
* On platforms with more than one power domain for the GPU, they are
153
+
* stored here in @domain_devs, along with links between them in
154
+
* @domain_links. The size of @domain_devs is given by @domain_count,
155
+
* while the size of @domain_links is (2 * @domain_count) - 1.
156
+
*/
149
157
struct pvr_device_power {
150
158
struct device **domain_devs;
151
159
struct device_link **domain_links;
+6
-1
drivers/gpu/drm/sti/sti_vtg.c
+6
-1
drivers/gpu/drm/sti/sti_vtg.c
···
143
143
struct sti_vtg *of_vtg_find(struct device_node *np)
144
144
{
145
145
struct platform_device *pdev;
146
+
struct sti_vtg *vtg;
146
147
147
148
pdev = of_find_device_by_node(np);
148
149
if (!pdev)
149
150
return NULL;
150
151
151
-
return (struct sti_vtg *)platform_get_drvdata(pdev);
152
+
vtg = platform_get_drvdata(pdev);
153
+
154
+
put_device(&pdev->dev);
155
+
156
+
return vtg;
152
157
}
153
158
154
159
static void vtg_reset(struct sti_vtg *vtg)
+1
-6
drivers/gpu/drm/xe/xe_gt_clock.c
+1
-6
drivers/gpu/drm/xe/xe_gt_clock.c
···
93
93
return 0;
94
94
}
95
95
96
-
static u64 div_u64_roundup(u64 n, u32 d)
97
-
{
98
-
return div_u64(n + d - 1, d);
99
-
}
100
-
101
96
/**
102
97
* xe_gt_clock_interval_to_ms - Convert sampled GT clock ticks to msec
103
98
*
···
103
108
*/
104
109
u64 xe_gt_clock_interval_to_ms(struct xe_gt *gt, u64 count)
105
110
{
106
-
return div_u64_roundup(count * MSEC_PER_SEC, gt->info.reference_clock);
111
+
return mul_u64_u32_div(count, MSEC_PER_SEC, gt->info.reference_clock);
107
112
}
+9
-6
drivers/gpu/drm/xe/xe_guc_ct.c
+9
-6
drivers/gpu/drm/xe/xe_guc_ct.c
···
226
226
227
227
xe_gt_assert(gt, !(guc_ct_size() % PAGE_SIZE));
228
228
229
+
err = drmm_mutex_init(&xe->drm, &ct->lock);
230
+
if (err)
231
+
return err;
232
+
233
+
primelockdep(ct);
234
+
229
235
ct->g2h_wq = alloc_ordered_workqueue("xe-g2h-wq", WQ_MEM_RECLAIM);
230
236
if (!ct->g2h_wq)
231
237
return -ENOMEM;
···
243
237
#if IS_ENABLED(CONFIG_DRM_XE_DEBUG)
244
238
spin_lock_init(&ct->dead.lock);
245
239
INIT_WORK(&ct->dead.worker, ct_dead_worker_func);
240
+
#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_GUC)
241
+
stack_depot_init();
242
+
#endif
246
243
#endif
247
244
init_waitqueue_head(&ct->wq);
248
245
init_waitqueue_head(&ct->g2h_fence_wq);
249
-
250
-
err = drmm_mutex_init(&xe->drm, &ct->lock);
251
-
if (err)
252
-
return err;
253
-
254
-
primelockdep(ct);
255
246
256
247
err = drmm_add_action_or_reset(&xe->drm, guc_ct_fini, ct);
257
248
if (err)
+9
drivers/video/fbdev/core/fbcon.c
+9
drivers/video/fbdev/core/fbcon.c
···
66
66
#include <linux/string.h>
67
67
#include <linux/kd.h>
68
68
#include <linux/panic.h>
69
+
#include <linux/pci.h>
69
70
#include <linux/printk.h>
70
71
#include <linux/slab.h>
71
72
#include <linux/fb.h>
···
79
78
#include <linux/interrupt.h>
80
79
#include <linux/crc32.h> /* For counting font checksums */
81
80
#include <linux/uaccess.h>
81
+
#include <linux/vga_switcheroo.h>
82
82
#include <asm/irq.h>
83
83
84
84
#include "fbcon.h"
···
2901
2899
2902
2900
console_lock();
2903
2901
2902
+
if (info->device && dev_is_pci(info->device))
2903
+
vga_switcheroo_client_fb_set(to_pci_dev(info->device), NULL);
2904
+
2904
2905
fbcon_registered_fb[info->node] = NULL;
2905
2906
fbcon_num_registered_fb--;
2906
2907
···
3036
3031
set_con2fb_map(i, idx, 0);
3037
3032
}
3038
3033
}
3034
+
3035
+
/* Set the fb info for vga_switcheroo clients. Does nothing otherwise. */
3036
+
if (info->device && dev_is_pci(info->device))
3037
+
vga_switcheroo_client_fb_set(to_pci_dev(info->device), info);
3039
3038
3040
3039
return ret;
3041
3040
}