Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes-3.16' of git://people.freedesktop.org/~agd5f/linux
misc fixes, output fixes for 4k monitor, dpm lockup fixes
* 'drm-fixes-3.16' of git://people.freedesktop.org/~agd5f/linux:
drm/radeon: page table BOs are kernel allocations
drm/radeon/cik: fix typo in EOP packet
drm/radeon: Track the status of a page flip more explicitly
drm/radeon/dpm: fix vddci setup typo on cayman
drm/radeon/dpm: fix typo in vddci setup for eg/btc
drm/radeon: use RADEON_MAX_CRTCS, RADEON_MAX_AFMT_BLOCKS (v2)
drm/radeon: Use only one line for whole DPCD debug output
drm/radeon: add a module parameter to control deep color support
drm/radeon: enable bapm by default on desktop TN/RL boards
drm/radeon: enable bapm by default on KV/KB
drm/radeon: only apply bapm changes for AC power on ARUBA
drm/radeon: adjust default dispclk on DCE6 (v2)
+70
-26
+7
-5
drivers/gpu/drm/radeon/atombios_dp.c
+7
-5
drivers/gpu/drm/radeon/atombios_dp.c
···
403
403
{
404
404
struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
405
405
u8 msg[DP_DPCD_SIZE];
406
-
int ret, i;
406
+
int ret;
407
+
408
+
char dpcd_hex_dump[DP_DPCD_SIZE * 3];
407
409
408
410
ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
409
411
DP_DPCD_SIZE);
410
412
if (ret > 0) {
411
413
memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
412
-
DRM_DEBUG_KMS("DPCD: ");
413
-
for (i = 0; i < DP_DPCD_SIZE; i++)
414
-
DRM_DEBUG_KMS("%02x ", msg[i]);
415
-
DRM_DEBUG_KMS("\n");
414
+
415
+
hex_dump_to_buffer(dig_connector->dpcd, sizeof(dig_connector->dpcd),
416
+
32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
417
+
DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
416
418
417
419
radeon_dp_probe_oui(radeon_connector);
418
420
+1
-1
drivers/gpu/drm/radeon/cikd.h
+1
-1
drivers/gpu/drm/radeon/cikd.h
···
1752
1752
#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
1753
1753
#define EOP_TCL1_ACTION_EN (1 << 16)
1754
1754
#define EOP_TC_ACTION_EN (1 << 17) /* L2 */
1755
+
#define EOP_TCL2_VOLATILE (1 << 24)
1755
1756
#define EOP_CACHE_POLICY(x) ((x) << 25)
1756
1757
/* 0 - LRU
1757
1758
* 1 - Stream
1758
1759
* 2 - Bypass
1759
1760
*/
1760
-
#define EOP_TCL2_VOLATILE (1 << 27)
1761
1761
#define DATA_SEL(x) ((x) << 29)
1762
1762
/* 0 - discard
1763
1763
* 1 - send low 32bit data
+1
-1
drivers/gpu/drm/radeon/cypress_dpm.c
+1
-1
drivers/gpu/drm/radeon/cypress_dpm.c
···
1551
1551
1552
1552
table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0;
1553
1553
table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] =
1554
-
cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
1554
+
cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
1555
1555
}
1556
1556
1557
1557
return 0;
+1
-1
drivers/gpu/drm/radeon/kv_dpm.c
+1
-1
drivers/gpu/drm/radeon/kv_dpm.c
···
2726
2726
pi->caps_sclk_ds = true;
2727
2727
pi->enable_auto_thermal_throttling = true;
2728
2728
pi->disable_nb_ps3_in_battery = false;
2729
-
pi->bapm_enable = false;
2729
+
pi->bapm_enable = true;
2730
2730
pi->voltage_drop_t = 0;
2731
2731
pi->caps_sclk_throttle_low_notification = false;
2732
2732
pi->caps_fps = false; /* true? */
+1
-1
drivers/gpu/drm/radeon/ni_dpm.c
+1
-1
drivers/gpu/drm/radeon/ni_dpm.c
···
1315
1315
1316
1316
table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = 0;
1317
1317
table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] =
1318
-
cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
1318
+
cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
1319
1319
}
1320
1320
}
1321
1321
+1
-4
drivers/gpu/drm/radeon/radeon.h
+1
-4
drivers/gpu/drm/radeon/radeon.h
···
102
102
extern int radeon_hard_reset;
103
103
extern int radeon_vm_size;
104
104
extern int radeon_vm_block_size;
105
+
extern int radeon_deep_color;
105
106
106
107
/*
107
108
* Copy from radeon_drv.h so we don't have to include both and have conflicting
···
749
748
struct evergreen_irq_stat_regs evergreen;
750
749
struct cik_irq_stat_regs cik;
751
750
};
752
-
753
-
#define RADEON_MAX_HPD_PINS 7
754
-
#define RADEON_MAX_CRTCS 6
755
-
#define RADEON_MAX_AFMT_BLOCKS 7
756
751
757
752
struct radeon_irq {
758
753
bool installed;
+9
-1
drivers/gpu/drm/radeon/radeon_atombios.c
+9
-1
drivers/gpu/drm/radeon/radeon_atombios.c
···
1227
1227
rdev->clock.default_dispclk =
1228
1228
le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1229
1229
if (rdev->clock.default_dispclk == 0) {
1230
-
if (ASIC_IS_DCE5(rdev))
1230
+
if (ASIC_IS_DCE6(rdev))
1231
+
rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1232
+
else if (ASIC_IS_DCE5(rdev))
1231
1233
rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1232
1234
else
1233
1235
rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1236
+
}
1237
+
/* set a reasonable default for DP */
1238
+
if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1239
+
DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1240
+
rdev->clock.default_dispclk / 100);
1241
+
rdev->clock.default_dispclk = 60000;
1234
1242
}
1235
1243
rdev->clock.dp_extclk =
1236
1244
le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
+3
drivers/gpu/drm/radeon/radeon_connectors.c
+3
drivers/gpu/drm/radeon/radeon_connectors.c
+14
-5
drivers/gpu/drm/radeon/radeon_display.c
+14
-5
drivers/gpu/drm/radeon/radeon_display.c
···
285
285
void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
286
286
{
287
287
struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
288
-
struct radeon_flip_work *work;
289
288
unsigned long flags;
290
289
u32 update_pending;
291
290
int vpos, hpos;
···
294
295
return;
295
296
296
297
spin_lock_irqsave(&rdev->ddev->event_lock, flags);
297
-
work = radeon_crtc->flip_work;
298
-
if (work == NULL) {
298
+
if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
299
+
DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
300
+
"RADEON_FLIP_SUBMITTED(%d)\n",
301
+
radeon_crtc->flip_status,
302
+
RADEON_FLIP_SUBMITTED);
299
303
spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
300
304
return;
301
305
}
···
346
344
347
345
spin_lock_irqsave(&rdev->ddev->event_lock, flags);
348
346
work = radeon_crtc->flip_work;
349
-
if (work == NULL) {
347
+
if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
348
+
DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
349
+
"RADEON_FLIP_SUBMITTED(%d)\n",
350
+
radeon_crtc->flip_status,
351
+
RADEON_FLIP_SUBMITTED);
350
352
spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
351
353
return;
352
354
}
353
355
354
356
/* Pageflip completed. Clean up. */
357
+
radeon_crtc->flip_status = RADEON_FLIP_NONE;
355
358
radeon_crtc->flip_work = NULL;
356
359
357
360
/* wakeup userspace */
···
483
476
/* do the flip (mmio) */
484
477
radeon_page_flip(rdev, radeon_crtc->crtc_id, base);
485
478
479
+
radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
486
480
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
487
481
up_read(&rdev->exclusive_lock);
488
482
···
552
544
/* We borrow the event spin lock for protecting flip_work */
553
545
spin_lock_irqsave(&crtc->dev->event_lock, flags);
554
546
555
-
if (radeon_crtc->flip_work) {
547
+
if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
556
548
DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
557
549
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
558
550
drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
···
560
552
kfree(work);
561
553
return -EBUSY;
562
554
}
555
+
radeon_crtc->flip_status = RADEON_FLIP_PENDING;
563
556
radeon_crtc->flip_work = work;
564
557
565
558
/* update crtc fb */
+4
drivers/gpu/drm/radeon/radeon_drv.c
+4
drivers/gpu/drm/radeon/radeon_drv.c
···
175
175
int radeon_hard_reset = 0;
176
176
int radeon_vm_size = 4096;
177
177
int radeon_vm_block_size = 9;
178
+
int radeon_deep_color = 0;
178
179
179
180
MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
180
181
module_param_named(no_wb, radeon_no_wb, int, 0444);
···
248
247
249
248
MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default 9)");
250
249
module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
250
+
251
+
MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
252
+
module_param_named(deep_color, radeon_deep_color, int, 0444);
251
253
252
254
static struct pci_device_id pciidlist[] = {
253
255
radeon_PCI_IDS
+13
-2
drivers/gpu/drm/radeon/radeon_mode.h
+13
-2
drivers/gpu/drm/radeon/radeon_mode.h
···
46
46
#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
47
47
#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
48
48
49
+
#define RADEON_MAX_HPD_PINS 7
50
+
#define RADEON_MAX_CRTCS 6
51
+
#define RADEON_MAX_AFMT_BLOCKS 7
52
+
49
53
enum radeon_rmx_type {
50
54
RMX_OFF,
51
55
RMX_FULL,
···
237
233
struct card_info *atom_card_info;
238
234
enum radeon_connector_table connector_table;
239
235
bool mode_config_initialized;
240
-
struct radeon_crtc *crtcs[6];
241
-
struct radeon_afmt *afmt[7];
236
+
struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
237
+
struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
242
238
/* DVI-I properties */
243
239
struct drm_property *coherent_mode_property;
244
240
/* DAC enable load detect */
···
306
302
uint16_t amount;
307
303
};
308
304
305
+
enum radeon_flip_status {
306
+
RADEON_FLIP_NONE,
307
+
RADEON_FLIP_PENDING,
308
+
RADEON_FLIP_SUBMITTED
309
+
};
310
+
309
311
struct radeon_crtc {
310
312
struct drm_crtc base;
311
313
int crtc_id;
···
337
327
/* page flipping */
338
328
struct workqueue_struct *flip_queue;
339
329
struct radeon_flip_work *flip_work;
330
+
enum radeon_flip_status flip_status;
340
331
/* pll sharing */
341
332
struct radeon_atom_ss ss;
342
333
bool ss_enabled;
+4
-2
drivers/gpu/drm/radeon/radeon_pm.c
+4
-2
drivers/gpu/drm/radeon/radeon_pm.c
···
73
73
rdev->pm.dpm.ac_power = true;
74
74
else
75
75
rdev->pm.dpm.ac_power = false;
76
-
if (rdev->asic->dpm.enable_bapm)
77
-
radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
76
+
if (rdev->family == CHIP_ARUBA) {
77
+
if (rdev->asic->dpm.enable_bapm)
78
+
radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
79
+
}
78
80
mutex_unlock(&rdev->pm.mutex);
79
81
} else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
80
82
if (rdev->pm.profile == PM_PROFILE_AUTO) {
+2
-2
drivers/gpu/drm/radeon/radeon_vm.c
+2
-2
drivers/gpu/drm/radeon/radeon_vm.c
···
495
495
mutex_unlock(&vm->mutex);
496
496
497
497
r = radeon_bo_create(rdev, RADEON_VM_PTE_COUNT * 8,
498
-
RADEON_GPU_PAGE_SIZE, false,
498
+
RADEON_GPU_PAGE_SIZE, true,
499
499
RADEON_GEM_DOMAIN_VRAM, NULL, &pt);
500
500
if (r)
501
501
return r;
···
992
992
return -ENOMEM;
993
993
}
994
994
995
-
r = radeon_bo_create(rdev, pd_size, align, false,
995
+
r = radeon_bo_create(rdev, pd_size, align, true,
996
996
RADEON_GEM_DOMAIN_VRAM, NULL,
997
997
&vm->page_directory);
998
998
if (r)
+9
-1
drivers/gpu/drm/radeon/trinity_dpm.c
+9
-1
drivers/gpu/drm/radeon/trinity_dpm.c
···
1874
1874
for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
1875
1875
pi->at[i] = TRINITY_AT_DFLT;
1876
1876
1877
-
pi->enable_bapm = false;
1877
+
/* There are stability issues reported on latops with
1878
+
* bapm installed when switching between AC and battery
1879
+
* power. At the same time, some desktop boards hang
1880
+
* if it's not enabled and dpm is enabled.
1881
+
*/
1882
+
if (rdev->flags & RADEON_IS_MOBILITY)
1883
+
pi->enable_bapm = false;
1884
+
else
1885
+
pi->enable_bapm = true;
1878
1886
pi->enable_nbps_policy = true;
1879
1887
pi->enable_sclk_ds = true;
1880
1888
pi->enable_gfx_power_gating = true;