Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: Add SC8280XP GPU clock controller
Add driver for the GPU clock controller in the Qualcomm SC8280XP
platform.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
[bjorn: Included kernel.h and lower-cased hex numbers]
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220926173025.4747-3-quic_bjorande@quicinc.com
authored by
Bjorn Andersson
and committed by
Bjorn Andersson
e55d937d
9f60eb3e
+470
+8
drivers/clk/qcom/Kconfig
+8
drivers/clk/qcom/Kconfig
···
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Say Y if you want to support graphics controller devices and
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functionality such as 3D graphics.
455
455
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config SC_GPUCC_8280XP
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tristate "SC8280XP Graphics Clock Controller"
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select SC_GCC_8280XP
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help
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Support for the graphics clock controller on SC8280XP devices.
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Say Y if you want to support graphics controller devices and
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functionality such as 3D graphics.
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+
456
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config SC_LPASSCC_7280
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tristate "SC7280 Low Power Audio Subsystem (LPASS) Clock Controller"
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select SC_GCC_7280
+1
drivers/clk/qcom/Makefile
+1
drivers/clk/qcom/Makefile
···
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obj-$(CONFIG_SC_GCC_8280XP) += gcc-sc8280xp.o
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obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o
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obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o
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obj-$(CONFIG_SC_GPUCC_8280XP) += gpucc-sc8280xp.o
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obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o
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obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o
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obj-$(CONFIG_SC_LPASS_CORECC_7280) += lpasscorecc-sc7280.o lpassaudiocc-sc7280.o
+461
drivers/clk/qcom/gpucc-sc8280xp.c
+461
drivers/clk/qcom/gpucc-sc8280xp.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
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+
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
4
+
*/
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+
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+
#include <linux/clk-provider.h>
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+
#include <linux/kernel.h>
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+
#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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+
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#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
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+
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#include "clk-alpha-pll.h"
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+
#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap-divider.h"
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+
#include "common.h"
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#include "reset.h"
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#include "gdsc.h"
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+
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/* Need to match the order of clocks in DT binding */
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enum {
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DT_BI_TCXO,
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DT_GCC_GPU_GPLL0_CLK_SRC,
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DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
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};
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+
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enum {
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P_BI_TCXO,
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P_GCC_GPU_GPLL0_CLK_SRC,
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P_GCC_GPU_GPLL0_DIV_CLK_SRC,
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P_GPU_CC_PLL0_OUT_MAIN,
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P_GPU_CC_PLL1_OUT_MAIN,
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};
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+
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static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO };
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+
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static const struct pll_vco lucid_5lpe_vco[] = {
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{ 249600000, 1800000000, 0 },
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};
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+
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static struct alpha_pll_config gpu_cc_pll0_config = {
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.l = 0x1c,
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.alpha = 0xa555,
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+
.config_ctl_val = 0x20485699,
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+
.config_ctl_hi_val = 0x00002261,
48
+
.config_ctl_hi1_val = 0x2a9a699c,
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+
.test_ctl_val = 0x00000000,
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+
.test_ctl_hi_val = 0x00000000,
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+
.test_ctl_hi1_val = 0x01800000,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000805,
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.user_ctl_hi1_val = 0x00000000,
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};
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+
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static struct clk_alpha_pll gpu_cc_pll0 = {
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.offset = 0x0,
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.vco_table = lucid_5lpe_vco,
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.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
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.clkr = {
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_pll0",
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.parent_data = &parent_data_tcxo,
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+
.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_5lpe_ops,
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},
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},
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};
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+
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static struct alpha_pll_config gpu_cc_pll1_config = {
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.l = 0x1A,
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.alpha = 0xaaa,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002261,
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.config_ctl_hi1_val = 0x2a9a699c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000000,
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.test_ctl_hi1_val = 0x01800000,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000805,
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.user_ctl_hi1_val = 0x00000000,
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};
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+
86
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static struct clk_alpha_pll gpu_cc_pll1 = {
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.offset = 0x100,
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.vco_table = lucid_5lpe_vco,
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.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
90
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
91
+
.clkr = {
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.hw.init = &(const struct clk_init_data){
93
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.name = "gpu_cc_pll1",
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.parent_data = &parent_data_tcxo,
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+
.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_5lpe_ops,
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},
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},
99
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};
100
+
101
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static const struct parent_map gpu_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
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{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
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{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
107
+
};
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+
109
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static const struct clk_parent_data gpu_cc_parent_data_0[] = {
110
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{ .index = DT_BI_TCXO },
111
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{ .hw = &gpu_cc_pll0.clkr.hw },
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{ .hw = &gpu_cc_pll1.clkr.hw },
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
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{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
115
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};
116
+
117
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static const struct parent_map gpu_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
119
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
120
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{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
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{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
122
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};
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+
124
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static const struct clk_parent_data gpu_cc_parent_data_1[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &gpu_cc_pll1.clkr.hw },
127
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{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
128
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{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
129
+
};
130
+
131
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0),
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F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
135
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{ }
136
+
};
137
+
138
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static struct clk_rcg2 gpu_cc_gmu_clk_src = {
139
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.cmd_rcgr = 0x1120,
140
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.mnd_width = 0,
141
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_0,
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.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
144
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.clkr.hw.init = &(const struct clk_init_data){
145
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.name = "gpu_cc_gmu_clk_src",
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.parent_data = gpu_cc_parent_data_0,
147
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
148
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.ops = &clk_rcg2_shared_ops,
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},
150
+
};
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+
152
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static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
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F(200000000, P_GCC_GPU_GPLL0_CLK_SRC, 3, 0, 0),
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F(300000000, P_GCC_GPU_GPLL0_CLK_SRC, 2, 0, 0),
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F(400000000, P_GCC_GPU_GPLL0_CLK_SRC, 1.5, 0, 0),
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{ }
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};
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+
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static struct clk_rcg2 gpu_cc_hub_clk_src = {
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.cmd_rcgr = 0x117c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_1,
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.freq_tbl = ftbl_gpu_cc_hub_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_hub_clk_src",
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.parent_data = gpu_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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+
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static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
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.reg = 0x11c0,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "gpu_cc_hub_ahb_div_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_hub_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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+
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static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
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.reg = 0x11bc,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "gpu_cc_hub_cx_int_div_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_hub_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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+
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static struct clk_branch gpu_cc_ahb_clk = {
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.halt_reg = 0x1078,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1078,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_ahb_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpu_cc_crc_ahb_clk = {
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.halt_reg = 0x107c,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x107c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_crc_ahb_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
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},
232
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.num_parents = 1,
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+
.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch gpu_cc_cx_gmu_clk = {
240
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.halt_reg = 0x1098,
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.halt_check = BRANCH_HALT,
242
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.clkr = {
243
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.enable_reg = 0x1098,
244
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.enable_mask = BIT(0),
245
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.hw.init = &(const struct clk_init_data){
246
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.name = "gpu_cc_cx_gmu_clk",
247
+
.parent_hws = (const struct clk_hw*[]){
248
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&gpu_cc_gmu_clk_src.clkr.hw,
249
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},
250
+
.num_parents = 1,
251
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.flags = CLK_SET_RATE_PARENT,
252
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.ops = &clk_branch2_aon_ops,
253
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},
254
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},
255
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};
256
+
257
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static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
258
+
.halt_reg = 0x108c,
259
+
.halt_check = BRANCH_HALT_VOTED,
260
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.clkr = {
261
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.enable_reg = 0x108c,
262
+
.enable_mask = BIT(0),
263
+
.hw.init = &(const struct clk_init_data){
264
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.name = "gpu_cc_cx_snoc_dvm_clk",
265
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.ops = &clk_branch2_ops,
266
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},
267
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},
268
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};
269
+
270
+
static struct clk_branch gpu_cc_cxo_aon_clk = {
271
+
.halt_reg = 0x1004,
272
+
.halt_check = BRANCH_HALT_VOTED,
273
+
.clkr = {
274
+
.enable_reg = 0x1004,
275
+
.enable_mask = BIT(0),
276
+
.hw.init = &(const struct clk_init_data){
277
+
.name = "gpu_cc_cxo_aon_clk",
278
+
.ops = &clk_branch2_ops,
279
+
},
280
+
},
281
+
};
282
+
283
+
static struct clk_branch gpu_cc_gx_gmu_clk = {
284
+
.halt_reg = 0x1064,
285
+
.halt_check = BRANCH_HALT,
286
+
.clkr = {
287
+
.enable_reg = 0x1064,
288
+
.enable_mask = BIT(0),
289
+
.hw.init = &(const struct clk_init_data){
290
+
.name = "gpu_cc_gx_gmu_clk",
291
+
.parent_hws = (const struct clk_hw*[]){
292
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&gpu_cc_gmu_clk_src.clkr.hw,
293
+
},
294
+
.num_parents = 1,
295
+
.flags = CLK_SET_RATE_PARENT,
296
+
.ops = &clk_branch2_ops,
297
+
},
298
+
},
299
+
};
300
+
301
+
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
302
+
.halt_reg = 0x5000,
303
+
.halt_check = BRANCH_HALT_VOTED,
304
+
.clkr = {
305
+
.enable_reg = 0x5000,
306
+
.enable_mask = BIT(0),
307
+
.hw.init = &(const struct clk_init_data){
308
+
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
309
+
.ops = &clk_branch2_ops,
310
+
},
311
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},
312
+
};
313
+
314
+
static struct clk_branch gpu_cc_hub_aon_clk = {
315
+
.halt_reg = 0x1178,
316
+
.halt_check = BRANCH_HALT,
317
+
.clkr = {
318
+
.enable_reg = 0x1178,
319
+
.enable_mask = BIT(0),
320
+
.hw.init = &(const struct clk_init_data){
321
+
.name = "gpu_cc_hub_aon_clk",
322
+
.parent_hws = (const struct clk_hw*[]){
323
+
&gpu_cc_hub_clk_src.clkr.hw,
324
+
},
325
+
.num_parents = 1,
326
+
.flags = CLK_SET_RATE_PARENT,
327
+
.ops = &clk_branch2_aon_ops,
328
+
},
329
+
},
330
+
};
331
+
332
+
static struct clk_branch gpu_cc_hub_cx_int_clk = {
333
+
.halt_reg = 0x1204,
334
+
.halt_check = BRANCH_HALT,
335
+
.clkr = {
336
+
.enable_reg = 0x1204,
337
+
.enable_mask = BIT(0),
338
+
.hw.init = &(const struct clk_init_data){
339
+
.name = "gpu_cc_hub_cx_int_clk",
340
+
.parent_hws = (const struct clk_hw*[]){
341
+
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
342
+
},
343
+
.num_parents = 1,
344
+
.flags = CLK_SET_RATE_PARENT,
345
+
.ops = &clk_branch2_aon_ops,
346
+
},
347
+
},
348
+
};
349
+
350
+
static struct clk_branch gpu_cc_sleep_clk = {
351
+
.halt_reg = 0x1090,
352
+
.halt_check = BRANCH_HALT_VOTED,
353
+
.clkr = {
354
+
.enable_reg = 0x1090,
355
+
.enable_mask = BIT(0),
356
+
.hw.init = &(const struct clk_init_data){
357
+
.name = "gpu_cc_sleep_clk",
358
+
.ops = &clk_branch2_ops,
359
+
},
360
+
},
361
+
};
362
+
363
+
static struct clk_regmap *gpu_cc_sc8280xp_clocks[] = {
364
+
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
365
+
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
366
+
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
367
+
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
368
+
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
369
+
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
370
+
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
371
+
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
372
+
[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
373
+
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
374
+
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
375
+
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
376
+
[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
377
+
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
378
+
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
379
+
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
380
+
};
381
+
382
+
static struct gdsc cx_gdsc = {
383
+
.gdscr = 0x106c,
384
+
.gds_hw_ctrl = 0x1540,
385
+
.pd = {
386
+
.name = "cx_gdsc",
387
+
},
388
+
.pwrsts = PWRSTS_OFF_ON,
389
+
.flags = VOTABLE | RETAIN_FF_ENABLE,
390
+
};
391
+
392
+
static struct gdsc gx_gdsc = {
393
+
.gdscr = 0x100c,
394
+
.clamp_io_ctrl = 0x1508,
395
+
.pd = {
396
+
.name = "gx_gdsc",
397
+
.power_on = gdsc_gx_do_nothing_enable,
398
+
},
399
+
.pwrsts = PWRSTS_OFF_ON,
400
+
.flags = CLAMP_IO | RETAIN_FF_ENABLE,
401
+
};
402
+
403
+
static struct gdsc *gpu_cc_sc8280xp_gdscs[] = {
404
+
[GPU_CC_CX_GDSC] = &cx_gdsc,
405
+
[GPU_CC_GX_GDSC] = &gx_gdsc,
406
+
};
407
+
408
+
static const struct regmap_config gpu_cc_sc8280xp_regmap_config = {
409
+
.reg_bits = 32,
410
+
.reg_stride = 4,
411
+
.val_bits = 32,
412
+
.max_register = 0x8030,
413
+
.fast_io = true,
414
+
};
415
+
416
+
static struct qcom_cc_desc gpu_cc_sc8280xp_desc = {
417
+
.config = &gpu_cc_sc8280xp_regmap_config,
418
+
.clks = gpu_cc_sc8280xp_clocks,
419
+
.num_clks = ARRAY_SIZE(gpu_cc_sc8280xp_clocks),
420
+
.gdscs = gpu_cc_sc8280xp_gdscs,
421
+
.num_gdscs = ARRAY_SIZE(gpu_cc_sc8280xp_gdscs),
422
+
};
423
+
424
+
static int gpu_cc_sc8280xp_probe(struct platform_device *pdev)
425
+
{
426
+
struct regmap *regmap;
427
+
428
+
regmap = qcom_cc_map(pdev, &gpu_cc_sc8280xp_desc);
429
+
if (IS_ERR(regmap))
430
+
return PTR_ERR(regmap);
431
+
432
+
clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
433
+
clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
434
+
435
+
/*
436
+
* Keep the clocks always-ON
437
+
* GPU_CC_CB_CLK, GPU_CC_CXO_CLK
438
+
*/
439
+
regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0));
440
+
regmap_update_bits(regmap, 0x109c, BIT(0), BIT(0));
441
+
442
+
return qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap);
443
+
}
444
+
445
+
static const struct of_device_id gpu_cc_sc8280xp_match_table[] = {
446
+
{ .compatible = "qcom,sc8280xp-gpucc" },
447
+
{ }
448
+
};
449
+
MODULE_DEVICE_TABLE(of, gpu_cc_sc8280xp_match_table);
450
+
451
+
static struct platform_driver gpu_cc_sc8280xp_driver = {
452
+
.probe = gpu_cc_sc8280xp_probe,
453
+
.driver = {
454
+
.name = "gpu_cc-sc8280xp",
455
+
.of_match_table = gpu_cc_sc8280xp_match_table,
456
+
},
457
+
};
458
+
module_platform_driver(gpu_cc_sc8280xp_driver);
459
+
460
+
MODULE_DESCRIPTION("Qualcomm SC8280XP GPU clock controller");
461
+
MODULE_LICENSE("GPL");