Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'soc-fixes-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC fixes from Arnd Bergmann:
"The main code change is a revert of the Raspberry Pi RP1 overlay
support that was decided to not be ready.
The other fixes are all for devicetree sources:
- ethernet configuration on ixp42x-actiontec-mi424wr is board
revision specific
- validation warning fixes for imx27/imx51/imx6, hikey960 and k3
- Minor corrections across imx8 boards, addressing all types of
issues with interrups, dma, ethernet and clock settings, all simple
one-line changes"
* tag 'soc-fixes-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits)
arm64: dts: hisilicon: hikey960: Drop "snps,gctl-reset-quirk" and "snps,tx_de_emphasis*" properties
Documentation/process: maintainer-soc: Mark 'make' as commands
Documentation/process: maintainer-soc: Be more explicit about defconfig
arm64: dts: mba8mx: Fix Ethernet PHY IRQ support
arm64: dts: imx8qm-ss-dma: correct the dma channels of lpuart
arm64: dts: imx8mp: Fix LAN8740Ai PHY reference clock on DH electronics i.MX8M Plus DHCOM
arm64: dts: freescale: tx8p-ml81: fix eqos nvmem-cells
arm64: dts: freescale: moduline-display: fix compatible
dt-bindings: arm: fsl: moduline-display: fix compatible
ARM: dts: imx6q-ba16: fix RTC interrupt level
arm64: dts: freescale: imx95-toradex-smarc: fix SMARC_SDIO_WP label position
arm64: dts: freescale: imx95-toradex-smarc: use edge trigger for ethphy1 interrupt
arm64: dts: add off-on-delay-us for usdhc2 regulator
arm64: dts: imx8qm-mek: correct the light sensor interrupt type to low level
ARM: dts: nxp: imx: Fix mc13xxx LED node names
arm64: dts: imx95: correct I3C2 pclk to IMX95_CLK_BUSWAKEUP
MAINTAINERS: Fix a linusw mail address
arm64: dts: broadcom: rp1: drop RP1 overlay
arm64: dts: broadcom: bcm2712: fix RP1 endpoint PCI topology
misc: rp1: drop overlay support
...
+111
-150
+8
-1
Documentation/devicetree/bindings/arm/fsl.yaml
+8
-1
Documentation/devicetree/bindings/arm/fsl.yaml
···
1105
1105
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
1106
1106
- gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
1107
1107
- gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board
1108
-
- gocontroll,moduline-display # GOcontroll Moduline Display controller
1109
1108
- prt,prt8ml # Protonic PRT8ML
1110
1109
- skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate
1111
1110
- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
···
1161
1162
- enum:
1162
1163
- engicam,icore-mx8mp-edimm2.2 # i.MX8MP Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit
1163
1164
- const: engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM
1165
+
- const: fsl,imx8mp
1166
+
1167
+
- description: Ka-Ro TX8P-ML81 SoM based boards
1168
+
items:
1169
+
- enum:
1170
+
- gocontroll,moduline-display
1171
+
- gocontroll,moduline-display-106
1172
+
- const: karo,tx8p-ml81
1164
1173
- const: fsl,imx8mp
1165
1174
1166
1175
- description: Kontron i.MX8MP OSM-S SoM based Boards
+7
-1
Documentation/devicetree/bindings/misc/pci1de4,1.yaml
+7
-1
Documentation/devicetree/bindings/misc/pci1de4,1.yaml
···
25
25
items:
26
26
- const: pci1de4,1
27
27
28
+
reg:
29
+
maxItems: 1
30
+
description: The PCI Bus-Device-Function address.
31
+
28
32
'#interrupt-cells':
29
33
const: 2
30
34
description: |
···
105
101
106
102
required:
107
103
- compatible
104
+
- reg
108
105
- '#interrupt-cells'
109
106
- interrupt-controller
110
107
- pci-ep-bus@1
···
116
111
#address-cells = <3>;
117
112
#size-cells = <2>;
118
113
119
-
rp1@0,0 {
114
+
dev@0,0 {
120
115
compatible = "pci1de4,1";
116
+
reg = <0x10000 0x0 0x0 0x0 0x0>;
121
117
ranges = <0x01 0x00 0x00000000 0x82010000 0x00 0x00 0x00 0x400000>;
122
118
#address-cells = <3>;
123
119
#size-cells = <2>;
+6
-4
Documentation/process/maintainer-soc.rst
+6
-4
Documentation/process/maintainer-soc.rst
···
57
57
58
58
All typical platform related patches should be sent via SoC submaintainers
59
59
(platform-specific maintainers). This includes also changes to per-platform or
60
-
shared defconfigs (scripts/get_maintainer.pl might not provide correct
61
-
addresses in such case).
60
+
shared defconfigs. Note that scripts/get_maintainer.pl might not provide
61
+
correct addresses for the shared defconfig, so ignore its output and manually
62
+
create CC-list based on MAINTAINERS file or use something like
63
+
``scripts/get_maintainer.pl -f drivers/soc/FOO/``).
62
64
63
65
Submitting Patches to the Main SoC Maintainers
64
66
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
···
116
114
Usually the branch that includes a driver change will also include the
117
115
corresponding change to the devicetree binding description, to ensure they are
118
116
in fact compatible. This means that the devicetree branch can end up causing
119
-
warnings in the "make dtbs_check" step. If a devicetree change depends on
117
+
warnings in the ``make dtbs_check`` step. If a devicetree change depends on
120
118
missing additions to a header file in include/dt-bindings/, it will fail the
121
-
"make dtbs" step and not get merged.
119
+
``make dtbs`` step and not get merged.
122
120
123
121
There are multiple ways to deal with this:
124
122
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
2012
2012
M: Arnd Bergmann <arnd@arndb.de>
2013
2013
M: Krzysztof Kozlowski <krzk@kernel.org>
2014
2014
M: Alexandre Belloni <alexandre.belloni@bootlin.com>
2015
-
M: Linus Walleij <linus.walleij@linaro.org>
2015
+
M: Linus Walleij <linusw@kernel.org>
2016
2016
R: Drew Fustini <fustini@kernel.org>
2017
2017
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2018
2018
L: soc@lists.linux.dev
+11
arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts
+11
arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts
···
12
12
model = "Actiontec MI424WR rev A/C";
13
13
compatible = "actiontec,mi424wr-ac", "intel,ixp42x";
14
14
15
+
/* Connect the switch to EthC */
16
+
spi {
17
+
ethernet-switch@0 {
18
+
ethernet-ports {
19
+
ethernet-port@4 {
20
+
ethernet = <ðc>;
21
+
};
22
+
};
23
+
};
24
+
};
25
+
15
26
soc {
16
27
/* EthB used for WAN */
17
28
ethernet@c8009000 {
+11
arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts
+11
arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts
···
12
12
model = "Actiontec MI424WR rev D";
13
13
compatible = "actiontec,mi424wr-d", "intel,ixp42x";
14
14
15
+
/* Connect the switch to EthB */
16
+
spi {
17
+
ethernet-switch@0 {
18
+
ethernet-ports {
19
+
ethernet-port@4 {
20
+
ethernet = <ðb>;
21
+
};
22
+
};
23
+
};
24
+
};
25
+
15
26
soc {
16
27
/* EthB used for LAN */
17
28
ethernet@c8009000 {
-1
arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi
-1
arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi
+4
-4
arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts
+4
-4
arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts
···
248
248
linux,default-trigger = "nand-disk";
249
249
};
250
250
251
-
ledg3: led@10 {
252
-
reg = <10>;
251
+
ledg3: led@a {
252
+
reg = <0xa>;
253
253
label = "system:green3:live";
254
254
linux,default-trigger = "heartbeat";
255
255
};
256
256
257
-
ledb3: led@11 {
258
-
reg = <11>;
257
+
ledb3: led@b {
258
+
reg = <0xb>;
259
259
label = "system:blue3:cpu";
260
260
linux,default-trigger = "cpu0";
261
261
};
+2
-2
arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts
+2
-2
arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts
···
398
398
#size-cells = <0>;
399
399
led-control = <0x0 0x0 0x3f83f8 0x0>;
400
400
401
-
sysled0@3 {
401
+
led@3 {
402
402
reg = <3>;
403
403
label = "system:green:status";
404
404
linux,default-trigger = "default-on";
405
405
};
406
406
407
-
sysled1@4 {
407
+
led@4 {
408
408
reg = <4>;
409
409
label = "system:green:act";
410
410
linux,default-trigger = "heartbeat";
+2
-2
arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts
+2
-2
arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts
···
225
225
#size-cells = <0>;
226
226
led-control = <0x0 0x0 0x3f83f8 0x0>;
227
227
228
-
sysled3: led3@3 {
228
+
sysled3: led@3 {
229
229
reg = <3>;
230
230
label = "system:red:power";
231
231
linux,default-trigger = "default-on";
232
232
};
233
233
234
-
sysled4: led4@4 {
234
+
sysled4: led@4 {
235
235
reg = <4>;
236
236
label = "system:green:act";
237
237
linux,default-trigger = "heartbeat";
+2
-2
arch/arm/boot/dts/nxp/imx/imx51-zii-scu3-esb.dts
+2
-2
arch/arm/boot/dts/nxp/imx/imx51-zii-scu3-esb.dts
···
153
153
#size-cells = <0>;
154
154
led-control = <0x0 0x0 0x3f83f8 0x0>;
155
155
156
-
sysled3: led3@3 {
156
+
sysled3: led@3 {
157
157
reg = <3>;
158
158
label = "system:red:power";
159
159
linux,default-trigger = "default-on";
160
160
};
161
161
162
-
sysled4: led4@4 {
162
+
sysled4: led@4 {
163
163
reg = <4>;
164
164
label = "system:green:act";
165
165
linux,default-trigger = "heartbeat";
+1
-1
arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi
+1
-1
arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi
+1
-3
arch/arm64/boot/dts/broadcom/Makefile
+1
-3
arch/arm64/boot/dts/broadcom/Makefile
···
7
7
bcm2711-rpi-4-b.dtb \
8
8
bcm2711-rpi-cm4-io.dtb \
9
9
bcm2712-rpi-5-b.dtb \
10
-
bcm2712-rpi-5-b-ovl-rp1.dtb \
11
10
bcm2712-d-rpi-5-b.dtb \
12
11
bcm2837-rpi-2-b.dtb \
13
12
bcm2837-rpi-3-a-plus.dtb \
14
13
bcm2837-rpi-3-b.dtb \
15
14
bcm2837-rpi-3-b-plus.dtb \
16
15
bcm2837-rpi-cm3-io3.dtb \
17
-
bcm2837-rpi-zero-2-w.dtb \
18
-
rp1.dtbo
16
+
bcm2837-rpi-zero-2-w.dtb
19
17
20
18
subdir-y += bcmbca
21
19
subdir-y += northstar2
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
+26
-13
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
+26
-13
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
···
1
1
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
2
/*
3
-
* bcm2712-rpi-5-b-ovl-rp1.dts is the overlay-ready DT which will make
4
-
* the RP1 driver to load the RP1 dtb overlay at runtime, while
5
-
* bcm2712-rpi-5-b.dts (this file) is the fully defined one (i.e. it
6
-
* already contains RP1 node, so no overlay is loaded nor needed).
7
-
* This file is intended to host the override nodes for the RP1 peripherals,
8
-
* e.g. to declare the phy of the ethernet interface or the custom pin setup
9
-
* for several RP1 peripherals.
10
-
* This in turn is due to the fact that there's no current generic
11
-
* infrastructure to reference nodes (i.e. the nodes in rp1-common.dtsi) that
12
-
* are not yet defined in the DT since they are loaded at runtime via overlay.
3
+
* As a loose attempt to separate RP1 customizations from SoC peripherals
4
+
* definitioni, this file is intended to host the override nodes for the RP1
5
+
* peripherals, e.g. to declare the phy of the ethernet interface or custom
6
+
* pin setup.
13
7
* All other nodes that do not have anything to do with RP1 should be added
14
-
* to the included bcm2712-rpi-5-b-ovl-rp1.dts instead.
8
+
* to the included bcm2712-rpi-5-b-base.dtsi instead.
15
9
*/
16
10
17
11
/dts-v1/;
18
12
19
-
#include "bcm2712-rpi-5-b-ovl-rp1.dts"
13
+
#include "bcm2712-rpi-5-b-base.dtsi"
20
14
21
15
/ {
22
16
aliases {
···
19
25
};
20
26
21
27
&pcie2 {
22
-
#include "rp1-nexus.dtsi"
28
+
pci@0,0 {
29
+
reg = <0x0 0x0 0x0 0x0 0x0>;
30
+
ranges;
31
+
bus-range = <0 1>;
32
+
device_type = "pci";
33
+
#address-cells = <3>;
34
+
#size-cells = <2>;
35
+
36
+
dev@0,0 {
37
+
compatible = "pci1de4,1";
38
+
reg = <0x10000 0x0 0x0 0x0 0x0>;
39
+
ranges = <0x1 0x0 0x0 0x82010000 0x0 0x0 0x0 0x400000>;
40
+
interrupt-controller;
41
+
#interrupt-cells = <2>;
42
+
#address-cells = <3>;
43
+
#size-cells = <2>;
44
+
45
+
#include "rp1-common.dtsi"
46
+
};
47
+
};
23
48
};
24
49
25
50
&rp1_eth {
-14
arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi
-14
arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi
···
1
-
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
-
3
-
rp1_nexus {
4
-
compatible = "pci1de4,1";
5
-
#address-cells = <3>;
6
-
#size-cells = <2>;
7
-
ranges = <0x01 0x00 0x00000000
8
-
0x02000000 0x00 0x00000000
9
-
0x0 0x400000>;
10
-
interrupt-controller;
11
-
#interrupt-cells = <2>;
12
-
13
-
#include "rp1-common.dtsi"
14
-
};
-11
arch/arm64/boot/dts/broadcom/rp1.dtso
-11
arch/arm64/boot/dts/broadcom/rp1.dtso
+1
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
+1
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
···
113
113
ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
114
114
compatible = "ethernet-phy-id0007.c110",
115
115
"ethernet-phy-ieee802.3-c22";
116
+
clocks = <&clk IMX8MP_CLK_ENET_QOS>;
116
117
interrupt-parent = <&gpio3>;
117
118
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
118
119
pinctrl-0 = <&pinctrl_ethphy0>;
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts
···
9
9
#include "imx8mp-tx8p-ml81.dtsi"
10
10
11
11
/ {
12
-
compatible = "gocontroll,moduline-display", "fsl,imx8mp";
12
+
compatible = "gocontroll,moduline-display-106", "karo,tx8p-ml81", "fsl,imx8mp";
13
13
chassis-type = "embedded";
14
14
hardware = "Moduline Display V1.06";
15
15
model = "GOcontroll Moduline Display baseboard";
+5
arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
+5
arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
···
47
47
<&clk IMX8MP_SYS_PLL2_100M>,
48
48
<&clk IMX8MP_SYS_PLL2_50M>;
49
49
assigned-clock-rates = <266000000>, <100000000>, <50000000>;
50
+
nvmem-cells = <ð_mac1>;
50
51
phy-handle = <ðphy0>;
51
52
phy-mode = "rmii";
52
53
pinctrl-0 = <&pinctrl_eqos>;
···
74
73
smsc,disable-energy-detect;
75
74
};
76
75
};
76
+
};
77
+
78
+
&fec {
79
+
nvmem-cells = <ð_mac2>;
77
80
};
78
81
79
82
&gpio1 {
+2
-1
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+2
-1
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
···
263
263
regulator-max-microvolt = <3000000>;
264
264
gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
265
265
enable-active-high;
266
+
off-on-delay-us = <4800>;
266
267
};
267
268
268
269
reg_audio: regulator-audio {
···
577
576
compatible = "isil,isl29023";
578
577
reg = <0x44>;
579
578
interrupt-parent = <&lsio_gpio4>;
580
-
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
579
+
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
581
580
};
582
581
583
582
pressure-sensor@60 {
+4
-4
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
+4
-4
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
···
172
172
173
173
&lpuart0 {
174
174
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
175
-
dmas = <&edma2 13 0 0>, <&edma2 12 0 1>;
175
+
dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 13 0 0>;
176
176
dma-names = "rx","tx";
177
177
};
178
178
179
179
&lpuart1 {
180
180
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
181
-
dmas = <&edma2 15 0 0>, <&edma2 14 0 1>;
181
+
dmas = <&edma2 14 0 FSL_EDMA_RX>, <&edma2 15 0 0>;
182
182
dma-names = "rx","tx";
183
183
};
184
184
185
185
&lpuart2 {
186
186
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
187
-
dmas = <&edma2 17 0 0>, <&edma2 16 0 1>;
187
+
dmas = <&edma2 16 0 FSL_EDMA_RX>, <&edma2 17 0 0>;
188
188
dma-names = "rx","tx";
189
189
};
190
190
191
191
&lpuart3 {
192
192
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
193
-
dmas = <&edma2 19 0 0>, <&edma2 18 0 1>;
193
+
dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 19 0 0>;
194
194
dma-names = "rx","tx";
195
195
};
196
196
+1
-3
arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi
+1
-3
arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi
···
406
406
"",
407
407
"",
408
408
"",
409
-
"",
410
-
"",
411
409
"SMARC_SDIO_WP";
412
410
};
413
411
···
580
582
ethphy1: ethernet-phy@1 {
581
583
reg = <1>;
582
584
interrupt-parent = <&som_gpio_expander_1>;
583
-
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
585
+
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
584
586
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
585
587
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
586
588
};
+1
-1
arch/arm64/boot/dts/freescale/imx95.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx95.dtsi
···
828
828
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
829
829
#address-cells = <3>;
830
830
#size-cells = <0>;
831
-
clocks = <&scmi_clk IMX95_CLK_BUSAON>,
831
+
clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
832
832
<&scmi_clk IMX95_CLK_I3C2SLOW>;
833
833
clock-names = "pclk", "fast_clk";
834
834
status = "disabled";
+1
-1
arch/arm64/boot/dts/freescale/mba8mx.dtsi
+1
-1
arch/arm64/boot/dts/freescale/mba8mx.dtsi
-3
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
-3
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
···
675
675
snps,lfps_filter_quirk;
676
676
snps,dis_u2_susphy_quirk;
677
677
snps,dis_u3_susphy_quirk;
678
-
snps,tx_de_emphasis_quirk;
679
-
snps,tx_de_emphasis = <1>;
680
678
snps,dis_enblslpm_quirk;
681
-
snps,gctl-reset-quirk;
682
679
usb-role-switch;
683
680
role-switch-default-mode = "host";
684
681
port {
+1
-1
arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso
+1
-1
arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso
+2
-5
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso
+2
-5
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso
···
30
30
<&main_pktdma 0xc206 15>, /* egress slice 1 */
31
31
<&main_pktdma 0xc207 15>, /* egress slice 1 */
32
32
<&main_pktdma 0x4200 15>, /* ingress slice 0 */
33
-
<&main_pktdma 0x4201 15>, /* ingress slice 1 */
34
-
<&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */
35
-
<&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */
33
+
<&main_pktdma 0x4201 15>; /* ingress slice 1 */
36
34
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
37
35
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
38
-
"rx0", "rx1",
39
-
"rxmgm0", "rxmgm1";
36
+
"rx0", "rx1";
40
37
41
38
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
42
39
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
+4
-4
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso
+4
-4
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso
···
20
20
};
21
21
22
22
&main_pmx0 {
23
-
main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-pins-default {
23
+
main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-default-pins {
24
24
pinctrl-single,pins = <
25
25
AM64X_IOPAD(0x0220, PIN_INPUT, 7) /* (D14) SPI1_CS1.GPIO1_48 */
26
26
>;
27
27
};
28
28
29
-
main_spi1_pins_default: main-spi1-pins-default {
29
+
main_spi1_pins_default: main-spi1-default-pins {
30
30
pinctrl-single,pins = <
31
31
AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */
32
32
AM64X_IOPAD(0x021C, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */
···
35
35
>;
36
36
};
37
37
38
-
main_uart3_pins_default: main-uart3-pins-default {
38
+
main_uart3_pins_default: main-uart3-default-pins {
39
39
pinctrl-single,pins = <
40
40
AM64X_IOPAD(0x0048, PIN_INPUT, 2) /* (U20) GPMC0_AD3.UART3_RXD */
41
41
AM64X_IOPAD(0x004c, PIN_OUTPUT, 2) /* (U18) GPMC0_AD4.UART3_TXD */
···
52
52
&main_spi1 {
53
53
pinctrl-names = "default";
54
54
pinctrl-0 = <&main_spi1_pins_default>;
55
-
ti,pindir-d0-out-d1-in = <1>;
55
+
ti,pindir-d0-out-d1-in;
56
56
status = "okay";
57
57
};
58
58
+1
-5
drivers/misc/rp1/Kconfig
+1
-5
drivers/misc/rp1/Kconfig
···
5
5
6
6
config MISC_RP1
7
7
tristate "RaspberryPi RP1 misc device"
8
-
depends on OF_IRQ && OF_OVERLAY && PCI_MSI && PCI_QUIRKS
9
-
select PCI_DYNAMIC_OF_NODES
8
+
depends on OF_IRQ && PCI_MSI
10
9
help
11
10
Support the RP1 peripheral chip found on Raspberry Pi 5 board.
12
11
···
14
15
15
16
The driver is responsible for enabling the DT node once the PCIe
16
17
endpoint has been configured, and handling interrupts.
17
-
18
-
This driver uses an overlay to load other drivers to support for
19
-
RP1 internal sub-devices.
+1
-2
drivers/misc/rp1/Makefile
+1
-2
drivers/misc/rp1/Makefile
-25
drivers/misc/rp1/rp1-pci.dtso
-25
drivers/misc/rp1/rp1-pci.dtso
···
1
-
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
-
3
-
/*
4
-
* The dts overlay is included from the dts directory so
5
-
* it can be possible to check it with CHECK_DTBS while
6
-
* also compile it from the driver source directory.
7
-
*/
8
-
9
-
/dts-v1/;
10
-
/plugin/;
11
-
12
-
/ {
13
-
fragment@0 {
14
-
target-path="";
15
-
__overlay__ {
16
-
compatible = "pci1de4,1";
17
-
#address-cells = <3>;
18
-
#size-cells = <2>;
19
-
interrupt-controller;
20
-
#interrupt-cells = <2>;
21
-
22
-
#include "arm64/broadcom/rp1-common.dtsi"
23
-
};
24
-
};
25
-
};
+4
-33
drivers/misc/rp1/rp1_pci.c
+4
-33
drivers/misc/rp1/rp1_pci.c
···
34
34
/* Interrupts */
35
35
#define RP1_INT_END 61
36
36
37
-
/* Embedded dtbo symbols created by cmd_wrap_S_dtb in scripts/Makefile.lib */
38
-
extern char __dtbo_rp1_pci_begin[];
39
-
extern char __dtbo_rp1_pci_end[];
40
-
41
37
struct rp1_dev {
42
38
struct pci_dev *pdev;
43
39
struct irq_domain *domain;
44
40
struct irq_data *pcie_irqds[64];
45
41
void __iomem *bar1;
46
-
int ovcs_id; /* overlay changeset id */
47
42
bool level_triggered_irq[RP1_INT_END];
48
43
};
49
44
···
179
184
180
185
static int rp1_probe(struct pci_dev *pdev, const struct pci_device_id *id)
181
186
{
182
-
u32 dtbo_size = __dtbo_rp1_pci_end - __dtbo_rp1_pci_begin;
183
-
void *dtbo_start = __dtbo_rp1_pci_begin;
184
187
struct device *dev = &pdev->dev;
185
188
struct device_node *rp1_node;
186
-
bool skip_ovl = true;
187
189
struct rp1_dev *rp1;
188
190
int err = 0;
189
191
int i;
190
192
191
-
/*
192
-
* Either use rp1_nexus node if already present in DT, or
193
-
* set a flag to load it from overlay at runtime
194
-
*/
195
-
rp1_node = of_find_node_by_name(NULL, "rp1_nexus");
196
-
if (!rp1_node) {
197
-
rp1_node = dev_of_node(dev);
198
-
skip_ovl = false;
199
-
}
193
+
rp1_node = dev_of_node(dev);
200
194
201
195
if (!rp1_node) {
202
196
dev_err(dev, "Missing of_node for device\n");
···
260
276
rp1_chained_handle_irq, rp1);
261
277
}
262
278
263
-
if (!skip_ovl) {
264
-
err = of_overlay_fdt_apply(dtbo_start, dtbo_size, &rp1->ovcs_id,
265
-
rp1_node);
266
-
if (err)
267
-
goto err_unregister_interrupts;
268
-
}
269
-
270
279
err = of_platform_default_populate(rp1_node, NULL, dev);
271
280
if (err) {
272
281
dev_err_probe(&pdev->dev, err, "Error populating devicetree\n");
273
-
goto err_unload_overlay;
282
+
goto err_unregister_interrupts;
274
283
}
275
284
276
-
if (skip_ovl)
277
-
of_node_put(rp1_node);
285
+
of_node_put(rp1_node);
278
286
279
287
return 0;
280
288
281
-
err_unload_overlay:
282
-
of_overlay_remove(&rp1->ovcs_id);
283
289
err_unregister_interrupts:
284
290
rp1_unregister_interrupts(pdev);
285
291
err_put_node:
286
-
if (skip_ovl)
287
-
of_node_put(rp1_node);
292
+
of_node_put(rp1_node);
288
293
289
294
return err;
290
295
}
291
296
292
297
static void rp1_remove(struct pci_dev *pdev)
293
298
{
294
-
struct rp1_dev *rp1 = pci_get_drvdata(pdev);
295
299
struct device *dev = &pdev->dev;
296
300
297
301
of_platform_depopulate(dev);
298
-
of_overlay_remove(&rp1->ovcs_id);
299
302
rp1_unregister_interrupts(pdev);
300
303
}
301
304
-1
drivers/pci/quirks.c
-1
drivers/pci/quirks.c
···
6308
6308
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
6309
6309
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
6310
6310
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node);
6311
-
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RPI, PCI_DEVICE_ID_RPI_RP1_C0, of_pci_make_dev_node);
6312
6311
6313
6312
/*
6314
6313
* Devices known to require a longer delay before first config space access