tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 apic updates from Thomas Gleixner:
"After stopping the full x86/apic branch, I took some time to go
through the first block of patches again, which are mostly cleanups
and preparatory work for the irqdomain conversion and ioapic hotplug
support.

Unfortunaly one of the real problematic commits was right at the
beginning, so I rebased this portion of the pending patches without
the offenders.

It would be great to get this into 3.19. That makes reworking the
problematic parts simpler. The usual tip testing did not unearth any
issues and it is fully bisectible now.

I'm pretty confident that this wont affect the calmness of the xmas
season.

Changes:
- Split the convoluted io_apic.c code into domain specific parts
(vector, ioapic, msi, htirq)
- Introduce proper helper functions to retrieve irq specific data
instead of open coded dereferencing of pointers
- Preparatory work for ioapic hotplug and irqdomain conversion
- Removal of the non functional pci-ioapic driver
- Removal of unused irq entry stubs
- Make native_smp_prepare_cpus() preemtible to avoid GFP_ATOMIC
allocations for everything which is called from there.
- Small cleanups and fixes"

* 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (36 commits)
iommu/amd: Use helpers to access irq_cfg data structure associated with IRQ
iommu/vt-d: Use helpers to access irq_cfg data structure associated with IRQ
x86: irq_remapping: Use helpers to access irq_cfg data structure associated with IRQ
x86, irq: Use helpers to access irq_cfg data structure associated with IRQ
x86, irq: Make MSI and HT_IRQ indepenent of X86_IO_APIC
x86, irq: Move IRQ initialization routines from io_apic.c into vector.c
x86, irq: Move IOAPIC related declarations from hw_irq.h into io_apic.h
x86, irq: Move HT IRQ related code from io_apic.c into htirq.c
x86, irq: Move PCI MSI related code from io_apic.c into msi.c
x86, irq: Replace printk(KERN_LVL) with pr_lvl() utilities
x86, irq: Make UP version of irq_complete_move() an inline stub
x86, irq: Move local APIC related code from io_apic.c into vector.c
x86, irq: Introduce helpers to access struct irq_cfg
x86, irq: Protect __clear_irq_vector() with vector_lock
x86, irq: Rename local APIC related functions in io_apic.c as apic_xxx()
x86, irq: Refine hw_irq.h to prepare for irqdomain support
x86, irq: Convert irq_2_pin list to generic list
x86, irq: Kill useless parameter 'irq_attr' of IO_APIC_get_PCI_irq_vector()
x86, irq, acpi: Get rid of special handling of GSI for ACPI SCI
x86, irq: Introduce helper to check whether an IOAPIC has been registered
...

Linus Torvalds e589c9e1 4bb9374e

+1607 -1412
+3 -3
arch/x86/Kconfig
··· 883 883 config X86_LOCAL_APIC 884 884 def_bool y 885 885 depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_APIC || PCI_MSI 886 + select GENERIC_IRQ_LEGACY_ALLOC_HWIRQ 886 887 887 888 config X86_IO_APIC 888 - def_bool y 889 - depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_IOAPIC || PCI_MSI 890 - select GENERIC_IRQ_LEGACY_ALLOC_HWIRQ 889 + def_bool X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_IOAPIC 890 + depends on X86_LOCAL_APIC 891 891 select IRQ_DOMAIN 892 892 893 893 config X86_REROUTE_FOR_BROKEN_BOOT_IRQS
+35 -49
arch/x86/include/asm/hw_irq.h
··· 94 94 #define trace_kvm_posted_intr_ipi kvm_posted_intr_ipi 95 95 #endif /* CONFIG_TRACING */ 96 96 97 - /* IOAPIC */ 98 - #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1<<(x)) & io_apic_irqs)) 99 - extern unsigned long io_apic_irqs; 100 - 101 - extern void setup_IO_APIC(void); 102 - extern void disable_IO_APIC(void); 103 - 104 - struct io_apic_irq_attr { 105 - int ioapic; 106 - int ioapic_pin; 107 - int trigger; 108 - int polarity; 109 - }; 110 - 111 - static inline void set_io_apic_irq_attr(struct io_apic_irq_attr *irq_attr, 112 - int ioapic, int ioapic_pin, 113 - int trigger, int polarity) 114 - { 115 - irq_attr->ioapic = ioapic; 116 - irq_attr->ioapic_pin = ioapic_pin; 117 - irq_attr->trigger = trigger; 118 - irq_attr->polarity = polarity; 119 - } 120 - 97 + #ifdef CONFIG_IRQ_REMAP 121 98 /* Intel specific interrupt remapping information */ 122 99 struct irq_2_iommu { 123 100 struct intel_iommu *iommu; ··· 108 131 u16 devid; /* Device ID for IRTE table */ 109 132 u16 index; /* Index into IRTE table*/ 110 133 }; 134 + #endif /* CONFIG_IRQ_REMAP */ 111 135 112 - /* 113 - * This is performance-critical, we want to do it O(1) 114 - * 115 - * Most irqs are mapped 1:1 with pins. 116 - */ 136 + #ifdef CONFIG_X86_LOCAL_APIC 137 + struct irq_data; 138 + 117 139 struct irq_cfg { 118 - struct irq_pin_list *irq_2_pin; 119 140 cpumask_var_t domain; 120 141 cpumask_var_t old_domain; 121 142 u8 vector; ··· 125 150 struct irq_2_irte irq_2_irte; 126 151 }; 127 152 #endif 153 + union { 154 + #ifdef CONFIG_X86_IO_APIC 155 + struct { 156 + struct list_head irq_2_pin; 157 + }; 158 + #endif 159 + }; 128 160 }; 129 161 162 + extern struct irq_cfg *irq_cfg(unsigned int irq); 163 + extern struct irq_cfg *irqd_cfg(struct irq_data *irq_data); 164 + extern struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node); 165 + extern void lock_vector_lock(void); 166 + extern void unlock_vector_lock(void); 130 167 extern int assign_irq_vector(int, struct irq_cfg *, const struct cpumask *); 168 + extern void clear_irq_vector(int irq, struct irq_cfg *cfg); 169 + extern void setup_vector_irq(int cpu); 170 + #ifdef CONFIG_SMP 131 171 extern void send_cleanup_vector(struct irq_cfg *); 172 + extern void irq_complete_move(struct irq_cfg *cfg); 173 + #else 174 + static inline void send_cleanup_vector(struct irq_cfg *c) { } 175 + static inline void irq_complete_move(struct irq_cfg *c) { } 176 + #endif 132 177 133 - struct irq_data; 134 - int __ioapic_set_affinity(struct irq_data *, const struct cpumask *, 135 - unsigned int *dest_id); 136 - extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin, struct io_apic_irq_attr *irq_attr); 137 - extern void setup_ioapic_dest(void); 138 - 139 - extern void enable_IO_APIC(void); 178 + extern int apic_retrigger_irq(struct irq_data *data); 179 + extern void apic_ack_edge(struct irq_data *data); 180 + extern int apic_set_affinity(struct irq_data *data, const struct cpumask *mask, 181 + unsigned int *dest_id); 182 + #else /* CONFIG_X86_LOCAL_APIC */ 183 + static inline void lock_vector_lock(void) {} 184 + static inline void unlock_vector_lock(void) {} 185 + #endif /* CONFIG_X86_LOCAL_APIC */ 140 186 141 187 /* Statistics */ 142 188 extern atomic_t irq_err_count; ··· 181 185 extern __visible void smp_invalidate_interrupt(struct pt_regs *); 182 186 #endif 183 187 184 - extern void (*__initconst interrupt[NR_VECTORS-FIRST_EXTERNAL_VECTOR])(void); 188 + extern void (*__initconst interrupt[FIRST_SYSTEM_VECTOR 189 + - FIRST_EXTERNAL_VECTOR])(void); 185 190 #ifdef CONFIG_TRACING 186 191 #define trace_interrupt interrupt 187 192 #endif ··· 192 195 193 196 typedef int vector_irq_t[NR_VECTORS]; 194 197 DECLARE_PER_CPU(vector_irq_t, vector_irq); 195 - extern void setup_vector_irq(int cpu); 196 - 197 - #ifdef CONFIG_X86_IO_APIC 198 - extern void lock_vector_lock(void); 199 - extern void unlock_vector_lock(void); 200 - extern void __setup_vector_irq(int cpu); 201 - #else 202 - static inline void lock_vector_lock(void) {} 203 - static inline void unlock_vector_lock(void) {} 204 - static inline void __setup_vector_irq(int cpu) {} 205 - #endif 206 198 207 199 #endif /* !ASSEMBLY_ */ 208 200
+25 -10
arch/x86/include/asm/io_apic.h
··· 132 132 /* -1 if "noapic" boot option passed */ 133 133 extern int noioapicreroute; 134 134 135 + extern unsigned long io_apic_irqs; 136 + 137 + #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs)) 138 + 135 139 /* 136 140 * If we use the IO-APIC for IRQ routing, disable automatic 137 141 * assignment of PCI IRQ's. ··· 143 139 #define io_apic_assign_pci_irqs \ 144 140 (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs) 145 141 146 - struct io_apic_irq_attr; 147 142 struct irq_cfg; 148 143 extern void ioapic_insert_resources(void); 144 + extern int arch_early_ioapic_init(void); 149 145 150 146 extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *, 151 147 unsigned int, int, 152 148 struct io_apic_irq_attr *); 153 149 extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg); 154 150 155 - extern void native_compose_msi_msg(struct pci_dev *pdev, 156 - unsigned int irq, unsigned int dest, 157 - struct msi_msg *msg, u8 hpet_id); 158 151 extern void native_eoi_ioapic_pin(int apic, int pin, int vector); 159 152 160 153 extern int save_ioapic_entries(void); ··· 160 159 161 160 extern void setup_ioapic_ids_from_mpc(void); 162 161 extern void setup_ioapic_ids_from_mpc_nocheck(void); 162 + 163 + struct io_apic_irq_attr { 164 + int ioapic; 165 + int ioapic_pin; 166 + int trigger; 167 + int polarity; 168 + }; 163 169 164 170 enum ioapic_domain_type { 165 171 IOAPIC_DOMAIN_INVALID, ··· 196 188 extern u32 mp_pin_to_gsi(int ioapic, int pin); 197 189 extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags); 198 190 extern void mp_unmap_irq(int irq); 199 - extern void __init mp_register_ioapic(int id, u32 address, u32 gsi_base, 200 - struct ioapic_domain_cfg *cfg); 191 + extern int mp_register_ioapic(int id, u32 address, u32 gsi_base, 192 + struct ioapic_domain_cfg *cfg); 193 + extern int mp_unregister_ioapic(u32 gsi_base); 194 + extern int mp_ioapic_registered(u32 gsi_base); 201 195 extern int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq, 202 196 irq_hw_number_t hwirq); 203 197 extern void mp_irqdomain_unmap(struct irq_domain *domain, unsigned int virq); ··· 237 227 238 228 extern void io_apic_eoi(unsigned int apic, unsigned int vector); 239 229 240 - extern bool mp_should_keep_irq(struct device *dev); 241 - 230 + extern void setup_IO_APIC(void); 231 + extern void enable_IO_APIC(void); 232 + extern void disable_IO_APIC(void); 233 + extern void setup_ioapic_dest(void); 234 + extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin); 235 + extern void print_IO_APICs(void); 242 236 #else /* !CONFIG_X86_IO_APIC */ 243 237 238 + #define IO_APIC_IRQ(x) 0 244 239 #define io_apic_assign_pci_irqs 0 245 240 #define setup_ioapic_ids_from_mpc x86_init_noop 246 241 static inline void ioapic_insert_resources(void) { } 242 + static inline int arch_early_ioapic_init(void) { return 0; } 243 + static inline void print_IO_APICs(void) {} 247 244 #define gsi_top (NR_IRQS_LEGACY) 248 245 static inline int mp_find_ioapic(u32 gsi) { return 0; } 249 246 static inline u32 mp_pin_to_gsi(int ioapic, int pin) { return UINT_MAX; } 250 247 static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags) { return gsi; } 251 248 static inline void mp_unmap_irq(int irq) { } 252 - static inline bool mp_should_keep_irq(struct device *dev) { return 1; } 253 249 254 250 static inline int save_ioapic_entries(void) 255 251 { ··· 278 262 #define native_io_apic_print_entries NULL 279 263 #define native_ioapic_set_affinity NULL 280 264 #define native_setup_ioapic_entry NULL 281 - #define native_compose_msi_msg NULL 282 265 #define native_eoi_ioapic_pin NULL 283 266 #endif 284 267
+6
arch/x86/include/asm/irq_vectors.h
··· 126 126 127 127 #define NR_VECTORS 256 128 128 129 + #ifdef CONFIG_X86_LOCAL_APIC 130 + #define FIRST_SYSTEM_VECTOR LOCAL_TIMER_VECTOR 131 + #else 132 + #define FIRST_SYSTEM_VECTOR NR_VECTORS 133 + #endif 134 + 129 135 #define FPU_IRQ 13 130 136 131 137 #define FIRST_VM86_IRQ 3
+3
arch/x86/include/asm/pci.h
··· 96 96 #ifdef CONFIG_PCI_MSI 97 97 /* implemented in arch/x86/kernel/apic/io_apic. */ 98 98 struct msi_desc; 99 + void native_compose_msi_msg(struct pci_dev *pdev, unsigned int irq, 100 + unsigned int dest, struct msi_msg *msg, u8 hpet_id); 99 101 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); 100 102 void native_teardown_msi_irq(unsigned int irq); 101 103 void native_restore_msi_irqs(struct pci_dev *dev); 102 104 int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, 103 105 unsigned int irq_base, unsigned int irq_offset); 104 106 #else 107 + #define native_compose_msi_msg NULL 105 108 #define native_setup_msi_irqs NULL 106 109 #define native_teardown_msi_irq NULL 107 110 #endif
+2
arch/x86/include/asm/pci_x86.h
··· 93 93 extern int (*pcibios_enable_irq)(struct pci_dev *dev); 94 94 extern void (*pcibios_disable_irq)(struct pci_dev *dev); 95 95 96 + extern bool mp_should_keep_irq(struct device *dev); 97 + 96 98 struct pci_raw_ops { 97 99 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn, 98 100 int reg, int len, u32 *val);
+85 -14
arch/x86/kernel/acpi/boot.c
··· 76 76 static u64 acpi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE; 77 77 #endif 78 78 79 + /* 80 + * Locks related to IOAPIC hotplug 81 + * Hotplug side: 82 + * ->device_hotplug_lock 83 + * ->acpi_ioapic_lock 84 + * ->ioapic_lock 85 + * Interrupt mapping side: 86 + * ->acpi_ioapic_lock 87 + * ->ioapic_mutex 88 + * ->ioapic_lock 89 + */ 90 + static DEFINE_MUTEX(acpi_ioapic_lock); 91 + 79 92 /* -------------------------------------------------------------------------- 80 93 Boot-time Configuration 81 94 -------------------------------------------------------------------------- */ ··· 408 395 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC) 409 396 return gsi; 410 397 411 - /* Don't set up the ACPI SCI because it's already set up */ 412 - if (acpi_gbl_FADT.sci_interrupt == gsi) 413 - return mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC); 414 - 415 398 trigger = trigger == ACPI_EDGE_SENSITIVE ? 0 : 1; 416 399 polarity = polarity == ACPI_ACTIVE_HIGH ? 0 : 1; 417 400 node = dev ? dev_to_node(dev) : NUMA_NO_NODE; ··· 420 411 if (irq < 0) 421 412 return irq; 422 413 423 - if (enable_update_mptable) 414 + /* Don't set up the ACPI SCI because it's already set up */ 415 + if (enable_update_mptable && acpi_gbl_FADT.sci_interrupt != gsi) 424 416 mp_config_acpi_gsi(dev, gsi, trigger, polarity); 425 417 426 418 return irq; ··· 432 422 int irq; 433 423 434 424 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC) 435 - return; 436 - 437 - if (acpi_gbl_FADT.sci_interrupt == gsi) 438 425 return; 439 426 440 427 irq = mp_map_gsi_to_irq(gsi, 0); ··· 616 609 if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) { 617 610 *irqp = gsi; 618 611 } else { 612 + mutex_lock(&acpi_ioapic_lock); 619 613 irq = mp_map_gsi_to_irq(gsi, 620 614 IOAPIC_MAP_ALLOC | IOAPIC_MAP_CHECK); 615 + mutex_unlock(&acpi_ioapic_lock); 621 616 if (irq < 0) 622 617 return -1; 623 618 *irqp = irq; ··· 659 650 int irq = gsi; 660 651 661 652 #ifdef CONFIG_X86_IO_APIC 653 + mutex_lock(&acpi_ioapic_lock); 662 654 irq = mp_register_gsi(dev, gsi, trigger, polarity); 655 + mutex_unlock(&acpi_ioapic_lock); 663 656 #endif 664 657 665 658 return irq; ··· 670 659 static void acpi_unregister_gsi_ioapic(u32 gsi) 671 660 { 672 661 #ifdef CONFIG_X86_IO_APIC 662 + mutex_lock(&acpi_ioapic_lock); 673 663 mp_unregister_gsi(gsi); 664 + mutex_unlock(&acpi_ioapic_lock); 674 665 #endif 675 666 } 676 667 ··· 703 690 } 704 691 EXPORT_SYMBOL_GPL(acpi_unregister_gsi); 705 692 693 + #ifdef CONFIG_X86_LOCAL_APIC 706 694 static void __init acpi_set_irq_model_ioapic(void) 707 695 { 708 696 acpi_irq_model = ACPI_IRQ_MODEL_IOAPIC; ··· 711 697 __acpi_unregister_gsi = acpi_unregister_gsi_ioapic; 712 698 acpi_ioapic = 1; 713 699 } 700 + #endif 714 701 715 702 /* 716 703 * ACPI based hotplug support for CPU ··· 774 759 775 760 int acpi_register_ioapic(acpi_handle handle, u64 phys_addr, u32 gsi_base) 776 761 { 777 - /* TBD */ 778 - return -EINVAL; 779 - } 762 + int ret = -ENOSYS; 763 + #ifdef CONFIG_ACPI_HOTPLUG_IOAPIC 764 + int ioapic_id; 765 + u64 addr; 766 + struct ioapic_domain_cfg cfg = { 767 + .type = IOAPIC_DOMAIN_DYNAMIC, 768 + .ops = &acpi_irqdomain_ops, 769 + }; 780 770 771 + ioapic_id = acpi_get_ioapic_id(handle, gsi_base, &addr); 772 + if (ioapic_id < 0) { 773 + unsigned long long uid; 774 + acpi_status status; 775 + 776 + status = acpi_evaluate_integer(handle, METHOD_NAME__UID, 777 + NULL, &uid); 778 + if (ACPI_FAILURE(status)) { 779 + acpi_handle_warn(handle, "failed to get IOAPIC ID.\n"); 780 + return -EINVAL; 781 + } 782 + ioapic_id = (int)uid; 783 + } 784 + 785 + mutex_lock(&acpi_ioapic_lock); 786 + ret = mp_register_ioapic(ioapic_id, phys_addr, gsi_base, &cfg); 787 + mutex_unlock(&acpi_ioapic_lock); 788 + #endif 789 + 790 + return ret; 791 + } 781 792 EXPORT_SYMBOL(acpi_register_ioapic); 782 793 783 794 int acpi_unregister_ioapic(acpi_handle handle, u32 gsi_base) 784 795 { 785 - /* TBD */ 786 - return -EINVAL; 787 - } 796 + int ret = -ENOSYS; 788 797 798 + #ifdef CONFIG_ACPI_HOTPLUG_IOAPIC 799 + mutex_lock(&acpi_ioapic_lock); 800 + ret = mp_unregister_ioapic(gsi_base); 801 + mutex_unlock(&acpi_ioapic_lock); 802 + #endif 803 + 804 + return ret; 805 + } 789 806 EXPORT_SYMBOL(acpi_unregister_ioapic); 807 + 808 + /** 809 + * acpi_ioapic_registered - Check whether IOAPIC assoicatied with @gsi_base 810 + * has been registered 811 + * @handle: ACPI handle of the IOAPIC deivce 812 + * @gsi_base: GSI base associated with the IOAPIC 813 + * 814 + * Assume caller holds some type of lock to serialize acpi_ioapic_registered() 815 + * with acpi_register_ioapic()/acpi_unregister_ioapic(). 816 + */ 817 + int acpi_ioapic_registered(acpi_handle handle, u32 gsi_base) 818 + { 819 + int ret = 0; 820 + 821 + #ifdef CONFIG_ACPI_HOTPLUG_IOAPIC 822 + mutex_lock(&acpi_ioapic_lock); 823 + ret = mp_ioapic_registered(gsi_base); 824 + mutex_unlock(&acpi_ioapic_lock); 825 + #endif 826 + 827 + return ret; 828 + } 790 829 791 830 static int __init acpi_parse_sbf(struct acpi_table_header *table) 792 831 { ··· 1254 1185 /* 1255 1186 * Parse MADT IO-APIC entries 1256 1187 */ 1188 + mutex_lock(&acpi_ioapic_lock); 1257 1189 error = acpi_parse_madt_ioapic_entries(); 1190 + mutex_unlock(&acpi_ioapic_lock); 1258 1191 if (!error) { 1259 1192 acpi_set_irq_model_ioapic(); 1260 1193
+3 -1
arch/x86/kernel/apic/Makefile
··· 2 2 # Makefile for local APIC drivers and for the IO-APIC code 3 3 # 4 4 5 - obj-$(CONFIG_X86_LOCAL_APIC) += apic.o apic_noop.o ipi.o 5 + obj-$(CONFIG_X86_LOCAL_APIC) += apic.o apic_noop.o ipi.o vector.o 6 6 obj-y += hw_nmi.o 7 7 8 8 obj-$(CONFIG_X86_IO_APIC) += io_apic.o 9 + obj-$(CONFIG_PCI_MSI) += msi.o 10 + obj-$(CONFIG_HT_IRQ) += htirq.o 9 11 obj-$(CONFIG_SMP) += ipi.o 10 12 11 13 ifeq ($(CONFIG_X86_64),y)
+12 -10
arch/x86/kernel/apic/apic.c
··· 196 196 int local_apic_timer_c2_ok; 197 197 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 198 198 199 - int first_system_vector = 0xfe; 199 + int first_system_vector = FIRST_SYSTEM_VECTOR; 200 200 201 201 /* 202 202 * Debug level, exported for io_apic.c ··· 1930 1930 /* 1931 1931 * This interrupt should _never_ happen with our APIC/SMP architecture 1932 1932 */ 1933 - static inline void __smp_spurious_interrupt(void) 1933 + static inline void __smp_spurious_interrupt(u8 vector) 1934 1934 { 1935 1935 u32 v; 1936 1936 ··· 1939 1939 * if it is a vectored one. Just in case... 1940 1940 * Spurious interrupts should not be ACKed. 1941 1941 */ 1942 - v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1943 - if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1942 + v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 1943 + if (v & (1 << (vector & 0x1f))) 1944 1944 ack_APIC_irq(); 1945 1945 1946 1946 inc_irq_stat(irq_spurious_count); 1947 1947 1948 1948 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1949 - pr_info("spurious APIC interrupt on CPU#%d, " 1950 - "should never happen.\n", smp_processor_id()); 1949 + pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 1950 + "should never happen.\n", vector, smp_processor_id()); 1951 1951 } 1952 1952 1953 1953 __visible void smp_spurious_interrupt(struct pt_regs *regs) 1954 1954 { 1955 1955 entering_irq(); 1956 - __smp_spurious_interrupt(); 1956 + __smp_spurious_interrupt(~regs->orig_ax); 1957 1957 exiting_irq(); 1958 1958 } 1959 1959 1960 1960 __visible void smp_trace_spurious_interrupt(struct pt_regs *regs) 1961 1961 { 1962 + u8 vector = ~regs->orig_ax; 1963 + 1962 1964 entering_irq(); 1963 - trace_spurious_apic_entry(SPURIOUS_APIC_VECTOR); 1964 - __smp_spurious_interrupt(); 1965 - trace_spurious_apic_exit(SPURIOUS_APIC_VECTOR); 1965 + trace_spurious_apic_entry(vector); 1966 + __smp_spurious_interrupt(vector); 1967 + trace_spurious_apic_exit(vector); 1966 1968 exiting_irq(); 1967 1969 } 1968 1970
+107
arch/x86/kernel/apic/htirq.c
··· 1 + /* 2 + * Support Hypertransport IRQ 3 + * 4 + * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo 5 + * Moved from arch/x86/kernel/apic/io_apic.c. 6 + * 7 + * This program is free software; you can redistribute it and/or modify 8 + * it under the terms of the GNU General Public License version 2 as 9 + * published by the Free Software Foundation. 10 + */ 11 + #include <linux/mm.h> 12 + #include <linux/interrupt.h> 13 + #include <linux/init.h> 14 + #include <linux/device.h> 15 + #include <linux/pci.h> 16 + #include <linux/htirq.h> 17 + #include <asm/hw_irq.h> 18 + #include <asm/apic.h> 19 + #include <asm/hypertransport.h> 20 + 21 + /* 22 + * Hypertransport interrupt support 23 + */ 24 + static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) 25 + { 26 + struct ht_irq_msg msg; 27 + 28 + fetch_ht_irq_msg(irq, &msg); 29 + 30 + msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); 31 + msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); 32 + 33 + msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); 34 + msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); 35 + 36 + write_ht_irq_msg(irq, &msg); 37 + } 38 + 39 + static int 40 + ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) 41 + { 42 + struct irq_cfg *cfg = irqd_cfg(data); 43 + unsigned int dest; 44 + int ret; 45 + 46 + ret = apic_set_affinity(data, mask, &dest); 47 + if (ret) 48 + return ret; 49 + 50 + target_ht_irq(data->irq, dest, cfg->vector); 51 + return IRQ_SET_MASK_OK_NOCOPY; 52 + } 53 + 54 + static struct irq_chip ht_irq_chip = { 55 + .name = "PCI-HT", 56 + .irq_mask = mask_ht_irq, 57 + .irq_unmask = unmask_ht_irq, 58 + .irq_ack = apic_ack_edge, 59 + .irq_set_affinity = ht_set_affinity, 60 + .irq_retrigger = apic_retrigger_irq, 61 + .flags = IRQCHIP_SKIP_SET_WAKE, 62 + }; 63 + 64 + int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) 65 + { 66 + struct irq_cfg *cfg; 67 + struct ht_irq_msg msg; 68 + unsigned dest; 69 + int err; 70 + 71 + if (disable_apic) 72 + return -ENXIO; 73 + 74 + cfg = irq_cfg(irq); 75 + err = assign_irq_vector(irq, cfg, apic->target_cpus()); 76 + if (err) 77 + return err; 78 + 79 + err = apic->cpu_mask_to_apicid_and(cfg->domain, 80 + apic->target_cpus(), &dest); 81 + if (err) 82 + return err; 83 + 84 + msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); 85 + 86 + msg.address_lo = 87 + HT_IRQ_LOW_BASE | 88 + HT_IRQ_LOW_DEST_ID(dest) | 89 + HT_IRQ_LOW_VECTOR(cfg->vector) | 90 + ((apic->irq_dest_mode == 0) ? 91 + HT_IRQ_LOW_DM_PHYSICAL : 92 + HT_IRQ_LOW_DM_LOGICAL) | 93 + HT_IRQ_LOW_RQEOI_EDGE | 94 + ((apic->irq_delivery_mode != dest_LowestPrio) ? 95 + HT_IRQ_LOW_MT_FIXED : 96 + HT_IRQ_LOW_MT_ARBITRATED) | 97 + HT_IRQ_LOW_IRQ_MASKED; 98 + 99 + write_ht_irq_msg(irq, &msg); 100 + 101 + irq_set_chip_and_handler_name(irq, &ht_irq_chip, 102 + handle_edge_irq, "edge"); 103 + 104 + dev_dbg(&dev->dev, "irq %d for HT\n", irq); 105 + 106 + return 0; 107 + }
+236 -1120
arch/x86/kernel/apic/io_apic.c
··· 32 32 #include <linux/module.h> 33 33 #include <linux/syscore_ops.h> 34 34 #include <linux/irqdomain.h> 35 - #include <linux/msi.h> 36 - #include <linux/htirq.h> 37 35 #include <linux/freezer.h> 38 36 #include <linux/kthread.h> 39 37 #include <linux/jiffies.h> /* time_after() */ 40 38 #include <linux/slab.h> 41 39 #include <linux/bootmem.h> 42 - #include <linux/dmar.h> 43 - #include <linux/hpet.h> 44 40 45 41 #include <asm/idle.h> 46 42 #include <asm/io.h> ··· 48 52 #include <asm/dma.h> 49 53 #include <asm/timer.h> 50 54 #include <asm/i8259.h> 51 - #include <asm/msidef.h> 52 - #include <asm/hypertransport.h> 53 55 #include <asm/setup.h> 54 56 #include <asm/irq_remapping.h> 55 - #include <asm/hpet.h> 56 57 #include <asm/hw_irq.h> 57 58 58 59 #include <asm/apic.h> 59 - 60 - #define __apicdebuginit(type) static type __init 61 60 62 61 #define for_each_ioapic(idx) \ 63 62 for ((idx) = 0; (idx) < nr_ioapics; (idx)++) ··· 65 74 for_each_pin((idx), (pin)) 66 75 67 76 #define for_each_irq_pin(entry, head) \ 68 - for (entry = head; entry; entry = entry->next) 77 + list_for_each_entry(entry, &head, list) 69 78 70 79 /* 71 80 * Is the SiS APIC rmw bug present ? ··· 74 83 int sis_apic_bug = -1; 75 84 76 85 static DEFINE_RAW_SPINLOCK(ioapic_lock); 77 - static DEFINE_RAW_SPINLOCK(vector_lock); 78 86 static DEFINE_MUTEX(ioapic_mutex); 79 87 static unsigned int ioapic_dynirq_base; 80 88 static int ioapic_initialized; ··· 102 112 struct ioapic_domain_cfg irqdomain_cfg; 103 113 struct irq_domain *irqdomain; 104 114 struct mp_pin_info *pin_info; 115 + struct resource *iomem_res; 105 116 } ioapics[MAX_IO_APICS]; 106 117 107 118 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver ··· 196 205 } 197 206 early_param("noapic", parse_noapic); 198 207 199 - static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node); 200 - 201 208 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ 202 209 void mp_save_irq(struct mpc_intsrc *m) 203 210 { ··· 217 228 } 218 229 219 230 struct irq_pin_list { 231 + struct list_head list; 220 232 int apic, pin; 221 - struct irq_pin_list *next; 222 233 }; 223 234 224 235 static struct irq_pin_list *alloc_irq_pin_list(int node) ··· 226 237 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); 227 238 } 228 239 229 - int __init arch_early_irq_init(void) 240 + static void alloc_ioapic_saved_registers(int idx) 241 + { 242 + size_t size; 243 + 244 + if (ioapics[idx].saved_registers) 245 + return; 246 + 247 + size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers; 248 + ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL); 249 + if (!ioapics[idx].saved_registers) 250 + pr_err("IOAPIC %d: suspend/resume impossible!\n", idx); 251 + } 252 + 253 + static void free_ioapic_saved_registers(int idx) 254 + { 255 + kfree(ioapics[idx].saved_registers); 256 + ioapics[idx].saved_registers = NULL; 257 + } 258 + 259 + int __init arch_early_ioapic_init(void) 230 260 { 231 261 struct irq_cfg *cfg; 232 262 int i, node = cpu_to_node(0); ··· 253 245 if (!nr_legacy_irqs()) 254 246 io_apic_irqs = ~0UL; 255 247 256 - for_each_ioapic(i) { 257 - ioapics[i].saved_registers = 258 - kzalloc(sizeof(struct IO_APIC_route_entry) * 259 - ioapics[i].nr_registers, GFP_KERNEL); 260 - if (!ioapics[i].saved_registers) 261 - pr_err("IOAPIC %d: suspend/resume impossible!\n", i); 262 - } 248 + for_each_ioapic(i) 249 + alloc_ioapic_saved_registers(i); 263 250 264 251 /* 265 252 * For legacy IRQ's, start with assigning irq0 to irq15 to ··· 267 264 } 268 265 269 266 return 0; 270 - } 271 - 272 - static inline struct irq_cfg *irq_cfg(unsigned int irq) 273 - { 274 - return irq_get_chip_data(irq); 275 - } 276 - 277 - static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) 278 - { 279 - struct irq_cfg *cfg; 280 - 281 - cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); 282 - if (!cfg) 283 - return NULL; 284 - if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) 285 - goto out_cfg; 286 - if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) 287 - goto out_domain; 288 - return cfg; 289 - out_domain: 290 - free_cpumask_var(cfg->domain); 291 - out_cfg: 292 - kfree(cfg); 293 - return NULL; 294 - } 295 - 296 - static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) 297 - { 298 - if (!cfg) 299 - return; 300 - irq_set_chip_data(at, NULL); 301 - free_cpumask_var(cfg->domain); 302 - free_cpumask_var(cfg->old_domain); 303 - kfree(cfg); 304 - } 305 - 306 - static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) 307 - { 308 - int res = irq_alloc_desc_at(at, node); 309 - struct irq_cfg *cfg; 310 - 311 - if (res < 0) { 312 - if (res != -EEXIST) 313 - return NULL; 314 - cfg = irq_cfg(at); 315 - if (cfg) 316 - return cfg; 317 - } 318 - 319 - cfg = alloc_irq_cfg(at, node); 320 - if (cfg) 321 - irq_set_chip_data(at, cfg); 322 - else 323 - irq_free_desc(at); 324 - return cfg; 325 267 } 326 268 327 269 struct io_apic { ··· 393 445 */ 394 446 static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) 395 447 { 396 - struct irq_pin_list **last, *entry; 448 + struct irq_pin_list *entry; 397 449 398 450 /* don't allow duplicates */ 399 - last = &cfg->irq_2_pin; 400 - for_each_irq_pin(entry, cfg->irq_2_pin) { 451 + for_each_irq_pin(entry, cfg->irq_2_pin) 401 452 if (entry->apic == apic && entry->pin == pin) 402 453 return 0; 403 - last = &entry->next; 404 - } 405 454 406 455 entry = alloc_irq_pin_list(node); 407 456 if (!entry) { ··· 409 464 entry->apic = apic; 410 465 entry->pin = pin; 411 466 412 - *last = entry; 467 + list_add_tail(&entry->list, &cfg->irq_2_pin); 413 468 return 0; 414 469 } 415 470 416 471 static void __remove_pin_from_irq(struct irq_cfg *cfg, int apic, int pin) 417 472 { 418 - struct irq_pin_list **last, *entry; 473 + struct irq_pin_list *tmp, *entry; 419 474 420 - last = &cfg->irq_2_pin; 421 - for_each_irq_pin(entry, cfg->irq_2_pin) 475 + list_for_each_entry_safe(entry, tmp, &cfg->irq_2_pin, list) 422 476 if (entry->apic == apic && entry->pin == pin) { 423 - *last = entry->next; 477 + list_del(&entry->list); 424 478 kfree(entry); 425 479 return; 426 - } else { 427 - last = &entry->next; 428 480 } 429 481 } 430 482 ··· 501 559 502 560 static void mask_ioapic_irq(struct irq_data *data) 503 561 { 504 - mask_ioapic(data->chip_data); 562 + mask_ioapic(irqd_cfg(data)); 505 563 } 506 564 507 565 static void __unmask_ioapic(struct irq_cfg *cfg) ··· 520 578 521 579 static void unmask_ioapic_irq(struct irq_data *data) 522 580 { 523 - unmask_ioapic(data->chip_data); 581 + unmask_ioapic(irqd_cfg(data)); 524 582 } 525 583 526 584 /* ··· 1106 1164 * Find a specific PCI IRQ entry. 1107 1165 * Not an __init, possibly needed by modules 1108 1166 */ 1109 - int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, 1110 - struct io_apic_irq_attr *irq_attr) 1167 + int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) 1111 1168 { 1112 1169 int irq, i, best_ioapic = -1, best_idx = -1; 1113 1170 ··· 1160 1219 return -1; 1161 1220 1162 1221 out: 1163 - irq = pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, 1164 - IOAPIC_MAP_ALLOC); 1165 - if (irq > 0) 1166 - set_io_apic_irq_attr(irq_attr, best_ioapic, 1167 - mp_irqs[best_idx].dstirq, 1168 - irq_trigger(best_idx), 1169 - irq_polarity(best_idx)); 1170 - return irq; 1222 + return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, 1223 + IOAPIC_MAP_ALLOC); 1171 1224 } 1172 1225 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); 1173 - 1174 - void lock_vector_lock(void) 1175 - { 1176 - /* Used to the online set of cpus does not change 1177 - * during assign_irq_vector. 1178 - */ 1179 - raw_spin_lock(&vector_lock); 1180 - } 1181 - 1182 - void unlock_vector_lock(void) 1183 - { 1184 - raw_spin_unlock(&vector_lock); 1185 - } 1186 - 1187 - static int 1188 - __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) 1189 - { 1190 - /* 1191 - * NOTE! The local APIC isn't very good at handling 1192 - * multiple interrupts at the same interrupt level. 1193 - * As the interrupt level is determined by taking the 1194 - * vector number and shifting that right by 4, we 1195 - * want to spread these out a bit so that they don't 1196 - * all fall in the same interrupt level. 1197 - * 1198 - * Also, we've got to be careful not to trash gate 1199 - * 0x80, because int 0x80 is hm, kind of importantish. ;) 1200 - */ 1201 - static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; 1202 - static int current_offset = VECTOR_OFFSET_START % 16; 1203 - int cpu, err; 1204 - cpumask_var_t tmp_mask; 1205 - 1206 - if (cfg->move_in_progress) 1207 - return -EBUSY; 1208 - 1209 - if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) 1210 - return -ENOMEM; 1211 - 1212 - /* Only try and allocate irqs on cpus that are present */ 1213 - err = -ENOSPC; 1214 - cpumask_clear(cfg->old_domain); 1215 - cpu = cpumask_first_and(mask, cpu_online_mask); 1216 - while (cpu < nr_cpu_ids) { 1217 - int new_cpu, vector, offset; 1218 - 1219 - apic->vector_allocation_domain(cpu, tmp_mask, mask); 1220 - 1221 - if (cpumask_subset(tmp_mask, cfg->domain)) { 1222 - err = 0; 1223 - if (cpumask_equal(tmp_mask, cfg->domain)) 1224 - break; 1225 - /* 1226 - * New cpumask using the vector is a proper subset of 1227 - * the current in use mask. So cleanup the vector 1228 - * allocation for the members that are not used anymore. 1229 - */ 1230 - cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask); 1231 - cfg->move_in_progress = 1232 - cpumask_intersects(cfg->old_domain, cpu_online_mask); 1233 - cpumask_and(cfg->domain, cfg->domain, tmp_mask); 1234 - break; 1235 - } 1236 - 1237 - vector = current_vector; 1238 - offset = current_offset; 1239 - next: 1240 - vector += 16; 1241 - if (vector >= first_system_vector) { 1242 - offset = (offset + 1) % 16; 1243 - vector = FIRST_EXTERNAL_VECTOR + offset; 1244 - } 1245 - 1246 - if (unlikely(current_vector == vector)) { 1247 - cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask); 1248 - cpumask_andnot(tmp_mask, mask, cfg->old_domain); 1249 - cpu = cpumask_first_and(tmp_mask, cpu_online_mask); 1250 - continue; 1251 - } 1252 - 1253 - if (test_bit(vector, used_vectors)) 1254 - goto next; 1255 - 1256 - for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) { 1257 - if (per_cpu(vector_irq, new_cpu)[vector] > VECTOR_UNDEFINED) 1258 - goto next; 1259 - } 1260 - /* Found one! */ 1261 - current_vector = vector; 1262 - current_offset = offset; 1263 - if (cfg->vector) { 1264 - cpumask_copy(cfg->old_domain, cfg->domain); 1265 - cfg->move_in_progress = 1266 - cpumask_intersects(cfg->old_domain, cpu_online_mask); 1267 - } 1268 - for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) 1269 - per_cpu(vector_irq, new_cpu)[vector] = irq; 1270 - cfg->vector = vector; 1271 - cpumask_copy(cfg->domain, tmp_mask); 1272 - err = 0; 1273 - break; 1274 - } 1275 - free_cpumask_var(tmp_mask); 1276 - return err; 1277 - } 1278 - 1279 - int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) 1280 - { 1281 - int err; 1282 - unsigned long flags; 1283 - 1284 - raw_spin_lock_irqsave(&vector_lock, flags); 1285 - err = __assign_irq_vector(irq, cfg, mask); 1286 - raw_spin_unlock_irqrestore(&vector_lock, flags); 1287 - return err; 1288 - } 1289 - 1290 - static void __clear_irq_vector(int irq, struct irq_cfg *cfg) 1291 - { 1292 - int cpu, vector; 1293 - 1294 - BUG_ON(!cfg->vector); 1295 - 1296 - vector = cfg->vector; 1297 - for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) 1298 - per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; 1299 - 1300 - cfg->vector = 0; 1301 - cpumask_clear(cfg->domain); 1302 - 1303 - if (likely(!cfg->move_in_progress)) 1304 - return; 1305 - for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { 1306 - for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { 1307 - if (per_cpu(vector_irq, cpu)[vector] != irq) 1308 - continue; 1309 - per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; 1310 - break; 1311 - } 1312 - } 1313 - cfg->move_in_progress = 0; 1314 - } 1315 - 1316 - void __setup_vector_irq(int cpu) 1317 - { 1318 - /* Initialize vector_irq on a new cpu */ 1319 - int irq, vector; 1320 - struct irq_cfg *cfg; 1321 - 1322 - /* 1323 - * vector_lock will make sure that we don't run into irq vector 1324 - * assignments that might be happening on another cpu in parallel, 1325 - * while we setup our initial vector to irq mappings. 1326 - */ 1327 - raw_spin_lock(&vector_lock); 1328 - /* Mark the inuse vectors */ 1329 - for_each_active_irq(irq) { 1330 - cfg = irq_cfg(irq); 1331 - if (!cfg) 1332 - continue; 1333 - 1334 - if (!cpumask_test_cpu(cpu, cfg->domain)) 1335 - continue; 1336 - vector = cfg->vector; 1337 - per_cpu(vector_irq, cpu)[vector] = irq; 1338 - } 1339 - /* Mark the free vectors */ 1340 - for (vector = 0; vector < NR_VECTORS; ++vector) { 1341 - irq = per_cpu(vector_irq, cpu)[vector]; 1342 - if (irq <= VECTOR_UNDEFINED) 1343 - continue; 1344 - 1345 - cfg = irq_cfg(irq); 1346 - if (!cpumask_test_cpu(cpu, cfg->domain)) 1347 - per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; 1348 - } 1349 - raw_spin_unlock(&vector_lock); 1350 - } 1351 1226 1352 1227 static struct irq_chip ioapic_chip; 1353 1228 ··· 1253 1496 &dest)) { 1254 1497 pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n", 1255 1498 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); 1256 - __clear_irq_vector(irq, cfg); 1499 + clear_irq_vector(irq, cfg); 1257 1500 1258 1501 return; 1259 1502 } ··· 1267 1510 if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) { 1268 1511 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n", 1269 1512 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); 1270 - __clear_irq_vector(irq, cfg); 1513 + clear_irq_vector(irq, cfg); 1271 1514 1272 1515 return; 1273 1516 } ··· 1398 1641 raw_spin_lock_init(&ioapic_lock); 1399 1642 } 1400 1643 1401 - __apicdebuginit(void) print_IO_APIC(int ioapic_idx) 1644 + static void __init print_IO_APIC(int ioapic_idx) 1402 1645 { 1403 1646 union IO_APIC_reg_00 reg_00; 1404 1647 union IO_APIC_reg_01 reg_01; ··· 1455 1698 x86_io_apic_ops.print_entries(ioapic_idx, reg_01.bits.entries); 1456 1699 } 1457 1700 1458 - __apicdebuginit(void) print_IO_APICs(void) 1701 + void __init print_IO_APICs(void) 1459 1702 { 1460 1703 int ioapic_idx; 1461 1704 struct irq_cfg *cfg; ··· 1488 1731 cfg = irq_cfg(irq); 1489 1732 if (!cfg) 1490 1733 continue; 1491 - entry = cfg->irq_2_pin; 1492 - if (!entry) 1734 + if (list_empty(&cfg->irq_2_pin)) 1493 1735 continue; 1494 1736 printk(KERN_DEBUG "IRQ%d ", irq); 1495 1737 for_each_irq_pin(entry, cfg->irq_2_pin) ··· 1498 1742 1499 1743 printk(KERN_INFO ".................................... done.\n"); 1500 1744 } 1501 - 1502 - __apicdebuginit(void) print_APIC_field(int base) 1503 - { 1504 - int i; 1505 - 1506 - printk(KERN_DEBUG); 1507 - 1508 - for (i = 0; i < 8; i++) 1509 - pr_cont("%08x", apic_read(base + i*0x10)); 1510 - 1511 - pr_cont("\n"); 1512 - } 1513 - 1514 - __apicdebuginit(void) print_local_APIC(void *dummy) 1515 - { 1516 - unsigned int i, v, ver, maxlvt; 1517 - u64 icr; 1518 - 1519 - printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", 1520 - smp_processor_id(), hard_smp_processor_id()); 1521 - v = apic_read(APIC_ID); 1522 - printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); 1523 - v = apic_read(APIC_LVR); 1524 - printk(KERN_INFO "... APIC VERSION: %08x\n", v); 1525 - ver = GET_APIC_VERSION(v); 1526 - maxlvt = lapic_get_maxlvt(); 1527 - 1528 - v = apic_read(APIC_TASKPRI); 1529 - printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); 1530 - 1531 - if (APIC_INTEGRATED(ver)) { /* !82489DX */ 1532 - if (!APIC_XAPIC(ver)) { 1533 - v = apic_read(APIC_ARBPRI); 1534 - printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, 1535 - v & APIC_ARBPRI_MASK); 1536 - } 1537 - v = apic_read(APIC_PROCPRI); 1538 - printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); 1539 - } 1540 - 1541 - /* 1542 - * Remote read supported only in the 82489DX and local APIC for 1543 - * Pentium processors. 1544 - */ 1545 - if (!APIC_INTEGRATED(ver) || maxlvt == 3) { 1546 - v = apic_read(APIC_RRR); 1547 - printk(KERN_DEBUG "... APIC RRR: %08x\n", v); 1548 - } 1549 - 1550 - v = apic_read(APIC_LDR); 1551 - printk(KERN_DEBUG "... APIC LDR: %08x\n", v); 1552 - if (!x2apic_enabled()) { 1553 - v = apic_read(APIC_DFR); 1554 - printk(KERN_DEBUG "... APIC DFR: %08x\n", v); 1555 - } 1556 - v = apic_read(APIC_SPIV); 1557 - printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); 1558 - 1559 - printk(KERN_DEBUG "... APIC ISR field:\n"); 1560 - print_APIC_field(APIC_ISR); 1561 - printk(KERN_DEBUG "... APIC TMR field:\n"); 1562 - print_APIC_field(APIC_TMR); 1563 - printk(KERN_DEBUG "... APIC IRR field:\n"); 1564 - print_APIC_field(APIC_IRR); 1565 - 1566 - if (APIC_INTEGRATED(ver)) { /* !82489DX */ 1567 - if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1568 - apic_write(APIC_ESR, 0); 1569 - 1570 - v = apic_read(APIC_ESR); 1571 - printk(KERN_DEBUG "... APIC ESR: %08x\n", v); 1572 - } 1573 - 1574 - icr = apic_icr_read(); 1575 - printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); 1576 - printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); 1577 - 1578 - v = apic_read(APIC_LVTT); 1579 - printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); 1580 - 1581 - if (maxlvt > 3) { /* PC is LVT#4. */ 1582 - v = apic_read(APIC_LVTPC); 1583 - printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); 1584 - } 1585 - v = apic_read(APIC_LVT0); 1586 - printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); 1587 - v = apic_read(APIC_LVT1); 1588 - printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); 1589 - 1590 - if (maxlvt > 2) { /* ERR is LVT#3. */ 1591 - v = apic_read(APIC_LVTERR); 1592 - printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); 1593 - } 1594 - 1595 - v = apic_read(APIC_TMICT); 1596 - printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); 1597 - v = apic_read(APIC_TMCCT); 1598 - printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); 1599 - v = apic_read(APIC_TDCR); 1600 - printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); 1601 - 1602 - if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { 1603 - v = apic_read(APIC_EFEAT); 1604 - maxlvt = (v >> 16) & 0xff; 1605 - printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); 1606 - v = apic_read(APIC_ECTRL); 1607 - printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); 1608 - for (i = 0; i < maxlvt; i++) { 1609 - v = apic_read(APIC_EILVTn(i)); 1610 - printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); 1611 - } 1612 - } 1613 - pr_cont("\n"); 1614 - } 1615 - 1616 - __apicdebuginit(void) print_local_APICs(int maxcpu) 1617 - { 1618 - int cpu; 1619 - 1620 - if (!maxcpu) 1621 - return; 1622 - 1623 - preempt_disable(); 1624 - for_each_online_cpu(cpu) { 1625 - if (cpu >= maxcpu) 1626 - break; 1627 - smp_call_function_single(cpu, print_local_APIC, NULL, 1); 1628 - } 1629 - preempt_enable(); 1630 - } 1631 - 1632 - __apicdebuginit(void) print_PIC(void) 1633 - { 1634 - unsigned int v; 1635 - unsigned long flags; 1636 - 1637 - if (!nr_legacy_irqs()) 1638 - return; 1639 - 1640 - printk(KERN_DEBUG "\nprinting PIC contents\n"); 1641 - 1642 - raw_spin_lock_irqsave(&i8259A_lock, flags); 1643 - 1644 - v = inb(0xa1) << 8 | inb(0x21); 1645 - printk(KERN_DEBUG "... PIC IMR: %04x\n", v); 1646 - 1647 - v = inb(0xa0) << 8 | inb(0x20); 1648 - printk(KERN_DEBUG "... PIC IRR: %04x\n", v); 1649 - 1650 - outb(0x0b,0xa0); 1651 - outb(0x0b,0x20); 1652 - v = inb(0xa0) << 8 | inb(0x20); 1653 - outb(0x0a,0xa0); 1654 - outb(0x0a,0x20); 1655 - 1656 - raw_spin_unlock_irqrestore(&i8259A_lock, flags); 1657 - 1658 - printk(KERN_DEBUG "... PIC ISR: %04x\n", v); 1659 - 1660 - v = inb(0x4d1) << 8 | inb(0x4d0); 1661 - printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); 1662 - } 1663 - 1664 - static int __initdata show_lapic = 1; 1665 - static __init int setup_show_lapic(char *arg) 1666 - { 1667 - int num = -1; 1668 - 1669 - if (strcmp(arg, "all") == 0) { 1670 - show_lapic = CONFIG_NR_CPUS; 1671 - } else { 1672 - get_option(&arg, &num); 1673 - if (num >= 0) 1674 - show_lapic = num; 1675 - } 1676 - 1677 - return 1; 1678 - } 1679 - __setup("show_lapic=", setup_show_lapic); 1680 - 1681 - __apicdebuginit(int) print_ICs(void) 1682 - { 1683 - if (apic_verbosity == APIC_QUIET) 1684 - return 0; 1685 - 1686 - print_PIC(); 1687 - 1688 - /* don't print out if apic is not there */ 1689 - if (!cpu_has_apic && !apic_from_smp_config()) 1690 - return 0; 1691 - 1692 - print_local_APICs(show_lapic); 1693 - print_IO_APICs(); 1694 - 1695 - return 0; 1696 - } 1697 - 1698 - late_initcall(print_ICs); 1699 - 1700 1745 1701 1746 /* Where if anywhere is the i8259 connect in external int mode */ 1702 1747 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; ··· 1801 2244 if (legacy_pic->irq_pending(irq)) 1802 2245 was_pending = 1; 1803 2246 } 1804 - __unmask_ioapic(data->chip_data); 2247 + __unmask_ioapic(irqd_cfg(data)); 1805 2248 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 1806 2249 1807 2250 return was_pending; 1808 - } 1809 - 1810 - static int ioapic_retrigger_irq(struct irq_data *data) 1811 - { 1812 - struct irq_cfg *cfg = data->chip_data; 1813 - unsigned long flags; 1814 - int cpu; 1815 - 1816 - raw_spin_lock_irqsave(&vector_lock, flags); 1817 - cpu = cpumask_first_and(cfg->domain, cpu_online_mask); 1818 - apic->send_IPI_mask(cpumask_of(cpu), cfg->vector); 1819 - raw_spin_unlock_irqrestore(&vector_lock, flags); 1820 - 1821 - return 1; 1822 2251 } 1823 2252 1824 2253 /* ··· 1815 2272 * edge-triggered handler, without risking IRQ storms and other ugly 1816 2273 * races. 1817 2274 */ 1818 - 1819 - #ifdef CONFIG_SMP 1820 - void send_cleanup_vector(struct irq_cfg *cfg) 1821 - { 1822 - cpumask_var_t cleanup_mask; 1823 - 1824 - if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { 1825 - unsigned int i; 1826 - for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) 1827 - apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); 1828 - } else { 1829 - cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); 1830 - apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); 1831 - free_cpumask_var(cleanup_mask); 1832 - } 1833 - cfg->move_in_progress = 0; 1834 - } 1835 - 1836 - asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) 1837 - { 1838 - unsigned vector, me; 1839 - 1840 - ack_APIC_irq(); 1841 - irq_enter(); 1842 - exit_idle(); 1843 - 1844 - me = smp_processor_id(); 1845 - for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { 1846 - int irq; 1847 - unsigned int irr; 1848 - struct irq_desc *desc; 1849 - struct irq_cfg *cfg; 1850 - irq = __this_cpu_read(vector_irq[vector]); 1851 - 1852 - if (irq <= VECTOR_UNDEFINED) 1853 - continue; 1854 - 1855 - desc = irq_to_desc(irq); 1856 - if (!desc) 1857 - continue; 1858 - 1859 - cfg = irq_cfg(irq); 1860 - if (!cfg) 1861 - continue; 1862 - 1863 - raw_spin_lock(&desc->lock); 1864 - 1865 - /* 1866 - * Check if the irq migration is in progress. If so, we 1867 - * haven't received the cleanup request yet for this irq. 1868 - */ 1869 - if (cfg->move_in_progress) 1870 - goto unlock; 1871 - 1872 - if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) 1873 - goto unlock; 1874 - 1875 - irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 1876 - /* 1877 - * Check if the vector that needs to be cleanedup is 1878 - * registered at the cpu's IRR. If so, then this is not 1879 - * the best time to clean it up. Lets clean it up in the 1880 - * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR 1881 - * to myself. 1882 - */ 1883 - if (irr & (1 << (vector % 32))) { 1884 - apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); 1885 - goto unlock; 1886 - } 1887 - __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED); 1888 - unlock: 1889 - raw_spin_unlock(&desc->lock); 1890 - } 1891 - 1892 - irq_exit(); 1893 - } 1894 - 1895 - static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) 1896 - { 1897 - unsigned me; 1898 - 1899 - if (likely(!cfg->move_in_progress)) 1900 - return; 1901 - 1902 - me = smp_processor_id(); 1903 - 1904 - if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) 1905 - send_cleanup_vector(cfg); 1906 - } 1907 - 1908 - static void irq_complete_move(struct irq_cfg *cfg) 1909 - { 1910 - __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); 1911 - } 1912 - 1913 - void irq_force_complete_move(int irq) 1914 - { 1915 - struct irq_cfg *cfg = irq_cfg(irq); 1916 - 1917 - if (!cfg) 1918 - return; 1919 - 1920 - __irq_complete_move(cfg, cfg->vector); 1921 - } 1922 - #else 1923 - static inline void irq_complete_move(struct irq_cfg *cfg) { } 1924 - #endif 1925 2275 1926 2276 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) 1927 2277 { ··· 1836 2400 } 1837 2401 } 1838 2402 1839 - /* 1840 - * Either sets data->affinity to a valid value, and returns 1841 - * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and 1842 - * leaves data->affinity untouched. 1843 - */ 1844 - int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, 1845 - unsigned int *dest_id) 1846 - { 1847 - struct irq_cfg *cfg = data->chip_data; 1848 - unsigned int irq = data->irq; 1849 - int err; 1850 - 1851 - if (!config_enabled(CONFIG_SMP)) 1852 - return -EPERM; 1853 - 1854 - if (!cpumask_intersects(mask, cpu_online_mask)) 1855 - return -EINVAL; 1856 - 1857 - err = assign_irq_vector(irq, cfg, mask); 1858 - if (err) 1859 - return err; 1860 - 1861 - err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id); 1862 - if (err) { 1863 - if (assign_irq_vector(irq, cfg, data->affinity)) 1864 - pr_err("Failed to recover vector for irq %d\n", irq); 1865 - return err; 1866 - } 1867 - 1868 - cpumask_copy(data->affinity, mask); 1869 - 1870 - return 0; 1871 - } 1872 - 1873 - 1874 2403 int native_ioapic_set_affinity(struct irq_data *data, 1875 2404 const struct cpumask *mask, 1876 2405 bool force) ··· 1848 2447 return -EPERM; 1849 2448 1850 2449 raw_spin_lock_irqsave(&ioapic_lock, flags); 1851 - ret = __ioapic_set_affinity(data, mask, &dest); 2450 + ret = apic_set_affinity(data, mask, &dest); 1852 2451 if (!ret) { 1853 2452 /* Only the high 8 bits are valid. */ 1854 2453 dest = SET_APIC_LOGICAL_ID(dest); 1855 - __target_IO_APIC_irq(irq, dest, data->chip_data); 2454 + __target_IO_APIC_irq(irq, dest, irqd_cfg(data)); 1856 2455 ret = IRQ_SET_MASK_OK_NOCOPY; 1857 2456 } 1858 2457 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 1859 2458 return ret; 1860 - } 1861 - 1862 - static void ack_apic_edge(struct irq_data *data) 1863 - { 1864 - irq_complete_move(data->chip_data); 1865 - irq_move_irq(data); 1866 - ack_APIC_irq(); 1867 2459 } 1868 2460 1869 2461 atomic_t irq_mis_count; ··· 1941 2547 } 1942 2548 #endif 1943 2549 1944 - static void ack_apic_level(struct irq_data *data) 2550 + static void ack_ioapic_level(struct irq_data *data) 1945 2551 { 1946 - struct irq_cfg *cfg = data->chip_data; 2552 + struct irq_cfg *cfg = irqd_cfg(data); 1947 2553 int i, irq = data->irq; 1948 2554 unsigned long v; 1949 2555 bool masked; ··· 2013 2619 .irq_startup = startup_ioapic_irq, 2014 2620 .irq_mask = mask_ioapic_irq, 2015 2621 .irq_unmask = unmask_ioapic_irq, 2016 - .irq_ack = ack_apic_edge, 2017 - .irq_eoi = ack_apic_level, 2622 + .irq_ack = apic_ack_edge, 2623 + .irq_eoi = ack_ioapic_level, 2018 2624 .irq_set_affinity = native_ioapic_set_affinity, 2019 - .irq_retrigger = ioapic_retrigger_irq, 2625 + .irq_retrigger = apic_retrigger_irq, 2020 2626 .flags = IRQCHIP_SKIP_SET_WAKE, 2021 2627 }; 2022 2628 ··· 2359 2965 return 0; 2360 2966 } 2361 2967 2968 + static void ioapic_destroy_irqdomain(int idx) 2969 + { 2970 + if (ioapics[idx].irqdomain) { 2971 + irq_domain_remove(ioapics[idx].irqdomain); 2972 + ioapics[idx].irqdomain = NULL; 2973 + } 2974 + kfree(ioapics[idx].pin_info); 2975 + ioapics[idx].pin_info = NULL; 2976 + } 2977 + 2362 2978 void __init setup_IO_APIC(void) 2363 2979 { 2364 2980 int ioapic; ··· 2448 3044 2449 3045 device_initcall(ioapic_init_ops); 2450 3046 2451 - /* 2452 - * Dynamic irq allocate and deallocation. Should be replaced by irq domains! 2453 - */ 2454 - int arch_setup_hwirq(unsigned int irq, int node) 2455 - { 2456 - struct irq_cfg *cfg; 2457 - unsigned long flags; 2458 - int ret; 2459 - 2460 - cfg = alloc_irq_cfg(irq, node); 2461 - if (!cfg) 2462 - return -ENOMEM; 2463 - 2464 - raw_spin_lock_irqsave(&vector_lock, flags); 2465 - ret = __assign_irq_vector(irq, cfg, apic->target_cpus()); 2466 - raw_spin_unlock_irqrestore(&vector_lock, flags); 2467 - 2468 - if (!ret) 2469 - irq_set_chip_data(irq, cfg); 2470 - else 2471 - free_irq_cfg(irq, cfg); 2472 - return ret; 2473 - } 2474 - 2475 - void arch_teardown_hwirq(unsigned int irq) 2476 - { 2477 - struct irq_cfg *cfg = irq_cfg(irq); 2478 - unsigned long flags; 2479 - 2480 - free_remapped_irq(irq); 2481 - raw_spin_lock_irqsave(&vector_lock, flags); 2482 - __clear_irq_vector(irq, cfg); 2483 - raw_spin_unlock_irqrestore(&vector_lock, flags); 2484 - free_irq_cfg(irq, cfg); 2485 - } 2486 - 2487 - /* 2488 - * MSI message composition 2489 - */ 2490 - void native_compose_msi_msg(struct pci_dev *pdev, 2491 - unsigned int irq, unsigned int dest, 2492 - struct msi_msg *msg, u8 hpet_id) 2493 - { 2494 - struct irq_cfg *cfg = irq_cfg(irq); 2495 - 2496 - msg->address_hi = MSI_ADDR_BASE_HI; 2497 - 2498 - if (x2apic_enabled()) 2499 - msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest); 2500 - 2501 - msg->address_lo = 2502 - MSI_ADDR_BASE_LO | 2503 - ((apic->irq_dest_mode == 0) ? 2504 - MSI_ADDR_DEST_MODE_PHYSICAL: 2505 - MSI_ADDR_DEST_MODE_LOGICAL) | 2506 - ((apic->irq_delivery_mode != dest_LowestPrio) ? 2507 - MSI_ADDR_REDIRECTION_CPU: 2508 - MSI_ADDR_REDIRECTION_LOWPRI) | 2509 - MSI_ADDR_DEST_ID(dest); 2510 - 2511 - msg->data = 2512 - MSI_DATA_TRIGGER_EDGE | 2513 - MSI_DATA_LEVEL_ASSERT | 2514 - ((apic->irq_delivery_mode != dest_LowestPrio) ? 2515 - MSI_DATA_DELIVERY_FIXED: 2516 - MSI_DATA_DELIVERY_LOWPRI) | 2517 - MSI_DATA_VECTOR(cfg->vector); 2518 - } 2519 - 2520 - #ifdef CONFIG_PCI_MSI 2521 - static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, 2522 - struct msi_msg *msg, u8 hpet_id) 2523 - { 2524 - struct irq_cfg *cfg; 2525 - int err; 2526 - unsigned dest; 2527 - 2528 - if (disable_apic) 2529 - return -ENXIO; 2530 - 2531 - cfg = irq_cfg(irq); 2532 - err = assign_irq_vector(irq, cfg, apic->target_cpus()); 2533 - if (err) 2534 - return err; 2535 - 2536 - err = apic->cpu_mask_to_apicid_and(cfg->domain, 2537 - apic->target_cpus(), &dest); 2538 - if (err) 2539 - return err; 2540 - 2541 - x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id); 2542 - 2543 - return 0; 2544 - } 2545 - 2546 - static int 2547 - msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) 2548 - { 2549 - struct irq_cfg *cfg = data->chip_data; 2550 - struct msi_msg msg; 2551 - unsigned int dest; 2552 - int ret; 2553 - 2554 - ret = __ioapic_set_affinity(data, mask, &dest); 2555 - if (ret) 2556 - return ret; 2557 - 2558 - __get_cached_msi_msg(data->msi_desc, &msg); 2559 - 2560 - msg.data &= ~MSI_DATA_VECTOR_MASK; 2561 - msg.data |= MSI_DATA_VECTOR(cfg->vector); 2562 - msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; 2563 - msg.address_lo |= MSI_ADDR_DEST_ID(dest); 2564 - 2565 - __pci_write_msi_msg(data->msi_desc, &msg); 2566 - 2567 - return IRQ_SET_MASK_OK_NOCOPY; 2568 - } 2569 - 2570 - /* 2571 - * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, 2572 - * which implement the MSI or MSI-X Capability Structure. 2573 - */ 2574 - static struct irq_chip msi_chip = { 2575 - .name = "PCI-MSI", 2576 - .irq_unmask = pci_msi_unmask_irq, 2577 - .irq_mask = pci_msi_mask_irq, 2578 - .irq_ack = ack_apic_edge, 2579 - .irq_set_affinity = msi_set_affinity, 2580 - .irq_retrigger = ioapic_retrigger_irq, 2581 - .flags = IRQCHIP_SKIP_SET_WAKE, 2582 - }; 2583 - 2584 - int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, 2585 - unsigned int irq_base, unsigned int irq_offset) 2586 - { 2587 - struct irq_chip *chip = &msi_chip; 2588 - struct msi_msg msg; 2589 - unsigned int irq = irq_base + irq_offset; 2590 - int ret; 2591 - 2592 - ret = msi_compose_msg(dev, irq, &msg, -1); 2593 - if (ret < 0) 2594 - return ret; 2595 - 2596 - irq_set_msi_desc_off(irq_base, irq_offset, msidesc); 2597 - 2598 - /* 2599 - * MSI-X message is written per-IRQ, the offset is always 0. 2600 - * MSI message denotes a contiguous group of IRQs, written for 0th IRQ. 2601 - */ 2602 - if (!irq_offset) 2603 - pci_write_msi_msg(irq, &msg); 2604 - 2605 - setup_remapped_irq(irq, irq_cfg(irq), chip); 2606 - 2607 - irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); 2608 - 2609 - dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); 2610 - 2611 - return 0; 2612 - } 2613 - 2614 - int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 2615 - { 2616 - struct msi_desc *msidesc; 2617 - unsigned int irq; 2618 - int node, ret; 2619 - 2620 - /* Multiple MSI vectors only supported with interrupt remapping */ 2621 - if (type == PCI_CAP_ID_MSI && nvec > 1) 2622 - return 1; 2623 - 2624 - node = dev_to_node(&dev->dev); 2625 - 2626 - list_for_each_entry(msidesc, &dev->msi_list, list) { 2627 - irq = irq_alloc_hwirq(node); 2628 - if (!irq) 2629 - return -ENOSPC; 2630 - 2631 - ret = setup_msi_irq(dev, msidesc, irq, 0); 2632 - if (ret < 0) { 2633 - irq_free_hwirq(irq); 2634 - return ret; 2635 - } 2636 - 2637 - } 2638 - return 0; 2639 - } 2640 - 2641 - void native_teardown_msi_irq(unsigned int irq) 2642 - { 2643 - irq_free_hwirq(irq); 2644 - } 2645 - 2646 - #ifdef CONFIG_DMAR_TABLE 2647 - static int 2648 - dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, 2649 - bool force) 2650 - { 2651 - struct irq_cfg *cfg = data->chip_data; 2652 - unsigned int dest, irq = data->irq; 2653 - struct msi_msg msg; 2654 - int ret; 2655 - 2656 - ret = __ioapic_set_affinity(data, mask, &dest); 2657 - if (ret) 2658 - return ret; 2659 - 2660 - dmar_msi_read(irq, &msg); 2661 - 2662 - msg.data &= ~MSI_DATA_VECTOR_MASK; 2663 - msg.data |= MSI_DATA_VECTOR(cfg->vector); 2664 - msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; 2665 - msg.address_lo |= MSI_ADDR_DEST_ID(dest); 2666 - msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); 2667 - 2668 - dmar_msi_write(irq, &msg); 2669 - 2670 - return IRQ_SET_MASK_OK_NOCOPY; 2671 - } 2672 - 2673 - static struct irq_chip dmar_msi_type = { 2674 - .name = "DMAR_MSI", 2675 - .irq_unmask = dmar_msi_unmask, 2676 - .irq_mask = dmar_msi_mask, 2677 - .irq_ack = ack_apic_edge, 2678 - .irq_set_affinity = dmar_msi_set_affinity, 2679 - .irq_retrigger = ioapic_retrigger_irq, 2680 - .flags = IRQCHIP_SKIP_SET_WAKE, 2681 - }; 2682 - 2683 - int arch_setup_dmar_msi(unsigned int irq) 2684 - { 2685 - int ret; 2686 - struct msi_msg msg; 2687 - 2688 - ret = msi_compose_msg(NULL, irq, &msg, -1); 2689 - if (ret < 0) 2690 - return ret; 2691 - dmar_msi_write(irq, &msg); 2692 - irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, 2693 - "edge"); 2694 - return 0; 2695 - } 2696 - #endif 2697 - 2698 - #ifdef CONFIG_HPET_TIMER 2699 - 2700 - static int hpet_msi_set_affinity(struct irq_data *data, 2701 - const struct cpumask *mask, bool force) 2702 - { 2703 - struct irq_cfg *cfg = data->chip_data; 2704 - struct msi_msg msg; 2705 - unsigned int dest; 2706 - int ret; 2707 - 2708 - ret = __ioapic_set_affinity(data, mask, &dest); 2709 - if (ret) 2710 - return ret; 2711 - 2712 - hpet_msi_read(data->handler_data, &msg); 2713 - 2714 - msg.data &= ~MSI_DATA_VECTOR_MASK; 2715 - msg.data |= MSI_DATA_VECTOR(cfg->vector); 2716 - msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; 2717 - msg.address_lo |= MSI_ADDR_DEST_ID(dest); 2718 - 2719 - hpet_msi_write(data->handler_data, &msg); 2720 - 2721 - return IRQ_SET_MASK_OK_NOCOPY; 2722 - } 2723 - 2724 - static struct irq_chip hpet_msi_type = { 2725 - .name = "HPET_MSI", 2726 - .irq_unmask = hpet_msi_unmask, 2727 - .irq_mask = hpet_msi_mask, 2728 - .irq_ack = ack_apic_edge, 2729 - .irq_set_affinity = hpet_msi_set_affinity, 2730 - .irq_retrigger = ioapic_retrigger_irq, 2731 - .flags = IRQCHIP_SKIP_SET_WAKE, 2732 - }; 2733 - 2734 - int default_setup_hpet_msi(unsigned int irq, unsigned int id) 2735 - { 2736 - struct irq_chip *chip = &hpet_msi_type; 2737 - struct msi_msg msg; 2738 - int ret; 2739 - 2740 - ret = msi_compose_msg(NULL, irq, &msg, id); 2741 - if (ret < 0) 2742 - return ret; 2743 - 2744 - hpet_msi_write(irq_get_handler_data(irq), &msg); 2745 - irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); 2746 - setup_remapped_irq(irq, irq_cfg(irq), chip); 2747 - 2748 - irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); 2749 - return 0; 2750 - } 2751 - #endif 2752 - 2753 - #endif /* CONFIG_PCI_MSI */ 2754 - /* 2755 - * Hypertransport interrupt support 2756 - */ 2757 - #ifdef CONFIG_HT_IRQ 2758 - 2759 - static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) 2760 - { 2761 - struct ht_irq_msg msg; 2762 - fetch_ht_irq_msg(irq, &msg); 2763 - 2764 - msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); 2765 - msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); 2766 - 2767 - msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); 2768 - msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); 2769 - 2770 - write_ht_irq_msg(irq, &msg); 2771 - } 2772 - 2773 - static int 2774 - ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) 2775 - { 2776 - struct irq_cfg *cfg = data->chip_data; 2777 - unsigned int dest; 2778 - int ret; 2779 - 2780 - ret = __ioapic_set_affinity(data, mask, &dest); 2781 - if (ret) 2782 - return ret; 2783 - 2784 - target_ht_irq(data->irq, dest, cfg->vector); 2785 - return IRQ_SET_MASK_OK_NOCOPY; 2786 - } 2787 - 2788 - static struct irq_chip ht_irq_chip = { 2789 - .name = "PCI-HT", 2790 - .irq_mask = mask_ht_irq, 2791 - .irq_unmask = unmask_ht_irq, 2792 - .irq_ack = ack_apic_edge, 2793 - .irq_set_affinity = ht_set_affinity, 2794 - .irq_retrigger = ioapic_retrigger_irq, 2795 - .flags = IRQCHIP_SKIP_SET_WAKE, 2796 - }; 2797 - 2798 - int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) 2799 - { 2800 - struct irq_cfg *cfg; 2801 - struct ht_irq_msg msg; 2802 - unsigned dest; 2803 - int err; 2804 - 2805 - if (disable_apic) 2806 - return -ENXIO; 2807 - 2808 - cfg = irq_cfg(irq); 2809 - err = assign_irq_vector(irq, cfg, apic->target_cpus()); 2810 - if (err) 2811 - return err; 2812 - 2813 - err = apic->cpu_mask_to_apicid_and(cfg->domain, 2814 - apic->target_cpus(), &dest); 2815 - if (err) 2816 - return err; 2817 - 2818 - msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); 2819 - 2820 - msg.address_lo = 2821 - HT_IRQ_LOW_BASE | 2822 - HT_IRQ_LOW_DEST_ID(dest) | 2823 - HT_IRQ_LOW_VECTOR(cfg->vector) | 2824 - ((apic->irq_dest_mode == 0) ? 2825 - HT_IRQ_LOW_DM_PHYSICAL : 2826 - HT_IRQ_LOW_DM_LOGICAL) | 2827 - HT_IRQ_LOW_RQEOI_EDGE | 2828 - ((apic->irq_delivery_mode != dest_LowestPrio) ? 2829 - HT_IRQ_LOW_MT_FIXED : 2830 - HT_IRQ_LOW_MT_ARBITRATED) | 2831 - HT_IRQ_LOW_IRQ_MASKED; 2832 - 2833 - write_ht_irq_msg(irq, &msg); 2834 - 2835 - irq_set_chip_and_handler_name(irq, &ht_irq_chip, 2836 - handle_edge_irq, "edge"); 2837 - 2838 - dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); 2839 - 2840 - return 0; 2841 - } 2842 - #endif /* CONFIG_HT_IRQ */ 2843 - 2844 3047 static int 2845 3048 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) 2846 3049 { ··· 2462 3451 return ret; 2463 3452 } 2464 3453 2465 - static int __init io_apic_get_redir_entries(int ioapic) 3454 + static int io_apic_get_redir_entries(int ioapic) 2466 3455 { 2467 3456 union IO_APIC_reg_01 reg_01; 2468 3457 unsigned long flags; ··· 2487 3476 return ioapic_initialized ? ioapic_dynirq_base : gsi_top; 2488 3477 } 2489 3478 2490 - int __init arch_probe_nr_irqs(void) 2491 - { 2492 - int nr; 2493 - 2494 - if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) 2495 - nr_irqs = NR_VECTORS * nr_cpu_ids; 2496 - 2497 - nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; 2498 - #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) 2499 - /* 2500 - * for MSI and HT dyn irq 2501 - */ 2502 - nr += gsi_top * 16; 2503 - #endif 2504 - if (nr < nr_irqs) 2505 - nr_irqs = nr; 2506 - 2507 - return 0; 2508 - } 2509 - 2510 3479 #ifdef CONFIG_X86_32 2511 - static int __init io_apic_get_unique_id(int ioapic, int apic_id) 3480 + static int io_apic_get_unique_id(int ioapic, int apic_id) 2512 3481 { 2513 3482 union IO_APIC_reg_00 reg_00; 2514 3483 static physid_mask_t apic_id_map = PHYSID_MASK_NONE; ··· 2563 3572 return apic_id; 2564 3573 } 2565 3574 2566 - static u8 __init io_apic_unique_id(u8 id) 3575 + static u8 io_apic_unique_id(int idx, u8 id) 2567 3576 { 2568 3577 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 2569 3578 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) 2570 - return io_apic_get_unique_id(nr_ioapics, id); 3579 + return io_apic_get_unique_id(idx, id); 2571 3580 else 2572 3581 return id; 2573 3582 } 2574 3583 #else 2575 - static u8 __init io_apic_unique_id(u8 id) 3584 + static u8 io_apic_unique_id(int idx, u8 id) 2576 3585 { 2577 - int i; 3586 + union IO_APIC_reg_00 reg_00; 2578 3587 DECLARE_BITMAP(used, 256); 3588 + unsigned long flags; 3589 + u8 new_id; 3590 + int i; 2579 3591 2580 3592 bitmap_zero(used, 256); 2581 3593 for_each_ioapic(i) 2582 3594 __set_bit(mpc_ioapic_id(i), used); 3595 + 3596 + /* Hand out the requested id if available */ 2583 3597 if (!test_bit(id, used)) 2584 3598 return id; 2585 - return find_first_zero_bit(used, 256); 3599 + 3600 + /* 3601 + * Read the current id from the ioapic and keep it if 3602 + * available. 3603 + */ 3604 + raw_spin_lock_irqsave(&ioapic_lock, flags); 3605 + reg_00.raw = io_apic_read(idx, 0); 3606 + raw_spin_unlock_irqrestore(&ioapic_lock, flags); 3607 + new_id = reg_00.bits.ID; 3608 + if (!test_bit(new_id, used)) { 3609 + apic_printk(APIC_VERBOSE, KERN_INFO 3610 + "IOAPIC[%d]: Using reg apic_id %d instead of %d\n", 3611 + idx, new_id, id); 3612 + return new_id; 3613 + } 3614 + 3615 + /* 3616 + * Get the next free id and write it to the ioapic. 3617 + */ 3618 + new_id = find_first_zero_bit(used, 256); 3619 + reg_00.bits.ID = new_id; 3620 + raw_spin_lock_irqsave(&ioapic_lock, flags); 3621 + io_apic_write(idx, 0, reg_00.raw); 3622 + reg_00.raw = io_apic_read(idx, 0); 3623 + raw_spin_unlock_irqrestore(&ioapic_lock, flags); 3624 + /* Sanity check */ 3625 + BUG_ON(reg_00.bits.ID != new_id); 3626 + 3627 + return new_id; 2586 3628 } 2587 3629 #endif 2588 3630 2589 - static int __init io_apic_get_version(int ioapic) 3631 + static int io_apic_get_version(int ioapic) 2590 3632 { 2591 3633 union IO_APIC_reg_01 reg_01; 2592 3634 unsigned long flags; ··· 2726 3702 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); 2727 3703 mem += IOAPIC_RESOURCE_NAME_SIZE; 2728 3704 num++; 3705 + ioapics[i].iomem_res = res; 2729 3706 } 2730 3707 2731 3708 ioapic_resources = res; ··· 2824 3799 return gsi - gsi_cfg->gsi_base; 2825 3800 } 2826 3801 2827 - static __init int bad_ioapic(unsigned long address) 2828 - { 2829 - if (nr_ioapics >= MAX_IO_APICS) { 2830 - pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n", 2831 - MAX_IO_APICS, nr_ioapics); 2832 - return 1; 2833 - } 2834 - if (!address) { 2835 - pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n"); 2836 - return 1; 2837 - } 2838 - return 0; 2839 - } 2840 - 2841 - static __init int bad_ioapic_register(int idx) 3802 + static int bad_ioapic_register(int idx) 2842 3803 { 2843 3804 union IO_APIC_reg_00 reg_00; 2844 3805 union IO_APIC_reg_01 reg_01; ··· 2843 3832 return 0; 2844 3833 } 2845 3834 2846 - void __init mp_register_ioapic(int id, u32 address, u32 gsi_base, 2847 - struct ioapic_domain_cfg *cfg) 3835 + static int find_free_ioapic_entry(void) 2848 3836 { 2849 - int idx = 0; 2850 - int entries; 3837 + int idx; 3838 + 3839 + for (idx = 0; idx < MAX_IO_APICS; idx++) 3840 + if (ioapics[idx].nr_registers == 0) 3841 + return idx; 3842 + 3843 + return MAX_IO_APICS; 3844 + } 3845 + 3846 + /** 3847 + * mp_register_ioapic - Register an IOAPIC device 3848 + * @id: hardware IOAPIC ID 3849 + * @address: physical address of IOAPIC register area 3850 + * @gsi_base: base of GSI associated with the IOAPIC 3851 + * @cfg: configuration information for the IOAPIC 3852 + */ 3853 + int mp_register_ioapic(int id, u32 address, u32 gsi_base, 3854 + struct ioapic_domain_cfg *cfg) 3855 + { 3856 + bool hotplug = !!ioapic_initialized; 2851 3857 struct mp_ioapic_gsi *gsi_cfg; 3858 + int idx, ioapic, entries; 3859 + u32 gsi_end; 2852 3860 2853 - if (bad_ioapic(address)) 2854 - return; 3861 + if (!address) { 3862 + pr_warn("Bogus (zero) I/O APIC address found, skipping!\n"); 3863 + return -EINVAL; 3864 + } 3865 + for_each_ioapic(ioapic) 3866 + if (ioapics[ioapic].mp_config.apicaddr == address) { 3867 + pr_warn("address 0x%x conflicts with IOAPIC%d\n", 3868 + address, ioapic); 3869 + return -EEXIST; 3870 + } 2855 3871 2856 - idx = nr_ioapics; 3872 + idx = find_free_ioapic_entry(); 3873 + if (idx >= MAX_IO_APICS) { 3874 + pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n", 3875 + MAX_IO_APICS, idx); 3876 + return -ENOSPC; 3877 + } 2857 3878 2858 3879 ioapics[idx].mp_config.type = MP_IOAPIC; 2859 3880 ioapics[idx].mp_config.flags = MPC_APIC_USABLE; 2860 3881 ioapics[idx].mp_config.apicaddr = address; 2861 - ioapics[idx].irqdomain = NULL; 2862 - ioapics[idx].irqdomain_cfg = *cfg; 2863 3882 2864 3883 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); 2865 - 2866 3884 if (bad_ioapic_register(idx)) { 2867 3885 clear_fixmap(FIX_IO_APIC_BASE_0 + idx); 2868 - return; 3886 + return -ENODEV; 2869 3887 } 2870 3888 2871 - ioapics[idx].mp_config.apicid = io_apic_unique_id(id); 3889 + ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id); 2872 3890 ioapics[idx].mp_config.apicver = io_apic_get_version(idx); 2873 3891 2874 3892 /* ··· 2905 3865 * and to prevent reprogramming of IOAPIC pins (PCI GSIs). 2906 3866 */ 2907 3867 entries = io_apic_get_redir_entries(idx); 3868 + gsi_end = gsi_base + entries - 1; 3869 + for_each_ioapic(ioapic) { 3870 + gsi_cfg = mp_ioapic_gsi_routing(ioapic); 3871 + if ((gsi_base >= gsi_cfg->gsi_base && 3872 + gsi_base <= gsi_cfg->gsi_end) || 3873 + (gsi_end >= gsi_cfg->gsi_base && 3874 + gsi_end <= gsi_cfg->gsi_end)) { 3875 + pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n", 3876 + gsi_base, gsi_end, 3877 + gsi_cfg->gsi_base, gsi_cfg->gsi_end); 3878 + clear_fixmap(FIX_IO_APIC_BASE_0 + idx); 3879 + return -ENOSPC; 3880 + } 3881 + } 2908 3882 gsi_cfg = mp_ioapic_gsi_routing(idx); 2909 3883 gsi_cfg->gsi_base = gsi_base; 2910 - gsi_cfg->gsi_end = gsi_base + entries - 1; 3884 + gsi_cfg->gsi_end = gsi_end; 3885 + 3886 + ioapics[idx].irqdomain = NULL; 3887 + ioapics[idx].irqdomain_cfg = *cfg; 2911 3888 2912 3889 /* 2913 - * The number of IO-APIC IRQ registers (== #pins): 3890 + * If mp_register_ioapic() is called during early boot stage when 3891 + * walking ACPI/SFI/DT tables, it's too early to create irqdomain, 3892 + * we are still using bootmem allocator. So delay it to setup_IO_APIC(). 2914 3893 */ 2915 - ioapics[idx].nr_registers = entries; 3894 + if (hotplug) { 3895 + if (mp_irqdomain_create(idx)) { 3896 + clear_fixmap(FIX_IO_APIC_BASE_0 + idx); 3897 + return -ENOMEM; 3898 + } 3899 + alloc_ioapic_saved_registers(idx); 3900 + } 2916 3901 2917 3902 if (gsi_cfg->gsi_end >= gsi_top) 2918 3903 gsi_top = gsi_cfg->gsi_end + 1; 3904 + if (nr_ioapics <= idx) 3905 + nr_ioapics = idx + 1; 3906 + 3907 + /* Set nr_registers to mark entry present */ 3908 + ioapics[idx].nr_registers = entries; 2919 3909 2920 3910 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", 2921 3911 idx, mpc_ioapic_id(idx), 2922 3912 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), 2923 3913 gsi_cfg->gsi_base, gsi_cfg->gsi_end); 2924 3914 2925 - nr_ioapics++; 3915 + return 0; 3916 + } 3917 + 3918 + int mp_unregister_ioapic(u32 gsi_base) 3919 + { 3920 + int ioapic, pin; 3921 + int found = 0; 3922 + struct mp_pin_info *pin_info; 3923 + 3924 + for_each_ioapic(ioapic) 3925 + if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) { 3926 + found = 1; 3927 + break; 3928 + } 3929 + if (!found) { 3930 + pr_warn("can't find IOAPIC for GSI %d\n", gsi_base); 3931 + return -ENODEV; 3932 + } 3933 + 3934 + for_each_pin(ioapic, pin) { 3935 + pin_info = mp_pin_info(ioapic, pin); 3936 + if (pin_info->count) { 3937 + pr_warn("pin%d on IOAPIC%d is still in use.\n", 3938 + pin, ioapic); 3939 + return -EBUSY; 3940 + } 3941 + } 3942 + 3943 + /* Mark entry not present */ 3944 + ioapics[ioapic].nr_registers = 0; 3945 + ioapic_destroy_irqdomain(ioapic); 3946 + free_ioapic_saved_registers(ioapic); 3947 + if (ioapics[ioapic].iomem_res) 3948 + release_resource(ioapics[ioapic].iomem_res); 3949 + clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic); 3950 + memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic])); 3951 + 3952 + return 0; 3953 + } 3954 + 3955 + int mp_ioapic_registered(u32 gsi_base) 3956 + { 3957 + int ioapic; 3958 + 3959 + for_each_ioapic(ioapic) 3960 + if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) 3961 + return 1; 3962 + 3963 + return 0; 3964 + } 3965 + 3966 + static inline void set_io_apic_irq_attr(struct io_apic_irq_attr *irq_attr, 3967 + int ioapic, int ioapic_pin, 3968 + int trigger, int polarity) 3969 + { 3970 + irq_attr->ioapic = ioapic; 3971 + irq_attr->ioapic_pin = ioapic_pin; 3972 + irq_attr->trigger = trigger; 3973 + irq_attr->polarity = polarity; 2926 3974 } 2927 3975 2928 3976 int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq, ··· 3059 3931 3060 3932 ioapic_mask_entry(ioapic, pin); 3061 3933 __remove_pin_from_irq(cfg, ioapic, pin); 3062 - WARN_ON(cfg->irq_2_pin != NULL); 3934 + WARN_ON(!list_empty(&cfg->irq_2_pin)); 3063 3935 arch_teardown_hwirq(virq); 3064 3936 } 3065 3937 ··· 3090 3962 mutex_unlock(&ioapic_mutex); 3091 3963 3092 3964 return ret; 3093 - } 3094 - 3095 - bool mp_should_keep_irq(struct device *dev) 3096 - { 3097 - if (dev->power.is_prepared) 3098 - return true; 3099 - #ifdef CONFIG_PM 3100 - if (dev->power.runtime_status == RPM_SUSPENDING) 3101 - return true; 3102 - #endif 3103 - 3104 - return false; 3105 3965 } 3106 3966 3107 3967 /* Enable IOAPIC early just for system timer */
+286
arch/x86/kernel/apic/msi.c
··· 1 + /* 2 + * Support of MSI, HPET and DMAR interrupts. 3 + * 4 + * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo 5 + * Moved from arch/x86/kernel/apic/io_apic.c. 6 + * 7 + * This program is free software; you can redistribute it and/or modify 8 + * it under the terms of the GNU General Public License version 2 as 9 + * published by the Free Software Foundation. 10 + */ 11 + #include <linux/mm.h> 12 + #include <linux/interrupt.h> 13 + #include <linux/pci.h> 14 + #include <linux/dmar.h> 15 + #include <linux/hpet.h> 16 + #include <linux/msi.h> 17 + #include <asm/msidef.h> 18 + #include <asm/hpet.h> 19 + #include <asm/hw_irq.h> 20 + #include <asm/apic.h> 21 + #include <asm/irq_remapping.h> 22 + 23 + void native_compose_msi_msg(struct pci_dev *pdev, 24 + unsigned int irq, unsigned int dest, 25 + struct msi_msg *msg, u8 hpet_id) 26 + { 27 + struct irq_cfg *cfg = irq_cfg(irq); 28 + 29 + msg->address_hi = MSI_ADDR_BASE_HI; 30 + 31 + if (x2apic_enabled()) 32 + msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest); 33 + 34 + msg->address_lo = 35 + MSI_ADDR_BASE_LO | 36 + ((apic->irq_dest_mode == 0) ? 37 + MSI_ADDR_DEST_MODE_PHYSICAL : 38 + MSI_ADDR_DEST_MODE_LOGICAL) | 39 + ((apic->irq_delivery_mode != dest_LowestPrio) ? 40 + MSI_ADDR_REDIRECTION_CPU : 41 + MSI_ADDR_REDIRECTION_LOWPRI) | 42 + MSI_ADDR_DEST_ID(dest); 43 + 44 + msg->data = 45 + MSI_DATA_TRIGGER_EDGE | 46 + MSI_DATA_LEVEL_ASSERT | 47 + ((apic->irq_delivery_mode != dest_LowestPrio) ? 48 + MSI_DATA_DELIVERY_FIXED : 49 + MSI_DATA_DELIVERY_LOWPRI) | 50 + MSI_DATA_VECTOR(cfg->vector); 51 + } 52 + 53 + static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, 54 + struct msi_msg *msg, u8 hpet_id) 55 + { 56 + struct irq_cfg *cfg; 57 + int err; 58 + unsigned dest; 59 + 60 + if (disable_apic) 61 + return -ENXIO; 62 + 63 + cfg = irq_cfg(irq); 64 + err = assign_irq_vector(irq, cfg, apic->target_cpus()); 65 + if (err) 66 + return err; 67 + 68 + err = apic->cpu_mask_to_apicid_and(cfg->domain, 69 + apic->target_cpus(), &dest); 70 + if (err) 71 + return err; 72 + 73 + x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id); 74 + 75 + return 0; 76 + } 77 + 78 + static int 79 + msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) 80 + { 81 + struct irq_cfg *cfg = irqd_cfg(data); 82 + struct msi_msg msg; 83 + unsigned int dest; 84 + int ret; 85 + 86 + ret = apic_set_affinity(data, mask, &dest); 87 + if (ret) 88 + return ret; 89 + 90 + __get_cached_msi_msg(data->msi_desc, &msg); 91 + 92 + msg.data &= ~MSI_DATA_VECTOR_MASK; 93 + msg.data |= MSI_DATA_VECTOR(cfg->vector); 94 + msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; 95 + msg.address_lo |= MSI_ADDR_DEST_ID(dest); 96 + 97 + __pci_write_msi_msg(data->msi_desc, &msg); 98 + 99 + return IRQ_SET_MASK_OK_NOCOPY; 100 + } 101 + 102 + /* 103 + * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, 104 + * which implement the MSI or MSI-X Capability Structure. 105 + */ 106 + static struct irq_chip msi_chip = { 107 + .name = "PCI-MSI", 108 + .irq_unmask = pci_msi_unmask_irq, 109 + .irq_mask = pci_msi_mask_irq, 110 + .irq_ack = apic_ack_edge, 111 + .irq_set_affinity = msi_set_affinity, 112 + .irq_retrigger = apic_retrigger_irq, 113 + .flags = IRQCHIP_SKIP_SET_WAKE, 114 + }; 115 + 116 + int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, 117 + unsigned int irq_base, unsigned int irq_offset) 118 + { 119 + struct irq_chip *chip = &msi_chip; 120 + struct msi_msg msg; 121 + unsigned int irq = irq_base + irq_offset; 122 + int ret; 123 + 124 + ret = msi_compose_msg(dev, irq, &msg, -1); 125 + if (ret < 0) 126 + return ret; 127 + 128 + irq_set_msi_desc_off(irq_base, irq_offset, msidesc); 129 + 130 + /* 131 + * MSI-X message is written per-IRQ, the offset is always 0. 132 + * MSI message denotes a contiguous group of IRQs, written for 0th IRQ. 133 + */ 134 + if (!irq_offset) 135 + pci_write_msi_msg(irq, &msg); 136 + 137 + setup_remapped_irq(irq, irq_cfg(irq), chip); 138 + 139 + irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); 140 + 141 + dev_dbg(&dev->dev, "irq %d for MSI/MSI-X\n", irq); 142 + 143 + return 0; 144 + } 145 + 146 + int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 147 + { 148 + struct msi_desc *msidesc; 149 + unsigned int irq; 150 + int node, ret; 151 + 152 + /* Multiple MSI vectors only supported with interrupt remapping */ 153 + if (type == PCI_CAP_ID_MSI && nvec > 1) 154 + return 1; 155 + 156 + node = dev_to_node(&dev->dev); 157 + 158 + list_for_each_entry(msidesc, &dev->msi_list, list) { 159 + irq = irq_alloc_hwirq(node); 160 + if (!irq) 161 + return -ENOSPC; 162 + 163 + ret = setup_msi_irq(dev, msidesc, irq, 0); 164 + if (ret < 0) { 165 + irq_free_hwirq(irq); 166 + return ret; 167 + } 168 + 169 + } 170 + return 0; 171 + } 172 + 173 + void native_teardown_msi_irq(unsigned int irq) 174 + { 175 + irq_free_hwirq(irq); 176 + } 177 + 178 + #ifdef CONFIG_DMAR_TABLE 179 + static int 180 + dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, 181 + bool force) 182 + { 183 + struct irq_cfg *cfg = irqd_cfg(data); 184 + unsigned int dest, irq = data->irq; 185 + struct msi_msg msg; 186 + int ret; 187 + 188 + ret = apic_set_affinity(data, mask, &dest); 189 + if (ret) 190 + return ret; 191 + 192 + dmar_msi_read(irq, &msg); 193 + 194 + msg.data &= ~MSI_DATA_VECTOR_MASK; 195 + msg.data |= MSI_DATA_VECTOR(cfg->vector); 196 + msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; 197 + msg.address_lo |= MSI_ADDR_DEST_ID(dest); 198 + msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); 199 + 200 + dmar_msi_write(irq, &msg); 201 + 202 + return IRQ_SET_MASK_OK_NOCOPY; 203 + } 204 + 205 + static struct irq_chip dmar_msi_type = { 206 + .name = "DMAR_MSI", 207 + .irq_unmask = dmar_msi_unmask, 208 + .irq_mask = dmar_msi_mask, 209 + .irq_ack = apic_ack_edge, 210 + .irq_set_affinity = dmar_msi_set_affinity, 211 + .irq_retrigger = apic_retrigger_irq, 212 + .flags = IRQCHIP_SKIP_SET_WAKE, 213 + }; 214 + 215 + int arch_setup_dmar_msi(unsigned int irq) 216 + { 217 + int ret; 218 + struct msi_msg msg; 219 + 220 + ret = msi_compose_msg(NULL, irq, &msg, -1); 221 + if (ret < 0) 222 + return ret; 223 + dmar_msi_write(irq, &msg); 224 + irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, 225 + "edge"); 226 + return 0; 227 + } 228 + #endif 229 + 230 + /* 231 + * MSI message composition 232 + */ 233 + #ifdef CONFIG_HPET_TIMER 234 + 235 + static int hpet_msi_set_affinity(struct irq_data *data, 236 + const struct cpumask *mask, bool force) 237 + { 238 + struct irq_cfg *cfg = irqd_cfg(data); 239 + struct msi_msg msg; 240 + unsigned int dest; 241 + int ret; 242 + 243 + ret = apic_set_affinity(data, mask, &dest); 244 + if (ret) 245 + return ret; 246 + 247 + hpet_msi_read(data->handler_data, &msg); 248 + 249 + msg.data &= ~MSI_DATA_VECTOR_MASK; 250 + msg.data |= MSI_DATA_VECTOR(cfg->vector); 251 + msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; 252 + msg.address_lo |= MSI_ADDR_DEST_ID(dest); 253 + 254 + hpet_msi_write(data->handler_data, &msg); 255 + 256 + return IRQ_SET_MASK_OK_NOCOPY; 257 + } 258 + 259 + static struct irq_chip hpet_msi_type = { 260 + .name = "HPET_MSI", 261 + .irq_unmask = hpet_msi_unmask, 262 + .irq_mask = hpet_msi_mask, 263 + .irq_ack = apic_ack_edge, 264 + .irq_set_affinity = hpet_msi_set_affinity, 265 + .irq_retrigger = apic_retrigger_irq, 266 + .flags = IRQCHIP_SKIP_SET_WAKE, 267 + }; 268 + 269 + int default_setup_hpet_msi(unsigned int irq, unsigned int id) 270 + { 271 + struct irq_chip *chip = &hpet_msi_type; 272 + struct msi_msg msg; 273 + int ret; 274 + 275 + ret = msi_compose_msg(NULL, irq, &msg, id); 276 + if (ret < 0) 277 + return ret; 278 + 279 + hpet_msi_write(irq_get_handler_data(irq), &msg); 280 + irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); 281 + setup_remapped_irq(irq, irq_cfg(irq), chip); 282 + 283 + irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); 284 + return 0; 285 + } 286 + #endif
+719
arch/x86/kernel/apic/vector.c
··· 1 + /* 2 + * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. 3 + * 4 + * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo 5 + * Moved from arch/x86/kernel/apic/io_apic.c. 6 + * 7 + * This program is free software; you can redistribute it and/or modify 8 + * it under the terms of the GNU General Public License version 2 as 9 + * published by the Free Software Foundation. 10 + */ 11 + #include <linux/interrupt.h> 12 + #include <linux/init.h> 13 + #include <linux/compiler.h> 14 + #include <linux/irqdomain.h> 15 + #include <linux/slab.h> 16 + #include <asm/hw_irq.h> 17 + #include <asm/apic.h> 18 + #include <asm/i8259.h> 19 + #include <asm/desc.h> 20 + #include <asm/irq_remapping.h> 21 + 22 + static DEFINE_RAW_SPINLOCK(vector_lock); 23 + 24 + void lock_vector_lock(void) 25 + { 26 + /* Used to the online set of cpus does not change 27 + * during assign_irq_vector. 28 + */ 29 + raw_spin_lock(&vector_lock); 30 + } 31 + 32 + void unlock_vector_lock(void) 33 + { 34 + raw_spin_unlock(&vector_lock); 35 + } 36 + 37 + struct irq_cfg *irq_cfg(unsigned int irq) 38 + { 39 + return irq_get_chip_data(irq); 40 + } 41 + 42 + struct irq_cfg *irqd_cfg(struct irq_data *irq_data) 43 + { 44 + return irq_data->chip_data; 45 + } 46 + 47 + static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) 48 + { 49 + struct irq_cfg *cfg; 50 + 51 + cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); 52 + if (!cfg) 53 + return NULL; 54 + if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) 55 + goto out_cfg; 56 + if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) 57 + goto out_domain; 58 + #ifdef CONFIG_X86_IO_APIC 59 + INIT_LIST_HEAD(&cfg->irq_2_pin); 60 + #endif 61 + return cfg; 62 + out_domain: 63 + free_cpumask_var(cfg->domain); 64 + out_cfg: 65 + kfree(cfg); 66 + return NULL; 67 + } 68 + 69 + struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) 70 + { 71 + int res = irq_alloc_desc_at(at, node); 72 + struct irq_cfg *cfg; 73 + 74 + if (res < 0) { 75 + if (res != -EEXIST) 76 + return NULL; 77 + cfg = irq_cfg(at); 78 + if (cfg) 79 + return cfg; 80 + } 81 + 82 + cfg = alloc_irq_cfg(at, node); 83 + if (cfg) 84 + irq_set_chip_data(at, cfg); 85 + else 86 + irq_free_desc(at); 87 + return cfg; 88 + } 89 + 90 + static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) 91 + { 92 + if (!cfg) 93 + return; 94 + irq_set_chip_data(at, NULL); 95 + free_cpumask_var(cfg->domain); 96 + free_cpumask_var(cfg->old_domain); 97 + kfree(cfg); 98 + } 99 + 100 + static int 101 + __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) 102 + { 103 + /* 104 + * NOTE! The local APIC isn't very good at handling 105 + * multiple interrupts at the same interrupt level. 106 + * As the interrupt level is determined by taking the 107 + * vector number and shifting that right by 4, we 108 + * want to spread these out a bit so that they don't 109 + * all fall in the same interrupt level. 110 + * 111 + * Also, we've got to be careful not to trash gate 112 + * 0x80, because int 0x80 is hm, kind of importantish. ;) 113 + */ 114 + static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; 115 + static int current_offset = VECTOR_OFFSET_START % 16; 116 + int cpu, err; 117 + cpumask_var_t tmp_mask; 118 + 119 + if (cfg->move_in_progress) 120 + return -EBUSY; 121 + 122 + if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) 123 + return -ENOMEM; 124 + 125 + /* Only try and allocate irqs on cpus that are present */ 126 + err = -ENOSPC; 127 + cpumask_clear(cfg->old_domain); 128 + cpu = cpumask_first_and(mask, cpu_online_mask); 129 + while (cpu < nr_cpu_ids) { 130 + int new_cpu, vector, offset; 131 + 132 + apic->vector_allocation_domain(cpu, tmp_mask, mask); 133 + 134 + if (cpumask_subset(tmp_mask, cfg->domain)) { 135 + err = 0; 136 + if (cpumask_equal(tmp_mask, cfg->domain)) 137 + break; 138 + /* 139 + * New cpumask using the vector is a proper subset of 140 + * the current in use mask. So cleanup the vector 141 + * allocation for the members that are not used anymore. 142 + */ 143 + cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask); 144 + cfg->move_in_progress = 145 + cpumask_intersects(cfg->old_domain, cpu_online_mask); 146 + cpumask_and(cfg->domain, cfg->domain, tmp_mask); 147 + break; 148 + } 149 + 150 + vector = current_vector; 151 + offset = current_offset; 152 + next: 153 + vector += 16; 154 + if (vector >= first_system_vector) { 155 + offset = (offset + 1) % 16; 156 + vector = FIRST_EXTERNAL_VECTOR + offset; 157 + } 158 + 159 + if (unlikely(current_vector == vector)) { 160 + cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask); 161 + cpumask_andnot(tmp_mask, mask, cfg->old_domain); 162 + cpu = cpumask_first_and(tmp_mask, cpu_online_mask); 163 + continue; 164 + } 165 + 166 + if (test_bit(vector, used_vectors)) 167 + goto next; 168 + 169 + for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) { 170 + if (per_cpu(vector_irq, new_cpu)[vector] > 171 + VECTOR_UNDEFINED) 172 + goto next; 173 + } 174 + /* Found one! */ 175 + current_vector = vector; 176 + current_offset = offset; 177 + if (cfg->vector) { 178 + cpumask_copy(cfg->old_domain, cfg->domain); 179 + cfg->move_in_progress = 180 + cpumask_intersects(cfg->old_domain, cpu_online_mask); 181 + } 182 + for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) 183 + per_cpu(vector_irq, new_cpu)[vector] = irq; 184 + cfg->vector = vector; 185 + cpumask_copy(cfg->domain, tmp_mask); 186 + err = 0; 187 + break; 188 + } 189 + free_cpumask_var(tmp_mask); 190 + 191 + return err; 192 + } 193 + 194 + int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) 195 + { 196 + int err; 197 + unsigned long flags; 198 + 199 + raw_spin_lock_irqsave(&vector_lock, flags); 200 + err = __assign_irq_vector(irq, cfg, mask); 201 + raw_spin_unlock_irqrestore(&vector_lock, flags); 202 + return err; 203 + } 204 + 205 + void clear_irq_vector(int irq, struct irq_cfg *cfg) 206 + { 207 + int cpu, vector; 208 + unsigned long flags; 209 + 210 + raw_spin_lock_irqsave(&vector_lock, flags); 211 + BUG_ON(!cfg->vector); 212 + 213 + vector = cfg->vector; 214 + for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) 215 + per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; 216 + 217 + cfg->vector = 0; 218 + cpumask_clear(cfg->domain); 219 + 220 + if (likely(!cfg->move_in_progress)) { 221 + raw_spin_unlock_irqrestore(&vector_lock, flags); 222 + return; 223 + } 224 + 225 + for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { 226 + for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; 227 + vector++) { 228 + if (per_cpu(vector_irq, cpu)[vector] != irq) 229 + continue; 230 + per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; 231 + break; 232 + } 233 + } 234 + cfg->move_in_progress = 0; 235 + raw_spin_unlock_irqrestore(&vector_lock, flags); 236 + } 237 + 238 + int __init arch_probe_nr_irqs(void) 239 + { 240 + int nr; 241 + 242 + if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) 243 + nr_irqs = NR_VECTORS * nr_cpu_ids; 244 + 245 + nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; 246 + #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) 247 + /* 248 + * for MSI and HT dyn irq 249 + */ 250 + if (gsi_top <= NR_IRQS_LEGACY) 251 + nr += 8 * nr_cpu_ids; 252 + else 253 + nr += gsi_top * 16; 254 + #endif 255 + if (nr < nr_irqs) 256 + nr_irqs = nr; 257 + 258 + return nr_legacy_irqs(); 259 + } 260 + 261 + int __init arch_early_irq_init(void) 262 + { 263 + return arch_early_ioapic_init(); 264 + } 265 + 266 + static void __setup_vector_irq(int cpu) 267 + { 268 + /* Initialize vector_irq on a new cpu */ 269 + int irq, vector; 270 + struct irq_cfg *cfg; 271 + 272 + /* 273 + * vector_lock will make sure that we don't run into irq vector 274 + * assignments that might be happening on another cpu in parallel, 275 + * while we setup our initial vector to irq mappings. 276 + */ 277 + raw_spin_lock(&vector_lock); 278 + /* Mark the inuse vectors */ 279 + for_each_active_irq(irq) { 280 + cfg = irq_cfg(irq); 281 + if (!cfg) 282 + continue; 283 + 284 + if (!cpumask_test_cpu(cpu, cfg->domain)) 285 + continue; 286 + vector = cfg->vector; 287 + per_cpu(vector_irq, cpu)[vector] = irq; 288 + } 289 + /* Mark the free vectors */ 290 + for (vector = 0; vector < NR_VECTORS; ++vector) { 291 + irq = per_cpu(vector_irq, cpu)[vector]; 292 + if (irq <= VECTOR_UNDEFINED) 293 + continue; 294 + 295 + cfg = irq_cfg(irq); 296 + if (!cpumask_test_cpu(cpu, cfg->domain)) 297 + per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; 298 + } 299 + raw_spin_unlock(&vector_lock); 300 + } 301 + 302 + /* 303 + * Setup the vector to irq mappings. 304 + */ 305 + void setup_vector_irq(int cpu) 306 + { 307 + int irq; 308 + 309 + /* 310 + * On most of the platforms, legacy PIC delivers the interrupts on the 311 + * boot cpu. But there are certain platforms where PIC interrupts are 312 + * delivered to multiple cpu's. If the legacy IRQ is handled by the 313 + * legacy PIC, for the new cpu that is coming online, setup the static 314 + * legacy vector to irq mapping: 315 + */ 316 + for (irq = 0; irq < nr_legacy_irqs(); irq++) 317 + per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq; 318 + 319 + __setup_vector_irq(cpu); 320 + } 321 + 322 + int apic_retrigger_irq(struct irq_data *data) 323 + { 324 + struct irq_cfg *cfg = irqd_cfg(data); 325 + unsigned long flags; 326 + int cpu; 327 + 328 + raw_spin_lock_irqsave(&vector_lock, flags); 329 + cpu = cpumask_first_and(cfg->domain, cpu_online_mask); 330 + apic->send_IPI_mask(cpumask_of(cpu), cfg->vector); 331 + raw_spin_unlock_irqrestore(&vector_lock, flags); 332 + 333 + return 1; 334 + } 335 + 336 + void apic_ack_edge(struct irq_data *data) 337 + { 338 + irq_complete_move(irqd_cfg(data)); 339 + irq_move_irq(data); 340 + ack_APIC_irq(); 341 + } 342 + 343 + /* 344 + * Either sets data->affinity to a valid value, and returns 345 + * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and 346 + * leaves data->affinity untouched. 347 + */ 348 + int apic_set_affinity(struct irq_data *data, const struct cpumask *mask, 349 + unsigned int *dest_id) 350 + { 351 + struct irq_cfg *cfg = irqd_cfg(data); 352 + unsigned int irq = data->irq; 353 + int err; 354 + 355 + if (!config_enabled(CONFIG_SMP)) 356 + return -EPERM; 357 + 358 + if (!cpumask_intersects(mask, cpu_online_mask)) 359 + return -EINVAL; 360 + 361 + err = assign_irq_vector(irq, cfg, mask); 362 + if (err) 363 + return err; 364 + 365 + err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id); 366 + if (err) { 367 + if (assign_irq_vector(irq, cfg, data->affinity)) 368 + pr_err("Failed to recover vector for irq %d\n", irq); 369 + return err; 370 + } 371 + 372 + cpumask_copy(data->affinity, mask); 373 + 374 + return 0; 375 + } 376 + 377 + #ifdef CONFIG_SMP 378 + void send_cleanup_vector(struct irq_cfg *cfg) 379 + { 380 + cpumask_var_t cleanup_mask; 381 + 382 + if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { 383 + unsigned int i; 384 + 385 + for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) 386 + apic->send_IPI_mask(cpumask_of(i), 387 + IRQ_MOVE_CLEANUP_VECTOR); 388 + } else { 389 + cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); 390 + apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); 391 + free_cpumask_var(cleanup_mask); 392 + } 393 + cfg->move_in_progress = 0; 394 + } 395 + 396 + asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) 397 + { 398 + unsigned vector, me; 399 + 400 + ack_APIC_irq(); 401 + irq_enter(); 402 + exit_idle(); 403 + 404 + me = smp_processor_id(); 405 + for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { 406 + int irq; 407 + unsigned int irr; 408 + struct irq_desc *desc; 409 + struct irq_cfg *cfg; 410 + 411 + irq = __this_cpu_read(vector_irq[vector]); 412 + 413 + if (irq <= VECTOR_UNDEFINED) 414 + continue; 415 + 416 + desc = irq_to_desc(irq); 417 + if (!desc) 418 + continue; 419 + 420 + cfg = irq_cfg(irq); 421 + if (!cfg) 422 + continue; 423 + 424 + raw_spin_lock(&desc->lock); 425 + 426 + /* 427 + * Check if the irq migration is in progress. If so, we 428 + * haven't received the cleanup request yet for this irq. 429 + */ 430 + if (cfg->move_in_progress) 431 + goto unlock; 432 + 433 + if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) 434 + goto unlock; 435 + 436 + irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 437 + /* 438 + * Check if the vector that needs to be cleanedup is 439 + * registered at the cpu's IRR. If so, then this is not 440 + * the best time to clean it up. Lets clean it up in the 441 + * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR 442 + * to myself. 443 + */ 444 + if (irr & (1 << (vector % 32))) { 445 + apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); 446 + goto unlock; 447 + } 448 + __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED); 449 + unlock: 450 + raw_spin_unlock(&desc->lock); 451 + } 452 + 453 + irq_exit(); 454 + } 455 + 456 + static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) 457 + { 458 + unsigned me; 459 + 460 + if (likely(!cfg->move_in_progress)) 461 + return; 462 + 463 + me = smp_processor_id(); 464 + 465 + if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) 466 + send_cleanup_vector(cfg); 467 + } 468 + 469 + void irq_complete_move(struct irq_cfg *cfg) 470 + { 471 + __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); 472 + } 473 + 474 + void irq_force_complete_move(int irq) 475 + { 476 + struct irq_cfg *cfg = irq_cfg(irq); 477 + 478 + if (!cfg) 479 + return; 480 + 481 + __irq_complete_move(cfg, cfg->vector); 482 + } 483 + #endif 484 + 485 + /* 486 + * Dynamic irq allocate and deallocation. Should be replaced by irq domains! 487 + */ 488 + int arch_setup_hwirq(unsigned int irq, int node) 489 + { 490 + struct irq_cfg *cfg; 491 + unsigned long flags; 492 + int ret; 493 + 494 + cfg = alloc_irq_cfg(irq, node); 495 + if (!cfg) 496 + return -ENOMEM; 497 + 498 + raw_spin_lock_irqsave(&vector_lock, flags); 499 + ret = __assign_irq_vector(irq, cfg, apic->target_cpus()); 500 + raw_spin_unlock_irqrestore(&vector_lock, flags); 501 + 502 + if (!ret) 503 + irq_set_chip_data(irq, cfg); 504 + else 505 + free_irq_cfg(irq, cfg); 506 + return ret; 507 + } 508 + 509 + void arch_teardown_hwirq(unsigned int irq) 510 + { 511 + struct irq_cfg *cfg = irq_cfg(irq); 512 + 513 + free_remapped_irq(irq); 514 + clear_irq_vector(irq, cfg); 515 + free_irq_cfg(irq, cfg); 516 + } 517 + 518 + static void __init print_APIC_field(int base) 519 + { 520 + int i; 521 + 522 + printk(KERN_DEBUG); 523 + 524 + for (i = 0; i < 8; i++) 525 + pr_cont("%08x", apic_read(base + i*0x10)); 526 + 527 + pr_cont("\n"); 528 + } 529 + 530 + static void __init print_local_APIC(void *dummy) 531 + { 532 + unsigned int i, v, ver, maxlvt; 533 + u64 icr; 534 + 535 + pr_debug("printing local APIC contents on CPU#%d/%d:\n", 536 + smp_processor_id(), hard_smp_processor_id()); 537 + v = apic_read(APIC_ID); 538 + pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); 539 + v = apic_read(APIC_LVR); 540 + pr_info("... APIC VERSION: %08x\n", v); 541 + ver = GET_APIC_VERSION(v); 542 + maxlvt = lapic_get_maxlvt(); 543 + 544 + v = apic_read(APIC_TASKPRI); 545 + pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); 546 + 547 + /* !82489DX */ 548 + if (APIC_INTEGRATED(ver)) { 549 + if (!APIC_XAPIC(ver)) { 550 + v = apic_read(APIC_ARBPRI); 551 + pr_debug("... APIC ARBPRI: %08x (%02x)\n", 552 + v, v & APIC_ARBPRI_MASK); 553 + } 554 + v = apic_read(APIC_PROCPRI); 555 + pr_debug("... APIC PROCPRI: %08x\n", v); 556 + } 557 + 558 + /* 559 + * Remote read supported only in the 82489DX and local APIC for 560 + * Pentium processors. 561 + */ 562 + if (!APIC_INTEGRATED(ver) || maxlvt == 3) { 563 + v = apic_read(APIC_RRR); 564 + pr_debug("... APIC RRR: %08x\n", v); 565 + } 566 + 567 + v = apic_read(APIC_LDR); 568 + pr_debug("... APIC LDR: %08x\n", v); 569 + if (!x2apic_enabled()) { 570 + v = apic_read(APIC_DFR); 571 + pr_debug("... APIC DFR: %08x\n", v); 572 + } 573 + v = apic_read(APIC_SPIV); 574 + pr_debug("... APIC SPIV: %08x\n", v); 575 + 576 + pr_debug("... APIC ISR field:\n"); 577 + print_APIC_field(APIC_ISR); 578 + pr_debug("... APIC TMR field:\n"); 579 + print_APIC_field(APIC_TMR); 580 + pr_debug("... APIC IRR field:\n"); 581 + print_APIC_field(APIC_IRR); 582 + 583 + /* !82489DX */ 584 + if (APIC_INTEGRATED(ver)) { 585 + /* Due to the Pentium erratum 3AP. */ 586 + if (maxlvt > 3) 587 + apic_write(APIC_ESR, 0); 588 + 589 + v = apic_read(APIC_ESR); 590 + pr_debug("... APIC ESR: %08x\n", v); 591 + } 592 + 593 + icr = apic_icr_read(); 594 + pr_debug("... APIC ICR: %08x\n", (u32)icr); 595 + pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); 596 + 597 + v = apic_read(APIC_LVTT); 598 + pr_debug("... APIC LVTT: %08x\n", v); 599 + 600 + if (maxlvt > 3) { 601 + /* PC is LVT#4. */ 602 + v = apic_read(APIC_LVTPC); 603 + pr_debug("... APIC LVTPC: %08x\n", v); 604 + } 605 + v = apic_read(APIC_LVT0); 606 + pr_debug("... APIC LVT0: %08x\n", v); 607 + v = apic_read(APIC_LVT1); 608 + pr_debug("... APIC LVT1: %08x\n", v); 609 + 610 + if (maxlvt > 2) { 611 + /* ERR is LVT#3. */ 612 + v = apic_read(APIC_LVTERR); 613 + pr_debug("... APIC LVTERR: %08x\n", v); 614 + } 615 + 616 + v = apic_read(APIC_TMICT); 617 + pr_debug("... APIC TMICT: %08x\n", v); 618 + v = apic_read(APIC_TMCCT); 619 + pr_debug("... APIC TMCCT: %08x\n", v); 620 + v = apic_read(APIC_TDCR); 621 + pr_debug("... APIC TDCR: %08x\n", v); 622 + 623 + if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { 624 + v = apic_read(APIC_EFEAT); 625 + maxlvt = (v >> 16) & 0xff; 626 + pr_debug("... APIC EFEAT: %08x\n", v); 627 + v = apic_read(APIC_ECTRL); 628 + pr_debug("... APIC ECTRL: %08x\n", v); 629 + for (i = 0; i < maxlvt; i++) { 630 + v = apic_read(APIC_EILVTn(i)); 631 + pr_debug("... APIC EILVT%d: %08x\n", i, v); 632 + } 633 + } 634 + pr_cont("\n"); 635 + } 636 + 637 + static void __init print_local_APICs(int maxcpu) 638 + { 639 + int cpu; 640 + 641 + if (!maxcpu) 642 + return; 643 + 644 + preempt_disable(); 645 + for_each_online_cpu(cpu) { 646 + if (cpu >= maxcpu) 647 + break; 648 + smp_call_function_single(cpu, print_local_APIC, NULL, 1); 649 + } 650 + preempt_enable(); 651 + } 652 + 653 + static void __init print_PIC(void) 654 + { 655 + unsigned int v; 656 + unsigned long flags; 657 + 658 + if (!nr_legacy_irqs()) 659 + return; 660 + 661 + pr_debug("\nprinting PIC contents\n"); 662 + 663 + raw_spin_lock_irqsave(&i8259A_lock, flags); 664 + 665 + v = inb(0xa1) << 8 | inb(0x21); 666 + pr_debug("... PIC IMR: %04x\n", v); 667 + 668 + v = inb(0xa0) << 8 | inb(0x20); 669 + pr_debug("... PIC IRR: %04x\n", v); 670 + 671 + outb(0x0b, 0xa0); 672 + outb(0x0b, 0x20); 673 + v = inb(0xa0) << 8 | inb(0x20); 674 + outb(0x0a, 0xa0); 675 + outb(0x0a, 0x20); 676 + 677 + raw_spin_unlock_irqrestore(&i8259A_lock, flags); 678 + 679 + pr_debug("... PIC ISR: %04x\n", v); 680 + 681 + v = inb(0x4d1) << 8 | inb(0x4d0); 682 + pr_debug("... PIC ELCR: %04x\n", v); 683 + } 684 + 685 + static int show_lapic __initdata = 1; 686 + static __init int setup_show_lapic(char *arg) 687 + { 688 + int num = -1; 689 + 690 + if (strcmp(arg, "all") == 0) { 691 + show_lapic = CONFIG_NR_CPUS; 692 + } else { 693 + get_option(&arg, &num); 694 + if (num >= 0) 695 + show_lapic = num; 696 + } 697 + 698 + return 1; 699 + } 700 + __setup("show_lapic=", setup_show_lapic); 701 + 702 + static int __init print_ICs(void) 703 + { 704 + if (apic_verbosity == APIC_QUIET) 705 + return 0; 706 + 707 + print_PIC(); 708 + 709 + /* don't print out if apic is not there */ 710 + if (!cpu_has_apic && !apic_from_smp_config()) 711 + return 0; 712 + 713 + print_local_APICs(show_lapic); 714 + print_IO_APICs(); 715 + 716 + return 0; 717 + } 718 + 719 + late_initcall(print_ICs);
+1
arch/x86/kernel/crash.c
··· 28 28 #include <asm/nmi.h> 29 29 #include <asm/hw_irq.h> 30 30 #include <asm/apic.h> 31 + #include <asm/io_apic.h> 31 32 #include <asm/hpet.h> 32 33 #include <linux/kdebug.h> 33 34 #include <asm/cpu.h>
+2 -2
arch/x86/kernel/entry_32.S
··· 732 732 ENTRY(irq_entries_start) 733 733 RING0_INT_FRAME 734 734 vector=FIRST_EXTERNAL_VECTOR 735 - .rept (NR_VECTORS-FIRST_EXTERNAL_VECTOR+6)/7 735 + .rept (FIRST_SYSTEM_VECTOR-FIRST_EXTERNAL_VECTOR+6)/7 736 736 .balign 32 737 737 .rept 7 738 - .if vector < NR_VECTORS 738 + .if vector < FIRST_SYSTEM_VECTOR 739 739 .if vector <> FIRST_EXTERNAL_VECTOR 740 740 CFI_ADJUST_CFA_OFFSET -4 741 741 .endif
+2 -2
arch/x86/kernel/entry_64.S
··· 740 740 ENTRY(irq_entries_start) 741 741 INTR_FRAME 742 742 vector=FIRST_EXTERNAL_VECTOR 743 - .rept (NR_VECTORS-FIRST_EXTERNAL_VECTOR+6)/7 743 + .rept (FIRST_SYSTEM_VECTOR-FIRST_EXTERNAL_VECTOR+6)/7 744 744 .balign 32 745 745 .rept 7 746 - .if vector < NR_VECTORS 746 + .if vector < FIRST_SYSTEM_VECTOR 747 747 .if vector <> FIRST_EXTERNAL_VECTOR 748 748 CFI_ADJUST_CFA_OFFSET -8 749 749 .endif
+9 -26
arch/x86/kernel/irqinit.c
··· 99 99 x86_init.irqs.intr_init(); 100 100 } 101 101 102 - /* 103 - * Setup the vector to irq mappings. 104 - */ 105 - void setup_vector_irq(int cpu) 106 - { 107 - #ifndef CONFIG_X86_IO_APIC 108 - int irq; 109 - 110 - /* 111 - * On most of the platforms, legacy PIC delivers the interrupts on the 112 - * boot cpu. But there are certain platforms where PIC interrupts are 113 - * delivered to multiple cpu's. If the legacy IRQ is handled by the 114 - * legacy PIC, for the new cpu that is coming online, setup the static 115 - * legacy vector to irq mapping: 116 - */ 117 - for (irq = 0; irq < nr_legacy_irqs(); irq++) 118 - per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq; 119 - #endif 120 - 121 - __setup_vector_irq(cpu); 122 - } 123 - 124 102 static void __init smp_intr_init(void) 125 103 { 126 104 #ifdef CONFIG_SMP 127 - #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC) 128 105 /* 129 106 * The reschedule interrupt is a CPU-to-CPU reschedule-helper 130 107 * IPI, driven by wakeup. ··· 121 144 122 145 /* IPI used for rebooting/stopping */ 123 146 alloc_intr_gate(REBOOT_VECTOR, reboot_interrupt); 124 - #endif 125 147 #endif /* CONFIG_SMP */ 126 148 } 127 149 ··· 135 159 alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt); 136 160 #endif 137 161 138 - #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC) 162 + #ifdef CONFIG_X86_LOCAL_APIC 139 163 /* self generated IPI for local APIC timer */ 140 164 alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); 141 165 ··· 173 197 * 'special' SMP interrupts) 174 198 */ 175 199 i = FIRST_EXTERNAL_VECTOR; 176 - for_each_clear_bit_from(i, used_vectors, NR_VECTORS) { 200 + #ifndef CONFIG_X86_LOCAL_APIC 201 + #define first_system_vector NR_VECTORS 202 + #endif 203 + for_each_clear_bit_from(i, used_vectors, first_system_vector) { 177 204 /* IA32_SYSCALL_VECTOR could be used in trap_init already. */ 178 205 set_intr_gate(i, interrupt[i - FIRST_EXTERNAL_VECTOR]); 179 206 } 207 + #ifdef CONFIG_X86_LOCAL_APIC 208 + for_each_clear_bit_from(i, used_vectors, NR_VECTORS) 209 + set_intr_gate(i, spurious_interrupt); 210 + #endif 180 211 181 212 if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs()) 182 213 setup_irq(2, &irq2);
+1
arch/x86/kernel/machine_kexec_32.c
··· 20 20 #include <asm/tlbflush.h> 21 21 #include <asm/mmu_context.h> 22 22 #include <asm/apic.h> 23 + #include <asm/io_apic.h> 23 24 #include <asm/cpufeature.h> 24 25 #include <asm/desc.h> 25 26 #include <asm/cacheflush.h>
+1
arch/x86/kernel/machine_kexec_64.c
··· 22 22 #include <asm/pgtable.h> 23 23 #include <asm/tlbflush.h> 24 24 #include <asm/mmu_context.h> 25 + #include <asm/io_apic.h> 25 26 #include <asm/debugreg.h> 26 27 #include <asm/kexec-bzimage64.h> 27 28
+1
arch/x86/kernel/reboot.c
··· 12 12 #include <acpi/reboot.h> 13 13 #include <asm/io.h> 14 14 #include <asm/apic.h> 15 + #include <asm/io_apic.h> 15 16 #include <asm/desc.h> 16 17 #include <asm/hpet.h> 17 18 #include <asm/pgtable.h>
+1 -7
arch/x86/kernel/smpboot.c
··· 1084 1084 { 1085 1085 unsigned int i; 1086 1086 1087 - preempt_disable(); 1088 1087 smp_cpu_index_default(); 1089 1088 1090 1089 /* ··· 1101 1102 } 1102 1103 set_cpu_sibling_map(0); 1103 1104 1104 - 1105 1105 if (smp_sanity_check(max_cpus) < 0) { 1106 1106 pr_info("SMP disabled\n"); 1107 1107 disable_smp(); 1108 - goto out; 1108 + return; 1109 1109 } 1110 1110 1111 1111 default_setup_apic_routing(); 1112 1112 1113 - preempt_disable(); 1114 1113 if (read_apic_id() != boot_cpu_physical_apicid) { 1115 1114 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1116 1115 read_apic_id(), boot_cpu_physical_apicid); 1117 1116 /* Or can we switch back to PIC here? */ 1118 1117 } 1119 - preempt_enable(); 1120 1118 1121 1119 connect_bsp_APIC(); 1122 1120 ··· 1147 1151 uv_system_init(); 1148 1152 1149 1153 set_mtrr_aps_delayed_init(); 1150 - out: 1151 - preempt_enable(); 1152 1154 } 1153 1155 1154 1156 void arch_enable_nonboot_cpus_begin(void)
+1 -1
arch/x86/lguest/boot.c
··· 841 841 { 842 842 unsigned int i; 843 843 844 - for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) { 844 + for (i = FIRST_EXTERNAL_VECTOR; i < FIRST_SYSTEM_VECTOR; i++) { 845 845 /* Some systems map "vectors" to interrupts weirdly. Not us! */ 846 846 __this_cpu_write(vector_irq[i], i - FIRST_EXTERNAL_VECTOR); 847 847 if (i != SYSCALL_VECTOR)
+9 -1
arch/x86/pci/intel_mid_pci.c
··· 210 210 { 211 211 int polarity; 212 212 213 + if (dev->irq_managed && dev->irq > 0) 214 + return 0; 215 + 213 216 if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER) 214 217 polarity = 0; /* active high */ 215 218 else ··· 227 224 if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC) < 0) 228 225 return -EBUSY; 229 226 227 + dev->irq_managed = 1; 228 + 230 229 return 0; 231 230 } 232 231 233 232 static void intel_mid_pci_irq_disable(struct pci_dev *dev) 234 233 { 235 - if (!mp_should_keep_irq(&dev->dev) && dev->irq > 0) 234 + if (!mp_should_keep_irq(&dev->dev) && dev->irq_managed && 235 + dev->irq > 0) { 236 236 mp_unmap_irq(dev->irq); 237 + dev->irq_managed = 0; 238 + } 237 239 } 238 240 239 241 struct pci_ops intel_mid_pci_ops = {
+20 -5
arch/x86/pci/irq.c
··· 1200 1200 #ifdef CONFIG_X86_IO_APIC 1201 1201 struct pci_dev *temp_dev; 1202 1202 int irq; 1203 - struct io_apic_irq_attr irq_attr; 1203 + 1204 + if (dev->irq_managed && dev->irq > 0) 1205 + return 0; 1204 1206 1205 1207 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, 1206 - PCI_SLOT(dev->devfn), 1207 - pin - 1, &irq_attr); 1208 + PCI_SLOT(dev->devfn), pin - 1); 1208 1209 /* 1209 1210 * Busses behind bridges are typically not listed in the MP-table. 1210 1211 * In this case we have to look up the IRQ based on the parent bus, ··· 1219 1218 pin = pci_swizzle_interrupt_pin(dev, pin); 1220 1219 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 1221 1220 PCI_SLOT(bridge->devfn), 1222 - pin - 1, &irq_attr); 1221 + pin - 1); 1223 1222 if (irq >= 0) 1224 1223 dev_warn(&dev->dev, "using bridge %s " 1225 1224 "INT %c to get IRQ %d\n", ··· 1229 1228 } 1230 1229 dev = temp_dev; 1231 1230 if (irq >= 0) { 1231 + dev->irq_managed = 1; 1232 1232 dev->irq = irq; 1233 1233 dev_info(&dev->dev, "PCI->APIC IRQ transform: " 1234 1234 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq); ··· 1256 1254 return 0; 1257 1255 } 1258 1256 1257 + bool mp_should_keep_irq(struct device *dev) 1258 + { 1259 + if (dev->power.is_prepared) 1260 + return true; 1261 + #ifdef CONFIG_PM 1262 + if (dev->power.runtime_status == RPM_SUSPENDING) 1263 + return true; 1264 + #endif 1265 + 1266 + return false; 1267 + } 1268 + 1259 1269 static void pirq_disable_irq(struct pci_dev *dev) 1260 1270 { 1261 1271 if (io_apic_assign_pci_irqs && !mp_should_keep_irq(&dev->dev) && 1262 - dev->irq) { 1272 + dev->irq_managed && dev->irq) { 1263 1273 mp_unmap_irq(dev->irq); 1264 1274 dev->irq = 0; 1275 + dev->irq_managed = 0; 1265 1276 } 1266 1277 }
+3 -3
arch/x86/platform/uv/uv_irq.c
··· 131 131 unsigned long mmr_offset, int limit) 132 132 { 133 133 const struct cpumask *eligible_cpu = cpumask_of(cpu); 134 - struct irq_cfg *cfg = irq_get_chip_data(irq); 134 + struct irq_cfg *cfg = irq_cfg(irq); 135 135 unsigned long mmr_value; 136 136 struct uv_IO_APIC_route_entry *entry; 137 137 int mmr_pnode, err; ··· 198 198 uv_set_irq_affinity(struct irq_data *data, const struct cpumask *mask, 199 199 bool force) 200 200 { 201 - struct irq_cfg *cfg = data->chip_data; 201 + struct irq_cfg *cfg = irqd_cfg(data); 202 202 unsigned int dest; 203 203 unsigned long mmr_value, mmr_offset; 204 204 struct uv_IO_APIC_route_entry *entry; 205 205 int mmr_pnode; 206 206 207 - if (__ioapic_set_affinity(data, mask, &dest)) 207 + if (apic_set_affinity(data, mask, &dest)) 208 208 return -1; 209 209 210 210 mmr_value = 0;
+9 -2
drivers/acpi/pci_irq.c
··· 413 413 return 0; 414 414 } 415 415 416 + if (dev->irq_managed && dev->irq > 0) 417 + return 0; 418 + 416 419 entry = acpi_pci_irq_lookup(dev, pin); 417 420 if (!entry) { 418 421 /* ··· 459 456 return rc; 460 457 } 461 458 dev->irq = rc; 459 + dev->irq_managed = 1; 462 460 463 461 if (link) 464 462 snprintf(link_desc, sizeof(link_desc), " -> Link[%s]", link); ··· 482 478 u8 pin; 483 479 484 480 pin = dev->pin; 485 - if (!pin) 481 + if (!pin || !dev->irq_managed || dev->irq <= 0) 486 482 return; 487 483 488 484 /* Keep IOAPIC pin configuration when suspending */ ··· 510 506 */ 511 507 512 508 dev_dbg(&dev->dev, "PCI INT %c disabled\n", pin_name(pin)); 513 - if (gsi >= 0 && dev->irq > 0) 509 + if (gsi >= 0) { 514 510 acpi_unregister_gsi(gsi); 511 + dev->irq = 0; 512 + dev->irq_managed = 0; 513 + } 515 514 }
+4 -5
drivers/acpi/processor_core.c
··· 125 125 } 126 126 127 127 header = (struct acpi_subtable_header *)obj->buffer.pointer; 128 - if (header->type == ACPI_MADT_TYPE_LOCAL_APIC) { 128 + if (header->type == ACPI_MADT_TYPE_LOCAL_APIC) 129 129 map_lapic_id(header, acpi_id, &apic_id); 130 - } else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC) { 130 + else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC) 131 131 map_lsapic_id(header, type, acpi_id, &apic_id); 132 - } else if (header->type == ACPI_MADT_TYPE_LOCAL_X2APIC) { 132 + else if (header->type == ACPI_MADT_TYPE_LOCAL_X2APIC) 133 133 map_x2apic_id(header, type, acpi_id, &apic_id); 134 - } 135 134 136 135 exit: 137 136 kfree(buffer.pointer); ··· 163 164 * For example, 164 165 * 165 166 * Scope (_PR) 166 - * { 167 + * { 167 168 * Processor (CPU0, 0x00, 0x00000410, 0x06) {} 168 169 * Processor (CPU1, 0x01, 0x00000410, 0x06) {} 169 170 * Processor (CPU2, 0x02, 0x00000410, 0x06) {}
+1 -1
drivers/acpi/resource.c
··· 200 200 201 201 status = acpi_resource_to_address64(ares, &addr); 202 202 if (ACPI_FAILURE(status)) 203 - return true; 203 + return false; 204 204 205 205 res->start = addr.minimum; 206 206 res->end = addr.maximum;
+7 -7
drivers/iommu/amd_iommu.c
··· 4071 4071 int devid; 4072 4072 int ret; 4073 4073 4074 - cfg = irq_get_chip_data(irq); 4074 + cfg = irq_cfg(irq); 4075 4075 if (!cfg) 4076 4076 return -EINVAL; 4077 4077 ··· 4134 4134 if (!config_enabled(CONFIG_SMP)) 4135 4135 return -1; 4136 4136 4137 - cfg = data->chip_data; 4137 + cfg = irqd_cfg(data); 4138 4138 irq = data->irq; 4139 4139 irte_info = &cfg->irq_2_irte; 4140 4140 ··· 4172 4172 struct irq_2_irte *irte_info; 4173 4173 struct irq_cfg *cfg; 4174 4174 4175 - cfg = irq_get_chip_data(irq); 4175 + cfg = irq_cfg(irq); 4176 4176 if (!cfg) 4177 4177 return -EINVAL; 4178 4178 ··· 4191 4191 struct irq_cfg *cfg; 4192 4192 union irte irte; 4193 4193 4194 - cfg = irq_get_chip_data(irq); 4194 + cfg = irq_cfg(irq); 4195 4195 if (!cfg) 4196 4196 return; 4197 4197 ··· 4220 4220 if (!pdev) 4221 4221 return -EINVAL; 4222 4222 4223 - cfg = irq_get_chip_data(irq); 4223 + cfg = irq_cfg(irq); 4224 4224 if (!cfg) 4225 4225 return -EINVAL; 4226 4226 ··· 4240 4240 if (!pdev) 4241 4241 return -EINVAL; 4242 4242 4243 - cfg = irq_get_chip_data(irq); 4243 + cfg = irq_cfg(irq); 4244 4244 if (!cfg) 4245 4245 return -EINVAL; 4246 4246 ··· 4263 4263 struct irq_cfg *cfg; 4264 4264 int index, devid; 4265 4265 4266 - cfg = irq_get_chip_data(irq); 4266 + cfg = irq_cfg(irq); 4267 4267 if (!cfg) 4268 4268 return -EINVAL; 4269 4269
+5 -5
drivers/iommu/intel_irq_remapping.c
··· 54 54 55 55 static struct irq_2_iommu *irq_2_iommu(unsigned int irq) 56 56 { 57 - struct irq_cfg *cfg = irq_get_chip_data(irq); 57 + struct irq_cfg *cfg = irq_cfg(irq); 58 58 return cfg ? &cfg->irq_2_iommu : NULL; 59 59 } 60 60 ··· 85 85 { 86 86 struct ir_table *table = iommu->ir_table; 87 87 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); 88 - struct irq_cfg *cfg = irq_get_chip_data(irq); 88 + struct irq_cfg *cfg = irq_cfg(irq); 89 89 unsigned int mask = 0; 90 90 unsigned long flags; 91 91 int index; ··· 153 153 static int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) 154 154 { 155 155 struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); 156 - struct irq_cfg *cfg = irq_get_chip_data(irq); 156 + struct irq_cfg *cfg = irq_cfg(irq); 157 157 unsigned long flags; 158 158 159 159 if (!irq_iommu) ··· 1050 1050 intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, 1051 1051 bool force) 1052 1052 { 1053 - struct irq_cfg *cfg = data->chip_data; 1053 + struct irq_cfg *cfg = irqd_cfg(data); 1054 1054 unsigned int dest, irq = data->irq; 1055 1055 struct irte irte; 1056 1056 int err; ··· 1105 1105 u16 sub_handle = 0; 1106 1106 int ir_index; 1107 1107 1108 - cfg = irq_get_chip_data(irq); 1108 + cfg = irq_cfg(irq); 1109 1109 1110 1110 ir_index = map_irq_to_irte_handle(irq, &sub_handle); 1111 1111 BUG_ON(ir_index == -1);
+3 -3
drivers/iommu/irq_remapping.c
··· 298 298 299 299 void free_remapped_irq(int irq) 300 300 { 301 - struct irq_cfg *cfg = irq_get_chip_data(irq); 301 + struct irq_cfg *cfg = irq_cfg(irq); 302 302 303 303 if (!remap_ops || !remap_ops->free_irq) 304 304 return; ··· 311 311 unsigned int irq, unsigned int dest, 312 312 struct msi_msg *msg, u8 hpet_id) 313 313 { 314 - struct irq_cfg *cfg = irq_get_chip_data(irq); 314 + struct irq_cfg *cfg = irq_cfg(irq); 315 315 316 316 if (!irq_remapped(cfg)) 317 317 native_compose_msi_msg(pdev, irq, dest, msg, hpet_id); ··· 364 364 static void ir_ack_apic_level(struct irq_data *data) 365 365 { 366 366 ack_APIC_irq(); 367 - eoi_ioapic_irq(data->irq, data->chip_data); 367 + eoi_ioapic_irq(data->irq, irqd_cfg(data)); 368 368 } 369 369 370 370 static void ir_print_prefix(struct irq_data *data, struct seq_file *p)
+1 -8
drivers/pci/Kconfig
··· 67 67 config HT_IRQ 68 68 bool "Interrupts on hypertransport devices" 69 69 default y 70 - depends on PCI && X86_LOCAL_APIC && X86_IO_APIC 70 + depends on PCI && X86_LOCAL_APIC 71 71 help 72 72 This allows native hypertransport devices to use interrupts. 73 73 ··· 109 109 driver for it into your kernel. 110 110 111 111 If unsure, say N. 112 - 113 - config PCI_IOAPIC 114 - bool "PCI IO-APIC hotplug support" if X86 115 - depends on PCI 116 - depends on ACPI 117 - depends on X86_IO_APIC 118 - default !X86 119 112 120 113 config PCI_LABEL 121 114 def_bool y if (DMI || ACPI)
-2
drivers/pci/Makefile
··· 13 13 # Build PCI Express stuff if needed 14 14 obj-$(CONFIG_PCIEPORTBUS) += pcie/ 15 15 16 - obj-$(CONFIG_PCI_IOAPIC) += ioapic.o 17 - 18 16 # Build the PCI Hotplug drivers if we were asked to 19 17 obj-$(CONFIG_HOTPLUG_PCI) += hotplug/ 20 18 ifdef CONFIG_HOTPLUG_PCI
+2 -4
drivers/pci/hotplug/ibmphp_core.c
··· 36 36 #include <linux/wait.h> 37 37 #include "../pci.h" 38 38 #include <asm/pci_x86.h> /* for struct irq_routing_table */ 39 + #include <asm/io_apic.h> 39 40 #include "ibmphp.h" 40 41 41 42 #define attn_on(sl) ibmphp_hpc_writeslot (sl, HPC_SLOT_ATTNON) ··· 156 155 for (loop = 0; loop < len; loop++) { 157 156 if ((*cur_slot)->number == rtable->slots[loop].slot && 158 157 (*cur_slot)->bus == rtable->slots[loop].bus) { 159 - struct io_apic_irq_attr irq_attr; 160 - 161 158 (*cur_slot)->device = PCI_SLOT(rtable->slots[loop].devfn); 162 159 for (i = 0; i < 4; i++) 163 160 (*cur_slot)->irq[i] = IO_APIC_get_PCI_irq_vector((int) (*cur_slot)->bus, 164 - (int) (*cur_slot)->device, i, 165 - &irq_attr); 161 + (int) (*cur_slot)->device, i); 166 162 167 163 debug("(*cur_slot)->irq[0] = %x\n", 168 164 (*cur_slot)->irq[0]);
-121
drivers/pci/ioapic.c
··· 1 - /* 2 - * IOAPIC/IOxAPIC/IOSAPIC driver 3 - * 4 - * Copyright (C) 2009 Fujitsu Limited. 5 - * (c) Copyright 2009 Hewlett-Packard Development Company, L.P. 6 - * 7 - * This program is free software; you can redistribute it and/or modify 8 - * it under the terms of the GNU General Public License version 2 as 9 - * published by the Free Software Foundation. 10 - */ 11 - 12 - /* 13 - * This driver manages PCI I/O APICs added by hotplug after boot. We try to 14 - * claim all I/O APIC PCI devices, but those present at boot were registered 15 - * when we parsed the ACPI MADT, so we'll fail when we try to re-register 16 - * them. 17 - */ 18 - 19 - #include <linux/pci.h> 20 - #include <linux/module.h> 21 - #include <linux/acpi.h> 22 - #include <linux/slab.h> 23 - 24 - struct ioapic { 25 - acpi_handle handle; 26 - u32 gsi_base; 27 - }; 28 - 29 - static int ioapic_probe(struct pci_dev *dev, const struct pci_device_id *ent) 30 - { 31 - acpi_handle handle; 32 - acpi_status status; 33 - unsigned long long gsb; 34 - struct ioapic *ioapic; 35 - int ret; 36 - char *type; 37 - struct resource *res; 38 - 39 - handle = ACPI_HANDLE(&dev->dev); 40 - if (!handle) 41 - return -EINVAL; 42 - 43 - status = acpi_evaluate_integer(handle, "_GSB", NULL, &gsb); 44 - if (ACPI_FAILURE(status)) 45 - return -EINVAL; 46 - 47 - /* 48 - * The previous code in acpiphp evaluated _MAT if _GSB failed, but 49 - * ACPI spec 4.0 sec 6.2.2 requires _GSB for hot-pluggable I/O APICs. 50 - */ 51 - 52 - ioapic = kzalloc(sizeof(*ioapic), GFP_KERNEL); 53 - if (!ioapic) 54 - return -ENOMEM; 55 - 56 - ioapic->handle = handle; 57 - ioapic->gsi_base = (u32) gsb; 58 - 59 - if (dev->class == PCI_CLASS_SYSTEM_PIC_IOAPIC) 60 - type = "IOAPIC"; 61 - else 62 - type = "IOxAPIC"; 63 - 64 - ret = pci_enable_device(dev); 65 - if (ret < 0) 66 - goto exit_free; 67 - 68 - pci_set_master(dev); 69 - 70 - if (pci_request_region(dev, 0, type)) 71 - goto exit_disable; 72 - 73 - res = &dev->resource[0]; 74 - if (acpi_register_ioapic(ioapic->handle, res->start, ioapic->gsi_base)) 75 - goto exit_release; 76 - 77 - pci_set_drvdata(dev, ioapic); 78 - dev_info(&dev->dev, "%s at %pR, GSI %u\n", type, res, ioapic->gsi_base); 79 - return 0; 80 - 81 - exit_release: 82 - pci_release_region(dev, 0); 83 - exit_disable: 84 - pci_disable_device(dev); 85 - exit_free: 86 - kfree(ioapic); 87 - return -ENODEV; 88 - } 89 - 90 - static void ioapic_remove(struct pci_dev *dev) 91 - { 92 - struct ioapic *ioapic = pci_get_drvdata(dev); 93 - 94 - acpi_unregister_ioapic(ioapic->handle, ioapic->gsi_base); 95 - pci_release_region(dev, 0); 96 - pci_disable_device(dev); 97 - kfree(ioapic); 98 - } 99 - 100 - 101 - static const struct pci_device_id ioapic_devices[] = { 102 - { PCI_DEVICE_CLASS(PCI_CLASS_SYSTEM_PIC_IOAPIC, ~0) }, 103 - { PCI_DEVICE_CLASS(PCI_CLASS_SYSTEM_PIC_IOXAPIC, ~0) }, 104 - { } 105 - }; 106 - MODULE_DEVICE_TABLE(pci, ioapic_devices); 107 - 108 - static struct pci_driver ioapic_driver = { 109 - .name = "ioapic", 110 - .id_table = ioapic_devices, 111 - .probe = ioapic_probe, 112 - .remove = ioapic_remove, 113 - }; 114 - 115 - static int __init ioapic_init(void) 116 - { 117 - return pci_register_driver(&ioapic_driver); 118 - } 119 - module_init(ioapic_init); 120 - 121 - MODULE_LICENSE("GPL");
+1
include/linux/acpi.h
··· 153 153 154 154 int acpi_register_ioapic(acpi_handle handle, u64 phys_addr, u32 gsi_base); 155 155 int acpi_unregister_ioapic(acpi_handle handle, u32 gsi_base); 156 + int acpi_ioapic_registered(acpi_handle handle, u32 gsi_base); 156 157 void acpi_irq_stats_init(void); 157 158 extern u32 acpi_irq_handled; 158 159 extern u32 acpi_irq_not_handled;
+1
include/linux/pci.h
··· 349 349 unsigned int __aer_firmware_first:1; 350 350 unsigned int broken_intx_masking:1; 351 351 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 352 + unsigned int irq_managed:1; 352 353 pci_dev_flags_t dev_flags; 353 354 atomic_t enable_cnt; /* pci_enable_device has been called */ 354 355