Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge patch series "mpi3mr: bug fixes and minor updates"
Chandrakanth Patil <chandrakanth.patil@broadcom.com> says:
This series contains mpi3mr driver fixes and minor updates.
Link: https://lore.kernel.org/r/20250820084138.228471-1-chandrakanth.patil@broadcom.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+88
-15
+37
-1
drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h
+37
-1
drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h
···
322
322
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01)
323
323
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00)
324
324
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01)
325
+
#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_WARNING (0x00)
326
+
#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_CRITICAL (0x01)
327
+
#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_FATAL (0x02)
325
328
#define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP (0x00)
326
329
#define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP (0x01)
327
330
#define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT (0x00)
···
1253
1250
__le32 current_key[];
1254
1251
};
1255
1252
#define MPI3_IOUNIT17_PAGEVERSION (0x00)
1253
+
struct mpi3_io_unit_page18 {
1254
+
struct mpi3_config_page_header header;
1255
+
u8 flags;
1256
+
u8 poll_interval;
1257
+
__le16 reserved0a;
1258
+
__le32 reserved0c;
1259
+
};
1260
+
1261
+
#define MPI3_IOUNIT18_PAGEVERSION (0x00)
1262
+
#define MPI3_IOUNIT18_FLAGS_DIRECTATTACHED_ENABLE (0x01)
1263
+
#define MPI3_IOUNIT18_POLLINTERVAL_DISABLE (0x00)
1264
+
#ifndef MPI3_IOUNIT19_DEVICE_MAX
1265
+
#define MPI3_IOUNIT19_DEVICE_MAX (1)
1266
+
#endif
1267
+
struct mpi3_iounit19_device {
1268
+
__le16 temperature;
1269
+
__le16 dev_handle;
1270
+
__le16 persistent_id;
1271
+
__le16 reserved06;
1272
+
};
1273
+
1274
+
#define MPI3_IOUNIT19_DEVICE_TEMPERATURE_UNAVAILABLE (0x8000)
1275
+
struct mpi3_io_unit_page19 {
1276
+
struct mpi3_config_page_header header;
1277
+
__le16 num_devices;
1278
+
__le16 reserved0a;
1279
+
__le32 reserved0c;
1280
+
struct mpi3_iounit19_device device[MPI3_IOUNIT19_DEVICE_MAX];
1281
+
};
1282
+
1283
+
#define MPI3_IOUNIT19_PAGEVERSION (0x00)
1256
1284
struct mpi3_ioc_page0 {
1257
1285
struct mpi3_config_page_header header;
1258
1286
__le32 reserved08;
···
2390
2356
__le16 io_throttle_group;
2391
2357
__le16 io_throttle_group_low;
2392
2358
__le16 io_throttle_group_high;
2393
-
__le32 reserved0c;
2359
+
u8 vd_abort_to;
2360
+
u8 vd_reset_to;
2361
+
__le16 reserved0e;
2394
2362
};
2395
2363
#define MPI3_DEVICE0_VD_STATE_OFFLINE (0x00)
2396
2364
#define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED (0x01)
+2
drivers/scsi/mpi3mr/mpi/mpi30_pci.h
+2
drivers/scsi/mpi3mr/mpi/mpi30_pci.h
···
9
9
#define MPI3_NVME_ENCAP_CMD_MAX (1)
10
10
#endif
11
11
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_MASK (0x0002)
12
+
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_SHIFT (1)
12
13
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_FAIL_ONLY (0x0000)
13
14
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_ALL (0x0002)
14
15
#define MPI3_NVME_FLAGS_SUBMISSIONQ_MASK (0x0001)
16
+
#define MPI3_NVME_FLAGS_SUBMISSIONQ_SHIFT (0)
15
17
#define MPI3_NVME_FLAGS_SUBMISSIONQ_IO (0x0000)
16
18
#define MPI3_NVME_FLAGS_SUBMISSIONQ_ADMIN (0x0001)
17
19
+1
drivers/scsi/mpi3mr/mpi/mpi30_sas.h
+1
drivers/scsi/mpi3mr/mpi/mpi30_sas.h
···
11
11
#define MPI3_SAS_DEVICE_INFO_STP_INITIATOR (0x00000010)
12
12
#define MPI3_SAS_DEVICE_INFO_SMP_INITIATOR (0x00000008)
13
13
#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_MASK (0x00000007)
14
+
#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_SHIFT (0)
14
15
#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_NO_DEVICE (0x00000000)
15
16
#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_END_DEVICE (0x00000001)
16
17
#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_EXPANDER (0x00000002)
+1
-1
drivers/scsi/mpi3mr/mpi/mpi30_transport.h
+1
-1
drivers/scsi/mpi3mr/mpi/mpi30_transport.h
+6
-2
drivers/scsi/mpi3mr/mpi3mr.h
+6
-2
drivers/scsi/mpi3mr/mpi3mr.h
···
56
56
extern int prot_mask;
57
57
extern atomic64_t event_counter;
58
58
59
-
#define MPI3MR_DRIVER_VERSION "8.14.0.5.50"
60
-
#define MPI3MR_DRIVER_RELDATE "27-June-2025"
59
+
#define MPI3MR_DRIVER_VERSION "8.15.0.5.50"
60
+
#define MPI3MR_DRIVER_RELDATE "12-August-2025"
61
61
62
62
#define MPI3MR_DRIVER_NAME "mpi3mr"
63
63
#define MPI3MR_DRIVER_LICENSE "GPL"
···
697
697
u16 tg_id;
698
698
u32 tg_high;
699
699
u32 tg_low;
700
+
u8 abort_to;
701
+
u8 reset_to;
700
702
struct mpi3mr_throttle_group_info *tg;
701
703
};
702
704
···
740
738
* @wwid: World wide ID
741
739
* @enclosure_logical_id: Enclosure logical identifier
742
740
* @dev_spec: Device type specific information
741
+
* @abort_to: Timeout for abort TM
742
+
* @reset_to: Timeout for Target/LUN reset TM
743
743
* @ref_count: Reference count
744
744
* @state: device state
745
745
*/
+13
drivers/scsi/mpi3mr/mpi3mr_fw.c
+13
drivers/scsi/mpi3mr/mpi3mr_fw.c
···
2353
2353
{
2354
2354
int retval = 0;
2355
2355
u16 num_queues = 0, i = 0, msix_count_op_q = 1;
2356
+
u32 ioc_status;
2357
+
enum mpi3mr_iocstate ioc_state;
2356
2358
2357
2359
num_queues = min_t(int, mrioc->facts.max_op_reply_q,
2358
2360
mrioc->facts.max_op_req_q);
···
2407
2405
2408
2406
if (i == 0) {
2409
2407
/* Not even one queue is created successfully*/
2408
+
retval = -1;
2409
+
goto out_failed;
2410
+
}
2411
+
ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2412
+
ioc_state = mpi3mr_get_iocstate(mrioc);
2413
+
if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
2414
+
ioc_state != MRIOC_STATE_READY) {
2415
+
mpi3mr_print_fault_info(mrioc);
2410
2416
retval = -1;
2411
2417
goto out_failed;
2412
2418
}
···
5430
5420
mpi3mr_reset_rc_name(reset_reason));
5431
5421
5432
5422
mrioc->device_refresh_on = 0;
5423
+
scsi_block_requests(mrioc->shost);
5433
5424
mrioc->reset_in_progress = 1;
5434
5425
mrioc->stop_bsgs = 1;
5435
5426
mrioc->prev_reset_result = -1;
···
5539
5528
if (!retval) {
5540
5529
mrioc->diagsave_timeout = 0;
5541
5530
mrioc->reset_in_progress = 0;
5531
+
scsi_unblock_requests(mrioc->shost);
5542
5532
mrioc->pel_abort_requested = 0;
5543
5533
if (mrioc->pel_enabled) {
5544
5534
mrioc->pel_cmds.retry_count = 0;
···
5564
5552
mrioc->device_refresh_on = 0;
5565
5553
mrioc->unrecoverable = 1;
5566
5554
mrioc->reset_in_progress = 0;
5555
+
scsi_unblock_requests(mrioc->shost);
5567
5556
mrioc->stop_bsgs = 0;
5568
5557
retval = -1;
5569
5558
mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
+19
-9
drivers/scsi/mpi3mr/mpi3mr_os.c
+19
-9
drivers/scsi/mpi3mr/mpi3mr_os.c
···
1308
1308
if (vdinf->vd_state == MPI3_DEVICE0_VD_STATE_OFFLINE)
1309
1309
tgtdev->is_hidden = 1;
1310
1310
tgtdev->non_stl = 1;
1311
+
tgtdev->dev_spec.vd_inf.reset_to =
1312
+
max_t(u8, vdinf->vd_reset_to,
1313
+
MPI3MR_INTADMCMD_TIMEOUT);
1314
+
tgtdev->dev_spec.vd_inf.abort_to =
1315
+
max_t(u8, vdinf->vd_abort_to,
1316
+
MPI3MR_INTADMCMD_TIMEOUT);
1311
1317
tgtdev->dev_spec.vd_inf.tg_id = vdinf_io_throttle_group;
1312
1318
tgtdev->dev_spec.vd_inf.tg_high =
1313
1319
le16_to_cpu(vdinf->io_throttle_group_high) * 2048;
···
2055
2049
if (!fwevt->process_evt)
2056
2050
goto evt_ack;
2057
2051
2058
-
dprint_event_bh(mrioc, "processing event(0x%02x) in the bottom half handler\n",
2059
-
fwevt->event_id);
2052
+
dprint_event_bh(mrioc, "processing event(0x%02x) -(0x%08x) in the bottom half handler\n",
2053
+
fwevt->event_id, fwevt->evt_ctx);
2060
2054
2061
2055
switch (fwevt->event_id) {
2062
2056
case MPI3_EVENT_DEVICE_ADDED:
···
2872
2866
"prepare for reset event top half with rc=start\n");
2873
2867
if (mrioc->prepare_for_reset)
2874
2868
return;
2869
+
scsi_block_requests(mrioc->shost);
2875
2870
mrioc->prepare_for_reset = 1;
2876
2871
mrioc->prepare_for_reset_timeout_counter = 0;
2877
2872
} else if (evtdata->reason_code == MPI3_EVENT_PREPARE_RESET_RC_ABORT) {
2878
2873
dprint_event_th(mrioc,
2879
2874
"prepare for reset top half with rc=abort\n");
2880
2875
mrioc->prepare_for_reset = 0;
2876
+
scsi_unblock_requests(mrioc->shost);
2881
2877
mrioc->prepare_for_reset_timeout_counter = 0;
2882
2878
}
2883
2879
if ((event_reply->msg_flags & MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK)
···
3084
3076
}
3085
3077
if (process_evt_bh || ack_req) {
3086
3078
dprint_event_th(mrioc,
3087
-
"scheduling bottom half handler for event(0x%02x),ack_required=%d\n",
3088
-
evt_type, ack_req);
3079
+
"scheduling bottom half handler for event(0x%02x) - (0x%08x), ack_required=%d\n",
3080
+
evt_type, le32_to_cpu(event_reply->event_context), ack_req);
3089
3081
sz = event_reply->event_data_length * 4;
3090
3082
fwevt = mpi3mr_alloc_fwevt(sz);
3091
3083
if (!fwevt) {
···
3923
3915
if (scsi_tgt_priv_data)
3924
3916
atomic_inc(&scsi_tgt_priv_data->block_io);
3925
3917
3926
-
if (tgtdev && (tgtdev->dev_type == MPI3_DEVICE_DEVFORM_PCIE)) {
3927
-
if (cmd_priv && tgtdev->dev_spec.pcie_inf.abort_to)
3928
-
timeout = tgtdev->dev_spec.pcie_inf.abort_to;
3929
-
else if (!cmd_priv && tgtdev->dev_spec.pcie_inf.reset_to)
3930
-
timeout = tgtdev->dev_spec.pcie_inf.reset_to;
3918
+
if (tgtdev) {
3919
+
if (tgtdev->dev_type == MPI3_DEVICE_DEVFORM_PCIE)
3920
+
timeout = cmd_priv ? tgtdev->dev_spec.pcie_inf.abort_to
3921
+
: tgtdev->dev_spec.pcie_inf.reset_to;
3922
+
else if (tgtdev->dev_type == MPI3_DEVICE_DEVFORM_VD)
3923
+
timeout = cmd_priv ? tgtdev->dev_spec.vd_inf.abort_to
3924
+
: tgtdev->dev_spec.vd_inf.reset_to;
3931
3925
}
3932
3926
3933
3927
init_completion(&drv_cmd->done);
+9
-2
drivers/scsi/mpi3mr/mpi3mr_transport.c
+9
-2
drivers/scsi/mpi3mr/mpi3mr_transport.c
···
413
413
sas_address, hba_port);
414
414
if (tgtdev) {
415
415
if (!list_empty(&tgtdev->list)) {
416
-
list_del_init(&tgtdev->list);
417
416
was_on_tgtdev_list = 1;
418
-
mpi3mr_tgtdev_put(tgtdev);
417
+
if (tgtdev->state == MPI3MR_DEV_REMOVE_HS_STARTED) {
418
+
list_del_init(&tgtdev->list);
419
+
mpi3mr_tgtdev_put(tgtdev);
420
+
}
419
421
}
420
422
}
421
423
spin_unlock_irqrestore(&mrioc->tgtdev_lock, flags);
···
2081
2079
link_rate = (expander_pg1.negotiated_link_rate &
2082
2080
MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK) >>
2083
2081
MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT;
2082
+
if (link_rate < MPI3_SAS_NEG_LINK_RATE_1_5)
2083
+
link_rate = MPI3_SAS_NEG_LINK_RATE_1_5;
2084
2084
mpi3mr_update_links(mrioc, sas_address_parent,
2085
2085
handle, i, link_rate, hba_port);
2086
2086
}
···
2391
2387
tgtdev->dev_spec.sas_sata_inf.hba_port = hba_port;
2392
2388
2393
2389
link_rate = mpi3mr_get_sas_negotiated_logical_linkrate(mrioc, tgtdev);
2390
+
2391
+
if (link_rate < MPI3_SAS_NEG_LINK_RATE_1_5)
2392
+
link_rate = MPI3_SAS_NEG_LINK_RATE_1_5;
2394
2393
2395
2394
mpi3mr_update_links(mrioc, sas_address_parent, tgtdev->dev_handle,
2396
2395
parent_phy_number, link_rate, hba_port);