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spi: spi-geni-qcom: Add support for SE DMA mode

SE DMA mode can be used for larger transfers and FIFO mode
for smaller transfers.

Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/1670509544-15977-1-git-send-email-quic_vnivarth@quicinc.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Vijaya Krishna Nivarthi and committed by
Mark Brown e5f0dfa7 1b929c02

+163 -44
+163 -44
drivers/spi/spi-geni-qcom.c
··· 87 87 struct completion cs_done; 88 88 struct completion cancel_done; 89 89 struct completion abort_done; 90 + struct completion tx_reset_done; 91 + struct completion rx_reset_done; 90 92 unsigned int oversampling; 91 93 spinlock_t lock; 92 94 int irq; ··· 97 95 struct dma_chan *tx; 98 96 struct dma_chan *rx; 99 97 int cur_xfer_mode; 98 + dma_addr_t tx_se_dma; 99 + dma_addr_t rx_se_dma; 100 100 }; 101 101 102 102 static int get_spi_clk_cfg(unsigned int speed_hz, ··· 133 129 return ret; 134 130 } 135 131 136 - static void handle_fifo_timeout(struct spi_master *spi, 132 + static void handle_se_timeout(struct spi_master *spi, 137 133 struct spi_message *msg) 138 134 { 139 135 struct spi_geni_master *mas = spi_master_get_devdata(spi); 140 136 unsigned long time_left; 141 137 struct geni_se *se = &mas->se; 138 + const struct spi_transfer *xfer; 142 139 143 140 spin_lock_irq(&mas->lock); 144 141 reinit_completion(&mas->cancel_done); 145 - writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 142 + if (mas->cur_xfer_mode == GENI_SE_FIFO) 143 + writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 144 + 145 + xfer = mas->cur_xfer; 146 146 mas->cur_xfer = NULL; 147 147 geni_se_cancel_m_cmd(se); 148 148 spin_unlock_irq(&mas->lock); 149 149 150 150 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); 151 151 if (time_left) 152 - return; 152 + goto unmap_if_dma; 153 153 154 154 spin_lock_irq(&mas->lock); 155 155 reinit_completion(&mas->abort_done); ··· 169 161 * access this from an interrupt. 170 162 */ 171 163 mas->abort_failed = true; 164 + } 165 + 166 + unmap_if_dma: 167 + if (mas->cur_xfer_mode == GENI_SE_DMA) { 168 + if (xfer) { 169 + if (xfer->tx_buf && mas->tx_se_dma) { 170 + spin_lock_irq(&mas->lock); 171 + reinit_completion(&mas->tx_reset_done); 172 + writel(1, se->base + SE_DMA_TX_FSM_RST); 173 + spin_unlock_irq(&mas->lock); 174 + time_left = wait_for_completion_timeout(&mas->tx_reset_done, HZ); 175 + if (!time_left) 176 + dev_err(mas->dev, "DMA TX RESET failed\n"); 177 + geni_se_tx_dma_unprep(se, mas->tx_se_dma, xfer->len); 178 + } 179 + if (xfer->rx_buf && mas->rx_se_dma) { 180 + spin_lock_irq(&mas->lock); 181 + reinit_completion(&mas->rx_reset_done); 182 + writel(1, se->base + SE_DMA_RX_FSM_RST); 183 + spin_unlock_irq(&mas->lock); 184 + time_left = wait_for_completion_timeout(&mas->rx_reset_done, HZ); 185 + if (!time_left) 186 + dev_err(mas->dev, "DMA RX RESET failed\n"); 187 + geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len); 188 + } 189 + } else { 190 + /* 191 + * This can happen if a timeout happened and we had to wait 192 + * for lock in this function because isr was holding the lock 193 + * and handling transfer completion at that time. 194 + */ 195 + dev_warn(mas->dev, "Cancel/Abort on completed SPI transfer\n"); 196 + } 172 197 } 173 198 } 174 199 ··· 219 178 220 179 switch (mas->cur_xfer_mode) { 221 180 case GENI_SE_FIFO: 222 - handle_fifo_timeout(spi, msg); 181 + case GENI_SE_DMA: 182 + handle_se_timeout(spi, msg); 223 183 break; 224 184 case GENI_GPI_DMA: 225 185 handle_gpi_timeout(spi, msg); ··· 292 250 } 293 251 294 252 mas->cs_flag = set_flag; 253 + /* set xfer_mode to FIFO to complete cs_done in isr */ 254 + mas->cur_xfer_mode = GENI_SE_FIFO; 295 255 reinit_completion(&mas->cs_done); 296 256 if (set_flag) 297 257 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0); ··· 304 260 time_left = wait_for_completion_timeout(&mas->cs_done, HZ); 305 261 if (!time_left) { 306 262 dev_warn(mas->dev, "Timeout setting chip select\n"); 307 - handle_fifo_timeout(spi, NULL); 263 + handle_se_timeout(spi, NULL); 308 264 } 309 265 310 266 exit: ··· 526 482 { 527 483 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); 528 484 529 - /* check if dma is supported */ 530 - return mas->cur_xfer_mode != GENI_SE_FIFO; 485 + /* 486 + * Return true if transfer needs to be mapped prior to 487 + * calling transfer_one which is the case only for GPI_DMA. 488 + * For SE_DMA mode, map/unmap is done in geni_se_*x_dma_prep. 489 + */ 490 + return mas->cur_xfer_mode == GENI_GPI_DMA; 531 491 } 532 492 533 493 static int spi_geni_prepare_message(struct spi_master *spi, ··· 542 494 543 495 switch (mas->cur_xfer_mode) { 544 496 case GENI_SE_FIFO: 497 + case GENI_SE_DMA: 545 498 if (spi_geni_is_abort_still_pending(mas)) 546 499 return -EBUSY; 547 500 ret = setup_fifo_params(spi_msg->spi, spi); ··· 646 597 break; 647 598 } 648 599 /* 649 - * in case of failure to get dma channel, we can still do the 600 + * in case of failure to get gpi dma channel, we can still do the 650 601 * FIFO mode, so fallthrough 651 602 */ 652 603 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n"); ··· 765 716 mas->rx_rem_bytes -= rx_bytes; 766 717 } 767 718 768 - static void setup_fifo_xfer(struct spi_transfer *xfer, 719 + static int setup_se_xfer(struct spi_transfer *xfer, 769 720 struct spi_geni_master *mas, 770 721 u16 mode, struct spi_master *spi) 771 722 { 772 723 u32 m_cmd = 0; 773 - u32 len; 724 + u32 len, fifo_size; 774 725 struct geni_se *se = &mas->se; 775 726 int ret; 776 727 ··· 797 748 /* Speed and bits per word can be overridden per transfer */ 798 749 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); 799 750 if (ret) 800 - return; 751 + return ret; 801 752 802 753 mas->tx_rem_bytes = 0; 803 754 mas->rx_rem_bytes = 0; ··· 821 772 mas->rx_rem_bytes = xfer->len; 822 773 } 823 774 775 + /* Select transfer mode based on transfer length */ 776 + fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / mas->cur_bits_per_word; 777 + mas->cur_xfer_mode = (len <= fifo_size) ? GENI_SE_FIFO : GENI_SE_DMA; 778 + geni_se_select_mode(se, mas->cur_xfer_mode); 779 + 824 780 /* 825 781 * Lock around right before we start the transfer since our 826 782 * interrupt could come in at any time now. 827 783 */ 828 784 spin_lock_irq(&mas->lock); 829 785 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION); 830 - if (m_cmd & SPI_TX_ONLY) { 786 + 787 + if (mas->cur_xfer_mode == GENI_SE_DMA) { 788 + if (m_cmd & SPI_RX_ONLY) { 789 + ret = geni_se_rx_dma_prep(se, xfer->rx_buf, 790 + xfer->len, &mas->rx_se_dma); 791 + if (ret) { 792 + dev_err(mas->dev, "Failed to setup Rx dma %d\n", ret); 793 + mas->rx_se_dma = 0; 794 + goto unlock_and_return; 795 + } 796 + } 797 + if (m_cmd & SPI_TX_ONLY) { 798 + ret = geni_se_tx_dma_prep(se, (void *)xfer->tx_buf, 799 + xfer->len, &mas->tx_se_dma); 800 + if (ret) { 801 + dev_err(mas->dev, "Failed to setup Tx dma %d\n", ret); 802 + mas->tx_se_dma = 0; 803 + if (m_cmd & SPI_RX_ONLY) { 804 + /* Unmap rx buffer if duplex transfer */ 805 + geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len); 806 + mas->rx_se_dma = 0; 807 + } 808 + goto unlock_and_return; 809 + } 810 + } 811 + } else if (m_cmd & SPI_TX_ONLY) { 831 812 if (geni_spi_handle_tx(mas)) 832 813 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); 833 814 } 815 + 816 + unlock_and_return: 834 817 spin_unlock_irq(&mas->lock); 818 + return ret; 835 819 } 836 820 837 821 static int spi_geni_transfer_one(struct spi_master *spi, ··· 872 790 struct spi_transfer *xfer) 873 791 { 874 792 struct spi_geni_master *mas = spi_master_get_devdata(spi); 793 + int ret; 875 794 876 795 if (spi_geni_is_abort_still_pending(mas)) 877 796 return -EBUSY; ··· 881 798 if (!xfer->len) 882 799 return 0; 883 800 884 - if (mas->cur_xfer_mode == GENI_SE_FIFO) { 885 - setup_fifo_xfer(xfer, mas, slv->mode, spi); 886 - return 1; 801 + if (mas->cur_xfer_mode == GENI_SE_FIFO || mas->cur_xfer_mode == GENI_SE_DMA) { 802 + ret = setup_se_xfer(xfer, mas, slv->mode, spi); 803 + /* SPI framework expects +ve ret code to wait for transfer complete */ 804 + if (!ret) 805 + ret = 1; 806 + return ret; 887 807 } 888 808 return setup_gsi_xfer(xfer, mas, slv, spi); 889 809 } ··· 909 823 910 824 spin_lock(&mas->lock); 911 825 912 - if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) 913 - geni_spi_handle_rx(mas); 826 + if (mas->cur_xfer_mode == GENI_SE_FIFO) { 827 + if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) 828 + geni_spi_handle_rx(mas); 914 829 915 - if (m_irq & M_TX_FIFO_WATERMARK_EN) 916 - geni_spi_handle_tx(mas); 830 + if (m_irq & M_TX_FIFO_WATERMARK_EN) 831 + geni_spi_handle_tx(mas); 917 832 918 - if (m_irq & M_CMD_DONE_EN) { 919 - if (mas->cur_xfer) { 833 + if (m_irq & M_CMD_DONE_EN) { 834 + if (mas->cur_xfer) { 835 + spi_finalize_current_transfer(spi); 836 + mas->cur_xfer = NULL; 837 + /* 838 + * If this happens, then a CMD_DONE came before all the 839 + * Tx buffer bytes were sent out. This is unusual, log 840 + * this condition and disable the WM interrupt to 841 + * prevent the system from stalling due an interrupt 842 + * storm. 843 + * 844 + * If this happens when all Rx bytes haven't been 845 + * received, log the condition. The only known time 846 + * this can happen is if bits_per_word != 8 and some 847 + * registers that expect xfer lengths in num spi_words 848 + * weren't written correctly. 849 + */ 850 + if (mas->tx_rem_bytes) { 851 + writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 852 + dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", 853 + mas->tx_rem_bytes, mas->cur_bits_per_word); 854 + } 855 + if (mas->rx_rem_bytes) 856 + dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", 857 + mas->rx_rem_bytes, mas->cur_bits_per_word); 858 + } else { 859 + complete(&mas->cs_done); 860 + } 861 + } 862 + } else if (mas->cur_xfer_mode == GENI_SE_DMA) { 863 + const struct spi_transfer *xfer = mas->cur_xfer; 864 + u32 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT); 865 + u32 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT); 866 + 867 + if (dma_tx_status) 868 + writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR); 869 + if (dma_rx_status) 870 + writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR); 871 + if (dma_tx_status & TX_DMA_DONE) 872 + mas->tx_rem_bytes = 0; 873 + if (dma_rx_status & RX_DMA_DONE) 874 + mas->rx_rem_bytes = 0; 875 + if (dma_tx_status & TX_RESET_DONE) 876 + complete(&mas->tx_reset_done); 877 + if (dma_rx_status & RX_RESET_DONE) 878 + complete(&mas->rx_reset_done); 879 + if (!mas->tx_rem_bytes && !mas->rx_rem_bytes && xfer) { 880 + if (xfer->tx_buf && mas->tx_se_dma) { 881 + geni_se_tx_dma_unprep(se, mas->tx_se_dma, xfer->len); 882 + mas->tx_se_dma = 0; 883 + } 884 + if (xfer->rx_buf && mas->rx_se_dma) { 885 + geni_se_rx_dma_unprep(se, mas->rx_se_dma, xfer->len); 886 + mas->rx_se_dma = 0; 887 + } 920 888 spi_finalize_current_transfer(spi); 921 889 mas->cur_xfer = NULL; 922 - /* 923 - * If this happens, then a CMD_DONE came before all the 924 - * Tx buffer bytes were sent out. This is unusual, log 925 - * this condition and disable the WM interrupt to 926 - * prevent the system from stalling due an interrupt 927 - * storm. 928 - * 929 - * If this happens when all Rx bytes haven't been 930 - * received, log the condition. The only known time 931 - * this can happen is if bits_per_word != 8 and some 932 - * registers that expect xfer lengths in num spi_words 933 - * weren't written correctly. 934 - */ 935 - if (mas->tx_rem_bytes) { 936 - writel(0, se->base + SE_GENI_TX_WATERMARK_REG); 937 - dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", 938 - mas->tx_rem_bytes, mas->cur_bits_per_word); 939 - } 940 - if (mas->rx_rem_bytes) 941 - dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", 942 - mas->rx_rem_bytes, mas->cur_bits_per_word); 943 - } else { 944 - complete(&mas->cs_done); 945 890 } 946 891 } 947 892 ··· 1066 949 init_completion(&mas->cs_done); 1067 950 init_completion(&mas->cancel_done); 1068 951 init_completion(&mas->abort_done); 952 + init_completion(&mas->tx_reset_done); 953 + init_completion(&mas->rx_reset_done); 1069 954 spin_lock_init(&mas->lock); 1070 955 pm_runtime_use_autosuspend(&pdev->dev); 1071 956 pm_runtime_set_autosuspend_delay(&pdev->dev, 250);