Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
media: i2c: imx290: Simplify error handling when writing registers
Error handling for register writes requires checking the error status of
every single write. This makes the code complex, or incorrect when the
checks are omitted. Simplify this by passing a pointer to an error code
to the imx290_write_reg() function, which allows writing multiple
registers in a row and only checking for errors at the end.
While at it, rename imx290_write_reg() to imx290_write() as there's
nothing else than registers to write, and rename imx290_read_reg()
accordingly.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
authored by
Laurent Pinchart
and committed by
Sakari Ailus
e611f3da
454a86f3
+32
-54
+32
-54
drivers/media/i2c/imx290.c
+32
-54
drivers/media/i2c/imx290.c
···
367
367
return container_of(_sd, struct imx290, sd);
368
368
}
369
369
370
-
static int __always_unused imx290_read_reg(struct imx290 *imx290, u32 addr, u32 *value)
370
+
static int __always_unused imx290_read(struct imx290 *imx290, u32 addr, u32 *value)
371
371
{
372
372
u8 data[3] = { 0, 0, 0 };
373
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int ret;
···
385
385
return 0;
386
386
}
387
387
388
-
static int imx290_write_reg(struct imx290 *imx290, u32 addr, u32 value)
388
+
static int imx290_write(struct imx290 *imx290, u32 addr, u32 value, int *err)
389
389
{
390
390
u8 data[3] = { value & 0xff, (value >> 8) & 0xff, value >> 16 };
391
391
int ret;
392
392
393
+
if (err && *err)
394
+
return *err;
395
+
393
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ret = regmap_raw_write(imx290->regmap, addr & IMX290_REG_ADDR_MASK,
394
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data, (addr >> IMX290_REG_SIZE_SHIFT) & 3);
395
-
if (ret < 0)
398
+
if (ret < 0) {
396
399
dev_err(imx290->dev, "%u-bit write to 0x%04x failed: %d\n",
397
400
((addr >> IMX290_REG_SIZE_SHIFT) & 3) * 8,
398
401
addr & IMX290_REG_ADDR_MASK, ret);
402
+
if (err)
403
+
*err = ret;
404
+
}
399
405
400
406
return ret;
401
407
}
···
414
408
int ret;
415
409
416
410
for (i = 0; i < num_settings; ++i, ++settings) {
417
-
ret = imx290_write_reg(imx290, settings->reg, settings->val);
411
+
ret = imx290_write(imx290, settings->reg, settings->val, NULL);
418
412
if (ret < 0)
419
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return ret;
420
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}
···
425
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return 0;
426
420
}
427
421
428
-
static int imx290_set_gain(struct imx290 *imx290, u32 value)
429
-
{
430
-
int ret;
431
-
432
-
ret = imx290_write_reg(imx290, IMX290_GAIN, value);
433
-
if (ret)
434
-
dev_err(imx290->dev, "Unable to write gain\n");
435
-
436
-
return ret;
437
-
}
438
-
439
422
/* Stop streaming */
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static int imx290_stop_streaming(struct imx290 *imx290)
441
424
{
442
-
int ret;
425
+
int ret = 0;
443
426
444
-
ret = imx290_write_reg(imx290, IMX290_STANDBY, 0x01);
445
-
if (ret < 0)
446
-
return ret;
427
+
imx290_write(imx290, IMX290_STANDBY, 0x01, &ret);
447
428
448
429
msleep(30);
449
430
450
-
return imx290_write_reg(imx290, IMX290_XMSTA, 0x01);
431
+
return imx290_write(imx290, IMX290_XMSTA, 0x01, &ret);
451
432
}
452
433
453
434
static int imx290_set_ctrl(struct v4l2_ctrl *ctrl)
···
449
456
450
457
switch (ctrl->id) {
451
458
case V4L2_CID_GAIN:
452
-
ret = imx290_set_gain(imx290, ctrl->val);
459
+
ret = imx290_write(imx290, IMX290_GAIN, ctrl->val, NULL);
453
460
break;
454
461
case V4L2_CID_TEST_PATTERN:
455
462
if (ctrl->val) {
456
-
imx290_write_reg(imx290, IMX290_BLKLEVEL, 0);
463
+
imx290_write(imx290, IMX290_BLKLEVEL, 0, &ret);
457
464
usleep_range(10000, 11000);
458
-
imx290_write_reg(imx290, IMX290_PGCTRL,
459
-
(u8)(IMX290_PGCTRL_REGEN |
460
-
IMX290_PGCTRL_THRU |
461
-
IMX290_PGCTRL_MODE(ctrl->val)));
465
+
imx290_write(imx290, IMX290_PGCTRL,
466
+
(u8)(IMX290_PGCTRL_REGEN |
467
+
IMX290_PGCTRL_THRU |
468
+
IMX290_PGCTRL_MODE(ctrl->val)), &ret);
462
469
} else {
463
-
imx290_write_reg(imx290, IMX290_PGCTRL, 0x00);
470
+
imx290_write(imx290, IMX290_PGCTRL, 0x00, &ret);
464
471
usleep_range(10000, 11000);
465
472
if (imx290->bpp == 10)
466
-
imx290_write_reg(imx290, IMX290_BLKLEVEL,
467
-
0x3c);
473
+
imx290_write(imx290, IMX290_BLKLEVEL, 0x3c,
474
+
&ret);
468
475
else /* 12 bits per pixel */
469
-
imx290_write_reg(imx290, IMX290_BLKLEVEL,
470
-
0xf0);
476
+
imx290_write(imx290, IMX290_BLKLEVEL, 0xf0,
477
+
&ret);
471
478
}
472
479
break;
473
480
default:
···
688
695
return ret;
689
696
}
690
697
691
-
ret = imx290_write_reg(imx290, IMX290_HMAX, imx290->current_mode->hmax);
698
+
ret = imx290_write(imx290, IMX290_HMAX, imx290->current_mode->hmax,
699
+
NULL);
692
700
if (ret)
693
701
return ret;
694
702
···
700
706
return ret;
701
707
}
702
708
703
-
ret = imx290_write_reg(imx290, IMX290_STANDBY, 0x00);
704
-
if (ret < 0)
705
-
return ret;
709
+
imx290_write(imx290, IMX290_STANDBY, 0x00, &ret);
706
710
707
711
msleep(30);
708
712
709
713
/* Start streaming */
710
-
return imx290_write_reg(imx290, IMX290_XMSTA, 0x00);
714
+
return imx290_write(imx290, IMX290_XMSTA, 0x00, &ret);
711
715
}
712
716
713
717
static int imx290_set_stream(struct v4l2_subdev *sd, int enable)
···
764
772
* validated in probe itself
765
773
*/
766
774
dev_err(imx290->dev, "Lane configuration not supported\n");
767
-
ret = -EINVAL;
768
-
goto exit;
775
+
return -EINVAL;
769
776
}
770
777
771
-
ret = imx290_write_reg(imx290, IMX290_PHY_LANE_NUM, laneval);
772
-
if (ret) {
773
-
dev_err(imx290->dev, "Error setting Physical Lane number register\n");
774
-
goto exit;
775
-
}
778
+
imx290_write(imx290, IMX290_PHY_LANE_NUM, laneval, &ret);
779
+
imx290_write(imx290, IMX290_CSI_LANE_MODE, laneval, &ret);
780
+
imx290_write(imx290, IMX290_FR_FDG_SEL, frsel, &ret);
776
781
777
-
ret = imx290_write_reg(imx290, IMX290_CSI_LANE_MODE, laneval);
778
-
if (ret) {
779
-
dev_err(imx290->dev, "Error setting CSI Lane mode register\n");
780
-
goto exit;
781
-
}
782
-
783
-
ret = imx290_write_reg(imx290, IMX290_FR_FDG_SEL, frsel);
784
-
if (ret)
785
-
dev_err(imx290->dev, "Error setting FR/FDG SEL register\n");
786
-
787
-
exit:
788
782
return ret;
789
783
}
790
784