Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arc-4.9-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC fixes from Vineet Gupta:
- mmap handler for dma ops as generic handler no longer works for us
[Alexey]
- Fixes for EZChip platform [Noam]
- Fix RTC clocksource driver build issue
- ARC IRQ handling fixes [Yuriy]
- Revert a recent makefile change which doesn't go well with oldish
tools out in the wild
* tag 'arc-4.9-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARCv2: MCIP: Use IDU_M_DISTRI_DEST mode if there is only 1 destination core
ARC: IRQ: Do not use hwirq as virq and vice versa
ARC: [plat-eznps] set default baud for early console
ARC: [plat-eznps] remove IPI clear from SMP operations
Revert "ARC: build: retire old toggles"
ARC: timer: rtc: implement read loop in "C" vs. inline asm
ARC: change return value of userspace cmpxchg assist syscall
arc: Implement arch-specific dma_map_ops.mmap
ARC: [SMP] avoid overriding present cpumask
ARC: Enable PERF_EVENTS in nSIM driven platforms
+104
-49
+3
arch/arc/Makefile
+3
arch/arc/Makefile
+1
-1
arch/arc/boot/dts/axc001.dtsi
+1
-1
arch/arc/boot/dts/axc001.dtsi
+1
-1
arch/arc/boot/dts/nsim_700.dts
+1
-1
arch/arc/boot/dts/nsim_700.dts
+4
arch/arc/boot/dts/nsimosci.dts
+4
arch/arc/boot/dts/nsimosci.dts
+1
arch/arc/configs/nsim_700_defconfig
+1
arch/arc/configs/nsim_700_defconfig
+1
arch/arc/configs/nsim_hs_defconfig
+1
arch/arc/configs/nsim_hs_defconfig
+1
arch/arc/configs/nsim_hs_smp_defconfig
+1
arch/arc/configs/nsim_hs_smp_defconfig
+1
arch/arc/configs/nsimosci_defconfig
+1
arch/arc/configs/nsimosci_defconfig
+1
arch/arc/configs/nsimosci_hs_defconfig
+1
arch/arc/configs/nsimosci_hs_defconfig
+1
-2
arch/arc/configs/nsimosci_hs_smp_defconfig
+1
-2
arch/arc/configs/nsimosci_hs_smp_defconfig
···
10
10
# CONFIG_PID_NS is not set
11
11
CONFIG_BLK_DEV_INITRD=y
12
12
CONFIG_INITRAMFS_SOURCE="../arc_initramfs_hs/"
13
+
CONFIG_PERF_EVENTS=y
13
14
# CONFIG_COMPAT_BRK is not set
14
15
CONFIG_KPROBES=y
15
16
CONFIG_MODULES=y
···
35
34
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
36
35
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
37
36
# CONFIG_INET_XFRM_MODE_BEET is not set
38
-
# CONFIG_INET_LRO is not set
39
37
# CONFIG_IPV6 is not set
40
38
# CONFIG_WIRELESS is not set
41
39
CONFIG_DEVTMPFS=y
···
72
72
# CONFIG_HWMON is not set
73
73
CONFIG_DRM=y
74
74
CONFIG_DRM_ARCPGU=y
75
-
CONFIG_FRAMEBUFFER_CONSOLE=y
76
75
CONFIG_LOGO=y
77
76
# CONFIG_HID is not set
78
77
# CONFIG_USB_SUPPORT is not set
+2
arch/arc/include/asm/arcregs.h
+2
arch/arc/include/asm/arcregs.h
···
43
43
#define STATUS_AE_BIT 5 /* Exception active */
44
44
#define STATUS_DE_BIT 6 /* PC is in delay slot */
45
45
#define STATUS_U_BIT 7 /* User/Kernel mode */
46
+
#define STATUS_Z_BIT 11
46
47
#define STATUS_L_BIT 12 /* Loop inhibit */
47
48
48
49
/* These masks correspond to the status word(STATUS_32) bits */
49
50
#define STATUS_AE_MASK (1<<STATUS_AE_BIT)
50
51
#define STATUS_DE_MASK (1<<STATUS_DE_BIT)
51
52
#define STATUS_U_MASK (1<<STATUS_U_BIT)
53
+
#define STATUS_Z_MASK (1<<STATUS_Z_BIT)
52
54
#define STATUS_L_MASK (1<<STATUS_L_BIT)
53
55
54
56
/*
+2
-2
arch/arc/include/asm/smp.h
+2
-2
arch/arc/include/asm/smp.h
···
37
37
* API expected BY platform smp code (FROM arch smp code)
38
38
*
39
39
* smp_ipi_irq_setup:
40
-
* Takes @cpu and @irq to which the arch-common ISR is hooked up
40
+
* Takes @cpu and @hwirq to which the arch-common ISR is hooked up
41
41
*/
42
-
extern int smp_ipi_irq_setup(int cpu, int irq);
42
+
extern int smp_ipi_irq_setup(int cpu, irq_hw_number_t hwirq);
43
43
44
44
/*
45
45
* struct plat_smp_ops - SMP callbacks provided by platform to ARC SMP
+2
arch/arc/kernel/devtree.c
+2
arch/arc/kernel/devtree.c
···
31
31
arc_base_baud = 166666666; /* Fixed 166.6MHz clk (TB10x) */
32
32
else if (of_flat_dt_is_compatible(dt_root, "snps,arc-sdp"))
33
33
arc_base_baud = 33333333; /* Fixed 33MHz clk (AXS10x) */
34
+
else if (of_flat_dt_is_compatible(dt_root, "ezchip,arc-nps"))
35
+
arc_base_baud = 800000000; /* Fixed 800MHz clk (NPS) */
34
36
else
35
37
arc_base_baud = 50000000; /* Fixed default 50MHz */
36
38
}
+20
-12
arch/arc/kernel/mcip.c
+20
-12
arch/arc/kernel/mcip.c
···
181
181
{
182
182
unsigned long flags;
183
183
cpumask_t online;
184
+
unsigned int destination_bits;
185
+
unsigned int distribution_mode;
184
186
185
187
/* errout if no online cpu per @cpumask */
186
188
if (!cpumask_and(&online, cpumask, cpu_online_mask))
···
190
188
191
189
raw_spin_lock_irqsave(&mcip_lock, flags);
192
190
193
-
idu_set_dest(data->hwirq, cpumask_bits(&online)[0]);
194
-
idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, IDU_M_DISTRI_RR);
191
+
destination_bits = cpumask_bits(&online)[0];
192
+
idu_set_dest(data->hwirq, destination_bits);
193
+
194
+
if (ffs(destination_bits) == fls(destination_bits))
195
+
distribution_mode = IDU_M_DISTRI_DEST;
196
+
else
197
+
distribution_mode = IDU_M_DISTRI_RR;
198
+
199
+
idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, distribution_mode);
195
200
196
201
raw_spin_unlock_irqrestore(&mcip_lock, flags);
197
202
···
216
207
217
208
};
218
209
219
-
static int idu_first_irq;
210
+
static irq_hw_number_t idu_first_hwirq;
220
211
221
212
static void idu_cascade_isr(struct irq_desc *desc)
222
213
{
223
-
struct irq_domain *domain = irq_desc_get_handler_data(desc);
224
-
unsigned int core_irq = irq_desc_get_irq(desc);
225
-
unsigned int idu_irq;
214
+
struct irq_domain *idu_domain = irq_desc_get_handler_data(desc);
215
+
irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc));
216
+
irq_hw_number_t idu_hwirq = core_hwirq - idu_first_hwirq;
226
217
227
-
idu_irq = core_irq - idu_first_irq;
228
-
generic_handle_irq(irq_find_mapping(domain, idu_irq));
218
+
generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq));
229
219
}
230
220
231
221
static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq)
···
290
282
struct irq_domain *domain;
291
283
/* Read IDU BCR to confirm nr_irqs */
292
284
int nr_irqs = of_irq_count(intc);
293
-
int i, irq;
285
+
int i, virq;
294
286
struct mcip_bcr mp;
295
287
296
288
READ_BCR(ARC_REG_MCIP_BCR, mp);
···
311
303
* however we need it to get the parent virq and set IDU handler
312
304
* as first level isr
313
305
*/
314
-
irq = irq_of_parse_and_map(intc, i);
306
+
virq = irq_of_parse_and_map(intc, i);
315
307
if (!i)
316
-
idu_first_irq = irq;
308
+
idu_first_hwirq = irqd_to_hwirq(irq_get_irq_data(virq));
317
309
318
-
irq_set_chained_handler_and_data(irq, idu_cascade_isr, domain);
310
+
irq_set_chained_handler_and_data(virq, idu_cascade_isr, domain);
319
311
}
320
312
321
313
__mcip_cmd(CMD_IDU_ENABLE, 0);
+11
-9
arch/arc/kernel/process.c
+11
-9
arch/arc/kernel/process.c
···
43
43
44
44
SYSCALL_DEFINE3(arc_usr_cmpxchg, int *, uaddr, int, expected, int, new)
45
45
{
46
-
int uval;
47
-
int ret;
46
+
struct pt_regs *regs = current_pt_regs();
47
+
int uval = -EFAULT;
48
48
49
49
/*
50
50
* This is only for old cores lacking LLOCK/SCOND, which by defintion
···
54
54
*/
55
55
WARN_ON_ONCE(IS_ENABLED(CONFIG_SMP));
56
56
57
+
/* Z indicates to userspace if operation succeded */
58
+
regs->status32 &= ~STATUS_Z_MASK;
59
+
57
60
if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
58
61
return -EFAULT;
59
62
60
63
preempt_disable();
61
64
62
-
ret = __get_user(uval, uaddr);
63
-
if (ret)
65
+
if (__get_user(uval, uaddr))
64
66
goto done;
65
67
66
-
if (uval != expected)
67
-
ret = -EAGAIN;
68
-
else
69
-
ret = __put_user(new, uaddr);
68
+
if (uval == expected) {
69
+
if (!__put_user(new, uaddr))
70
+
regs->status32 |= STATUS_Z_MASK;
71
+
}
70
72
71
73
done:
72
74
preempt_enable();
73
75
74
-
return ret;
76
+
return uval;
75
77
}
76
78
77
79
void arch_cpu_idle(void)
+15
-8
arch/arc/kernel/smp.c
+15
-8
arch/arc/kernel/smp.c
···
22
22
#include <linux/atomic.h>
23
23
#include <linux/cpumask.h>
24
24
#include <linux/reboot.h>
25
+
#include <linux/irqdomain.h>
25
26
#include <asm/processor.h>
26
27
#include <asm/setup.h>
27
28
#include <asm/mach_desc.h>
···
68
67
int i;
69
68
70
69
/*
71
-
* Initialise the present map, which describes the set of CPUs
72
-
* actually populated at the present time.
70
+
* if platform didn't set the present map already, do it now
71
+
* boot cpu is set to present already by init/main.c
73
72
*/
74
-
for (i = 0; i < max_cpus; i++)
75
-
set_cpu_present(i, true);
73
+
if (num_present_cpus() <= 1) {
74
+
for (i = 0; i < max_cpus; i++)
75
+
set_cpu_present(i, true);
76
+
}
76
77
}
77
78
78
79
void __init smp_cpus_done(unsigned int max_cpus)
···
354
351
*/
355
352
static DEFINE_PER_CPU(int, ipi_dev);
356
353
357
-
int smp_ipi_irq_setup(int cpu, int irq)
354
+
int smp_ipi_irq_setup(int cpu, irq_hw_number_t hwirq)
358
355
{
359
356
int *dev = per_cpu_ptr(&ipi_dev, cpu);
357
+
unsigned int virq = irq_find_mapping(NULL, hwirq);
358
+
359
+
if (!virq)
360
+
panic("Cannot find virq for root domain and hwirq=%lu", hwirq);
360
361
361
362
/* Boot cpu calls request, all call enable */
362
363
if (!cpu) {
363
364
int rc;
364
365
365
-
rc = request_percpu_irq(irq, do_IPI, "IPI Interrupt", dev);
366
+
rc = request_percpu_irq(virq, do_IPI, "IPI Interrupt", dev);
366
367
if (rc)
367
-
panic("Percpu IRQ request failed for %d\n", irq);
368
+
panic("Percpu IRQ request failed for %u\n", virq);
368
369
}
369
370
370
-
enable_percpu_irq(irq, 0);
371
+
enable_percpu_irq(virq, 0);
371
372
372
373
return 0;
373
374
}
+11
-8
arch/arc/kernel/time.c
+11
-8
arch/arc/kernel/time.c
···
152
152
cycle_t full;
153
153
} stamp;
154
154
155
-
156
-
__asm__ __volatile(
157
-
"1: \n"
158
-
" lr %0, [AUX_RTC_LOW] \n"
159
-
" lr %1, [AUX_RTC_HIGH] \n"
160
-
" lr %2, [AUX_RTC_CTRL] \n"
161
-
" bbit0.nt %2, 31, 1b \n"
162
-
: "=r" (stamp.low), "=r" (stamp.high), "=r" (status));
155
+
/*
156
+
* hardware has an internal state machine which tracks readout of
157
+
* low/high and updates the CTRL.status if
158
+
* - interrupt/exception taken between the two reads
159
+
* - high increments after low has been read
160
+
*/
161
+
do {
162
+
stamp.low = read_aux_reg(AUX_RTC_LOW);
163
+
stamp.high = read_aux_reg(AUX_RTC_HIGH);
164
+
status = read_aux_reg(AUX_RTC_CTRL);
165
+
} while (!(status & _BITUL(31)));
163
166
164
167
return stamp.full;
165
168
}
+26
arch/arc/mm/dma.c
+26
arch/arc/mm/dma.c
···
105
105
__free_pages(page, get_order(size));
106
106
}
107
107
108
+
static int arc_dma_mmap(struct device *dev, struct vm_area_struct *vma,
109
+
void *cpu_addr, dma_addr_t dma_addr, size_t size,
110
+
unsigned long attrs)
111
+
{
112
+
unsigned long user_count = vma_pages(vma);
113
+
unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
114
+
unsigned long pfn = __phys_to_pfn(plat_dma_to_phys(dev, dma_addr));
115
+
unsigned long off = vma->vm_pgoff;
116
+
int ret = -ENXIO;
117
+
118
+
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
119
+
120
+
if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
121
+
return ret;
122
+
123
+
if (off < count && user_count <= (count - off)) {
124
+
ret = remap_pfn_range(vma, vma->vm_start,
125
+
pfn + off,
126
+
user_count << PAGE_SHIFT,
127
+
vma->vm_page_prot);
128
+
}
129
+
130
+
return ret;
131
+
}
132
+
108
133
/*
109
134
* streaming DMA Mapping API...
110
135
* CPU accesses page via normal paddr, thus needs to explicitly made
···
218
193
struct dma_map_ops arc_dma_ops = {
219
194
.alloc = arc_dma_alloc,
220
195
.free = arc_dma_free,
196
+
.mmap = arc_dma_mmap,
221
197
.map_page = arc_dma_map_page,
222
198
.map_sg = arc_dma_map_sg,
223
199
.sync_single_for_device = arc_dma_sync_single_for_device,
-6
arch/arc/plat-eznps/smp.c
-6
arch/arc/plat-eznps/smp.c
···
140
140
mtm_enable_core(cpu);
141
141
}
142
142
143
-
static void eznps_ipi_clear(int irq)
144
-
{
145
-
write_aux_reg(CTOP_AUX_IACK, 1 << irq);
146
-
}
147
-
148
143
struct plat_smp_ops plat_smp_ops = {
149
144
.info = smp_cpuinfo_buf,
150
145
.init_early_smp = eznps_init_cpumasks,
151
146
.cpu_kick = eznps_smp_wakeup_cpu,
152
147
.ipi_send = eznps_ipi_send,
153
148
.init_per_cpu = eznps_init_per_cpu,
154
-
.ipi_clear = eznps_ipi_clear,
155
149
};