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arm64: Add support for GICv5 GSB barriers

The GICv5 architecture introduces two barriers instructions
(GSB SYS, GSB ACK) that are used to manage interrupt effects.

Rework macro used to emit the SB barrier instruction and implement
the GSB barriers on top of it.

Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-19-12e71f1b3528@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

authored by

Lorenzo Pieralisi and committed by
Marc Zyngier e62e1e94 ba1004f8

+10 -3
+3
arch/arm64/include/asm/barrier.h
··· 44 44 SB_BARRIER_INSN"nop\n", \ 45 45 ARM64_HAS_SB)) 46 46 47 + #define gsb_ack() asm volatile(GSB_ACK_BARRIER_INSN : : : "memory") 48 + #define gsb_sys() asm volatile(GSB_SYS_BARRIER_INSN : : : "memory") 49 + 47 50 #ifdef CONFIG_ARM64_PSEUDO_NMI 48 51 #define pmr_sync() \ 49 52 do { \
+7 -3
arch/arm64/include/asm/sysreg.h
··· 113 113 /* Register-based PAN access, for save/restore purposes */ 114 114 #define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3) 115 115 116 - #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ 117 - __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) 116 + #define __SYS_BARRIER_INSN(op0, op1, CRn, CRm, op2, Rt) \ 117 + __emit_inst(0xd5000000 | \ 118 + sys_insn((op0), (op1), (CRn), (CRm), (op2)) | \ 119 + ((Rt) & 0x1f)) 118 120 119 - #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) 121 + #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 3, 3, 0, 7, 31) 122 + #define GSB_SYS_BARRIER_INSN __SYS_BARRIER_INSN(1, 0, 12, 0, 0, 31) 123 + #define GSB_ACK_BARRIER_INSN __SYS_BARRIER_INSN(1, 0, 12, 0, 1, 31) 120 124 121 125 /* Data cache zero operations */ 122 126 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)