Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'intel-wired-lan-driver-updates-2025-03-10-ice-ixgbe'
Tony Nguyen says:
====================
Intel Wired LAN Driver Updates 2025-03-10 (ice, ixgbe)
For ice:
Paul adds generic checksum support for E830 devices.
Karol refactors PTP code related to E825C; simplifying PHY register info
struct, utilizing GENMASK, removing unused defines, etc.
For ixgbe:
Piotr adds PTP support for E610 devices.
Jedrzej adds reporting when overheating is detected on E610 devices.
The following are changes since commit 8ef890df4031121a94407c84659125cbccd3fdbe:
net: move misc netdev_lock flavors to a separate header
and are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue 100GbE
====================
Link: https://patch.msgid.link/20250310174502.3708121-1-anthony.l.nguyen@intel.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+146
-95
+1
drivers/net/ethernet/intel/ice/ice.h
+1
drivers/net/ethernet/intel/ice/ice.h
+7
-2
drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h
+7
-2
drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h
···
229
229
__le16 status_error1;
230
230
u8 flexi_flags2;
231
231
u8 ts_low;
232
-
__le16 l2tag2_1st;
232
+
__le16 raw_csum;
233
233
__le16 l2tag2_2nd;
234
234
235
235
/* Qword 3 */
···
478
478
struct ice_tx_ctx_desc {
479
479
__le32 tunneling_params;
480
480
__le16 l2tag2;
481
-
__le16 rsvd;
481
+
__le16 gcs;
482
482
__le64 qw1;
483
483
};
484
+
485
+
#define ICE_TX_GCS_DESC_START_M GENMASK(7, 0)
486
+
#define ICE_TX_GCS_DESC_OFFSET_M GENMASK(11, 8)
487
+
#define ICE_TX_GCS_DESC_TYPE_M GENMASK(14, 12)
488
+
#define ICE_TX_GCS_DESC_CSUM_PSH 1
484
489
485
490
#define ICE_TXD_CTX_QW1_CMD_S 4
486
491
#define ICE_TXD_CTX_QW1_CMD_M (0x7FUL << ICE_TXD_CTX_QW1_CMD_S)
+7
-1
drivers/net/ethernet/intel/ice/ice_lib.c
+7
-1
drivers/net/ethernet/intel/ice/ice_lib.c
···
1431
1431
ring->dev = dev;
1432
1432
ring->count = vsi->num_rx_desc;
1433
1433
ring->cached_phctime = pf->ptp.cached_phc_time;
1434
+
1435
+
if (ice_is_feature_supported(pf, ICE_F_GCS))
1436
+
ring->flags |= ICE_RX_FLAGS_RING_GCS;
1437
+
1434
1438
WRITE_ONCE(vsi->rx_rings[i], ring);
1435
1439
}
1436
1440
···
3903
3899
break;
3904
3900
}
3905
3901
3906
-
if (pf->hw.mac_type == ICE_MAC_E830)
3902
+
if (pf->hw.mac_type == ICE_MAC_E830) {
3907
3903
ice_set_feature_support(pf, ICE_F_MBX_LIMIT);
3904
+
ice_set_feature_support(pf, ICE_F_GCS);
3905
+
}
3908
3906
}
3909
3907
3910
3908
/**
+18
drivers/net/ethernet/intel/ice/ice_main.c
+18
drivers/net/ethernet/intel/ice/ice_main.c
···
3634
3634
/* Allow core to manage IRQs affinity */
3635
3635
netif_set_affinity_auto(netdev);
3636
3636
3637
+
/* Mutual exclusivity for TSO and GCS is enforced by the set features
3638
+
* ndo callback.
3639
+
*/
3640
+
if (ice_is_feature_supported(pf, ICE_F_GCS))
3641
+
netdev->hw_features |= NETIF_F_HW_CSUM;
3642
+
3637
3643
netif_set_tso_max_size(netdev, ICE_MAX_TSO_SIZE);
3638
3644
}
3639
3645
···
6554
6548
6555
6549
if (changed & NETIF_F_LOOPBACK)
6556
6550
ret = ice_set_loopback(vsi, !!(features & NETIF_F_LOOPBACK));
6551
+
6552
+
/* Due to E830 hardware limitations, TSO (NETIF_F_ALL_TSO) with GCS
6553
+
* (NETIF_F_HW_CSUM) is not supported.
6554
+
*/
6555
+
if (ice_is_feature_supported(pf, ICE_F_GCS) &&
6556
+
((features & NETIF_F_HW_CSUM) && (features & NETIF_F_ALL_TSO))) {
6557
+
if (netdev->features & NETIF_F_HW_CSUM)
6558
+
dev_err(ice_pf_to_dev(pf), "To enable TSO, you must first disable HW checksum.\n");
6559
+
else
6560
+
dev_err(ice_pf_to_dev(pf), "To enable HW checksum, you must first disable TSO.\n");
6561
+
return -EIO;
6562
+
}
6557
6563
6558
6564
return ret;
6559
6565
}
+15
-60
drivers/net/ethernet/intel/ice/ice_ptp_consts.h
+15
-60
drivers/net/ethernet/intel/ice/ice_ptp_consts.h
···
10
10
/* Constants defined for the PTP 1588 clock hardware. */
11
11
12
12
const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES] = {
13
-
/* ETH56G_PHY_REG_PTP */
14
-
{
15
-
/* base_addr */
16
-
{
17
-
0x092000,
18
-
0x126000,
19
-
0x1BA000,
20
-
0x24E000,
21
-
0x2E2000,
22
-
},
23
-
/* step */
24
-
0x98,
13
+
[ETH56G_PHY_REG_PTP] = {
14
+
.base_addr = 0x092000,
15
+
.step = 0x98,
25
16
},
26
-
/* ETH56G_PHY_MEM_PTP */
27
-
{
28
-
/* base_addr */
29
-
{
30
-
0x093000,
31
-
0x127000,
32
-
0x1BB000,
33
-
0x24F000,
34
-
0x2E3000,
35
-
},
36
-
/* step */
37
-
0x200,
17
+
[ETH56G_PHY_MEM_PTP] = {
18
+
.base_addr = 0x093000,
19
+
.step = 0x200,
38
20
},
39
-
/* ETH56G_PHY_REG_XPCS */
40
-
{
41
-
/* base_addr */
42
-
{
43
-
0x000000,
44
-
0x009400,
45
-
0x128000,
46
-
0x1BC000,
47
-
0x250000,
48
-
},
49
-
/* step */
50
-
0x21000,
21
+
[ETH56G_PHY_REG_XPCS] = {
22
+
.base_addr = 0x000000,
23
+
.step = 0x21000,
51
24
},
52
-
/* ETH56G_PHY_REG_MAC */
53
-
{
54
-
/* base_addr */
55
-
{
56
-
0x085000,
57
-
0x119000,
58
-
0x1AD000,
59
-
0x241000,
60
-
0x2D5000,
61
-
},
62
-
/* step */
63
-
0x1000,
25
+
[ETH56G_PHY_REG_MAC] = {
26
+
.base_addr = 0x085000,
27
+
.step = 0x1000,
64
28
},
65
-
/* ETH56G_PHY_REG_GPCS */
66
-
{
67
-
/* base_addr */
68
-
{
69
-
0x084000,
70
-
0x118000,
71
-
0x1AC000,
72
-
0x240000,
73
-
0x2D4000,
74
-
},
75
-
/* step */
76
-
0x400,
29
+
[ETH56G_PHY_REG_GPCS] = {
30
+
.base_addr = 0x084000,
31
+
.step = 0x400,
77
32
},
78
33
};
79
34
+9
-10
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+9
-10
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
···
1010
1010
1011
1011
/* Lanes 4..7 are in fact 0..3 on a second PHY */
1012
1012
lane %= hw->ptp.ports_per_phy;
1013
-
*addr = eth56g_phy_res[res_type].base[0] +
1013
+
*addr = eth56g_phy_res[res_type].base_addr +
1014
1014
lane * eth56g_phy_res[res_type].step + offset;
1015
1015
1016
1016
return 0;
···
1240
1240
if (port >= hw->ptp.num_lports)
1241
1241
return -EIO;
1242
1242
1243
-
addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset;
1243
+
addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset;
1244
1244
1245
1245
return ice_write_phy_eth56g(hw, port, addr, val);
1246
1246
}
···
1265
1265
if (port >= hw->ptp.num_lports)
1266
1266
return -EIO;
1267
1267
1268
-
addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset;
1268
+
addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset;
1269
1269
1270
1270
return ice_read_phy_eth56g(hw, port, addr, val);
1271
1271
}
···
2650
2650
}
2651
2651
2652
2652
/**
2653
-
* ice_ptp_init_phc_eth56g - Perform E82X specific PHC initialization
2653
+
* ice_ptp_init_phc_e825 - Perform E825 specific PHC initialization
2654
2654
* @hw: pointer to HW struct
2655
2655
*
2656
-
* Perform PHC initialization steps specific to E82X devices.
2656
+
* Perform E825-specific PTP hardware clock initialization steps.
2657
2657
*
2658
-
* Return:
2659
-
* * %0 - success
2660
-
* * %other - failed to initialize CGU
2658
+
* Return: 0 on success, negative error code otherwise.
2661
2659
*/
2662
-
static int ice_ptp_init_phc_eth56g(struct ice_hw *hw)
2660
+
static int ice_ptp_init_phc_e825(struct ice_hw *hw)
2663
2661
{
2664
2662
ice_sb_access_ena_eth56g(hw, true);
2663
+
2665
2664
/* Initialize the Clock Generation Unit */
2666
2665
return ice_init_cgu_e82x(hw);
2667
2666
}
···
6122
6123
case ICE_MAC_GENERIC:
6123
6124
return ice_ptp_init_phc_e82x(hw);
6124
6125
case ICE_MAC_GENERIC_3K_E825:
6125
-
return ice_ptp_init_phc_eth56g(hw);
6126
+
return ice_ptp_init_phc_e825(hw);
6126
6127
default:
6127
6128
return -EOPNOTSUPP;
6128
6129
}
+16
-19
drivers/net/ethernet/intel/ice/ice_ptp_hw.h
+16
-19
drivers/net/ethernet/intel/ice/ice_ptp_hw.h
···
65
65
66
66
/**
67
67
* struct ice_phy_reg_info_eth56g - ETH56G PHY register parameters
68
-
* @base: base address for each PHY block
68
+
* @base_addr: base address for each PHY block
69
69
* @step: step between PHY lanes
70
70
*
71
71
* Characteristic information for the various PHY register parameters in the
72
72
* ETH56G devices
73
73
*/
74
74
struct ice_phy_reg_info_eth56g {
75
-
u32 base[NUM_ETH56G_PHY_RES];
75
+
u32 base_addr;
76
76
u32 step;
77
77
};
78
78
···
780
780
#define PHY_MAC_XIF_TS_SFD_ENA_M ICE_M(0x1, 20)
781
781
#define PHY_MAC_XIF_GMII_TS_SEL_M ICE_M(0x1, 21)
782
782
783
-
/* GPCS config register */
784
-
#define PHY_GPCS_CONFIG_REG0 0x268
785
-
#define PHY_GPCS_CONFIG_REG0_TX_THR_M ICE_M(0xF, 24)
786
-
#define PHY_GPCS_BITSLIP 0x5C
787
-
788
783
#define PHY_TS_INT_CONFIG_THRESHOLD_M ICE_M(0x3F, 0)
789
784
#define PHY_TS_INT_CONFIG_ENA_M BIT(6)
790
-
791
-
/* 1-step PTP config */
792
-
#define PHY_PTP_1STEP_CONFIG 0x270
793
-
#define PHY_PTP_1STEP_T1S_UP64_M ICE_M(0xF, 4)
794
-
#define PHY_PTP_1STEP_T1S_DELTA_M ICE_M(0xF, 8)
795
-
#define PHY_PTP_1STEP_PEER_DELAY(_port) (0x274 + 4 * (_port))
796
-
#define PHY_PTP_1STEP_PD_ADD_PD_M ICE_M(0x1, 0)
797
-
#define PHY_PTP_1STEP_PD_DELAY_M ICE_M(0x3fffffff, 1)
798
-
#define PHY_PTP_1STEP_PD_DLY_V_M ICE_M(0x1, 31)
799
785
800
786
/* Macros to derive offsets for TimeStampLow and TimeStampHigh */
801
787
#define PHY_TSTAMP_L(x) (((x) * 8) + 0)
802
788
#define PHY_TSTAMP_U(x) (((x) * 8) + 4)
803
-
804
-
#define PHY_REG_REVISION 0x85000
805
789
806
790
#define PHY_REG_DESKEW_0 0x94
807
791
#define PHY_REG_DESKEW_0_RLEVEL GENMASK(6, 0)
···
793
809
#define PHY_REG_DESKEW_0_RLEVEL_FRAC_W 3
794
810
#define PHY_REG_DESKEW_0_VALID GENMASK(10, 10)
795
811
796
-
#define PHY_REG_GPCS_BITSLIP 0x5C
797
812
#define PHY_REG_SD_BIT_SLIP(_port_offset) (0x29C + 4 * (_port_offset))
798
813
#define PHY_REVISION_ETH56G 0x10200
799
814
#define PHY_VENDOR_TXLANE_THRESH 0x2000C
···
812
829
#define PHY_MAC_BLOCKTIME 0x50
813
830
#define PHY_MAC_MARKERTIME 0x54
814
831
#define PHY_MAC_TX_OFFSET 0x58
832
+
#define PHY_GPCS_BITSLIP 0x5C
815
833
816
834
#define PHY_PTP_INT_STATUS 0x7FD140
835
+
836
+
/* ETH56G registers shared per quad */
837
+
/* GPCS config register */
838
+
#define PHY_GPCS_CONFIG_REG0 0x268
839
+
#define PHY_GPCS_CONFIG_REG0_TX_THR_M GENMASK(27, 24)
840
+
/* 1-step PTP config */
841
+
#define PHY_PTP_1STEP_CONFIG 0x270
842
+
#define PHY_PTP_1STEP_T1S_UP64_M GENMASK(7, 4)
843
+
#define PHY_PTP_1STEP_T1S_DELTA_M GENMASK(11, 8)
844
+
#define PHY_PTP_1STEP_PEER_DELAY(_quad_lane) (0x274 + 4 * (_quad_lane))
845
+
#define PHY_PTP_1STEP_PD_ADD_PD_M BIT(0)
846
+
#define PHY_PTP_1STEP_PD_DELAY_M GENMASK(30, 1)
847
+
#define PHY_PTP_1STEP_PD_DLY_V_M BIT(31)
817
848
818
849
#endif /* _ICE_PTP_HW_H_ */
+26
-1
drivers/net/ethernet/intel/ice/ice_txrx.c
+26
-1
drivers/net/ethernet/intel/ice/ice_txrx.c
···
1809
1809
static
1810
1810
int ice_tx_csum(struct ice_tx_buf *first, struct ice_tx_offload_params *off)
1811
1811
{
1812
+
const struct ice_tx_ring *tx_ring = off->tx_ring;
1812
1813
u32 l4_len = 0, l3_len = 0, l2_len = 0;
1813
1814
struct sk_buff *skb = first->skb;
1814
1815
union {
···
1958
1957
/* compute inner L3 header size */
1959
1958
l3_len = l4.hdr - ip.hdr;
1960
1959
offset |= (l3_len / 4) << ICE_TX_DESC_LEN_IPLEN_S;
1960
+
1961
+
if ((tx_ring->netdev->features & NETIF_F_HW_CSUM) &&
1962
+
!(first->tx_flags & ICE_TX_FLAGS_TSO) &&
1963
+
!skb_csum_is_sctp(skb)) {
1964
+
/* Set GCS */
1965
+
u16 csum_start = (skb->csum_start - skb->mac_header) / 2;
1966
+
u16 csum_offset = skb->csum_offset / 2;
1967
+
u16 gcs_params;
1968
+
1969
+
gcs_params = FIELD_PREP(ICE_TX_GCS_DESC_START_M, csum_start) |
1970
+
FIELD_PREP(ICE_TX_GCS_DESC_OFFSET_M, csum_offset) |
1971
+
FIELD_PREP(ICE_TX_GCS_DESC_TYPE_M,
1972
+
ICE_TX_GCS_DESC_CSUM_PSH);
1973
+
1974
+
/* Unlike legacy HW checksums, GCS requires a context
1975
+
* descriptor.
1976
+
*/
1977
+
off->cd_qw1 |= ICE_TX_DESC_DTYPE_CTX;
1978
+
off->cd_gcs_params = gcs_params;
1979
+
/* Fill out CSO info in data descriptors */
1980
+
off->td_offset |= offset;
1981
+
off->td_cmd |= cmd;
1982
+
return 1;
1983
+
}
1961
1984
1962
1985
/* Enable L4 checksum offloads */
1963
1986
switch (l4_proto) {
···
2466
2441
/* setup context descriptor */
2467
2442
cdesc->tunneling_params = cpu_to_le32(offload.cd_tunnel_params);
2468
2443
cdesc->l2tag2 = cpu_to_le16(offload.cd_l2tag2);
2469
-
cdesc->rsvd = cpu_to_le16(0);
2444
+
cdesc->gcs = cpu_to_le16(offload.cd_gcs_params);
2470
2445
cdesc->qw1 = cpu_to_le64(offload.cd_qw1);
2471
2446
}
2472
2447
+2
drivers/net/ethernet/intel/ice/ice_txrx.h
+2
drivers/net/ethernet/intel/ice/ice_txrx.h
···
193
193
u32 td_l2tag1;
194
194
u32 cd_tunnel_params;
195
195
u16 cd_l2tag2;
196
+
u16 cd_gcs_params;
196
197
u8 header_len;
197
198
};
198
199
···
367
366
#define ICE_RX_FLAGS_RING_BUILD_SKB BIT(1)
368
367
#define ICE_RX_FLAGS_CRC_STRIP_DIS BIT(2)
369
368
#define ICE_RX_FLAGS_MULTIDEV BIT(3)
369
+
#define ICE_RX_FLAGS_RING_GCS BIT(4)
370
370
u8 flags;
371
371
/* CL5 - 5th cacheline starts here */
372
372
struct xdp_rxq_info xdp_rxq;
+26
drivers/net/ethernet/intel/ice/ice_txrx_lib.c
+26
drivers/net/ethernet/intel/ice/ice_txrx_lib.c
···
81
81
}
82
82
83
83
/**
84
+
* ice_rx_gcs - Set generic checksum in skb
85
+
* @skb: skb currently being received and modified
86
+
* @rx_desc: receive descriptor
87
+
*/
88
+
static void ice_rx_gcs(struct sk_buff *skb,
89
+
const union ice_32b_rx_flex_desc *rx_desc)
90
+
{
91
+
const struct ice_32b_rx_flex_desc_nic *desc;
92
+
u16 csum;
93
+
94
+
desc = (struct ice_32b_rx_flex_desc_nic *)rx_desc;
95
+
skb->ip_summed = CHECKSUM_COMPLETE;
96
+
csum = (__force u16)desc->raw_csum;
97
+
skb->csum = csum_unfold((__force __sum16)swab16(csum));
98
+
}
99
+
100
+
/**
84
101
* ice_rx_csum - Indicate in skb if checksum is good
85
102
* @ring: the ring we care about
86
103
* @skb: skb currently being received and modified
···
123
106
124
107
rx_status0 = le16_to_cpu(rx_desc->wb.status_error0);
125
108
rx_status1 = le16_to_cpu(rx_desc->wb.status_error1);
109
+
110
+
if ((ring->flags & ICE_RX_FLAGS_RING_GCS) &&
111
+
rx_desc->wb.rxdid == ICE_RXDID_FLEX_NIC &&
112
+
(decoded.inner_prot == LIBETH_RX_PT_INNER_TCP ||
113
+
decoded.inner_prot == LIBETH_RX_PT_INNER_UDP ||
114
+
decoded.inner_prot == LIBETH_RX_PT_INNER_ICMP)) {
115
+
ice_rx_gcs(skb, rx_desc);
116
+
return;
117
+
}
126
118
127
119
/* check if HW has decoded the packet and checksum */
128
120
if (!(rx_status0 & BIT(ICE_RX_FLEX_DESC_STATUS0_L3L4P_S)))
+1
drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
+1
drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
+4
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+4
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
···
3185
3185
case ixgbe_aci_opc_get_link_status:
3186
3186
ixgbe_handle_link_status_event(adapter, &event);
3187
3187
break;
3188
+
case ixgbe_aci_opc_temp_tca_event:
3189
+
e_crit(drv, "%s\n", ixgbe_overheat_msg);
3190
+
ixgbe_down(adapter);
3191
+
break;
3188
3192
default:
3189
3193
e_warn(hw, "unknown FW async event captured\n");
3190
3194
break;
+11
-2
drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
+11
-2
drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
···
140
140
* proper mult and shift to convert the cycles into nanoseconds of time.
141
141
*/
142
142
#define IXGBE_X550_BASE_PERIOD 0xC80000000ULL
143
+
#define IXGBE_E610_BASE_PERIOD 0x333333333ULL
143
144
#define INCVALUE_MASK 0x7FFFFFFF
144
145
#define ISGN 0x80000000
145
146
···
416
415
case ixgbe_mac_X550:
417
416
case ixgbe_mac_X550EM_x:
418
417
case ixgbe_mac_x550em_a:
418
+
case ixgbe_mac_e610:
419
419
/* Upper 32 bits represent billions of cycles, lower 32 bits
420
420
* represent cycles. However, we use timespec64_to_ns for the
421
421
* correct math even though the units haven't been corrected
···
494
492
struct ixgbe_adapter *adapter =
495
493
container_of(ptp, struct ixgbe_adapter, ptp_caps);
496
494
struct ixgbe_hw *hw = &adapter->hw;
495
+
u64 rate, base;
497
496
bool neg_adj;
498
-
u64 rate;
499
497
u32 inca;
500
498
501
-
neg_adj = diff_by_scaled_ppm(IXGBE_X550_BASE_PERIOD, scaled_ppm, &rate);
499
+
base = hw->mac.type == ixgbe_mac_e610 ? IXGBE_E610_BASE_PERIOD :
500
+
IXGBE_X550_BASE_PERIOD;
501
+
neg_adj = diff_by_scaled_ppm(base, scaled_ppm, &rate);
502
502
503
503
/* warn if rate is too large */
504
504
if (rate >= INCVALUE_MASK)
···
563
559
case ixgbe_mac_X550:
564
560
case ixgbe_mac_X550EM_x:
565
561
case ixgbe_mac_x550em_a:
562
+
case ixgbe_mac_e610:
566
563
/* Upper 32 bits represent billions of cycles, lower 32 bits
567
564
* represent cycles. However, we use timespec64_to_ns for the
568
565
* correct math even though the units haven't been corrected
···
1072
1067
case ixgbe_mac_X550:
1073
1068
case ixgbe_mac_X550EM_x:
1074
1069
case ixgbe_mac_x550em_a:
1070
+
case ixgbe_mac_e610:
1075
1071
/* enable timestamping all packets only if at least some
1076
1072
* packets were requested. Otherwise, play nice and disable
1077
1073
* timestamping
···
1239
1233
fallthrough;
1240
1234
case ixgbe_mac_x550em_a:
1241
1235
case ixgbe_mac_X550:
1236
+
case ixgbe_mac_e610:
1242
1237
cc.read = ixgbe_ptp_read_X550;
1243
1238
break;
1244
1239
case ixgbe_mac_X540:
···
1287
1280
case ixgbe_mac_X550EM_x:
1288
1281
case ixgbe_mac_x550em_a:
1289
1282
case ixgbe_mac_X550:
1283
+
case ixgbe_mac_e610:
1290
1284
tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
1291
1285
1292
1286
/* Reset SYSTIME registers to 0 */
···
1415
1407
case ixgbe_mac_X550:
1416
1408
case ixgbe_mac_X550EM_x:
1417
1409
case ixgbe_mac_x550em_a:
1410
+
case ixgbe_mac_e610:
1418
1411
snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
1419
1412
adapter->ptp_caps.owner = THIS_MODULE;
1420
1413
adapter->ptp_caps.max_adj = 30000000;
+3
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h
+3
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h