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Merge branch 'net-phy-nxp-c45-tja11xx-add-errata-for-tja112xa-b'

Andrei Botila says:

====================
net: phy: nxp-c45-tja11xx: add errata for TJA112XA/B

This patch series implements two errata for TJA1120 and TJA1121.

The first errata applicable to both RGMII and SGMII version
of TJA1120 and TJA1121 deals with achieving full silicon performance.
The workaround in this case is putting the PHY in managed mode and
applying a series of PHY writes before the link gest established.

The second errata applicable only to SGMII version of TJA1120 and
TJA1121 deals with achieving a stable operation of SGMII after a
startup event.
The workaround puts the SGMII PCS into power down mode and back up
after restart or wakeup from sleep.
====================

Link: https://patch.msgid.link/20250304160619.181046-1-andrei.botila@oss.nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski e6360f0d df8ce77b

+68
+68
drivers/net/phy/nxp-c45-tja11xx.c
··· 22 22 #define PHY_ID_TJA_1103 0x001BB010 23 23 #define PHY_ID_TJA_1120 0x001BB031 24 24 25 + #define VEND1_DEVICE_ID3 0x0004 26 + #define TJA1120_DEV_ID3_SILICON_VERSION GENMASK(15, 12) 27 + #define TJA1120_DEV_ID3_SAMPLE_TYPE GENMASK(11, 8) 28 + #define DEVICE_ID3_SAMPLE_TYPE_R 0x9 29 + 25 30 #define VEND1_DEVICE_CONTROL 0x0040 26 31 #define DEVICE_CONTROL_RESET BIT(15) 27 32 #define DEVICE_CONTROL_CONFIG_GLOBAL_EN BIT(14) ··· 113 108 #define MII_BASIC_CONFIG_RGMII 0x7 114 109 #define MII_BASIC_CONFIG_RMII 0x5 115 110 #define MII_BASIC_CONFIG_MII 0x4 111 + 112 + #define VEND1_SGMII_BASIC_CONTROL 0xB000 113 + #define SGMII_LPM BIT(11) 116 114 117 115 #define VEND1_SYMBOL_ERROR_CNT_XTD 0x8351 118 116 #define EXTENDED_CNT_EN BIT(15) ··· 1601 1593 return 0; 1602 1594 } 1603 1595 1596 + /* Errata: ES_TJA1120 and ES_TJA1121 Rev. 1.0 — 28 November 2024 Section 3.1 & 3.2 */ 1597 + static void nxp_c45_tja1120_errata(struct phy_device *phydev) 1598 + { 1599 + bool macsec_ability, sgmii_ability; 1600 + int silicon_version, sample_type; 1601 + int phy_abilities; 1602 + int ret = 0; 1603 + 1604 + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3); 1605 + if (ret < 0) 1606 + return; 1607 + 1608 + sample_type = FIELD_GET(TJA1120_DEV_ID3_SAMPLE_TYPE, ret); 1609 + if (sample_type != DEVICE_ID3_SAMPLE_TYPE_R) 1610 + return; 1611 + 1612 + silicon_version = FIELD_GET(TJA1120_DEV_ID3_SILICON_VERSION, ret); 1613 + 1614 + phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1, 1615 + VEND1_PORT_ABILITIES); 1616 + macsec_ability = !!(phy_abilities & MACSEC_ABILITY); 1617 + sgmii_ability = !!(phy_abilities & SGMII_ABILITY); 1618 + if ((!macsec_ability && silicon_version == 2) || 1619 + (macsec_ability && silicon_version == 1)) { 1620 + /* TJA1120/TJA1121 PHY configuration errata workaround. 1621 + * Apply PHY writes sequence before link up. 1622 + */ 1623 + if (!macsec_ability) { 1624 + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95); 1625 + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd); 1626 + } else { 1627 + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7); 1628 + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893); 1629 + } 1630 + 1631 + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0); 1632 + 1633 + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x8921, 0xa3a); 1634 + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x89F1, 0x16c1); 1635 + 1636 + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0); 1637 + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0); 1638 + 1639 + if (sgmii_ability) { 1640 + /* TJA1120B/TJA1121B SGMII PCS restart errata workaround. 1641 + * Put SGMII PCS into power down mode and back up. 1642 + */ 1643 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 1644 + VEND1_SGMII_BASIC_CONTROL, 1645 + SGMII_LPM); 1646 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 1647 + VEND1_SGMII_BASIC_CONTROL, 1648 + SGMII_LPM); 1649 + } 1650 + } 1651 + } 1652 + 1604 1653 static int nxp_c45_config_init(struct phy_device *phydev) 1605 1654 { 1606 1655 int ret; ··· 1673 1608 */ 1674 1609 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1); 1675 1610 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2); 1611 + 1612 + if (phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, GENMASK(31, 4))) 1613 + nxp_c45_tja1120_errata(phydev); 1676 1614 1677 1615 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG, 1678 1616 PHY_CONFIG_AUTO);