tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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scsi: ufs: core: mcq: Use ufshcd_rmwl() instead of open-coding it

Currently, ufshcd_mcq_enable_esi() manually implements a
read-modify-write sequence using ufshcd_readl() and ufshcd_writel().
It also utilizes a hardcoded magic number (0x2) for the enable bit.

Use ufshcd_rmwl() helper, replace the magic number with the
ESI_ENABLE macro to improve code readability.

No functional change intended.

Signed-off-by: vamshi gajjela <vamshigajjela@google.com>
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Link: https://patch.msgid.link/20251211133227.4159394-1-vamshigajjela@google.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

authored by

vamshi gajjela and committed by
Martin K. Petersen e642331c 7011e8aa

+2 -2
+1 -2
drivers/ufs/core/ufs-mcq.c
··· 431 431 432 432 void ufshcd_mcq_enable_esi(struct ufs_hba *hba) 433 433 { 434 - ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x2, 435 - REG_UFS_MEM_CFG); 434 + ufshcd_rmwl(hba, ESI_ENABLE, ESI_ENABLE, REG_UFS_MEM_CFG); 436 435 } 437 436 EXPORT_SYMBOL_GPL(ufshcd_mcq_enable_esi); 438 437
+1
include/ufs/ufshci.h
··· 288 288 289 289 /* REG_UFS_MEM_CFG - Global Config Registers 300h */ 290 290 #define MCQ_MODE_SELECT BIT(0) 291 + #define ESI_ENABLE BIT(1) 291 292 292 293 /* CQISy - CQ y Interrupt Status Register */ 293 294 #define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1