Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'samsung-dt64-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.17
1. New SoC - Exynos2200 SoC - with basic nodes, pin controllers,
clock controllers and initial USB support. Add board using it:
Samsung Galaxy S22+ (SM-S906B), called G0S.
2. ExynosAutov920: Add CMU_HSI2 clock controller, remaining SPI nodes
3. Google GS101:
- Prepare to switching to architected timer, instead of Exynos MCT as
the primary one.
- Add secondary Maxim MAX77759 PMIC to Pixel boards, managing USB Type-C and
charger.
- Add incomplete description of the primary Samsung S2MPG10 PMIC.
Several bits, like regulators, are still missing, though.
- Add also secondary reboot-mode, via MAX77759 NVMEM.
- Switch the primary (SoC) reboot handler to Google specific
google,gs101-reboot which gives additional GS101 features (cold and
warm reboots).
This change will affect other users of this DTS, but to our
knowledge there is only Android, from which this change originates.
4. Exynos7870:
- Fix speed problems in USB gadget mode.
- Correct memory map to avoid crashes due to secure world.
* tag 'samsung-dt64-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos7870-j6lte: reduce memory ranges to base amount
arm64: dts: exynos7870-on7xelte: reduce memory ranges to base amount
arm64: dts: exynos7870: add quirk to disable USB2 LPM in gadget mode
arm64: dts: exynos: gs101: switch to gs101 specific reboot
arm64: dts: exynos: gs101-pixel-common: add main PMIC node
arm64: dts: exynos: gs101: ufs: add dma-coherent property
arm64: dts: exynos: gs101: add dm-verity-device-corrupted syscon-reboot-mode
arm64: dts: exynos: gs101-pixel-common: add nvmem-reboot-mode
arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 PMIC
arm64: dts: exynos5433: Align i2c-gpio node names with dtschema
arm64: dts: exynos: gs101: Add 'local-timer-stop' to cpuidle nodes
arm64: dts: exynosautov920: Add DT node for all SPI ports
arm64: dts: exynosautov920: add CMU_HSI2 clock DT nodes
MAINTAINERS: add entry for Samsung Exynos2200 SoC
arm64: dts: exynos: add initial support for Samsung Galaxy S22+
arm64: dts: exynos: add initial support for exynos2200 SoC
dt-bindings: arm: samsung: document g0s board binding
Link: https://lore.kernel.org/r/20250709191523.171359-6-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+2996
-7
+6
Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
+6
Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
···
45
45
- const: samsung,aries
46
46
- const: samsung,s5pv210
47
47
48
+
- description: Exynos2200 based boards
49
+
items:
50
+
- enum:
51
+
- samsung,g0s # Samsung Galaxy S22+ (SM-S906B)
52
+
- const: samsung,exynos2200
53
+
48
54
- description: Exynos3250 based boards
49
55
items:
50
56
- enum:
+10
MAINTAINERS
+10
MAINTAINERS
···
21941
21941
F: Documentation/devicetree/bindings/sound/samsung*
21942
21942
F: sound/soc/samsung/
21943
21943
21944
+
SAMSUNG EXYNOS2200 SoC SUPPORT
21945
+
M: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
21946
+
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
21947
+
L: linux-samsung-soc@vger.kernel.org
21948
+
S: Maintained
21949
+
F: Documentation/devicetree/bindings/clock/samsung,exynos2200-cmu.yaml
21950
+
F: arch/arm64/boot/dts/exynos/exynos2200*
21951
+
F: drivers/clk/samsung/clk-exynos2200.c
21952
+
F: include/dt-bindings/clock/samsung,exynos2200-cmu.h
21953
+
21944
21954
SAMSUNG EXYNOS850 SoC SUPPORT
21945
21955
M: Sam Protsenko <semen.protsenko@linaro.org>
21946
21956
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+1
arch/arm64/boot/dts/exynos/Makefile
+1
arch/arm64/boot/dts/exynos/Makefile
+169
arch/arm64/boot/dts/exynos/exynos2200-g0s.dts
+169
arch/arm64/boot/dts/exynos/exynos2200-g0s.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2
+
/*
3
+
* Samsung Galaxy S22+ (g0s/SM-S906B) device tree source
4
+
*
5
+
* Copyright (c) 2025, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
6
+
*/
7
+
8
+
/dts-v1/;
9
+
#include "exynos2200.dtsi"
10
+
#include <dt-bindings/gpio/gpio.h>
11
+
#include <dt-bindings/input/input.h>
12
+
#include <dt-bindings/interrupt-controller/irq.h>
13
+
14
+
/ {
15
+
model = "Samsung Galaxy S22+ (SM-S906B)";
16
+
compatible = "samsung,g0s", "samsung,exynos2200";
17
+
chassis-type = "handset";
18
+
19
+
chosen {
20
+
#address-cells = <2>;
21
+
#size-cells = <2>;
22
+
ranges;
23
+
24
+
framebuffer: framebuffer {
25
+
compatible = "simple-framebuffer";
26
+
memory-region = <&cont_splash_mem>;
27
+
width = <1080>;
28
+
height = <2340>;
29
+
stride = <(1080 * 4)>;
30
+
format = "a8r8g8b8";
31
+
};
32
+
};
33
+
34
+
/*
35
+
* RTC clock (XrtcXTI); external, must be 32.768 kHz.
36
+
*
37
+
* TODO: Remove this once RTC clock is implemented properly as part of
38
+
* PMIC driver.
39
+
*/
40
+
rtcclk: clock-rtcclk {
41
+
compatible = "fixed-clock";
42
+
clock-output-names = "rtcclk";
43
+
#clock-cells = <0>;
44
+
clock-frequency = <32768>;
45
+
};
46
+
47
+
gpio-keys {
48
+
compatible = "gpio-keys";
49
+
50
+
pinctrl-0 = <&key_volup>;
51
+
pinctrl-names = "default";
52
+
53
+
volup-key {
54
+
label = "Volume Up";
55
+
linux,code = <KEY_VOLUMEUP>;
56
+
gpios = <&gpa3 0 GPIO_ACTIVE_LOW>;
57
+
wakeup-source;
58
+
};
59
+
};
60
+
61
+
memory@80000000 {
62
+
device_type = "memory";
63
+
reg = <0x0 0x80000000 0x0 0x80000000>,
64
+
<0x8 0x80000000 0x1 0x7e000000>;
65
+
};
66
+
67
+
/* TODO: Remove this once PMIC is implemented */
68
+
reg_dummy: regulator-0 {
69
+
compatible = "regulator-fixed";
70
+
regulator-name = "dummy_reg";
71
+
};
72
+
73
+
reserved-memory {
74
+
#address-cells = <2>;
75
+
#size-cells = <2>;
76
+
ranges;
77
+
78
+
cont_splash_mem: framebuffer@f6200000 {
79
+
reg = <0x0 0xf6200000 0x0 (1080 * 2340 * 4)>;
80
+
no-map;
81
+
};
82
+
83
+
debug_kinfo_reserved: debug-kinfo-reserved@fcfff000 {
84
+
reg = <0x0 0xfcfff000 0x0 0x1000>;
85
+
no-map;
86
+
};
87
+
88
+
log_itmon: log-itmon@fffe0000 {
89
+
reg = <0x0 0xfffe0000 0x0 0x20000>;
90
+
no-map;
91
+
};
92
+
};
93
+
};
94
+
95
+
&cmu_hsi0 {
96
+
clocks = <&xtcxo>,
97
+
<&rtcclk>,
98
+
<&cmu_top CLK_DOUT_CMU_HSI0_NOC>,
99
+
<&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>,
100
+
<&cmu_top CLK_DOUT_CMU_HSI0_DPOSC>,
101
+
<&cmu_top CLK_DOUT_CMU_HSI0_USB32DRD>;
102
+
clock-names = "oscclk", "rtcclk", "noc", "dpgtc", "dposc", "usb";
103
+
};
104
+
105
+
/*
106
+
* cpu2 and cpu3 fail to come up consistently, which leads to a hang later
107
+
* in the boot process. Disable them until the issue is figured out.
108
+
*/
109
+
&cpu2 {
110
+
status = "fail";
111
+
};
112
+
113
+
&cpu3 {
114
+
status = "fail";
115
+
};
116
+
117
+
&ext_26m {
118
+
clock-frequency = <26000000>;
119
+
};
120
+
121
+
&ext_200m {
122
+
clock-frequency = <200000000>;
123
+
};
124
+
125
+
&mct_peris {
126
+
status = "okay";
127
+
};
128
+
129
+
&pinctrl_alive {
130
+
key_volup: key-volup-pins {
131
+
samsung,pins = "gpa3-0";
132
+
samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
133
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
134
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
135
+
};
136
+
};
137
+
138
+
&ppi_cluster0 {
139
+
affinity = <&cpu0 &cpu1>;
140
+
};
141
+
142
+
&usb {
143
+
/* TODO: Replace these once PMIC is implemented */
144
+
vdd10-supply = <®_dummy>;
145
+
vdd33-supply = <®_dummy>;
146
+
status = "okay";
147
+
};
148
+
149
+
&usb32drd {
150
+
status = "okay";
151
+
};
152
+
153
+
&usb_dwc3 {
154
+
dr_mode = "otg";
155
+
usb-role-switch;
156
+
role-switch-default-mode = "peripheral";
157
+
maximum-speed = "high-speed";
158
+
};
159
+
160
+
&usb_hsphy {
161
+
/* TODO: Replace these once PMIC is implemented */
162
+
vdda12-supply = <®_dummy>;
163
+
vdd-supply = <®_dummy>;
164
+
status = "okay";
165
+
};
166
+
167
+
&xtcxo {
168
+
clock-frequency = <76800000>;
169
+
};
+1765
arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi
+1765
arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2
+
/*
3
+
* Samsung's Exynos 2200 SoC pin-mux and pin-config device tree source
4
+
*
5
+
* Copyright (c) 2025, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
6
+
*/
7
+
8
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
9
+
#include "exynos-pinctrl.h"
10
+
11
+
&pinctrl_alive {
12
+
gpa0: gpa0-gpio-bank {
13
+
gpio-controller;
14
+
#gpio-cells = <2>;
15
+
16
+
interrupt-controller;
17
+
#interrupt-cells = <2>;
18
+
interrupt-parent = <&gic>;
19
+
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
20
+
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
21
+
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
22
+
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
23
+
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
24
+
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
25
+
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
26
+
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>;
27
+
};
28
+
29
+
gpa1: gpa1-gpio-bank {
30
+
gpio-controller;
31
+
#gpio-cells = <2>;
32
+
33
+
interrupt-controller;
34
+
#interrupt-cells = <2>;
35
+
interrupt-parent = <&gic>;
36
+
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
37
+
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>,
38
+
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
39
+
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
40
+
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>,
41
+
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
42
+
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
43
+
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
44
+
};
45
+
46
+
gpa2: gpa2-gpio-bank {
47
+
gpio-controller;
48
+
#gpio-cells = <2>;
49
+
50
+
interrupt-controller;
51
+
#interrupt-cells = <2>;
52
+
interrupt-parent = <&gic>;
53
+
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>,
54
+
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>,
55
+
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>,
56
+
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
57
+
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
58
+
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
59
+
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>,
60
+
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
61
+
};
62
+
63
+
gpa3: gpa3-gpio-bank {
64
+
gpio-controller;
65
+
#gpio-cells = <2>;
66
+
67
+
interrupt-controller;
68
+
#interrupt-cells = <2>;
69
+
interrupt-parent = <&gic>;
70
+
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>,
71
+
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>,
72
+
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>,
73
+
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>,
74
+
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
75
+
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>,
76
+
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
77
+
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
78
+
};
79
+
80
+
gpa4: gpa4-gpio-bank {
81
+
gpio-controller;
82
+
#gpio-cells = <2>;
83
+
84
+
interrupt-controller;
85
+
#interrupt-cells = <2>;
86
+
interrupt-parent = <&gic>;
87
+
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>,
88
+
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH 0>;
89
+
};
90
+
91
+
gpq0: gpq0-gpio-bank {
92
+
gpio-controller;
93
+
#gpio-cells = <2>;
94
+
};
95
+
96
+
gpq1: gpq1-gpio-bank {
97
+
gpio-controller;
98
+
#gpio-cells = <2>;
99
+
};
100
+
101
+
gpq2: gpq2-gpio-bank {
102
+
gpio-controller;
103
+
#gpio-cells = <2>;
104
+
};
105
+
106
+
bt_hostwake: bt-hostwake-pins {
107
+
samsung,pins = "gpa0-3";
108
+
samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
109
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
110
+
};
111
+
112
+
uart1_bus: uart1-bus-pins {
113
+
samsung,pins = "gpq0-3", "gpq0-2", "gpq0-1", "gpq0-0";
114
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
115
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
116
+
};
117
+
118
+
wlan_host_wake: wlan-host-wake-pins {
119
+
samsung,pins = "gpa0-2";
120
+
samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
121
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
122
+
};
123
+
};
124
+
125
+
&pinctrl_cmgp {
126
+
gpm0: gpm0-gpio-bank {
127
+
gpio-controller;
128
+
#gpio-cells = <2>;
129
+
130
+
interrupt-controller;
131
+
#interrupt-cells = <2>;
132
+
interrupt-parent = <&gic>;
133
+
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>,
134
+
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
135
+
};
136
+
137
+
gpm1: gpm1-gpio-bank {
138
+
gpio-controller;
139
+
#gpio-cells = <2>;
140
+
141
+
interrupt-controller;
142
+
#interrupt-cells = <2>;
143
+
interrupt-parent = <&gic>;
144
+
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
145
+
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
146
+
};
147
+
148
+
gpm2: gpm2-gpio-bank {
149
+
gpio-controller;
150
+
#gpio-cells = <2>;
151
+
152
+
interrupt-controller;
153
+
#interrupt-cells = <2>;
154
+
interrupt-parent = <&gic>;
155
+
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>,
156
+
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>;
157
+
};
158
+
159
+
gpm3: gpm3-gpio-bank {
160
+
gpio-controller;
161
+
#gpio-cells = <2>;
162
+
163
+
interrupt-controller;
164
+
#interrupt-cells = <2>;
165
+
interrupt-parent = <&gic>;
166
+
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH 0>,
167
+
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
168
+
};
169
+
170
+
gpm4: gpm4-gpio-bank {
171
+
gpio-controller;
172
+
#gpio-cells = <2>;
173
+
174
+
interrupt-controller;
175
+
#interrupt-cells = <2>;
176
+
interrupt-parent = <&gic>;
177
+
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>,
178
+
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>;
179
+
};
180
+
181
+
gpm5: gpm5-gpio-bank {
182
+
gpio-controller;
183
+
#gpio-cells = <2>;
184
+
185
+
interrupt-controller;
186
+
#interrupt-cells = <2>;
187
+
interrupt-parent = <&gic>;
188
+
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>,
189
+
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>;
190
+
};
191
+
192
+
gpm6: gpm6-gpio-bank {
193
+
gpio-controller;
194
+
#gpio-cells = <2>;
195
+
196
+
interrupt-controller;
197
+
#interrupt-cells = <2>;
198
+
interrupt-parent = <&gic>;
199
+
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>,
200
+
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
201
+
};
202
+
203
+
gpm7: gpm7-gpio-bank {
204
+
gpio-controller;
205
+
#gpio-cells = <2>;
206
+
207
+
interrupt-controller;
208
+
#interrupt-cells = <2>;
209
+
interrupt-parent = <&gic>;
210
+
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>,
211
+
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
212
+
};
213
+
214
+
gpm8: gpm8-gpio-bank {
215
+
gpio-controller;
216
+
#gpio-cells = <2>;
217
+
218
+
interrupt-controller;
219
+
#interrupt-cells = <2>;
220
+
interrupt-parent = <&gic>;
221
+
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>,
222
+
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>;
223
+
};
224
+
225
+
gpm9: gpm9-gpio-bank {
226
+
gpio-controller;
227
+
#gpio-cells = <2>;
228
+
229
+
interrupt-controller;
230
+
#interrupt-cells = <2>;
231
+
interrupt-parent = <&gic>;
232
+
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>,
233
+
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
234
+
};
235
+
236
+
gpm10: gpm10-gpio-bank {
237
+
gpio-controller;
238
+
#gpio-cells = <2>;
239
+
240
+
interrupt-controller;
241
+
#interrupt-cells = <2>;
242
+
interrupt-parent = <&gic>;
243
+
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>,
244
+
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>;
245
+
};
246
+
247
+
gpm11: gpm11-gpio-bank {
248
+
gpio-controller;
249
+
#gpio-cells = <2>;
250
+
251
+
interrupt-controller;
252
+
#interrupt-cells = <2>;
253
+
interrupt-parent = <&gic>;
254
+
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>,
255
+
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>;
256
+
};
257
+
258
+
gpm12: gpm12-gpio-bank {
259
+
gpio-controller;
260
+
#gpio-cells = <2>;
261
+
262
+
interrupt-controller;
263
+
#interrupt-cells = <2>;
264
+
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>,
265
+
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
266
+
};
267
+
268
+
gpm13: gpm13-gpio-bank {
269
+
gpio-controller;
270
+
#gpio-cells = <2>;
271
+
272
+
interrupt-controller;
273
+
#interrupt-cells = <2>;
274
+
interrupt-parent = <&gic>;
275
+
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>,
276
+
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
277
+
};
278
+
279
+
gpm14: gpm14-gpio-bank {
280
+
gpio-controller;
281
+
#gpio-cells = <2>;
282
+
283
+
interrupt-controller;
284
+
#interrupt-cells = <2>;
285
+
interrupt-parent = <&gic>;
286
+
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
287
+
};
288
+
289
+
gpm15: gpm15-gpio-bank {
290
+
gpio-controller;
291
+
#gpio-cells = <2>;
292
+
293
+
interrupt-controller;
294
+
#interrupt-cells = <2>;
295
+
interrupt-parent = <&gic>;
296
+
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH 0>;
297
+
};
298
+
299
+
gpm16: gpm16-gpio-bank {
300
+
gpio-controller;
301
+
#gpio-cells = <2>;
302
+
303
+
interrupt-controller;
304
+
#interrupt-cells = <2>;
305
+
interrupt-parent = <&gic>;
306
+
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH 0>;
307
+
};
308
+
309
+
gpm17: gpm17-gpio-bank {
310
+
gpio-controller;
311
+
#gpio-cells = <2>;
312
+
313
+
interrupt-controller;
314
+
#interrupt-cells = <2>;
315
+
interrupt-parent = <&gic>;
316
+
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
317
+
};
318
+
319
+
gpm20: gpm20-gpio-bank {
320
+
gpio-controller;
321
+
#gpio-cells = <2>;
322
+
323
+
interrupt-controller;
324
+
#interrupt-cells = <2>;
325
+
interrupt-parent = <&gic>;
326
+
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
327
+
};
328
+
329
+
gpm21: gpm21-gpio-bank {
330
+
gpio-controller;
331
+
#gpio-cells = <2>;
332
+
333
+
interrupt-controller;
334
+
#interrupt-cells = <2>;
335
+
interrupt-parent = <&gic>;
336
+
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
337
+
};
338
+
339
+
gpm22: gpm22-gpio-bank {
340
+
gpio-controller;
341
+
#gpio-cells = <2>;
342
+
343
+
interrupt-controller;
344
+
#interrupt-cells = <2>;
345
+
interrupt-parent = <&gic>;
346
+
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
347
+
};
348
+
349
+
gpm23: gpm23-gpio-bank {
350
+
gpio-controller;
351
+
#gpio-cells = <2>;
352
+
353
+
interrupt-controller;
354
+
#interrupt-cells = <2>;
355
+
interrupt-parent = <&gic>;
356
+
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
357
+
};
358
+
359
+
gpm24: gpm24-gpio-bank {
360
+
gpio-controller;
361
+
#gpio-cells = <2>;
362
+
363
+
interrupt-controller;
364
+
365
+
#interrupt-cells = <2>;
366
+
interrupt-parent = <&gic>;
367
+
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
368
+
};
369
+
370
+
hsi2c24_bus: hsi2c24-bus-pins {
371
+
samsung,pins = "gpm0-0", "gpm0-1";
372
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
373
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
374
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
375
+
};
376
+
377
+
hsi2c25_bus: hsi2c25-bus-pins {
378
+
samsung,pins = "gpm1-0", "gpm1-1";
379
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
380
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
381
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
382
+
};
383
+
384
+
hsi2c26_bus: hsi2c26-bus-pins {
385
+
samsung,pins = "gpm2-0", "gpm2-1";
386
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
387
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
388
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
389
+
};
390
+
391
+
hsi2c27_bus: hsi2c27-bus-pins {
392
+
samsung,pins = "gpm3-0", "gpm3-1";
393
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
394
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
395
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
396
+
};
397
+
398
+
hsi2c28_bus: hsi2c28-bus-pins {
399
+
samsung,pins = "gpm4-0", "gpm4-1";
400
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
401
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
402
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
403
+
};
404
+
405
+
hsi2c29_bus: hsi2c29-bus-pins {
406
+
samsung,pins = "gpm5-0", "gpm5-1";
407
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
408
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
409
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
410
+
};
411
+
412
+
hsi2c30_bus: hsi2c30-bus-pins {
413
+
samsung,pins = "gpm6-0", "gpm6-1";
414
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
415
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
416
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
417
+
};
418
+
419
+
hsi2c31_bus: hsi2c31-bus-pins {
420
+
samsung,pins = "gpm7-0", "gpm7-1";
421
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
422
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
423
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
424
+
};
425
+
426
+
hsi2c32_bus: hsi2c32-bus-pins {
427
+
samsung,pins = "gpm8-0", "gpm8-1";
428
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
429
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
430
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
431
+
};
432
+
433
+
hsi2c33_bus: hsi2c33-bus-pins {
434
+
samsung,pins = "gpm9-0", "gpm9-1";
435
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
436
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
437
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
438
+
};
439
+
440
+
hsi2c34_bus: hsi2c34-bus-pins {
441
+
samsung,pins = "gpm10-0", "gpm10-1";
442
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
443
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
444
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
445
+
};
446
+
447
+
hsi2c35_bus: hsi2c35-bus-pins {
448
+
samsung,pins = "gpm11-0", "gpm11-1";
449
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
450
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
451
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
452
+
};
453
+
454
+
hsi2c36_bus: hsi2c36-bus-pins {
455
+
samsung,pins = "gpm12-0", "gpm12-1";
456
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
457
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
458
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
459
+
};
460
+
461
+
hsi2c37_bus: hsi2c37-bus-pins {
462
+
samsung,pins = "gpm13-0", "gpm13-1";
463
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
464
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
465
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
466
+
};
467
+
468
+
hsi2c38_bus: hsi2c38-bus-pins {
469
+
samsung,pins = "gpm23-0", "gpm24-0";
470
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
471
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
472
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
473
+
};
474
+
475
+
spi12_bus: spi12-bus-pins {
476
+
samsung,pins = "gpm0-0", "gpm0-1", "gpm1-0";
477
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
478
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
479
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
480
+
};
481
+
482
+
spi12_cs: spi12-cs-pins {
483
+
samsung,pins = "gpm1-1";
484
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
485
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
486
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
487
+
};
488
+
489
+
spi12_cs_func: spi12-cs-func-pins {
490
+
samsung,pins = "gpm1-1";
491
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
492
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
493
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
494
+
};
495
+
496
+
spi13_bus: spi13-bus-pins {
497
+
samsung,pins = "gpm2-0", "gpm2-1", "gpm3-0";
498
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
499
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
500
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
501
+
};
502
+
503
+
spi13_cs: spi13-cs-pins {
504
+
samsung,pins = "gpm3-1";
505
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
506
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
507
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
508
+
};
509
+
510
+
spi13_cs_func: spi13-cs-func-pins {
511
+
samsung,pins = "gpm3-1";
512
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
513
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
514
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
515
+
};
516
+
517
+
spi14_bus: spi14-bus-pins {
518
+
samsung,pins = "gpm4-0", "gpm4-1", "gpm5-0";
519
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
520
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
521
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
522
+
};
523
+
524
+
spi14_cs: spi14-cs-pins {
525
+
samsung,pins = "gpm5-1";
526
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
527
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
528
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
529
+
};
530
+
531
+
spi14_cs_func: spi14-cs-func-pins {
532
+
samsung,pins = "gpm5-1";
533
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
534
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
535
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
536
+
};
537
+
538
+
spi15_bus: spi15-bus-pins {
539
+
samsung,pins = "gpm6-0", "gpm6-1", "gpm7-0";
540
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
541
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
542
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
543
+
};
544
+
545
+
spi15_cs: spi15-cs-pins {
546
+
samsung,pins = "gpm7-1";
547
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
548
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
549
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
550
+
};
551
+
552
+
spi15_cs_func: spi15-cs-func-pins {
553
+
samsung,pins = "gpm7-1";
554
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
555
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
556
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
557
+
};
558
+
559
+
spi16_bus: spi16-bus-pins {
560
+
samsung,pins = "gpm8-0", "gpm8-1", "gpm9-0";
561
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
562
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
563
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
564
+
};
565
+
566
+
spi16_cs: spi16-cs-pins {
567
+
samsung,pins = "gpm9-1";
568
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
569
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
570
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
571
+
};
572
+
573
+
spi16_cs_func: spi16-cs-func-pins {
574
+
samsung,pins = "gpm9-1";
575
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
576
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
577
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
578
+
};
579
+
580
+
spi17_bus: spi17-bus-pins {
581
+
samsung,pins = "gpm10-0", "gpm10-1", "gpm11-0";
582
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
583
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
584
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
585
+
};
586
+
587
+
spi17_cs: spi17-cs-pins {
588
+
samsung,pins = "gpm11-1";
589
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
590
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
591
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
592
+
};
593
+
594
+
spi17_cs_func: spi17-cs-func-pins {
595
+
samsung,pins = "gpm11-1";
596
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
597
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
598
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
599
+
};
600
+
601
+
spi18_bus: spi18-bus-pins {
602
+
samsung,pins = "gpm12-0", "gpm12-1", "gpm13-0";
603
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
604
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
605
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
606
+
};
607
+
608
+
spi18_cs: spi18-cs-pins {
609
+
samsung,pins = "gpm13-1";
610
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
611
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
612
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
613
+
};
614
+
615
+
spi18_cs_func: spi18-cs-func-pins {
616
+
samsung,pins = "gpm13-1";
617
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
618
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
619
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
620
+
};
621
+
622
+
uart14_bus_single: uart14-bus-single-pins {
623
+
samsung,pins = "gpm0-0", "gpm0-1", "gpm2-0", "gpm2-1";
624
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
625
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
626
+
};
627
+
628
+
uart14_bus_dual: uart14-bus-dual-pins {
629
+
samsung,pins = "gpm0-0", "gpm0-1";
630
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
631
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
632
+
};
633
+
634
+
uart15_bus_single: uart15-bus-single-pins {
635
+
samsung,pins = "gpm3-0", "gpm3-1", "gpm4-0", "gpm4-1";
636
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
637
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
638
+
};
639
+
640
+
uart15_bus_dual: uart15-bus-dual-pins {
641
+
samsung,pins = "gpm3-0", "gpm3-1";
642
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
643
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
644
+
};
645
+
646
+
uart16_bus_single: uart16-bus-single-pins {
647
+
samsung,pins = "gpm5-0", "gpm5-1", "gpm6-0", "gpm6-1";
648
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
649
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
650
+
};
651
+
652
+
uart16_bus_dual: uart16-bus-dual-pins {
653
+
samsung,pins = "gpm5-0", "gpm5-1";
654
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
655
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
656
+
};
657
+
658
+
uart17_bus_single: uart17-bus-single-pins {
659
+
samsung,pins = "gpm7-0", "gpm7-1", "gpm8-0", "gpm8-1";
660
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
661
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
662
+
};
663
+
664
+
uart17_bus_dual: uart17-bus-dual-pins {
665
+
samsung,pins = "gpm7-0", "gpm7-1";
666
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
667
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
668
+
};
669
+
670
+
uart18_bus_single: uart18-bus-single-pins {
671
+
samsung,pins = "gpm8-0", "gpm8-1", "gpm9-0", "gpm9-1";
672
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
673
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
674
+
};
675
+
676
+
uart18_bus_dual: uart18-bus-dual-pins {
677
+
samsung,pins = "gpm8-0", "gpm8-1";
678
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
679
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
680
+
};
681
+
682
+
uart19_bus_single: uart19-bus-single-pins {
683
+
samsung,pins = "gpm10-0", "gpm10-1", "gpm11-0", "gpm11-1";
684
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
685
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
686
+
};
687
+
688
+
uart19_bus_dual: uart19-bus-dual-pins {
689
+
samsung,pins = "gpm12-0", "gpm12-1";
690
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
691
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
692
+
};
693
+
694
+
uart20_bus_single: uart20-bus-single-pins {
695
+
samsung,pins = "gpm13-0", "gpm13-1", "gpm14-0", "gpm14-1";
696
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
697
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
698
+
};
699
+
700
+
uart20_bus_dual: uart20-bus-dual-pins {
701
+
samsung,pins = "gpm13-0", "gpm13-1";
702
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
703
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
704
+
};
705
+
706
+
};
707
+
708
+
&pinctrl_hsi1 {
709
+
gpf0: gpf0-gpio-bank {
710
+
gpio-controller;
711
+
#gpio-cells = <2>;
712
+
interrupt-controller;
713
+
#interrupt-cells = <2>;
714
+
};
715
+
716
+
pcie0_clkreq: pcie0-clkreq-pins {
717
+
samsung,pins = "gpf0-0";
718
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
719
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
720
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
721
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
722
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
723
+
};
724
+
725
+
pcie0_perst: pcie0-perst-pins {
726
+
samsung,pins = "gpf0-1";
727
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
728
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
729
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
730
+
};
731
+
732
+
pcie1_clkreq: pcie1-clkreq-pins {
733
+
samsung,pins = "gpf0-2";
734
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
735
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
736
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
737
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
738
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
739
+
};
740
+
741
+
pcie1_perst: pcie1-perst-pins {
742
+
samsung,pins = "gpf0-3";
743
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
744
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV4>;
745
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
746
+
};
747
+
};
748
+
749
+
&pinctrl_hsi1ufs {
750
+
gpf2: gpf2-gpio-bank {
751
+
gpio-controller;
752
+
#gpio-cells = <2>;
753
+
interrupt-controller;
754
+
#interrupt-cells = <2>;
755
+
};
756
+
757
+
ufs_rst_n: ufs-rst-n-pins {
758
+
samsung,pins = "gpf2-1";
759
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
760
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
761
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
762
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
763
+
};
764
+
765
+
ufs_refclk_out: ufs-refclk-out-pins {
766
+
samsung,pins = "gpf2-0";
767
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
768
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
769
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
770
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV3>;
771
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
772
+
};
773
+
};
774
+
775
+
&pinctrl_peric0 {
776
+
gpb0: gpb0-gpio-bank {
777
+
gpio-controller;
778
+
#gpio-cells = <2>;
779
+
interrupt-controller;
780
+
#interrupt-cells = <2>;
781
+
};
782
+
783
+
gpb1: gpb1-gpio-bank {
784
+
gpio-controller;
785
+
#gpio-cells = <2>;
786
+
interrupt-controller;
787
+
#interrupt-cells = <2>;
788
+
};
789
+
790
+
gpb2: gpb2-gpio-bank {
791
+
gpio-controller;
792
+
#gpio-cells = <2>;
793
+
interrupt-controller;
794
+
#interrupt-cells = <2>;
795
+
};
796
+
797
+
gpb3: gpb3-gpio-bank {
798
+
gpio-controller;
799
+
#gpio-cells = <2>;
800
+
interrupt-controller;
801
+
#interrupt-cells = <2>;
802
+
};
803
+
804
+
gpc0: gpc0-gpio-bank {
805
+
gpio-controller;
806
+
#gpio-cells = <2>;
807
+
interrupt-controller;
808
+
#interrupt-cells = <2>;
809
+
};
810
+
811
+
gpc1: gpc1-gpio-bank {
812
+
gpio-controller;
813
+
#gpio-cells = <2>;
814
+
interrupt-controller;
815
+
#interrupt-cells = <2>;
816
+
};
817
+
818
+
gpc2: gpc2-gpio-bank {
819
+
gpio-controller;
820
+
#gpio-cells = <2>;
821
+
interrupt-controller;
822
+
#interrupt-cells = <2>;
823
+
};
824
+
825
+
gpg1: gpg1-gpio-bank {
826
+
gpio-controller;
827
+
#gpio-cells = <2>;
828
+
interrupt-controller;
829
+
#interrupt-cells = <2>;
830
+
};
831
+
832
+
gpg2: gpg2-gpio-bank {
833
+
gpio-controller;
834
+
#gpio-cells = <2>;
835
+
interrupt-controller;
836
+
#interrupt-cells = <2>;
837
+
};
838
+
839
+
gpp4: gpp4-gpio-bank {
840
+
gpio-controller;
841
+
#gpio-cells = <2>;
842
+
interrupt-controller;
843
+
#interrupt-cells = <2>;
844
+
};
845
+
846
+
aud_i2s0_bus: aud-i2s0-bus-pins {
847
+
samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3";
848
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
849
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
850
+
};
851
+
852
+
aud_i2s1_bus: aud-i2s1-bus-pins {
853
+
samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
854
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
855
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
856
+
};
857
+
858
+
aud_i2s2_bus: aud-i2s2-bus-pins {
859
+
samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
860
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
861
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
862
+
};
863
+
864
+
aud_i2s3_bus: aud-i2s3-bus-pins {
865
+
samsung,pins = "gpb3-0", "gpb3-1", "gpb3-2", "gpb3-3";
866
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
867
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
868
+
};
869
+
870
+
aud_i2s3_pci: aud-i2s3-pci-pins {
871
+
samsung,pins = "gpb3-0", "gpb3-1";
872
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
873
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
874
+
};
875
+
876
+
aud_dsd_bus: aud-dsd-bus-pins {
877
+
samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2";
878
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
879
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
880
+
};
881
+
882
+
decon_0_te: decon-0-te-pins {
883
+
samsung,pins = "gpg2-0";
884
+
samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
885
+
};
886
+
887
+
hsi2c8_bus: hsi2c8-bus-pins {
888
+
samsung,pins = "gpp4-0", "gpp4-1";
889
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
890
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
891
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
892
+
};
893
+
894
+
hsi2c9_bus: hsi2c9-bus-pins {
895
+
samsung,pins = "gpp4-2", "gpp4-3";
896
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
897
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
898
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
899
+
};
900
+
901
+
i3c0_bus: i3c0-bus-pins {
902
+
samsung,pins = "gpc0-0", "gpc0-1";
903
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
904
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
905
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
906
+
};
907
+
908
+
i3c1_bus: i3c1-bus-pins {
909
+
samsung,pins = "gpc1-0", "gpc1-1";
910
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
911
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
912
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
913
+
};
914
+
915
+
i3c2_bus: i3c2-bus-pins {
916
+
samsung,pins = "gpc2-0", "gpc2-1";
917
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
918
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
919
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
920
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
921
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
922
+
};
923
+
924
+
spi4_bus: spi4-bus-pins {
925
+
samsung,pins = "gpp4-2", "gpp4-1", "gpp4-0";
926
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
927
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
928
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
929
+
};
930
+
931
+
spi4_cs: spi4-cs-pins {
932
+
samsung,pins = "gpp4-3";
933
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
934
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
935
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
936
+
};
937
+
938
+
spi4_cs_func: spi4-cs-func-pins {
939
+
samsung,pins = "gpp4-3";
940
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
941
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
942
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
943
+
};
944
+
945
+
uart6_bus_single: uart6-bus-single-pins {
946
+
samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2", "gpp4-3";
947
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
948
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
949
+
};
950
+
951
+
uart6_bus_dual: uart6-bus-dual-pins {
952
+
samsung,pins = "gpp4-0", "gpp4-1";
953
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
954
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
955
+
};
956
+
};
957
+
958
+
&pinctrl_peric1 {
959
+
gpp7: gpp7-gpio-bank {
960
+
gpio-controller;
961
+
#gpio-cells = <2>;
962
+
interrupt-controller;
963
+
#interrupt-cells = <2>;
964
+
};
965
+
966
+
gpp8: gpp8-gpio-bank {
967
+
gpio-controller;
968
+
#gpio-cells = <2>;
969
+
interrupt-controller;
970
+
#interrupt-cells = <2>;
971
+
};
972
+
973
+
gpp9: gpp9-gpio-bank {
974
+
gpio-controller;
975
+
#gpio-cells = <2>;
976
+
interrupt-controller;
977
+
#interrupt-cells = <2>;
978
+
};
979
+
980
+
gpp10: gpp10-gpio-bank {
981
+
gpio-controller;
982
+
#gpio-cells = <2>;
983
+
interrupt-controller;
984
+
#interrupt-cells = <2>;
985
+
};
986
+
987
+
hsi2c14_bus: hsi2c14-bus-pins {
988
+
samsung,pins = "gpp7-0", "gpp7-1";
989
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
990
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
991
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
992
+
};
993
+
994
+
hsi2c15_bus: hsi2c15-bus-pins {
995
+
samsung,pins = "gpp7-2", "gpp7-3";
996
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
997
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
998
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
999
+
};
1000
+
1001
+
hsi2c16_bus: hsi2c16-bus-pins {
1002
+
samsung,pins = "gpp8-0", "gpp8-1";
1003
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1004
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1005
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1006
+
};
1007
+
1008
+
hsi2c17_bus: hsi2c17-bus-pins {
1009
+
samsung,pins = "gpp8-2", "gpp8-3";
1010
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1011
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1012
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1013
+
};
1014
+
1015
+
hsi2c18_bus: hsi2c18-bus-pins {
1016
+
samsung,pins = "gpp9-0", "gpp9-1";
1017
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1018
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1019
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1020
+
};
1021
+
1022
+
hsi2c19_bus: hsi2c19-bus-pins {
1023
+
samsung,pins = "gpp9-2", "gpp9-3";
1024
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1025
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1026
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1027
+
};
1028
+
1029
+
hsi2c20_bus: hsi2c20-bus-pins {
1030
+
samsung,pins = "gpp10-0", "gpp10-1";
1031
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1032
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1033
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1034
+
};
1035
+
1036
+
hsi2c21_bus: hsi2c21-bus-pins {
1037
+
samsung,pins = "gpp10-2", "gpp10-3";
1038
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1039
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1040
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1041
+
};
1042
+
1043
+
spi7_bus: spi7-bus-pins {
1044
+
samsung,pins = "gpp7-2", "gpp7-1", "gpp7-0";
1045
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1046
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1047
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1048
+
};
1049
+
1050
+
spi7_cs: spi7-cs-pins {
1051
+
samsung,pins = "gpp7-3";
1052
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1053
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1054
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1055
+
};
1056
+
1057
+
spi7_cs_func: spi7-cs-func-pins {
1058
+
samsung,pins = "gpp7-3";
1059
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1060
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1061
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1062
+
};
1063
+
1064
+
spi8_bus: spi8-bus-pins {
1065
+
samsung,pins = "gpp8-2", "gpp8-1", "gpp8-0";
1066
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1067
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1068
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1069
+
};
1070
+
1071
+
spi8_cs: spi8-cs-pins {
1072
+
samsung,pins = "gpp8-3";
1073
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1074
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1075
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1076
+
};
1077
+
1078
+
spi8_cs_func: spi8-cs-func-pins {
1079
+
samsung,pins = "gpp8-3";
1080
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1081
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1082
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1083
+
};
1084
+
1085
+
spi9_bus: spi9-bus-pins {
1086
+
samsung,pins = "gpp9-2", "gpp9-1", "gpp9-0";
1087
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1088
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1089
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1090
+
};
1091
+
1092
+
spi9_cs: spi9-cs-pins {
1093
+
samsung,pins = "gpp9-3";
1094
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1095
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1096
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1097
+
};
1098
+
1099
+
spi9_cs_func: spi9-cs-func-pins {
1100
+
samsung,pins = "gpp9-3";
1101
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1102
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1103
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1104
+
};
1105
+
1106
+
spi10_bus: spi10-bus-pins {
1107
+
samsung,pins = "gpp10-2", "gpp10-1", "gpp10-0";
1108
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1109
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1110
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1111
+
};
1112
+
1113
+
spi10_cs: spi10-cs-pins {
1114
+
samsung,pins = "gpp10-3";
1115
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1116
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1117
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1118
+
};
1119
+
1120
+
spi10_cs_func: spi10-cs-func-pins {
1121
+
samsung,pins = "gpp10-3";
1122
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1123
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1124
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1125
+
};
1126
+
1127
+
uart9_bus_single: uart9-bus-single-pins {
1128
+
samsung,pins = "gpp7-3", "gpp7-2", "gpp7-1", "gpp7-0";
1129
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1130
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1131
+
};
1132
+
1133
+
uart9_bus_dual: uart9-bus-dual-pins {
1134
+
samsung,pins = "gpp7-0", "gpp7-1";
1135
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1136
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1137
+
};
1138
+
1139
+
uart10_bus_single: uart10-bus-single-pins {
1140
+
samsung,pins = "gpp8-3", "gpp8-2", "gpp8-1", "gpp8-0";
1141
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1142
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1143
+
};
1144
+
1145
+
uart10_bus_dual: uart10-bus-dual-pins {
1146
+
samsung,pins = "gpp8-0", "gpp8-1";
1147
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1148
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1149
+
};
1150
+
1151
+
uart11_bus_single: uart11-bus-single-pins {
1152
+
samsung,pins = "gpp9-3", "gpp9-2", "gpp9-1", "gpp9-0";
1153
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1154
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1155
+
};
1156
+
1157
+
uart11_bus_dual: uart11-bus-dual-pins {
1158
+
samsung,pins = "gpp9-0", "gpp9-1";
1159
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1160
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1161
+
};
1162
+
1163
+
uart12_bus_single: uart12-bus-single-pins {
1164
+
samsung,pins = "gpp10-3", "gpp10-2", "gpp10-1", "gpp10-0";
1165
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1166
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1167
+
};
1168
+
1169
+
uart12_bus_dual: uart12-bus-dual-pins {
1170
+
samsung,pins = "gpp10-0", "gpp10-1";
1171
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1172
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1173
+
};
1174
+
1175
+
};
1176
+
1177
+
&pinctrl_peric2 {
1178
+
gpc3: gpc3-gpio-bank {
1179
+
gpio-controller;
1180
+
#gpio-cells = <2>;
1181
+
interrupt-controller;
1182
+
#interrupt-cells = <2>;
1183
+
};
1184
+
1185
+
gpc4: gpc4-gpio-bank {
1186
+
gpio-controller;
1187
+
#gpio-cells = <2>;
1188
+
interrupt-controller;
1189
+
#interrupt-cells = <2>;
1190
+
};
1191
+
1192
+
gpc5: gpc5-gpio-bank {
1193
+
gpio-controller;
1194
+
#gpio-cells = <2>;
1195
+
interrupt-controller;
1196
+
#interrupt-cells = <2>;
1197
+
};
1198
+
1199
+
gpc6: gpc6-gpio-bank {
1200
+
gpio-controller;
1201
+
#gpio-cells = <2>;
1202
+
interrupt-controller;
1203
+
#interrupt-cells = <2>;
1204
+
};
1205
+
1206
+
gpc7: gpc7-gpio-bank {
1207
+
gpio-controller;
1208
+
#gpio-cells = <2>;
1209
+
interrupt-controller;
1210
+
#interrupt-cells = <2>;
1211
+
};
1212
+
1213
+
gpc8: gpc8-gpio-bank {
1214
+
gpio-controller;
1215
+
#gpio-cells = <2>;
1216
+
interrupt-controller;
1217
+
#interrupt-cells = <2>;
1218
+
};
1219
+
1220
+
gpc9: gpc9-gpio-bank {
1221
+
gpio-controller;
1222
+
#gpio-cells = <2>;
1223
+
interrupt-controller;
1224
+
#interrupt-cells = <2>;
1225
+
};
1226
+
1227
+
gpg0: gpg0-gpio-bank {
1228
+
gpio-controller;
1229
+
#gpio-cells = <2>;
1230
+
interrupt-controller;
1231
+
#interrupt-cells = <2>;
1232
+
};
1233
+
1234
+
gpp0: gpp0-gpio-bank {
1235
+
gpio-controller;
1236
+
#gpio-cells = <2>;
1237
+
interrupt-controller;
1238
+
#interrupt-cells = <2>;
1239
+
};
1240
+
1241
+
gpp1: gpp1-gpio-bank {
1242
+
gpio-controller;
1243
+
#gpio-cells = <2>;
1244
+
interrupt-controller;
1245
+
#interrupt-cells = <2>;
1246
+
};
1247
+
1248
+
gpp2: gpp2-gpio-bank {
1249
+
gpio-controller;
1250
+
#gpio-cells = <2>;
1251
+
interrupt-controller;
1252
+
#interrupt-cells = <2>;
1253
+
};
1254
+
1255
+
gpp3: gpp3-gpio-bank {
1256
+
gpio-controller;
1257
+
#gpio-cells = <2>;
1258
+
interrupt-controller;
1259
+
#interrupt-cells = <2>;
1260
+
};
1261
+
1262
+
gpp5: gpp5-gpio-bank {
1263
+
gpio-controller;
1264
+
#gpio-cells = <2>;
1265
+
interrupt-controller;
1266
+
#interrupt-cells = <2>;
1267
+
};
1268
+
1269
+
gpp6: gpp6-gpio-bank {
1270
+
gpio-controller;
1271
+
#gpio-cells = <2>;
1272
+
interrupt-controller;
1273
+
#interrupt-cells = <2>;
1274
+
};
1275
+
1276
+
gpp11: gpp11-gpio-bank {
1277
+
gpio-controller;
1278
+
#gpio-cells = <2>;
1279
+
interrupt-controller;
1280
+
#interrupt-cells = <2>;
1281
+
};
1282
+
1283
+
hsi2c0_bus: hsi2c0-bus-pins {
1284
+
samsung,pins = "gpp0-0", "gpp0-1";
1285
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1286
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1287
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1288
+
};
1289
+
1290
+
hsi2c1_bus: hsi2c1-bus-pins {
1291
+
samsung,pins = "gpp0-2", "gpp0-3";
1292
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1293
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1294
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1295
+
};
1296
+
1297
+
hsi2c2_bus: hsi2c2-bus-pins {
1298
+
samsung,pins = "gpp1-0", "gpp1-1";
1299
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1300
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1301
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1302
+
};
1303
+
1304
+
hsi2c3_bus: hsi2c3-bus-pins {
1305
+
samsung,pins = "gpp1-2", "gpp1-3";
1306
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1307
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1308
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1309
+
};
1310
+
1311
+
hsi2c4_bus: hsi2c4-bus-pins {
1312
+
samsung,pins = "gpp2-0", "gpp2-1";
1313
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1314
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1315
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1316
+
};
1317
+
1318
+
hsi2c5_bus: hsi2c5-bus-pins {
1319
+
samsung,pins = "gpp2-2", "gpp2-3";
1320
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1321
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1322
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1323
+
};
1324
+
1325
+
hsi2c6_bus: hsi2c6-bus-pins {
1326
+
samsung,pins = "gpp3-0", "gpp3-1";
1327
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1328
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1329
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1330
+
};
1331
+
1332
+
hsi2c7_bus: hsi2c7-bus-pins {
1333
+
samsung,pins = "gpp3-2", "gpp3-3";
1334
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1335
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1336
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1337
+
};
1338
+
1339
+
hsi2c10_bus: hsi2c10-bus-pins {
1340
+
samsung,pins = "gpp5-0", "gpp5-1";
1341
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1342
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1343
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1344
+
};
1345
+
1346
+
hsi2c11_bus: hsi2c11-bus-pins {
1347
+
samsung,pins = "gpp5-2", "gpp5-3";
1348
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1349
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1350
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1351
+
};
1352
+
1353
+
hsi2c12_bus: hsi2c12-bus-pins {
1354
+
samsung,pins = "gpp6-0", "gpp6-1";
1355
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1356
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1357
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1358
+
};
1359
+
1360
+
hsi2c13_bus: hsi2c13-bus-pins {
1361
+
samsung,pins = "gpp6-2", "gpp6-3";
1362
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1363
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1364
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1365
+
};
1366
+
1367
+
hsi2c22_bus: hsi2c22-bus-pins {
1368
+
samsung,pins = "gpp11-0", "gpp11-1";
1369
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1370
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1371
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1372
+
};
1373
+
1374
+
i3c3_bus: i3c3-bus-pins {
1375
+
samsung,pins = "gpc3-0", "gpc3-1";
1376
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1377
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1378
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1379
+
};
1380
+
1381
+
i3c4_bus: i3c4-bus-pins {
1382
+
samsung,pins = "gpc4-0", "gpc4-1";
1383
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1384
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1385
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1386
+
};
1387
+
1388
+
i3c5_bus: i3c5-bus-pins {
1389
+
samsung,pins = "gpc5-0", "gpc5-1";
1390
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1391
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1392
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1393
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
1394
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
1395
+
};
1396
+
1397
+
i3c6_bus: i3c6-bus-pins {
1398
+
samsung,pins = "gpc6-0", "gpc6-1";
1399
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1400
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1401
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1402
+
};
1403
+
1404
+
i3c7_bus: i3c7-bus-pins {
1405
+
samsung,pins = "gpc7-0", "gpc7-1";
1406
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1407
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1408
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1409
+
};
1410
+
1411
+
i3c8_bus: i3c8-bus-pins {
1412
+
samsung,pins = "gpc8-0", "gpc8-1";
1413
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1414
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1415
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1416
+
};
1417
+
1418
+
i3c9_bus: i3c9-bus-pins {
1419
+
samsung,pins = "gpc9-0", "gpc9-1";
1420
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1421
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1422
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1423
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
1424
+
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
1425
+
};
1426
+
1427
+
i3c10_bus: i3c10-bus-pins {
1428
+
samsung,pins = "gpp2-2", "gpp2-3";
1429
+
samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
1430
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1431
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1432
+
};
1433
+
1434
+
i3c11_bus: i3c11-bus-pins {
1435
+
samsung,pins = "gpp3-2", "gpp3-3";
1436
+
samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
1437
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1438
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1439
+
};
1440
+
1441
+
hsi223_bus: hsi2c23-bus-pins {
1442
+
samsung,pins = "gpp11-2", "gpp11-3";
1443
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1444
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1445
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1446
+
};
1447
+
1448
+
spi0_bus: spi0-bus-pins {
1449
+
samsung,pins = "gpp0-2", "gpp0-1", "gpp0-0";
1450
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1451
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1452
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1453
+
};
1454
+
1455
+
spi0_cs: spi0-cs-pins {
1456
+
samsung,pins = "gpp0-3";
1457
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1458
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1459
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1460
+
};
1461
+
1462
+
spi0_cs_func: spi0-cs-func-pins {
1463
+
samsung,pins = "gpp0-3";
1464
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1465
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1466
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1467
+
};
1468
+
1469
+
spi1_bus: spi1-bus-pins {
1470
+
samsung,pins = "gpp1-2", "gpp1-1", "gpp1-0";
1471
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1472
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1473
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1474
+
};
1475
+
1476
+
spi1_cs: spi1-cs-pins {
1477
+
samsung,pins = "gpp1-3";
1478
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1479
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1480
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1481
+
};
1482
+
1483
+
spi1_cs_func: spi1-cs-func-pins {
1484
+
samsung,pins = "gpp1-3";
1485
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1486
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1487
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1488
+
};
1489
+
1490
+
spi2_bus: spi2-bus-pins {
1491
+
samsung,pins = "gpp2-2", "gpp2-1", "gpp2-0";
1492
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1493
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1494
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1495
+
};
1496
+
1497
+
spi2_cs: spi2-cs-pins {
1498
+
samsung,pins = "gpp2-3";
1499
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1500
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1501
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1502
+
};
1503
+
1504
+
spi2_cs_func: spi2-cs-func-pins {
1505
+
samsung,pins = "gpp2-3";
1506
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1507
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1508
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1509
+
};
1510
+
1511
+
spi3_bus: spi3-bus-pins {
1512
+
samsung,pins = "gpp3-2", "gpp3-1", "gpp3-0";
1513
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1514
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1515
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1516
+
};
1517
+
1518
+
spi3_cs: spi3-cs-pins {
1519
+
samsung,pins = "gpp3-3";
1520
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1521
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1522
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1523
+
};
1524
+
1525
+
spi3_cs_func: spi3-cs-func-pins {
1526
+
samsung,pins = "gpp3-3";
1527
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1528
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1529
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1530
+
};
1531
+
1532
+
spi5_bus: spi5-bus-pins {
1533
+
samsung,pins = "gpp5-2", "gpp5-1", "gpp5-0";
1534
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1535
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1536
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1537
+
};
1538
+
1539
+
spi5_cs: spi5-cs-pins {
1540
+
samsung,pins = "gpp5-3";
1541
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1542
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1543
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1544
+
};
1545
+
1546
+
spi5_cs_func: spi5-cs-func-pins {
1547
+
samsung,pins = "gpp5-3";
1548
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1549
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1550
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1551
+
};
1552
+
1553
+
spi6_bus: spi6-bus-pins {
1554
+
samsung,pins = "gpp6-2", "gpp6-1", "gpp6-0";
1555
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1556
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1557
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1558
+
};
1559
+
1560
+
spi6_cs: spi6-cs-pins {
1561
+
samsung,pins = "gpp6-3";
1562
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1563
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1564
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1565
+
};
1566
+
1567
+
spi6_cs_func: spi6-cs-func-pins {
1568
+
samsung,pins = "gpp6-3";
1569
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1570
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1571
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1572
+
};
1573
+
1574
+
spi11_bus: spi11-bus-pins {
1575
+
samsung,pins = "gpp11-2", "gpp11-1", "gpp11-0";
1576
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1577
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1578
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1579
+
};
1580
+
1581
+
spi11_cs: spi11-cs-pins {
1582
+
samsung,pins = "gpp11-3";
1583
+
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
1584
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1585
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1586
+
};
1587
+
1588
+
spi11_cs_func: spi11-cs-func-pins {
1589
+
samsung,pins = "gpp11-3";
1590
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1591
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1592
+
samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>;
1593
+
};
1594
+
1595
+
uart0_bus_single: uart0-bus-single-pins {
1596
+
samsung,pins = "gpg0-2", "gpg0-3";
1597
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1598
+
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1599
+
};
1600
+
1601
+
uart2_bus_single: uart2-bus-single-pins {
1602
+
samsung,pins = "gpp0-0", "gpp0-1", "gpp0-2", "gpp0-3";
1603
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1604
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1605
+
};
1606
+
1607
+
uart2_bus_dual: uart2-bus-dual-pins {
1608
+
samsung,pins = "gpp0-0", "gpp0-1";
1609
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1610
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1611
+
};
1612
+
1613
+
uart3_bus_single: uart3-bus-single-pins {
1614
+
samsung,pins = "gpp1-0", "gpp1-1", "gpp1-2", "gpp1-3";
1615
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1616
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1617
+
};
1618
+
1619
+
uart3_bus_dual: uart3-bus-dual-pins {
1620
+
samsung,pins = "gpp1-0", "gpp1-1";
1621
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1622
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1623
+
};
1624
+
1625
+
uart4_bus_single: uart4-bus-single-pins {
1626
+
samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";
1627
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1628
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1629
+
};
1630
+
1631
+
uart4_bus_dual: uart4-bus-dual-pins {
1632
+
samsung,pins = "gpp2-0", "gpp2-1";
1633
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1634
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1635
+
};
1636
+
1637
+
uart5_bus_single: uart5-bus-single-pins {
1638
+
samsung,pins = "gpp3-0", "gpp3-1", "gpp3-2", "gpp3-3";
1639
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1640
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1641
+
};
1642
+
1643
+
uart5_bus_dual: uart5-bus-dual-pins {
1644
+
samsung,pins = "gpp3-0", "gpp3-1";
1645
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1646
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1647
+
};
1648
+
1649
+
uart7_bus_single: uart7-bus-single-pins {
1650
+
samsung,pins = "gpp5-0", "gpp5-1", "gpp5-2", "gpp5-3";
1651
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1652
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1653
+
};
1654
+
1655
+
uart7_bus_dual: uart7-bus-dual-pins {
1656
+
samsung,pins = "gpp5-0", "gpp5-1";
1657
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1658
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1659
+
};
1660
+
1661
+
uart8_bus_single: uart8-bus-single-pins {
1662
+
samsung,pins = "gpp6-3", "gpp6-2", "gpp6-1", "gpp6-0";
1663
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1664
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1665
+
};
1666
+
1667
+
uart8_bus_dual: uart8-bus-dual-pins {
1668
+
samsung,pins = "gpp6-0", "gpp6-1";
1669
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1670
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1671
+
};
1672
+
1673
+
uart13_bus_single: uart13-bus-single-pins {
1674
+
samsung,pins = "gpp11-3", "gpp11-2", "gpp11-1", "gpp11-0";
1675
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1676
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1677
+
};
1678
+
1679
+
uart13_bus_dual: uart13-bus-dual-pins {
1680
+
samsung,pins = "gpp11-0", "gpp11-1";
1681
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1682
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1683
+
};
1684
+
};
1685
+
1686
+
&pinctrl_ufs {
1687
+
gpf1: gpf1-gpio-bank {
1688
+
gpio-controller;
1689
+
#gpio-cells = <2>;
1690
+
interrupt-controller;
1691
+
#interrupt-cells = <2>;
1692
+
};
1693
+
};
1694
+
1695
+
&pinctrl_vts {
1696
+
gpv0: gpv0-gpio-bank {
1697
+
gpio-controller;
1698
+
#gpio-cells = <2>;
1699
+
interrupt-controller;
1700
+
#interrupt-cells = <2>;
1701
+
};
1702
+
1703
+
amic_pdm0_bus: amic-pdm0-bus-pins {
1704
+
samsung,pins = "gpv0-3";
1705
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1706
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1707
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
1708
+
};
1709
+
1710
+
amic_pdm1_bus: amic-pdm1-bus-pins {
1711
+
samsung,pins = "gpv0-4";
1712
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1713
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1714
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
1715
+
};
1716
+
1717
+
amic_pdm2_bus: amic-pdm2-bus-pins {
1718
+
samsung,pins = "gpv0-5";
1719
+
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
1720
+
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1721
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
1722
+
};
1723
+
1724
+
dmic_bus_clk0: dmic-bus-clk0-pins {
1725
+
samsung,pins = "gpv0-0";
1726
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1727
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1728
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
1729
+
};
1730
+
1731
+
dmic_bus_clk1: dmic-bus-clk1-pins {
1732
+
samsung,pins = "gpv0-1";
1733
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1734
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1735
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
1736
+
};
1737
+
1738
+
dmic_bus_clk2: dmic-bus-clk2-pins {
1739
+
samsung,pins = "gpv0-2";
1740
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1741
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1742
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
1743
+
};
1744
+
1745
+
dmic_pdm0_bus: dmic-pdm0-bus-pins {
1746
+
samsung,pins = "gpv0-3";
1747
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1748
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1749
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
1750
+
};
1751
+
1752
+
dmic_pdm1_bus: dmic-pdm1-bus-pins {
1753
+
samsung,pins = "gpv0-4";
1754
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1755
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1756
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
1757
+
};
1758
+
1759
+
dmic_pdm2_bus: dmic-pdm2-bus-pins {
1760
+
samsung,pins = "gpv0-5";
1761
+
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
1762
+
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
1763
+
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
1764
+
};
1765
+
};
+561
arch/arm64/boot/dts/exynos/exynos2200.dtsi
+561
arch/arm64/boot/dts/exynos/exynos2200.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2
+
/*
3
+
* Samsung's Exynos 2200 SoC device tree source
4
+
*
5
+
* Copyright (c) 2025, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
6
+
*/
7
+
8
+
#include <dt-bindings/clock/samsung,exynos2200-cmu.h>
9
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
10
+
11
+
/ {
12
+
compatible = "samsung,exynos2200";
13
+
#address-cells = <2>;
14
+
#size-cells = <2>;
15
+
16
+
interrupt-parent = <&gic>;
17
+
18
+
aliases {
19
+
pinctrl0 = &pinctrl_alive;
20
+
pinctrl1 = &pinctrl_cmgp;
21
+
pinctrl2 = &pinctrl_hsi1;
22
+
pinctrl3 = &pinctrl_ufs;
23
+
pinctrl4 = &pinctrl_hsi1ufs;
24
+
pinctrl5 = &pinctrl_peric0;
25
+
pinctrl6 = &pinctrl_peric1;
26
+
pinctrl7 = &pinctrl_peric2;
27
+
pinctrl8 = &pinctrl_vts;
28
+
};
29
+
30
+
xtcxo: clock-1 {
31
+
compatible = "fixed-clock";
32
+
#clock-cells = <0>;
33
+
clock-output-names = "oscclk";
34
+
};
35
+
36
+
ext_26m: clock-2 {
37
+
compatible = "fixed-clock";
38
+
#clock-cells = <0>;
39
+
clock-output-names = "ext-26m";
40
+
};
41
+
42
+
ext_200m: clock-3 {
43
+
compatible = "fixed-clock";
44
+
#clock-cells = <0>;
45
+
clock-output-names = "ext-200m";
46
+
};
47
+
48
+
cpus {
49
+
#address-cells = <1>;
50
+
#size-cells = <0>;
51
+
52
+
cpu-map {
53
+
cluster0 {
54
+
core0 {
55
+
cpu = <&cpu0>;
56
+
};
57
+
58
+
core1 {
59
+
cpu = <&cpu1>;
60
+
};
61
+
62
+
core2 {
63
+
cpu = <&cpu2>;
64
+
};
65
+
66
+
core3 {
67
+
cpu = <&cpu3>;
68
+
};
69
+
};
70
+
71
+
cluster1 {
72
+
core0 {
73
+
cpu = <&cpu4>;
74
+
};
75
+
76
+
core1 {
77
+
cpu = <&cpu5>;
78
+
};
79
+
80
+
core2 {
81
+
cpu = <&cpu6>;
82
+
};
83
+
};
84
+
85
+
cluster2 {
86
+
core0 {
87
+
cpu = <&cpu7>;
88
+
};
89
+
};
90
+
};
91
+
92
+
cpu0: cpu@0 {
93
+
device_type = "cpu";
94
+
compatible = "arm,cortex-a510";
95
+
reg = <0>;
96
+
capacity-dmips-mhz = <260>;
97
+
dynamic-power-coefficient = <189>;
98
+
enable-method = "psci";
99
+
cpu-idle-states = <&little_cpu_sleep>;
100
+
};
101
+
102
+
cpu1: cpu@100 {
103
+
device_type = "cpu";
104
+
compatible = "arm,cortex-a510";
105
+
reg = <0x100>;
106
+
capacity-dmips-mhz = <260>;
107
+
dynamic-power-coefficient = <189>;
108
+
enable-method = "psci";
109
+
cpu-idle-states = <&little_cpu_sleep>;
110
+
};
111
+
112
+
cpu2: cpu@200 {
113
+
device_type = "cpu";
114
+
compatible = "arm,cortex-a510";
115
+
reg = <0x200>;
116
+
capacity-dmips-mhz = <260>;
117
+
dynamic-power-coefficient = <189>;
118
+
enable-method = "psci";
119
+
cpu-idle-states = <&little_cpu_sleep>;
120
+
};
121
+
122
+
cpu3: cpu@300 {
123
+
device_type = "cpu";
124
+
compatible = "arm,cortex-a510";
125
+
reg = <0x300>;
126
+
capacity-dmips-mhz = <260>;
127
+
dynamic-power-coefficient = <189>;
128
+
enable-method = "psci";
129
+
cpu-idle-states = <&little_cpu_sleep>;
130
+
};
131
+
132
+
cpu4: cpu@400 {
133
+
device_type = "cpu";
134
+
compatible = "arm,cortex-a710";
135
+
reg = <0x400>;
136
+
capacity-dmips-mhz = <380>;
137
+
dynamic-power-coefficient = <560>;
138
+
enable-method = "psci";
139
+
cpu-idle-states = <&big_cpu_sleep>;
140
+
};
141
+
142
+
cpu5: cpu@500 {
143
+
device_type = "cpu";
144
+
compatible = "arm,cortex-a710";
145
+
reg = <0x500>;
146
+
capacity-dmips-mhz = <380>;
147
+
dynamic-power-coefficient = <560>;
148
+
enable-method = "psci";
149
+
cpu-idle-states = <&big_cpu_sleep>;
150
+
};
151
+
152
+
cpu6: cpu@600 {
153
+
device_type = "cpu";
154
+
compatible = "arm,cortex-a710";
155
+
reg = <0x600>;
156
+
capacity-dmips-mhz = <380>;
157
+
dynamic-power-coefficient = <560>;
158
+
enable-method = "psci";
159
+
cpu-idle-states = <&big_cpu_sleep>;
160
+
};
161
+
162
+
cpu7: cpu@700 {
163
+
device_type = "cpu";
164
+
compatible = "arm,cortex-x2";
165
+
reg = <0x700>;
166
+
capacity-dmips-mhz = <488>;
167
+
dynamic-power-coefficient = <765>;
168
+
enable-method = "psci";
169
+
cpu-idle-states = <&prime_cpu_sleep>;
170
+
};
171
+
172
+
idle-states {
173
+
entry-method = "psci";
174
+
175
+
little_cpu_sleep: cpu-sleep-0 {
176
+
compatible = "arm,idle-state";
177
+
idle-state-name = "c2";
178
+
entry-latency-us = <70>;
179
+
exit-latency-us = <170>;
180
+
min-residency-us = <2000>;
181
+
arm,psci-suspend-param = <0x10000>;
182
+
};
183
+
184
+
big_cpu_sleep: cpu-sleep-1 {
185
+
compatible = "arm,idle-state";
186
+
idle-state-name = "c2";
187
+
entry-latency-us = <235>;
188
+
exit-latency-us = <220>;
189
+
min-residency-us = <3500>;
190
+
arm,psci-suspend-param = <0x10000>;
191
+
};
192
+
193
+
prime_cpu_sleep: cpu-sleep-2 {
194
+
compatible = "arm,idle-state";
195
+
idle-state-name = "c2";
196
+
entry-latency-us = <150>;
197
+
exit-latency-us = <190>;
198
+
min-residency-us = <2500>;
199
+
arm,psci-suspend-param = <0x10000>;
200
+
};
201
+
};
202
+
};
203
+
204
+
pmu-a510 {
205
+
compatible = "arm,cortex-a510-pmu";
206
+
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
207
+
};
208
+
209
+
pmu-a710 {
210
+
compatible = "arm,cortex-a710-pmu";
211
+
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
212
+
};
213
+
214
+
pmu-x2 {
215
+
compatible = "arm,cortex-x2-pmu";
216
+
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>;
217
+
};
218
+
219
+
psci {
220
+
compatible = "arm,psci-1.0";
221
+
method = "smc";
222
+
};
223
+
224
+
soc {
225
+
compatible = "simple-bus";
226
+
ranges;
227
+
228
+
#address-cells = <2>;
229
+
#size-cells = <2>;
230
+
231
+
chipid@10000000 {
232
+
compatible = "samsung,exynos2200-chipid",
233
+
"samsung,exynos850-chipid";
234
+
reg = <0x0 0x10000000 0x0 0x24>;
235
+
};
236
+
237
+
cmu_peris: clock-controller@10020000 {
238
+
compatible = "samsung,exynos2200-cmu-peris";
239
+
reg = <0x0 0x10020000 0x0 0x8000>;
240
+
#clock-cells = <1>;
241
+
242
+
clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>,
243
+
<&cmu_top CLK_DOUT_CMU_PERIS_NOC>,
244
+
<&cmu_top CLK_DOUT_CMU_PERIS_GIC>;
245
+
clock-names = "tcxo_div3",
246
+
"noc",
247
+
"gic";
248
+
};
249
+
250
+
mct_peris: timer@10040000 {
251
+
compatible = "samsung,exynos2200-mct-peris",
252
+
"samsung,exynos4210-mct";
253
+
reg = <0x0 0x10040000 0x0 0x800>;
254
+
clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>, <&cmu_peris CLK_MOUT_PERIS_GIC>;
255
+
clock-names = "fin_pll", "mct";
256
+
interrupts = <GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH 0>,
257
+
<GIC_SPI 944 IRQ_TYPE_LEVEL_HIGH 0>,
258
+
<GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH 0>,
259
+
<GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH 0>,
260
+
<GIC_SPI 947 IRQ_TYPE_LEVEL_HIGH 0>,
261
+
<GIC_SPI 948 IRQ_TYPE_LEVEL_HIGH 0>,
262
+
<GIC_SPI 949 IRQ_TYPE_LEVEL_HIGH 0>,
263
+
<GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH 0>,
264
+
<GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH 0>,
265
+
<GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH 0>,
266
+
<GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH 0>,
267
+
<GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH 0>;
268
+
status = "disabled";
269
+
};
270
+
271
+
gic: interrupt-controller@10200000 {
272
+
compatible = "arm,gic-v3";
273
+
reg = <0x0 0x10200000 0x0 0x10000>, /* GICD */
274
+
<0x0 0x10240000 0x0 0x200000>; /* GICR * 8 */
275
+
276
+
#interrupt-cells = <4>;
277
+
interrupt-controller;
278
+
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
279
+
280
+
ppi-partitions {
281
+
ppi_cluster0: interrupt-partition-0 {
282
+
affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
283
+
};
284
+
285
+
ppi_cluster1: interrupt-partition-1 {
286
+
affinity = <&cpu4 &cpu5 &cpu6>;
287
+
};
288
+
289
+
ppi_cluster2: interrupt-partition-2 {
290
+
affinity = <&cpu7>;
291
+
};
292
+
};
293
+
};
294
+
295
+
cmu_peric0: clock-controller@10400000 {
296
+
compatible = "samsung,exynos2200-cmu-peric0";
297
+
reg = <0x0 0x10400000 0x0 0x8000>;
298
+
#clock-cells = <1>;
299
+
300
+
clocks = <&xtcxo>,
301
+
<&cmu_top CLK_DOUT_CMU_PERIC0_NOC>,
302
+
<&cmu_top CLK_DOUT_CMU_PERIC0_IP0>,
303
+
<&cmu_top CLK_DOUT_CMU_PERIC0_IP1>;
304
+
clock-names = "oscclk", "noc", "ip0", "ip1";
305
+
};
306
+
307
+
syscon_peric0: syscon@10420000 {
308
+
compatible = "samsung,exynos2200-peric0-sysreg", "syscon";
309
+
reg = <0x0 0x10420000 0x0 0x2000>;
310
+
};
311
+
312
+
pinctrl_peric0: pinctrl@10430000 {
313
+
compatible = "samsung,exynos2200-pinctrl";
314
+
reg = <0x0 0x10430000 0x0 0x1000>;
315
+
};
316
+
317
+
cmu_peric1: clock-controller@10700000 {
318
+
compatible = "samsung,exynos2200-cmu-peric1";
319
+
reg = <0x0 0x10700000 0x0 0x8000>;
320
+
#clock-cells = <1>;
321
+
322
+
clocks = <&xtcxo>,
323
+
<&cmu_top CLK_DOUT_CMU_PERIC1_NOC>,
324
+
<&cmu_top CLK_DOUT_CMU_PERIC1_IP0>,
325
+
<&cmu_top CLK_DOUT_CMU_PERIC1_IP1>;
326
+
clock-names = "oscclk", "noc", "ip0", "ip1";
327
+
};
328
+
329
+
syscon_peric1: syscon@10720000 {
330
+
compatible = "samsung,exynos2200-peric1-sysreg", "syscon";
331
+
reg = <0x0 0x10720000 0x0 0x2000>;
332
+
};
333
+
334
+
pinctrl_peric1: pinctrl@10730000 {
335
+
compatible = "samsung,exynos2200-pinctrl";
336
+
reg = <0x0 0x10730000 0x0 0x1000>;
337
+
};
338
+
339
+
cmu_hsi0: clock-controller@10a00000 {
340
+
compatible = "samsung,exynos2200-cmu-hsi0";
341
+
reg = <0x0 0x10a00000 0x0 0x8000>;
342
+
#clock-cells = <1>;
343
+
};
344
+
345
+
usb32drd: phy@10aa0000 {
346
+
compatible = "samsung,exynos2200-usb32drd-phy";
347
+
reg = <0x0 0x10aa0000 0x0 0x10000>;
348
+
349
+
clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>;
350
+
clock-names = "phy";
351
+
352
+
#phy-cells = <1>;
353
+
phys = <&usb_hsphy>;
354
+
phy-names = "hs";
355
+
356
+
samsung,pmu-syscon = <&pmu_system_controller>;
357
+
358
+
status = "disabled";
359
+
};
360
+
361
+
usb_hsphy: phy@10ab0000 {
362
+
compatible = "samsung,exynos2200-eusb2-phy";
363
+
reg = <0x0 0x10ab0000 0x0 0x10000>;
364
+
365
+
clocks = <&cmu_hsi0 CLK_MOUT_HSI0_USB32DRD>,
366
+
<&cmu_hsi0 CLK_MOUT_HSI0_NOC>,
367
+
<&cmu_hsi0 CLK_DOUT_DIV_CLK_HSI0_EUSB>;
368
+
clock-names = "ref", "bus", "ctrl";
369
+
370
+
#phy-cells = <0>;
371
+
372
+
status = "disabled";
373
+
};
374
+
375
+
usb: usb@10b00000 {
376
+
compatible = "samsung,exynos2200-dwusb3";
377
+
ranges = <0x0 0x0 0x10b00000 0x10000>;
378
+
379
+
clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>;
380
+
clock-names = "link_aclk";
381
+
382
+
#address-cells = <1>;
383
+
#size-cells = <1>;
384
+
385
+
status = "disabled";
386
+
387
+
usb_dwc3: usb@0 {
388
+
compatible = "snps,dwc3";
389
+
reg = <0x0 0x10000>;
390
+
391
+
clocks = <&cmu_hsi0 CLK_MOUT_HSI0_USB32DRD>;
392
+
clock-names = "ref";
393
+
394
+
interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH 0>;
395
+
396
+
phys = <&usb32drd 0>;
397
+
phy-names = "usb2-phy";
398
+
399
+
snps,dis-u2-freeclk-exists-quirk;
400
+
snps,gfladj-refclk-lpm-sel-quirk;
401
+
snps,has-lpm-erratum;
402
+
snps,quirk-frame-length-adjustment = <0x20>;
403
+
snps,usb3_lpm_capable;
404
+
};
405
+
};
406
+
407
+
cmu_ufs: clock-controller@11000000 {
408
+
compatible = "samsung,exynos2200-cmu-ufs";
409
+
reg = <0x0 0x11000000 0x0 0x8000>;
410
+
#clock-cells = <1>;
411
+
412
+
clocks = <&xtcxo>,
413
+
<&cmu_top CLK_DOUT_CMU_UFS_NOC>,
414
+
<&cmu_top CLK_MOUT_CMU_UFS_MMC_CARD>,
415
+
<&cmu_top CLK_DOUT_CMU_UFS_UFS_EMBD>;
416
+
clock-names = "oscclk", "noc", "mmc", "ufs";
417
+
};
418
+
419
+
syscon_ufs: syscon@11020000 {
420
+
compatible = "samsung,exynos2200-ufs-sysreg", "syscon";
421
+
reg = <0x0 0x11020000 0x0 0x2000>;
422
+
};
423
+
424
+
pinctrl_ufs: pinctrl@11040000 {
425
+
compatible = "samsung,exynos2200-pinctrl";
426
+
reg = <0x0 0x11040000 0x0 0x1000>;
427
+
};
428
+
429
+
pinctrl_hsi1ufs: pinctrl@11060000 {
430
+
compatible = "samsung,exynos2200-pinctrl";
431
+
reg = <0x0 0x11060000 0x0 0x1000>;
432
+
};
433
+
434
+
pinctrl_hsi1: pinctrl@11240000 {
435
+
compatible = "samsung,exynos2200-pinctrl";
436
+
reg = <0x0 0x11240000 0x0 0x1000>;
437
+
};
438
+
439
+
cmu_peric2: clock-controller@11c00000 {
440
+
compatible = "samsung,exynos2200-cmu-peric2";
441
+
reg = <0x0 0x11c00000 0x0 0x8000>;
442
+
#clock-cells = <1>;
443
+
444
+
clocks = <&xtcxo>,
445
+
<&cmu_top CLK_DOUT_CMU_PERIC2_NOC>,
446
+
<&cmu_top CLK_DOUT_CMU_PERIC2_IP0>,
447
+
<&cmu_top CLK_DOUT_CMU_PERIC2_IP1>;
448
+
clock-names = "oscclk", "noc", "ip0", "ip1";
449
+
};
450
+
451
+
syscon_peric2: syscon@11c20000 {
452
+
compatible = "samsung,exynos2200-peric2-sysreg", "syscon";
453
+
reg = <0x0 0x11c20000 0x0 0x4000>;
454
+
};
455
+
456
+
pinctrl_peric2: pinctrl@11c30000 {
457
+
compatible = "samsung,exynos2200-pinctrl";
458
+
reg = <0x0 0x11c30000 0x0 0x1000>;
459
+
};
460
+
461
+
cmu_cmgp: clock-controller@14e00000 {
462
+
compatible = "samsung,exynos2200-cmu-cmgp";
463
+
reg = <0x0 0x14e00000 0x0 0x8000>;
464
+
#clock-cells = <1>;
465
+
466
+
clocks = <&xtcxo>,
467
+
<&cmu_alive CLK_DOUT_ALIVE_CMGP_NOC>,
468
+
<&cmu_alive CLK_DOUT_ALIVE_CMGP_PERI>;
469
+
clock-names = "oscclk", "noc", "peri";
470
+
};
471
+
472
+
syscon_cmgp: syscon@14e20000 {
473
+
compatible = "samsung,exynos2200-cmgp-sysreg", "syscon";
474
+
reg = <0x0 0x14e20000 0x0 0x2000>;
475
+
};
476
+
477
+
pinctrl_cmgp: pinctrl@14e30000 {
478
+
compatible = "samsung,exynos2200-pinctrl";
479
+
reg = <0x0 0x14e30000 0x0 0x1000>;
480
+
481
+
wakeup-interrupt-controller {
482
+
compatible = "samsung,exynos2200-wakeup-eint",
483
+
"samsung,exynos850-wakeup-eint",
484
+
"samsung,exynos7-wakeup-eint";
485
+
};
486
+
};
487
+
488
+
cmu_vts: clock-controller@15300000 {
489
+
compatible = "samsung,exynos2200-cmu-vts";
490
+
reg = <0x0 0x15300000 0x0 0x8000>;
491
+
#clock-cells = <1>;
492
+
493
+
clocks = <&xtcxo>,
494
+
<&cmu_top CLK_DOUT_CMU_VTS_DMIC>;
495
+
clock-names = "oscclk", "dmic";
496
+
};
497
+
498
+
pinctrl_vts: pinctrl@15320000 {
499
+
compatible = "samsung,exynos2200-pinctrl";
500
+
reg = <0x0 0x15320000 0x0 0x1000>;
501
+
};
502
+
503
+
cmu_alive: clock-controller@15800000 {
504
+
compatible = "samsung,exynos2200-cmu-alive";
505
+
reg = <0x0 0x15800000 0x0 0x8000>;
506
+
#clock-cells = <1>;
507
+
508
+
clocks = <&xtcxo>,
509
+
<&cmu_top CLK_DOUT_CMU_ALIVE_NOC>;
510
+
clock-names = "oscclk", "noc";
511
+
};
512
+
513
+
pinctrl_alive: pinctrl@15850000 {
514
+
compatible = "samsung,exynos2200-pinctrl";
515
+
reg = <0x0 0x15850000 0x0 0x1000>;
516
+
517
+
wakeup-interrupt-controller {
518
+
compatible = "samsung,exynos2200-wakeup-eint",
519
+
"samsung,exynos850-wakeup-eint",
520
+
"samsung,exynos7-wakeup-eint";
521
+
};
522
+
};
523
+
524
+
pmu_system_controller: system-controller@15860000 {
525
+
compatible = "samsung,exynos2200-pmu",
526
+
"samsung,exynos7-pmu", "syscon";
527
+
reg = <0x0 0x15860000 0x0 0x10000>;
528
+
529
+
reboot: syscon-reboot {
530
+
compatible = "syscon-reboot";
531
+
offset = <0x3c00>; /* SYSTEM_CONFIGURATION */
532
+
mask = <0x2>; /* SWRESET_SYSTEM */
533
+
value = <0x2>; /* reset value */
534
+
};
535
+
};
536
+
537
+
cmu_top: clock-controller@1a320000 {
538
+
compatible = "samsung,exynos2200-cmu-top";
539
+
reg = <0x0 0x1a320000 0x0 0x8000>;
540
+
#clock-cells = <1>;
541
+
542
+
clocks = <&xtcxo>;
543
+
clock-names = "oscclk";
544
+
};
545
+
};
546
+
547
+
timer {
548
+
compatible = "arm,armv8-timer";
549
+
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
550
+
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
551
+
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
552
+
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
553
+
/*
554
+
* Non-updatable, broken stock Samsung bootloader does not
555
+
* configure CNTFRQ_EL0
556
+
*/
557
+
clock-frequency = <25600000>;
558
+
};
559
+
};
560
+
561
+
#include "exynos2200-pinctrl.dtsi"
+1
-1
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+1
-1
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+1
-1
arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts
+1
-1
arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts
+1
-1
arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts
+1
-1
arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts
+1
arch/arm64/boot/dts/exynos/exynos7870.dtsi
+1
arch/arm64/boot/dts/exynos/exynos7870.dtsi
+378
arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+378
arch/arm64/boot/dts/exynos/exynosautov920.dtsi
···
455
455
samsung,uart-fifosize = <256>;
456
456
status = "disabled";
457
457
};
458
+
459
+
spi_0: spi@10880000 {
460
+
compatible = "samsung,exynosautov920-spi",
461
+
"samsung,exynos850-spi";
462
+
reg = <0x10880000 0x30>;
463
+
interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
464
+
pinctrl-names = "default";
465
+
pinctrl-0 = <&spi0_bus &spi0_cs_func>;
466
+
clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
467
+
<&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
468
+
clock-names = "spi", "spi_busclk0";
469
+
samsung,spi-src-clk = <0>;
470
+
dmas = <&pdma0 1>, <&pdma0 0>;
471
+
dma-names = "tx", "rx";
472
+
num-cs = <1>;
473
+
#address-cells = <1>;
474
+
#size-cells = <0>;
475
+
fifo-depth = <256>;
476
+
status = "disabled";
477
+
};
458
478
};
459
479
460
480
usi_1: usi@108a00c0 {
···
502
482
<&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>;
503
483
clock-names = "uart", "clk_uart_baud0";
504
484
samsung,uart-fifosize = <256>;
485
+
status = "disabled";
486
+
};
487
+
488
+
spi_1: spi@108a0000 {
489
+
compatible = "samsung,exynosautov920-spi",
490
+
"samsung,exynos850-spi";
491
+
reg = <0x108a0000 0x30>;
492
+
interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>;
493
+
pinctrl-names = "default";
494
+
pinctrl-0 = <&spi1_bus &spi1_cs_func>;
495
+
clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
496
+
<&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>;
497
+
clock-names = "spi", "spi_busclk0";
498
+
samsung,spi-src-clk = <0>;
499
+
dmas = <&pdma0 3>, <&pdma0 2>;
500
+
dma-names = "tx", "rx";
501
+
num-cs = <1>;
502
+
#address-cells = <1>;
503
+
#size-cells = <0>;
504
+
fifo-depth = <256>;
505
505
status = "disabled";
506
506
};
507
507
};
···
553
513
samsung,uart-fifosize = <64>;
554
514
status = "disabled";
555
515
};
516
+
517
+
spi_2: spi@108c0000 {
518
+
compatible = "samsung,exynosautov920-spi",
519
+
"samsung,exynos850-spi";
520
+
reg = <0x108c0000 0x30>;
521
+
interrupts = <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>;
522
+
pinctrl-names = "default";
523
+
pinctrl-0 = <&spi2_bus &spi2_cs_func>;
524
+
clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
525
+
<&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>;
526
+
clock-names = "spi", "spi_busclk0";
527
+
samsung,spi-src-clk = <0>;
528
+
dmas = <&pdma0 5>, <&pdma0 4>;
529
+
dma-names = "tx", "rx";
530
+
num-cs = <1>;
531
+
#address-cells = <1>;
532
+
#size-cells = <0>;
533
+
fifo-depth = <64>;
534
+
status = "disabled";
535
+
};
556
536
};
557
537
558
538
usi_3: usi@108e00c0 {
···
600
540
<&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>;
601
541
clock-names = "uart", "clk_uart_baud0";
602
542
samsung,uart-fifosize = <64>;
543
+
status = "disabled";
544
+
};
545
+
546
+
spi_3: spi@108e0000 {
547
+
compatible = "samsung,exynosautov920-spi",
548
+
"samsung,exynos850-spi";
549
+
reg = <0x108e0000 0x30>;
550
+
interrupts = <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>;
551
+
pinctrl-names = "default";
552
+
pinctrl-0 = <&spi3_bus &spi3_cs_func>;
553
+
clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
554
+
<&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>;
555
+
clock-names = "spi", "spi_busclk0";
556
+
samsung,spi-src-clk = <0>;
557
+
dmas = <&pdma0 7>, <&pdma0 6>;
558
+
dma-names = "tx", "rx";
559
+
num-cs = <1>;
560
+
#address-cells = <1>;
561
+
#size-cells = <0>;
562
+
fifo-depth = <64>;
603
563
status = "disabled";
604
564
};
605
565
};
···
651
571
samsung,uart-fifosize = <64>;
652
572
status = "disabled";
653
573
};
574
+
575
+
spi_4: spi@10900000 {
576
+
compatible = "samsung,exynosautov920-spi",
577
+
"samsung,exynos850-spi";
578
+
reg = <0x10900000 0x30>;
579
+
interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>;
580
+
pinctrl-names = "default";
581
+
pinctrl-0 = <&spi4_bus &spi4_cs_func>;
582
+
clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
583
+
<&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>;
584
+
clock-names = "spi", "spi_busclk0";
585
+
samsung,spi-src-clk = <0>;
586
+
dmas = <&pdma0 9>, <&pdma0 8>;
587
+
dma-names = "tx", "rx";
588
+
num-cs = <1>;
589
+
#address-cells = <1>;
590
+
#size-cells = <0>;
591
+
fifo-depth = <64>;
592
+
status = "disabled";
593
+
};
654
594
};
655
595
656
596
usi_5: usi@109200c0 {
···
698
598
<&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>;
699
599
clock-names = "uart", "clk_uart_baud0";
700
600
samsung,uart-fifosize = <64>;
601
+
status = "disabled";
602
+
};
603
+
604
+
spi_5: spi@10920000 {
605
+
compatible = "samsung,exynosautov920-spi",
606
+
"samsung,exynos850-spi";
607
+
reg = <0x10920000 0x30>;
608
+
interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
609
+
pinctrl-names = "default";
610
+
pinctrl-0 = <&spi5_bus &spi5_cs_func>;
611
+
clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
612
+
<&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>;
613
+
clock-names = "spi", "spi_busclk0";
614
+
samsung,spi-src-clk = <0>;
615
+
dmas = <&pdma0 11>, <&pdma0 10>;
616
+
dma-names = "tx", "rx";
617
+
num-cs = <1>;
618
+
#address-cells = <1>;
619
+
#size-cells = <0>;
620
+
fifo-depth = <64>;
701
621
status = "disabled";
702
622
};
703
623
};
···
749
629
samsung,uart-fifosize = <64>;
750
630
status = "disabled";
751
631
};
632
+
633
+
spi_6: spi@10940000 {
634
+
compatible = "samsung,exynosautov920-spi",
635
+
"samsung,exynos850-spi";
636
+
reg = <0x10940000 0x30>;
637
+
interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>;
638
+
pinctrl-names = "default";
639
+
pinctrl-0 = <&spi6_bus &spi6_cs_func>;
640
+
clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
641
+
<&cmu_peric0 CLK_DOUT_PERIC0_USI06_USI>;
642
+
clock-names = "spi", "spi_busclk0";
643
+
samsung,spi-src-clk = <0>;
644
+
dmas = <&pdma0 13>, <&pdma0 12>;
645
+
dma-names = "tx", "rx";
646
+
num-cs = <1>;
647
+
#address-cells = <1>;
648
+
#size-cells = <0>;
649
+
fifo-depth = <64>;
650
+
status = "disabled";
651
+
};
752
652
};
753
653
754
654
usi_7: usi@109600c0 {
···
796
656
<&cmu_peric0 CLK_DOUT_PERIC0_USI07_USI>;
797
657
clock-names = "uart", "clk_uart_baud0";
798
658
samsung,uart-fifosize = <64>;
659
+
status = "disabled";
660
+
};
661
+
662
+
spi_7: spi@10960000 {
663
+
compatible = "samsung,exynosautov920-spi",
664
+
"samsung,exynos850-spi";
665
+
reg = <0x10960000 0x30>;
666
+
interrupts = <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>;
667
+
pinctrl-names = "default";
668
+
pinctrl-0 = <&spi7_bus &spi7_cs_func>;
669
+
clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
670
+
<&cmu_peric0 CLK_DOUT_PERIC0_USI07_USI>;
671
+
clock-names = "spi", "spi_busclk0";
672
+
samsung,spi-src-clk = <0>;
673
+
dmas = <&pdma0 15>, <&pdma0 14>;
674
+
dma-names = "tx", "rx";
675
+
num-cs = <1>;
676
+
#address-cells = <1>;
677
+
#size-cells = <0>;
678
+
fifo-depth = <64>;
799
679
status = "disabled";
800
680
};
801
681
};
···
847
687
samsung,uart-fifosize = <64>;
848
688
status = "disabled";
849
689
};
690
+
691
+
spi_8: spi@10980000 {
692
+
compatible = "samsung,exynosautov920-spi",
693
+
"samsung,exynos850-spi";
694
+
reg = <0x10980000 0x30>;
695
+
interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>;
696
+
pinctrl-names = "default";
697
+
pinctrl-0 = <&spi8_bus &spi8_cs_func>;
698
+
clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
699
+
<&cmu_peric0 CLK_DOUT_PERIC0_USI08_USI>;
700
+
clock-names = "spi", "spi_busclk0";
701
+
samsung,spi-src-clk = <0>;
702
+
dmas = <&pdma0 17>, <&pdma0 16>;
703
+
dma-names = "tx", "rx";
704
+
num-cs = <1>;
705
+
#address-cells = <1>;
706
+
#size-cells = <0>;
707
+
fifo-depth = <64>;
708
+
status = "disabled";
709
+
};
710
+
850
711
};
851
712
852
713
pwm: pwm@109b0000 {
···
933
752
samsung,uart-fifosize = <256>;
934
753
status = "disabled";
935
754
};
755
+
756
+
spi_9: spi@10c80000 {
757
+
compatible = "samsung,exynosautov920-spi",
758
+
"samsung,exynos850-spi";
759
+
reg = <0x10c80000 0x30>;
760
+
interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>;
761
+
pinctrl-names = "default";
762
+
pinctrl-0 = <&spi9_bus &spi9_cs_func>;
763
+
clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
764
+
<&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>;
765
+
clock-names = "spi", "spi_busclk0";
766
+
samsung,spi-src-clk = <0>;
767
+
dmas = <&pdma1 1>, <&pdma1 0>;
768
+
dma-names = "tx", "rx";
769
+
num-cs = <1>;
770
+
#address-cells = <1>;
771
+
#size-cells = <0>;
772
+
fifo-depth = <256>;
773
+
status = "disabled";
774
+
};
936
775
};
937
776
938
777
usi_10: usi@10ca00c0 {
···
980
779
<&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>;
981
780
clock-names = "uart", "clk_uart_baud0";
982
781
samsung,uart-fifosize = <64>;
782
+
status = "disabled";
783
+
};
784
+
785
+
spi_10: spi@10ca0000 {
786
+
compatible = "samsung,exynosautov920-spi",
787
+
"samsung,exynos850-spi";
788
+
reg = <0x10ca0000 0x30>;
789
+
interrupts = <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>;
790
+
pinctrl-names = "default";
791
+
pinctrl-0 = <&spi10_bus &spi10_cs_func>;
792
+
clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
793
+
<&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>;
794
+
clock-names = "spi", "spi_busclk0";
795
+
samsung,spi-src-clk = <0>;
796
+
dmas = <&pdma1 3>, <&pdma1 2>;
797
+
dma-names = "tx", "rx";
798
+
num-cs = <1>;
799
+
#address-cells = <1>;
800
+
#size-cells = <0>;
801
+
fifo-depth = <64>;
983
802
status = "disabled";
984
803
};
985
804
};
···
1031
810
samsung,uart-fifosize = <64>;
1032
811
status = "disabled";
1033
812
};
813
+
814
+
spi_11: spi@10cc0000 {
815
+
compatible = "samsung,exynosautov920-spi",
816
+
"samsung,exynos850-spi";
817
+
reg = <0x10cc0000 0x30>;
818
+
interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>;
819
+
pinctrl-names = "default";
820
+
pinctrl-0 = <&spi11_bus &spi11_cs_func>;
821
+
clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
822
+
<&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>;
823
+
clock-names = "spi", "spi_busclk0";
824
+
samsung,spi-src-clk = <0>;
825
+
dmas = <&pdma1 5>, <&pdma1 4>;
826
+
dma-names = "tx", "rx";
827
+
num-cs = <1>;
828
+
#address-cells = <1>;
829
+
#size-cells = <0>;
830
+
fifo-depth = <64>;
831
+
status = "disabled";
832
+
};
1034
833
};
1035
834
1036
835
usi_12: usi@10ce00c0 {
···
1078
837
<&cmu_peric1 CLK_DOUT_PERIC1_USI12_USI>;
1079
838
clock-names = "uart", "clk_uart_baud0";
1080
839
samsung,uart-fifosize = <64>;
840
+
status = "disabled";
841
+
};
842
+
843
+
spi_12: spi@10ce0000 {
844
+
compatible = "samsung,exynosautov920-spi",
845
+
"samsung,exynos850-spi";
846
+
reg = <0x10ce0000 0x30>;
847
+
interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>;
848
+
pinctrl-names = "default";
849
+
pinctrl-0 = <&spi12_bus &spi12_cs_func>;
850
+
clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
851
+
<&cmu_peric1 CLK_DOUT_PERIC1_USI12_USI>;
852
+
clock-names = "spi", "spi_busclk0";
853
+
samsung,spi-src-clk = <0>;
854
+
dmas = <&pdma1 7>, <&pdma1 6>;
855
+
dma-names = "tx", "rx";
856
+
num-cs = <1>;
857
+
#address-cells = <1>;
858
+
#size-cells = <0>;
859
+
fifo-depth = <64>;
1081
860
status = "disabled";
1082
861
};
1083
862
};
···
1129
868
samsung,uart-fifosize = <64>;
1130
869
status = "disabled";
1131
870
};
871
+
872
+
spi_13: spi@10d00000 {
873
+
compatible = "samsung,exynosautov920-spi",
874
+
"samsung,exynos850-spi";
875
+
reg = <0x10d00000 0x30>;
876
+
interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>;
877
+
pinctrl-names = "default";
878
+
pinctrl-0 = <&spi13_bus &spi13_cs_func>;
879
+
clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
880
+
<&cmu_peric1 CLK_DOUT_PERIC1_USI13_USI>;
881
+
clock-names = "spi", "spi_busclk0";
882
+
samsung,spi-src-clk = <0>;
883
+
dmas = <&pdma1 9>, <&pdma1 8>;
884
+
dma-names = "tx", "rx";
885
+
num-cs = <1>;
886
+
#address-cells = <1>;
887
+
#size-cells = <0>;
888
+
fifo-depth = <64>;
889
+
status = "disabled";
890
+
};
1132
891
};
1133
892
1134
893
usi_14: usi@10d200c0 {
···
1176
895
<&cmu_peric1 CLK_DOUT_PERIC1_USI14_USI>;
1177
896
clock-names = "uart", "clk_uart_baud0";
1178
897
samsung,uart-fifosize = <64>;
898
+
status = "disabled";
899
+
};
900
+
901
+
spi_14: spi@10d20000 {
902
+
compatible = "samsung,exynosautov920-spi",
903
+
"samsung,exynos850-spi";
904
+
reg = <0x10d20000 0x30>;
905
+
interrupts = <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>;
906
+
pinctrl-names = "default";
907
+
pinctrl-0 = <&spi14_bus &spi14_cs_func>;
908
+
clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
909
+
<&cmu_peric1 CLK_DOUT_PERIC1_USI14_USI>;
910
+
clock-names = "spi", "spi_busclk0";
911
+
samsung,spi-src-clk = <0>;
912
+
dmas = <&pdma1 11>, <&pdma1 10>;
913
+
dma-names = "tx", "rx";
914
+
num-cs = <1>;
915
+
#address-cells = <1>;
916
+
#size-cells = <0>;
917
+
fifo-depth = <64>;
1179
918
status = "disabled";
1180
919
};
1181
920
};
···
1227
926
samsung,uart-fifosize = <64>;
1228
927
status = "disabled";
1229
928
};
929
+
930
+
spi_15: spi@10d40000 {
931
+
compatible = "samsung,exynosautov920-spi",
932
+
"samsung,exynos850-spi";
933
+
reg = <0x10d40000 0x30>;
934
+
interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
935
+
pinctrl-names = "default";
936
+
pinctrl-0 = <&spi15_bus &spi15_cs_func>;
937
+
clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
938
+
<&cmu_peric1 CLK_DOUT_PERIC1_USI15_USI>;
939
+
clock-names = "spi", "spi_busclk0";
940
+
samsung,spi-src-clk = <0>;
941
+
dmas = <&pdma1 13>, <&pdma1 12>;
942
+
dma-names = "tx", "rx";
943
+
num-cs = <1>;
944
+
#address-cells = <1>;
945
+
#size-cells = <0>;
946
+
fifo-depth = <64>;
947
+
status = "disabled";
948
+
};
1230
949
};
1231
950
1232
951
usi_16: usi@10d600c0 {
···
1276
955
samsung,uart-fifosize = <64>;
1277
956
status = "disabled";
1278
957
};
958
+
959
+
spi_16: spi@10d60000 {
960
+
compatible = "samsung,exynosautov920-spi",
961
+
"samsung,exynos850-spi";
962
+
reg = <0x10d60000 0x30>;
963
+
interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
964
+
pinctrl-names = "default";
965
+
pinctrl-0 = <&spi16_bus &spi16_cs_func>;
966
+
clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
967
+
<&cmu_peric1 CLK_DOUT_PERIC1_USI16_USI>;
968
+
clock-names = "spi", "spi_busclk0";
969
+
samsung,spi-src-clk = <0>;
970
+
dmas = <&pdma1 15>, <&pdma1 14>;
971
+
dma-names = "tx", "rx";
972
+
num-cs = <1>;
973
+
#address-cells = <1>;
974
+
#size-cells = <0>;
975
+
fifo-depth = <64>;
976
+
status = "disabled";
977
+
};
1279
978
};
1280
979
1281
980
usi_17: usi@10d800c0 {
···
1323
982
<&cmu_peric1 CLK_DOUT_PERIC1_USI17_USI>;
1324
983
clock-names = "uart", "clk_uart_baud0";
1325
984
samsung,uart-fifosize = <64>;
985
+
status = "disabled";
986
+
};
987
+
988
+
spi_17: spi@10d80000 {
989
+
compatible = "samsung,exynosautov920-spi",
990
+
"samsung,exynos850-spi";
991
+
reg = <0x10d80000 0x30>;
992
+
interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
993
+
pinctrl-names = "default";
994
+
pinctrl-0 = <&spi17_bus &spi17_cs_func>;
995
+
clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>,
996
+
<&cmu_peric1 CLK_DOUT_PERIC1_USI17_USI>;
997
+
clock-names = "spi", "spi_busclk0";
998
+
samsung,spi-src-clk = <0>;
999
+
dmas = <&pdma1 17>, <&pdma1 16>;
1000
+
dma-names = "tx", "rx";
1001
+
num-cs = <1>;
1002
+
#address-cells = <1>;
1003
+
#size-cells = <0>;
1004
+
fifo-depth = <64>;
1326
1005
status = "disabled";
1327
1006
};
1328
1007
};
···
1407
1046
compatible = "samsung,exynosautov920-pinctrl";
1408
1047
reg = <0x16450000 0x10000>;
1409
1048
interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
1049
+
};
1050
+
1051
+
cmu_hsi2: clock-controller@16b00000 {
1052
+
compatible = "samsung,exynosautov920-cmu-hsi2";
1053
+
reg = <0x16b00000 0x8000>;
1054
+
#clock-cells = <1>;
1055
+
1056
+
clocks = <&xtcxo>,
1057
+
<&cmu_top DOUT_CLKCMU_HSI2_NOC>,
1058
+
<&cmu_top DOUT_CLKCMU_HSI2_NOC_UFS>,
1059
+
<&cmu_top DOUT_CLKCMU_HSI2_UFS_EMBD>,
1060
+
<&cmu_top DOUT_CLKCMU_HSI2_ETHERNET>;
1061
+
clock-names = "oscclk",
1062
+
"noc",
1063
+
"ufs",
1064
+
"embd",
1065
+
"ethernet";
1410
1066
};
1411
1067
1412
1068
pinctrl_hsi2: pinctrl@16c10000 {
+96
arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi
+96
arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi
···
60
60
};
61
61
};
62
62
63
+
reboot-mode {
64
+
compatible = "nvmem-reboot-mode";
65
+
nvmem-cells = <&nvmem_reboot_mode>;
66
+
nvmem-cell-names = "reboot-mode";
67
+
mode-bootloader = <0x800000fc>;
68
+
mode-charge = <0x8000000a>;
69
+
mode-dm-verity-device-corrupted = <0x80000050>;
70
+
mode-fastboot = <0x800000fa>;
71
+
mode-reboot-ab-update = <0x80000052>;
72
+
mode-recovery = <0x800000ff>;
73
+
mode-rescue = <0x800000f9>;
74
+
mode-shutdown-thermal = <0x80000051>;
75
+
mode-shutdown-thermal-battery = <0x80000051>;
76
+
};
77
+
63
78
/* TODO: Remove this once PMIC is implemented */
64
79
reg_placeholder: regulator-0 {
65
80
compatible = "regulator-fixed";
···
96
81
reg = <0x0 0xfac00000 0x0>;
97
82
no-map;
98
83
status = "disabled";
84
+
};
85
+
};
86
+
};
87
+
88
+
&acpm_ipc {
89
+
pmic {
90
+
compatible = "samsung,s2mpg10-pmic";
91
+
interrupts-extended = <&gpa0 6 IRQ_TYPE_LEVEL_LOW>;
92
+
pinctrl-names = "default";
93
+
pinctrl-0 = <&pmic_int>;
94
+
system-power-controller;
95
+
wakeup-source;
96
+
97
+
regulators {
99
98
};
100
99
};
101
100
};
···
217
188
};
218
189
};
219
190
};
191
+
192
+
pmic@66 {
193
+
compatible = "maxim,max77759";
194
+
reg = <0x66>;
195
+
196
+
pinctrl-0 = <&if_pmic_int>;
197
+
pinctrl-names = "default";
198
+
interrupts-extended = <&gpa8 3 IRQ_TYPE_LEVEL_LOW>;
199
+
200
+
interrupt-controller;
201
+
#interrupt-cells = <2>;
202
+
203
+
gpio {
204
+
compatible = "maxim,max77759-gpio";
205
+
206
+
gpio-controller;
207
+
#gpio-cells = <2>;
208
+
/*
209
+
* "Human-readable name [SIGNAL_LABEL]" where the
210
+
* latter comes from the schematic
211
+
*/
212
+
gpio-line-names = "OTG boost [OTG_BOOST_EN]",
213
+
"max20339 IRQ [MW_OVP_INT_L]";
214
+
215
+
interrupt-controller;
216
+
#interrupt-cells = <2>;
217
+
};
218
+
219
+
nvmem-0 {
220
+
compatible = "maxim,max77759-nvmem";
221
+
222
+
nvmem-layout {
223
+
compatible = "fixed-layout";
224
+
#address-cells = <1>;
225
+
#size-cells = <1>;
226
+
227
+
nvmem_reboot_mode: reboot-mode@0 {
228
+
reg = <0x0 0x4>;
229
+
};
230
+
231
+
boot-reason@4 {
232
+
reg = <0x4 0x4>;
233
+
};
234
+
235
+
shutdown-user-flag@8 {
236
+
reg = <0x8 0x1>;
237
+
};
238
+
239
+
rsoc@a {
240
+
reg = <0xa 0x2>;
241
+
};
242
+
};
243
+
};
244
+
};
220
245
};
221
246
222
247
&pinctrl_far_alive {
···
294
211
samsung,pin-pud = <GS101_PIN_PULL_UP>;
295
212
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
296
213
};
214
+
215
+
if_pmic_int: if-pmic-int-pins {
216
+
samsung,pins = "gpa8-3";
217
+
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
218
+
samsung,pin-pud = <GS101_PIN_PULL_UP>;
219
+
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
220
+
};
297
221
};
298
222
299
223
&pinctrl_gpio_alive {
224
+
pmic_int: pmic-int-pins {
225
+
samsung,pins = "gpa0-6";
226
+
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
227
+
samsung,pin-pud = <GS101_PIN_PULL_NONE>;
228
+
};
229
+
300
230
key_power: key-power-pins {
301
231
samsung,pins = "gpa10-1";
302
232
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
+6
-4
arch/arm64/boot/dts/exynos/google/gs101.dtsi
+6
-4
arch/arm64/boot/dts/exynos/google/gs101.dtsi
···
155
155
idle-state-name = "c2";
156
156
compatible = "arm,idle-state";
157
157
arm,psci-suspend-param = <0x0010000>;
158
+
local-timer-stop;
158
159
entry-latency-us = <70>;
159
160
exit-latency-us = <160>;
160
161
min-residency-us = <2000>;
···
165
164
idle-state-name = "c2";
166
165
compatible = "arm,idle-state";
167
166
arm,psci-suspend-param = <0x0010000>;
167
+
local-timer-stop;
168
168
entry-latency-us = <150>;
169
169
exit-latency-us = <190>;
170
170
min-residency-us = <2500>;
···
175
173
idle-state-name = "c2";
176
174
compatible = "arm,idle-state";
177
175
arm,psci-suspend-param = <0x0010000>;
176
+
local-timer-stop;
178
177
entry-latency-us = <235>;
179
178
exit-latency-us = <220>;
180
179
min-residency-us = <3500>;
···
1371
1368
<&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>;
1372
1369
clock-names = "core_clk", "sclk_unipro_main", "fmp",
1373
1370
"aclk", "pclk", "sysreg";
1371
+
dma-coherent;
1374
1372
freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>;
1375
1373
pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
1376
1374
pinctrl-names = "default";
···
1419
1415
};
1420
1416
1421
1417
reboot: syscon-reboot {
1422
-
compatible = "syscon-reboot";
1423
-
offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
1424
-
mask = <0x2>; /* SWRESET_SYSTEM */
1425
-
value = <0x2>; /* reset value */
1418
+
compatible = "google,gs101-reboot";
1426
1419
};
1427
1420
1428
1421
reboot-mode {
···
1427
1426
offset = <0x0810>; /* EXYNOS_PMU_SYSIP_DAT0 */
1428
1427
mode-bootloader = <0xfc>;
1429
1428
mode-charge = <0x0a>;
1429
+
mode-dm-verity-device-corrupted = <0x50>;
1430
1430
mode-fastboot = <0xfa>;
1431
1431
mode-reboot-ab-update = <0x52>;
1432
1432
mode-recovery = <0xff>;