drm/amdgpu: Add amdgpu_regs_pcie64 debugfs node

+112

1 changed file

expand all

drivers

gpu

drm

amd

amdgpu

amdgpu_debugfs.c

+112

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

··· 618 618 } 619 619 620 620 /** 621 + * amdgpu_debugfs_regs_pcie64_read - Read from a 64-bit PCIE register 622 + * 623 + * @f: open file handle 624 + * @buf: User buffer to store read data in 625 + * @size: Number of bytes to read 626 + * @pos: Offset to seek to 627 + */ 628 + static ssize_t amdgpu_debugfs_regs_pcie64_read(struct file *f, char __user *buf, 629 + size_t size, loff_t *pos) 630 + { 631 + struct amdgpu_device *adev = file_inode(f)->i_private; 632 + ssize_t result = 0; 633 + int r; 634 + 635 + if (size & 0x7 || *pos & 0x7) 636 + return -EINVAL; 637 + 638 + r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 639 + if (r < 0) { 640 + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 641 + return r; 642 + } 643 + 644 + r = amdgpu_virt_enable_access_debugfs(adev); 645 + if (r < 0) { 646 + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 647 + return r; 648 + } 649 + 650 + while (size) { 651 + uint64_t value; 652 + 653 + value = RREG64_PCIE_EXT(*pos); 654 + 655 + r = put_user(value, (uint64_t *)buf); 656 + if (r) 657 + goto out; 658 + 659 + result += 8; 660 + buf += 8; 661 + *pos += 8; 662 + size -= 8; 663 + } 664 + 665 + r = result; 666 + out: 667 + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 668 + amdgpu_virt_disable_access_debugfs(adev); 669 + return r; 670 + } 671 + 672 + /** 673 + * amdgpu_debugfs_regs_pcie64_write - Write to a 64-bit PCIE register 674 + * 675 + * @f: open file handle 676 + * @buf: User buffer to write data from 677 + * @size: Number of bytes to write 678 + * @pos: Offset to seek to 679 + */ 680 + static ssize_t amdgpu_debugfs_regs_pcie64_write(struct file *f, const char __user *buf, 681 + size_t size, loff_t *pos) 682 + { 683 + struct amdgpu_device *adev = file_inode(f)->i_private; 684 + ssize_t result = 0; 685 + int r; 686 + 687 + if (size & 0x7 || *pos & 0x7) 688 + return -EINVAL; 689 + 690 + r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 691 + if (r < 0) { 692 + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 693 + return r; 694 + } 695 + 696 + r = amdgpu_virt_enable_access_debugfs(adev); 697 + if (r < 0) { 698 + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 699 + return r; 700 + } 701 + 702 + while (size) { 703 + uint64_t value; 704 + 705 + r = get_user(value, (uint64_t *)buf); 706 + if (r) 707 + goto out; 708 + 709 + WREG64_PCIE_EXT(*pos, value); 710 + 711 + result += 8; 712 + buf += 8; 713 + *pos += 8; 714 + size -= 8; 715 + } 716 + 717 + r = result; 718 + out: 719 + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 720 + amdgpu_virt_disable_access_debugfs(adev); 721 + return r; 722 + } 723 + 724 + /** 621 725 * amdgpu_debugfs_regs_didt_read - Read from a DIDT register 622 726 * 623 727 * @f: open file handle ··· 1629 1525 .write = amdgpu_debugfs_regs_pcie_write, 1630 1526 .llseek = default_llseek 1631 1527 }; 1528 + static const struct file_operations amdgpu_debugfs_regs_pcie64_fops = { 1529 + .owner = THIS_MODULE, 1530 + .read = amdgpu_debugfs_regs_pcie64_read, 1531 + .write = amdgpu_debugfs_regs_pcie64_write, 1532 + .llseek = default_llseek 1533 + }; 1632 1534 static const struct file_operations amdgpu_debugfs_regs_smc_fops = { 1633 1535 .owner = THIS_MODULE, 1634 1536 .read = amdgpu_debugfs_regs_smc_read, ··· 1697 1587 &amdgpu_debugfs_gprwave_fops, 1698 1588 &amdgpu_debugfs_regs_didt_fops, 1699 1589 &amdgpu_debugfs_regs_pcie_fops, 1590 + &amdgpu_debugfs_regs_pcie64_fops, 1700 1591 &amdgpu_debugfs_regs_smc_fops, 1701 1592 &amdgpu_debugfs_gca_config_fops, 1702 1593 &amdgpu_debugfs_sensors_fops, ··· 1715 1604 "amdgpu_gprwave", 1716 1605 "amdgpu_regs_didt", 1717 1606 "amdgpu_regs_pcie", 1607 + "amdgpu_regs_pcie64", 1718 1608 "amdgpu_regs_smc", 1719 1609 "amdgpu_gca_config", 1720 1610 "amdgpu_sensors",

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