clk: qcom: gpucc-sa8775p: Remove the CLK_IS_CRITICAL and ALWAYS_ON flags

The GPU clocks/GDSCs have been marked critical from the clock driver
but the GPU driver votes on these resources as per the HW requirement.
In the case where these clocks & GDSCs are left enabled, would have
power impact and also cause GPU stability/corruptions.
Fix the same by removing the CLK_IS_CRITICAL for clocks and ALWAYS_ON
flags for the GPU GDSCs.

Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-4-adcc756a23df@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Taniya Das and committed by

Bjorn Andersson 2 years ago e69386d4 955606a7

+11 -16

1 changed file

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drivers

clk

qcom

gpucc-sa8775p.c

+11 -16

drivers/clk/qcom/gpucc-sa8775p.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 - * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 + * Copyright (c) 2021-2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 4 * Copyright (c) 2023, Linaro Limited 5 5 */ 6 6 ··· 280 280 &gpu_cc_hub_ahb_div_clk_src.clkr.hw, 281 281 }, 282 282 .num_parents = 1, 283 - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 283 + .flags = CLK_SET_RATE_PARENT, 284 284 .ops = &clk_branch2_ops, 285 285 }, 286 286 }, ··· 294 294 .enable_mask = BIT(0), 295 295 .hw.init = &(const struct clk_init_data){ 296 296 .name = "gpu_cc_cb_clk", 297 - .flags = CLK_IS_CRITICAL, 298 297 .ops = &clk_branch2_ops, 299 298 }, 300 299 }, ··· 311 312 &gpu_cc_hub_ahb_div_clk_src.clkr.hw, 312 313 }, 313 314 .num_parents = 1, 314 - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 315 + .flags = CLK_SET_RATE_PARENT, 315 316 .ops = &clk_branch2_ops, 316 317 }, 317 318 }, ··· 329 330 &gpu_cc_ff_clk_src.clkr.hw, 330 331 }, 331 332 .num_parents = 1, 332 - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 333 + .flags = CLK_SET_RATE_PARENT, 333 334 .ops = &clk_branch2_ops, 334 335 }, 335 336 }, ··· 347 348 &gpu_cc_gmu_clk_src.clkr.hw, 348 349 }, 349 350 .num_parents = 1, 350 - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 351 + .flags = CLK_SET_RATE_PARENT, 351 352 .ops = &clk_branch2_aon_ops, 352 353 }, 353 354 }, ··· 361 362 .enable_mask = BIT(0), 362 363 .hw.init = &(const struct clk_init_data){ 363 364 .name = "gpu_cc_cx_snoc_dvm_clk", 364 - .flags = CLK_IS_CRITICAL, 365 365 .ops = &clk_branch2_ops, 366 366 }, 367 367 }, ··· 378 380 &gpu_cc_xo_clk_src.clkr.hw, 379 381 }, 380 382 .num_parents = 1, 381 - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 383 + .flags = CLK_SET_RATE_PARENT, 382 384 .ops = &clk_branch2_ops, 383 385 }, 384 386 }, ··· 396 398 &gpu_cc_xo_clk_src.clkr.hw, 397 399 }, 398 400 .num_parents = 1, 399 - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 401 + .flags = CLK_SET_RATE_PARENT, 400 402 .ops = &clk_branch2_ops, 401 403 }, 402 404 }, ··· 414 416 &gpu_cc_demet_div_clk_src.clkr.hw, 415 417 }, 416 418 .num_parents = 1, 417 - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 419 + .flags = CLK_SET_RATE_PARENT, 418 420 .ops = &clk_branch2_aon_ops, 419 421 }, 420 422 }, ··· 428 430 .enable_mask = BIT(0), 429 431 .hw.init = &(const struct clk_init_data){ 430 432 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", 431 - .flags = CLK_IS_CRITICAL, 432 433 .ops = &clk_branch2_ops, 433 434 }, 434 435 }, ··· 445 448 &gpu_cc_hub_clk_src.clkr.hw, 446 449 }, 447 450 .num_parents = 1, 448 - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 451 + .flags = CLK_SET_RATE_PARENT, 449 452 .ops = &clk_branch2_aon_ops, 450 453 }, 451 454 }, ··· 463 466 &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, 464 467 }, 465 468 .num_parents = 1, 466 - .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 469 + .flags = CLK_SET_RATE_PARENT, 467 470 .ops = &clk_branch2_aon_ops, 468 471 }, 469 472 }, ··· 477 480 .enable_mask = BIT(0), 478 481 .hw.init = &(const struct clk_init_data){ 479 482 .name = "gpu_cc_memnoc_gfx_clk", 480 - .flags = CLK_IS_CRITICAL, 481 483 .ops = &clk_branch2_ops, 482 484 }, 483 485 }, ··· 490 494 .enable_mask = BIT(0), 491 495 .hw.init = &(const struct clk_init_data){ 492 496 .name = "gpu_cc_sleep_clk", 493 - .flags = CLK_IS_CRITICAL, 494 497 .ops = &clk_branch2_ops, 495 498 }, 496 499 }, ··· 528 533 .name = "cx_gdsc", 529 534 }, 530 535 .pwrsts = PWRSTS_OFF_ON, 531 - .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, 536 + .flags = VOTABLE | RETAIN_FF_ENABLE, 532 537 }; 533 538 534 539 static struct gdsc gx_gdsc = {

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