tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge master.kernel.org:/home/rmk/linux-2.6-arm

* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] 3762/1: Fix ptrace cache coherency bug for ARM1136 VIPT nonaliasing Harvard caches
[ARM] 3765/1: S3C24XX: cleanup include/asm-arm/arch-s3c2410/dma.h
[ARM] 3764/1: S3C24XX: change type naming to kernel style
[ARM] 3763/1: add both rtcs to csb337 defconfig
[ARM] Fix ARM __raw_read_trylock() implementation
[ARM] 3750/3: Fix double VFP emulation for EABI kernels

Linus Torvalds e6944202 3b6362b8

+229 -168
+34 -3
arch/arm/configs/csb337_defconfig
··· 621 621 # USB-based Watchdog Cards 622 622 # 623 623 # CONFIG_USBPCWATCHDOG is not set 624 + # CONFIG_HW_RANDOM is not set 624 625 # CONFIG_NVRAM is not set 625 - CONFIG_RTC=y 626 - # CONFIG_AT91_RTC is not set 627 626 # CONFIG_DTLK is not set 628 627 # CONFIG_R3964 is not set 629 628 ··· 955 956 CONFIG_MMC=y 956 957 # CONFIG_MMC_DEBUG is not set 957 958 CONFIG_MMC_BLOCK=y 958 - # CONFIG_MMC_WBSD is not set 959 959 CONFIG_MMC_AT91RM9200=y 960 + 961 + # 962 + # Real Time Clock 963 + # 964 + CONFIG_RTC_LIB=y 965 + CONFIG_RTC_CLASS=y 966 + CONFIG_RTC_HCTOSYS=y 967 + CONFIG_RTC_HCTOSYS_DEVICE="rtc1" 968 + 969 + # 970 + # RTC interfaces 971 + # 972 + # CONFIG_RTC_INTF_SYSFS is not set 973 + CONFIG_RTC_INTF_PROC=y 974 + CONFIG_RTC_INTF_DEV=y 975 + # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set 976 + 977 + # 978 + # RTC drivers 979 + # 980 + # CONFIG_RTC_DRV_X1205 is not set 981 + CONFIG_RTC_DRV_DS1307=y 982 + # CONFIG_RTC_DRV_DS1553 is not set 983 + # CONFIG_RTC_DRV_ISL1208 is not set 984 + # CONFIG_RTC_DRV_DS1672 is not set 985 + # CONFIG_RTC_DRV_DS1742 is not set 986 + # CONFIG_RTC_DRV_PCF8563 is not set 987 + # CONFIG_RTC_DRV_PCF8583 is not set 988 + # CONFIG_RTC_DRV_RS5C372 is not set 989 + # CONFIG_RTC_DRV_M48T86 is not set 990 + CONFIG_RTC_DRV_AT91=y 991 + # CONFIG_RTC_DRV_TEST is not set 992 + # CONFIG_RTC_DRV_V3020 is not set 960 993 961 994 # 962 995 # File systems
+44 -44
arch/arm/mach-s3c2410/dma.c
··· 60 60 static kmem_cache_t *dma_kmem; 61 61 62 62 /* dma channel state information */ 63 - s3c2410_dma_chan_t s3c2410_chans[S3C2410_DMA_CHANNELS]; 63 + struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS]; 64 64 65 65 /* debugging functions */ 66 66 ··· 74 74 #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg)) 75 75 #else 76 76 static inline void 77 - dma_wrreg(s3c2410_dma_chan_t *chan, int reg, unsigned long val) 77 + dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val) 78 78 { 79 79 pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg); 80 80 writel(val, dma_regaddr(chan, reg)); ··· 102 102 */ 103 103 104 104 static void 105 - dmadbg_capture(s3c2410_dma_chan_t *chan, struct s3c2410_dma_regstate *regs) 105 + dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs) 106 106 { 107 107 regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC); 108 108 regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC); ··· 112 112 } 113 113 114 114 static void 115 - dmadbg_dumpregs(const char *fname, int line, s3c2410_dma_chan_t *chan, 115 + dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan, 116 116 struct s3c2410_dma_regstate *regs) 117 117 { 118 118 printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n", ··· 122 122 } 123 123 124 124 static void 125 - dmadbg_showchan(const char *fname, int line, s3c2410_dma_chan_t *chan) 125 + dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan) 126 126 { 127 127 struct s3c2410_dma_regstate state; 128 128 ··· 136 136 } 137 137 138 138 static void 139 - dmadbg_showregs(const char *fname, int line, s3c2410_dma_chan_t *chan) 139 + dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan) 140 140 { 141 141 struct s3c2410_dma_regstate state; 142 142 ··· 164 164 */ 165 165 166 166 static void 167 - s3c2410_dma_stats_timeout(s3c2410_dma_stats_t *stats, int val) 167 + s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val) 168 168 { 169 169 if (stats == NULL) 170 170 return; ··· 183 183 */ 184 184 185 185 static int 186 - s3c2410_dma_waitforload(s3c2410_dma_chan_t *chan, int line) 186 + s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line) 187 187 { 188 188 int timeout = chan->load_timeout; 189 189 int took; ··· 230 230 */ 231 231 232 232 static inline int 233 - s3c2410_dma_loadbuffer(s3c2410_dma_chan_t *chan, 234 - s3c2410_dma_buf_t *buf) 233 + s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan, 234 + struct s3c2410_dma_buf *buf) 235 235 { 236 236 unsigned long reload; 237 237 ··· 304 304 */ 305 305 306 306 static void 307 - s3c2410_dma_call_op(s3c2410_dma_chan_t *chan, s3c2410_chan_op_t op) 307 + s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op) 308 308 { 309 309 if (chan->op_fn != NULL) { 310 310 (chan->op_fn)(chan, op); ··· 318 318 */ 319 319 320 320 static inline void 321 - s3c2410_dma_buffdone(s3c2410_dma_chan_t *chan, s3c2410_dma_buf_t *buf, 322 - s3c2410_dma_buffresult_t result) 321 + s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf, 322 + enum s3c2410_dma_buffresult result) 323 323 { 324 324 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n", 325 325 chan->callback_fn, buf, buf->id, buf->size, result); ··· 334 334 * start a dma channel going 335 335 */ 336 336 337 - static int s3c2410_dma_start(s3c2410_dma_chan_t *chan) 337 + static int s3c2410_dma_start(struct s3c2410_dma_chan *chan) 338 338 { 339 339 unsigned long tmp; 340 340 unsigned long flags; ··· 430 430 */ 431 431 432 432 static int 433 - s3c2410_dma_canload(s3c2410_dma_chan_t *chan) 433 + s3c2410_dma_canload(struct s3c2410_dma_chan *chan) 434 434 { 435 435 if (chan->load_state == S3C2410_DMALOAD_NONE || 436 436 chan->load_state == S3C2410_DMALOAD_1RUNNING) ··· 460 460 int s3c2410_dma_enqueue(unsigned int channel, void *id, 461 461 dma_addr_t data, int size) 462 462 { 463 - s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 464 - s3c2410_dma_buf_t *buf; 463 + struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 464 + struct s3c2410_dma_buf *buf; 465 465 unsigned long flags; 466 466 467 467 check_channel(channel); ··· 540 540 EXPORT_SYMBOL(s3c2410_dma_enqueue); 541 541 542 542 static inline void 543 - s3c2410_dma_freebuf(s3c2410_dma_buf_t *buf) 543 + s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf) 544 544 { 545 545 int magicok = (buf->magic == BUF_MAGIC); 546 546 ··· 560 560 */ 561 561 562 562 static inline void 563 - s3c2410_dma_lastxfer(s3c2410_dma_chan_t *chan) 563 + s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan) 564 564 { 565 565 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n", 566 566 chan->number, chan->load_state); ··· 601 601 static irqreturn_t 602 602 s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs) 603 603 { 604 - s3c2410_dma_chan_t *chan = (s3c2410_dma_chan_t *)devpw; 605 - s3c2410_dma_buf_t *buf; 604 + struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw; 605 + struct s3c2410_dma_buf *buf; 606 606 607 607 buf = chan->curr; 608 608 ··· 731 731 * get control of an dma channel 732 732 */ 733 733 734 - int s3c2410_dma_request(unsigned int channel, s3c2410_dma_client_t *client, 734 + int s3c2410_dma_request(unsigned int channel, struct s3c2410_dma_client *client, 735 735 void *dev) 736 736 { 737 - s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 737 + struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 738 738 unsigned long flags; 739 739 int err; 740 740 ··· 807 807 * allowed to go through. 808 808 */ 809 809 810 - int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *client) 810 + int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client) 811 811 { 812 - s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 812 + struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 813 813 unsigned long flags; 814 814 815 815 check_channel(channel); ··· 846 846 847 847 EXPORT_SYMBOL(s3c2410_dma_free); 848 848 849 - static int s3c2410_dma_dostop(s3c2410_dma_chan_t *chan) 849 + static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan) 850 850 { 851 851 unsigned long tmp; 852 852 unsigned long flags; ··· 880 880 return 0; 881 881 } 882 882 883 - void s3c2410_dma_waitforstop(s3c2410_dma_chan_t *chan) 883 + void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan) 884 884 { 885 885 unsigned long tmp; 886 886 unsigned int timeout = 0x10000; ··· 901 901 * stop the channel, and remove all current and pending transfers 902 902 */ 903 903 904 - static int s3c2410_dma_flush(s3c2410_dma_chan_t *chan) 904 + static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan) 905 905 { 906 - s3c2410_dma_buf_t *buf, *next; 906 + struct s3c2410_dma_buf *buf, *next; 907 907 unsigned long flags; 908 908 909 909 pr_debug("%s: chan %p (%d)\n", __FUNCTION__, chan, chan->number); ··· 958 958 } 959 959 960 960 int 961 - s3c2410_dma_started(s3c2410_dma_chan_t *chan) 961 + s3c2410_dma_started(struct s3c2410_dma_chan *chan) 962 962 { 963 963 unsigned long flags; 964 964 ··· 995 995 } 996 996 997 997 int 998 - s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op) 998 + s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op) 999 999 { 1000 - s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 1000 + struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 1001 1001 1002 1002 check_channel(channel); 1003 1003 ··· 1046 1046 int xferunit, 1047 1047 int dcon) 1048 1048 { 1049 - s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 1049 + struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 1050 1050 1051 1051 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n", 1052 1052 __FUNCTION__, channel, xferunit, dcon); ··· 1086 1086 1087 1087 int s3c2410_dma_setflags(dmach_t channel, unsigned int flags) 1088 1088 { 1089 - s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 1089 + struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 1090 1090 1091 1091 check_channel(channel); 1092 1092 ··· 1106 1106 1107 1107 int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn) 1108 1108 { 1109 - s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 1109 + struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 1110 1110 1111 1111 check_channel(channel); 1112 1112 ··· 1121 1121 1122 1122 int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn) 1123 1123 { 1124 - s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 1124 + struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 1125 1125 1126 1126 check_channel(channel); 1127 1127 ··· 1149 1149 */ 1150 1150 1151 1151 int s3c2410_dma_devconfig(int channel, 1152 - s3c2410_dmasrc_t source, 1152 + enum s3c2410_dmasrc source, 1153 1153 int hwcfg, 1154 1154 unsigned long devaddr) 1155 1155 { 1156 - s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 1156 + struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 1157 1157 1158 1158 check_channel(channel); 1159 1159 ··· 1200 1200 1201 1201 int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst) 1202 1202 { 1203 - s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 1203 + struct s3c2410_dma_chan *chan = &s3c2410_chans[channel]; 1204 1204 1205 1205 check_channel(channel); 1206 1206 ··· 1222 1222 1223 1223 static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state) 1224 1224 { 1225 - s3c2410_dma_chan_t *cp = container_of(dev, s3c2410_dma_chan_t, dev); 1225 + struct s3c2410_dma_chan *cp = container_of(dev, struct s3c2410_dma_chan, dev); 1226 1226 1227 1227 printk(KERN_DEBUG "suspending dma channel %d\n", cp->number); 1228 1228 ··· 1262 1262 1263 1263 static void s3c2410_dma_cache_ctor(void *p, kmem_cache_t *c, unsigned long f) 1264 1264 { 1265 - memset(p, 0, sizeof(s3c2410_dma_buf_t)); 1265 + memset(p, 0, sizeof(struct s3c2410_dma_buf)); 1266 1266 } 1267 1267 1268 1268 ··· 1270 1270 1271 1271 static int __init s3c2410_init_dma(void) 1272 1272 { 1273 - s3c2410_dma_chan_t *cp; 1273 + struct s3c2410_dma_chan *cp; 1274 1274 int channel; 1275 1275 int ret; 1276 1276 ··· 1288 1288 goto err; 1289 1289 } 1290 1290 1291 - dma_kmem = kmem_cache_create("dma_desc", sizeof(s3c2410_dma_buf_t), 0, 1291 + dma_kmem = kmem_cache_create("dma_desc", sizeof(struct s3c2410_dma_buf), 0, 1292 1292 SLAB_HWCACHE_ALIGN, 1293 1293 s3c2410_dma_cache_ctor, NULL); 1294 1294 ··· 1301 1301 for (channel = 0; channel < S3C2410_DMA_CHANNELS; channel++) { 1302 1302 cp = &s3c2410_chans[channel]; 1303 1303 1304 - memset(cp, 0, sizeof(s3c2410_dma_chan_t)); 1304 + memset(cp, 0, sizeof(struct s3c2410_dma_chan)); 1305 1305 1306 1306 /* dma channel irqs are in order.. */ 1307 1307 cp->number = channel;
+26
arch/arm/mm/flush.c
··· 87 87 if (cache_is_vipt_aliasing()) 88 88 flush_pfn_alias(pfn, user_addr); 89 89 } 90 + 91 + void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, 92 + unsigned long uaddr, void *kaddr, 93 + unsigned long len, int write) 94 + { 95 + if (cache_is_vivt()) { 96 + if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { 97 + unsigned long addr = (unsigned long)kaddr; 98 + __cpuc_coherent_kern_range(addr, addr + len); 99 + } 100 + return; 101 + } 102 + 103 + if (cache_is_vipt_aliasing()) { 104 + flush_pfn_alias(page_to_pfn(page), uaddr); 105 + return; 106 + } 107 + 108 + /* VIPT non-aliasing cache */ 109 + if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask) && 110 + vma->vm_flags | VM_EXEC) { 111 + unsigned long addr = (unsigned long)kaddr; 112 + /* only flushing the kernel mapping on non-aliasing VIPT */ 113 + __cpuc_coherent_kern_range(addr, addr + len); 114 + } 115 + } 90 116 #else 91 117 #define flush_pfn_alias(pfn,vaddr) do { } while (0) 92 118 #endif
+2 -8
arch/arm/vfp/vfp.h
··· 156 156 }; 157 157 158 158 extern s32 vfp_get_float(unsigned int reg); 159 - extern void vfp_put_float(unsigned int reg, s32 val); 159 + extern void vfp_put_float(s32 val, unsigned int reg); 160 160 161 161 /* 162 162 * VFP_SINGLE_MANTISSA_BITS - number of bits in the mantissa ··· 267 267 */ 268 268 #define VFP_REG_ZERO 16 269 269 extern u64 vfp_get_double(unsigned int reg); 270 - extern void vfp_put_double(unsigned int reg, u64 val); 270 + extern void vfp_put_double(u64 val, unsigned int reg); 271 271 272 272 #define VFP_DOUBLE_MANTISSA_BITS (52) 273 273 #define VFP_DOUBLE_EXPONENT_BITS (11) ··· 340 340 } 341 341 342 342 u32 vfp_double_normaliseround(int dd, struct vfp_double *vd, u32 fpscr, u32 exceptions, const char *func); 343 - 344 - /* 345 - * System registers 346 - */ 347 - extern u32 vfp_get_sys(unsigned int reg); 348 - extern void vfp_put_sys(unsigned int reg, u32 val); 349 343 350 344 u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand); 351 345
+10 -10
arch/arm/vfp/vfpdouble.c
··· 195 195 s64 d = vfp_double_pack(vd); 196 196 pr_debug("VFP: %s: d(d%d)=%016llx exceptions=%08x\n", func, 197 197 dd, d, exceptions); 198 - vfp_put_double(dd, d); 198 + vfp_put_double(d, dd); 199 199 } 200 200 return exceptions; 201 201 } ··· 250 250 */ 251 251 static u32 vfp_double_fabs(int dd, int unused, int dm, u32 fpscr) 252 252 { 253 - vfp_put_double(dd, vfp_double_packed_abs(vfp_get_double(dm))); 253 + vfp_put_double(vfp_double_packed_abs(vfp_get_double(dm)), dd); 254 254 return 0; 255 255 } 256 256 257 257 static u32 vfp_double_fcpy(int dd, int unused, int dm, u32 fpscr) 258 258 { 259 - vfp_put_double(dd, vfp_get_double(dm)); 259 + vfp_put_double(vfp_get_double(dm), dd); 260 260 return 0; 261 261 } 262 262 263 263 static u32 vfp_double_fneg(int dd, int unused, int dm, u32 fpscr) 264 264 { 265 - vfp_put_double(dd, vfp_double_packed_negate(vfp_get_double(dm))); 265 + vfp_put_double(vfp_double_packed_negate(vfp_get_double(dm)), dd); 266 266 return 0; 267 267 } 268 268 ··· 287 287 vdp = &vfp_double_default_qnan; 288 288 ret = FPSCR_IOC; 289 289 } 290 - vfp_put_double(dd, vfp_double_pack(vdp)); 290 + vfp_put_double(vfp_double_pack(vdp), dd); 291 291 return ret; 292 292 } 293 293 ··· 476 476 return vfp_single_normaliseround(sd, &vsd, fpscr, exceptions, "fcvts"); 477 477 478 478 pack_nan: 479 - vfp_put_float(sd, vfp_single_pack(&vsd)); 479 + vfp_put_float(vfp_single_pack(&vsd), sd); 480 480 return exceptions; 481 481 } 482 482 ··· 573 573 574 574 pr_debug("VFP: ftoui: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions); 575 575 576 - vfp_put_float(sd, d); 576 + vfp_put_float(d, sd); 577 577 578 578 return exceptions; 579 579 } ··· 648 648 649 649 pr_debug("VFP: ftosi: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions); 650 650 651 - vfp_put_float(sd, (s32)d); 651 + vfp_put_float((s32)d, sd); 652 652 653 653 return exceptions; 654 654 } ··· 1084 1084 vdn_nan: 1085 1085 exceptions = vfp_propagate_nan(&vdd, &vdn, &vdm, fpscr); 1086 1086 pack: 1087 - vfp_put_double(dd, vfp_double_pack(&vdd)); 1087 + vfp_put_double(vfp_double_pack(&vdd), dd); 1088 1088 return exceptions; 1089 1089 1090 1090 vdm_nan: ··· 1104 1104 goto pack; 1105 1105 1106 1106 invalid: 1107 - vfp_put_double(dd, vfp_double_pack(&vfp_double_default_qnan)); 1107 + vfp_put_double(vfp_double_pack(&vfp_double_default_qnan), dd); 1108 1108 return FPSCR_IOC; 1109 1109 } 1110 1110
+5 -5
arch/arm/vfp/vfphw.S
··· 178 178 179 179 .globl vfp_put_float 180 180 vfp_put_float: 181 - add pc, pc, r0, lsl #3 181 + add pc, pc, r1, lsl #3 182 182 mov r0, r0 183 183 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 184 - mcr p10, 0, r1, c\dr, c0, 0 @ fmsr r0, s0 184 + mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0 185 185 mov pc, lr 186 - mcr p10, 0, r1, c\dr, c0, 4 @ fmsr r0, s1 186 + mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1 187 187 mov pc, lr 188 188 .endr 189 189 ··· 203 203 204 204 .globl vfp_put_double 205 205 vfp_put_double: 206 - add pc, pc, r0, lsl #3 206 + add pc, pc, r2, lsl #3 207 207 mov r0, r0 208 208 .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 209 - fmdrr d\dr, r1, r2 209 + fmdrr d\dr, r0, r1 210 210 mov pc, lr 211 211 .endr
+10 -10
arch/arm/vfp/vfpsingle.c
··· 200 200 s32 d = vfp_single_pack(vs); 201 201 pr_debug("VFP: %s: d(s%d)=%08x exceptions=%08x\n", func, 202 202 sd, d, exceptions); 203 - vfp_put_float(sd, d); 203 + vfp_put_float(d, sd); 204 204 } 205 205 206 206 return exceptions; ··· 257 257 */ 258 258 static u32 vfp_single_fabs(int sd, int unused, s32 m, u32 fpscr) 259 259 { 260 - vfp_put_float(sd, vfp_single_packed_abs(m)); 260 + vfp_put_float(vfp_single_packed_abs(m), sd); 261 261 return 0; 262 262 } 263 263 264 264 static u32 vfp_single_fcpy(int sd, int unused, s32 m, u32 fpscr) 265 265 { 266 - vfp_put_float(sd, m); 266 + vfp_put_float(m, sd); 267 267 return 0; 268 268 } 269 269 270 270 static u32 vfp_single_fneg(int sd, int unused, s32 m, u32 fpscr) 271 271 { 272 - vfp_put_float(sd, vfp_single_packed_negate(m)); 272 + vfp_put_float(vfp_single_packed_negate(m), sd); 273 273 return 0; 274 274 } 275 275 ··· 333 333 vsp = &vfp_single_default_qnan; 334 334 ret = FPSCR_IOC; 335 335 } 336 - vfp_put_float(sd, vfp_single_pack(vsp)); 336 + vfp_put_float(vfp_single_pack(vsp), sd); 337 337 return ret; 338 338 } 339 339 ··· 517 517 return vfp_double_normaliseround(dd, &vdd, fpscr, exceptions, "fcvtd"); 518 518 519 519 pack_nan: 520 - vfp_put_double(dd, vfp_double_pack(&vdd)); 520 + vfp_put_double(vfp_double_pack(&vdd), dd); 521 521 return exceptions; 522 522 } 523 523 ··· 613 613 614 614 pr_debug("VFP: ftoui: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions); 615 615 616 - vfp_put_float(sd, d); 616 + vfp_put_float(d, sd); 617 617 618 618 return exceptions; 619 619 } ··· 692 692 693 693 pr_debug("VFP: ftosi: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions); 694 694 695 - vfp_put_float(sd, (s32)d); 695 + vfp_put_float((s32)d, sd); 696 696 697 697 return exceptions; 698 698 } ··· 1127 1127 vsn_nan: 1128 1128 exceptions = vfp_propagate_nan(&vsd, &vsn, &vsm, fpscr); 1129 1129 pack: 1130 - vfp_put_float(sd, vfp_single_pack(&vsd)); 1130 + vfp_put_float(vfp_single_pack(&vsd), sd); 1131 1131 return exceptions; 1132 1132 1133 1133 vsm_nan: ··· 1147 1147 goto pack; 1148 1148 1149 1149 invalid: 1150 - vfp_put_float(sd, vfp_single_pack(&vfp_single_default_qnan)); 1150 + vfp_put_float(vfp_single_pack(&vfp_single_default_qnan), sd); 1151 1151 return FPSCR_IOC; 1152 1152 } 1153 1153
+68 -84
include/asm-arm/arch-s3c2410/dma.h
··· 1 - /* linux/include/asm-arm/arch-bast/dma.h 1 + /* linux/include/asm-arm/arch-s3c2410/dma.h 2 2 * 3 - * Copyright (C) 2003,2004 Simtec Electronics 3 + * Copyright (C) 2003,2004,2006 Simtec Electronics 4 4 * Ben Dooks <ben@simtec.co.uk> 5 5 * 6 - * Samsung S3C2410X DMA support 6 + * Samsung S3C241XX DMA support 7 7 * 8 8 * This program is free software; you can redistribute it and/or modify 9 9 * it under the terms of the GNU General Public License version 2 as 10 10 * published by the Free Software Foundation. 11 - * 12 - * Changelog: 13 - * ??-May-2003 BJD Created file 14 - * ??-Jun-2003 BJD Added more dma functionality to go with arch 15 - * 10-Nov-2004 BJD Added sys_device support 16 11 */ 17 12 18 13 #ifndef __ASM_ARCH_DMA_H ··· 16 21 #include <linux/sysdev.h> 17 22 #include "hardware.h" 18 23 19 - 20 24 /* 21 25 * This is the maximum DMA address(physical address) that can be DMAd to. 22 26 * 23 27 */ 24 - #define MAX_DMA_ADDRESS 0x20000000 28 + #define MAX_DMA_ADDRESS 0x40000000 25 29 #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ 26 - 27 30 28 31 /* we have 4 dma channels */ 29 32 #define S3C2410_DMA_CHANNELS (4) 30 33 31 34 /* types */ 32 35 33 - typedef enum { 36 + enum s3c2410_dma_state { 34 37 S3C2410_DMA_IDLE, 35 38 S3C2410_DMA_RUNNING, 36 39 S3C2410_DMA_PAUSED 37 - } s3c2410_dma_state_t; 40 + }; 38 41 39 42 40 - /* s3c2410_dma_loadst_t 43 + /* enum s3c2410_dma_loadst 41 44 * 42 45 * This represents the state of the DMA engine, wrt to the loaded / running 43 46 * transfers. Since we don't have any way of knowing exactly the state of ··· 63 70 * currently running. 64 71 */ 65 72 66 - typedef enum { 73 + enum s3c2410_dma_loadst { 67 74 S3C2410_DMALOAD_NONE, 68 75 S3C2410_DMALOAD_1LOADED, 69 76 S3C2410_DMALOAD_1RUNNING, 70 77 S3C2410_DMALOAD_1LOADED_1RUNNING, 71 - } s3c2410_dma_loadst_t; 78 + }; 72 79 73 - typedef enum { 80 + enum s3c2410_dma_buffresult { 74 81 S3C2410_RES_OK, 75 82 S3C2410_RES_ERR, 76 83 S3C2410_RES_ABORT 77 - } s3c2410_dma_buffresult_t; 78 - 79 - 80 - typedef enum s3c2410_dmasrc_e s3c2410_dmasrc_t; 81 - 82 - enum s3c2410_dmasrc_e { 83 - S3C2410_DMASRC_HW, /* source is memory */ 84 - S3C2410_DMASRC_MEM /* source is hardware */ 85 84 }; 86 85 87 - /* enum s3c2410_chan_op_e 86 + enum s3c2410_dmasrc { 87 + S3C2410_DMASRC_HW, /* source is memory */ 88 + S3C2410_DMASRC_MEM /* source is hardware */ 89 + }; 90 + 91 + /* enum s3c2410_chan_op 88 92 * 89 93 * operation codes passed to the DMA code by the user, and also used 90 94 * to inform the current channel owner of any changes to the system state 91 95 */ 92 96 93 - enum s3c2410_chan_op_e { 97 + enum s3c2410_chan_op { 94 98 S3C2410_DMAOP_START, 95 99 S3C2410_DMAOP_STOP, 96 100 S3C2410_DMAOP_PAUSE, 97 101 S3C2410_DMAOP_RESUME, 98 102 S3C2410_DMAOP_FLUSH, 99 - S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */ 103 + S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */ 100 104 S3C2410_DMAOP_STARTED, /* indicate channel started */ 101 105 }; 102 - 103 - typedef enum s3c2410_chan_op_e s3c2410_chan_op_t; 104 106 105 107 /* flags */ 106 108 ··· 105 117 106 118 /* dma buffer */ 107 119 108 - typedef struct s3c2410_dma_buf_s s3c2410_dma_buf_t; 109 - 110 120 struct s3c2410_dma_client { 111 121 char *name; 112 122 }; 113 - 114 - typedef struct s3c2410_dma_client s3c2410_dma_client_t; 115 123 116 124 /* s3c2410_dma_buf_s 117 125 * ··· 115 131 * buffer. 116 132 */ 117 133 118 - struct s3c2410_dma_buf_s { 119 - s3c2410_dma_buf_t *next; 120 - int magic; /* magic */ 121 - int size; /* buffer size in bytes */ 122 - dma_addr_t data; /* start of DMA data */ 123 - dma_addr_t ptr; /* where the DMA got to [1] */ 124 - void *id; /* client's id */ 134 + struct s3c2410_dma_buf; 135 + struct s3c2410_dma_buf { 136 + struct s3c2410_dma_buf *next; 137 + int magic; /* magic */ 138 + int size; /* buffer size in bytes */ 139 + dma_addr_t data; /* start of DMA data */ 140 + dma_addr_t ptr; /* where the DMA got to [1] */ 141 + void *id; /* client's id */ 125 142 }; 126 143 127 144 /* [1] is this updated for both recv/send modes? */ 128 145 129 - typedef struct s3c2410_dma_chan_s s3c2410_dma_chan_t; 146 + struct s3c2410_dma_chan; 130 147 131 148 /* s3c2410_dma_cbfn_t 132 149 * 133 150 * buffer callback routine type 134 151 */ 135 152 136 - typedef void (*s3c2410_dma_cbfn_t)(s3c2410_dma_chan_t *, void *buf, int size, 137 - s3c2410_dma_buffresult_t result); 153 + typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *, 154 + void *buf, int size, 155 + enum s3c2410_dma_buffresult result); 138 156 139 - typedef int (*s3c2410_dma_opfn_t)(s3c2410_dma_chan_t *, 140 - s3c2410_chan_op_t ); 157 + typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *, 158 + enum s3c2410_chan_op ); 141 159 142 - struct s3c2410_dma_stats_s { 143 - unsigned long loads; 144 - unsigned long timeout_longest; 145 - unsigned long timeout_shortest; 146 - unsigned long timeout_avg; 147 - unsigned long timeout_failed; 160 + struct s3c2410_dma_stats { 161 + unsigned long loads; 162 + unsigned long timeout_longest; 163 + unsigned long timeout_shortest; 164 + unsigned long timeout_avg; 165 + unsigned long timeout_failed; 148 166 }; 149 167 150 - typedef struct s3c2410_dma_stats_s s3c2410_dma_stats_t; 151 - 152 - /* struct s3c2410_dma_chan_s 168 + /* struct s3c2410_dma_chan 153 169 * 154 170 * full state information for each DMA channel 155 171 */ 156 172 157 - struct s3c2410_dma_chan_s { 173 + struct s3c2410_dma_chan { 158 174 /* channel state flags and information */ 159 - unsigned char number; /* number of this dma channel */ 160 - unsigned char in_use; /* channel allocated */ 161 - unsigned char irq_claimed; /* irq claimed for channel */ 162 - unsigned char irq_enabled; /* irq enabled for channel */ 163 - unsigned char xfer_unit; /* size of an transfer */ 175 + unsigned char number; /* number of this dma channel */ 176 + unsigned char in_use; /* channel allocated */ 177 + unsigned char irq_claimed; /* irq claimed for channel */ 178 + unsigned char irq_enabled; /* irq enabled for channel */ 179 + unsigned char xfer_unit; /* size of an transfer */ 164 180 165 181 /* channel state */ 166 182 167 - s3c2410_dma_state_t state; 168 - s3c2410_dma_loadst_t load_state; 169 - s3c2410_dma_client_t *client; 183 + enum s3c2410_dma_state state; 184 + enum s3c2410_dma_loadst load_state; 185 + struct s3c2410_dma_client *client; 170 186 171 187 /* channel configuration */ 172 - s3c2410_dmasrc_t source; 173 - unsigned long dev_addr; 174 - unsigned long load_timeout; 175 - unsigned int flags; /* channel flags */ 188 + enum s3c2410_dmasrc source; 189 + unsigned long dev_addr; 190 + unsigned long load_timeout; 191 + unsigned int flags; /* channel flags */ 176 192 177 193 /* channel's hardware position and configuration */ 178 - void __iomem *regs; /* channels registers */ 179 - void __iomem *addr_reg; /* data address register */ 180 - unsigned int irq; /* channel irq */ 181 - unsigned long dcon; /* default value of DCON */ 194 + void __iomem *regs; /* channels registers */ 195 + void __iomem *addr_reg; /* data address register */ 196 + unsigned int irq; /* channel irq */ 197 + unsigned long dcon; /* default value of DCON */ 182 198 183 199 /* driver handles */ 184 - s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ 185 - s3c2410_dma_opfn_t op_fn; /* channel operation callback */ 200 + s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ 201 + s3c2410_dma_opfn_t op_fn; /* channel op callback */ 186 202 187 203 /* stats gathering */ 188 - s3c2410_dma_stats_t *stats; 189 - s3c2410_dma_stats_t stats_store; 204 + struct s3c2410_dma_stats *stats; 205 + struct s3c2410_dma_stats stats_store; 190 206 191 207 /* buffer list and information */ 192 - s3c2410_dma_buf_t *curr; /* current dma buffer */ 193 - s3c2410_dma_buf_t *next; /* next buffer to load */ 194 - s3c2410_dma_buf_t *end; /* end of queue */ 208 + struct s3c2410_dma_buf *curr; /* current dma buffer */ 209 + struct s3c2410_dma_buf *next; /* next buffer to load */ 210 + struct s3c2410_dma_buf *end; /* end of queue */ 195 211 196 212 /* system device */ 197 213 struct sys_device dev; 198 214 }; 199 215 200 216 /* the currently allocated channel information */ 201 - extern s3c2410_dma_chan_t s3c2410_chans[]; 217 + extern struct s3c2410_dma_chan s3c2410_chans[]; 202 218 203 219 /* note, we don't really use dma_device_t at the moment */ 204 220 typedef unsigned long dma_device_t; ··· 211 227 */ 212 228 213 229 extern int s3c2410_dma_request(dmach_t channel, 214 - s3c2410_dma_client_t *, void *dev); 230 + struct s3c2410_dma_client *, void *dev); 215 231 216 232 217 233 /* s3c2410_dma_ctrl ··· 219 235 * change the state of the dma channel 220 236 */ 221 237 222 - extern int s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op); 238 + extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op); 223 239 224 240 /* s3c2410_dma_setflags 225 241 * ··· 234 250 * free the dma channel (will also abort any outstanding operations) 235 251 */ 236 252 237 - extern int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *); 253 + extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *); 238 254 239 255 /* s3c2410_dma_enqueue 240 256 * ··· 258 274 * configure the device we're talking to 259 275 */ 260 276 261 - extern int s3c2410_dma_devconfig(int channel, s3c2410_dmasrc_t source, 277 + extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source, 262 278 int hwcfg, unsigned long devaddr); 263 279 264 280 /* s3c2410_dma_getposition
+15 -3
include/asm-arm/cacheflush.h
··· 247 247 */ 248 248 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ 249 249 do { \ 250 - flush_cache_page(vma, vaddr, page_to_pfn(page));\ 251 250 memcpy(dst, src, len); \ 252 - flush_dcache_page(page); \ 251 + flush_ptrace_access(vma, page, vaddr, dst, len, 1);\ 253 252 } while (0) 254 253 255 254 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 256 255 do { \ 257 - flush_cache_page(vma, vaddr, page_to_pfn(page));\ 258 256 memcpy(dst, src, len); \ 259 257 } while (0) 260 258 ··· 283 285 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); 284 286 } 285 287 } 288 + 289 + static inline void 290 + flush_ptrace_access(struct vm_area_struct *vma, struct page *page, 291 + unsigned long uaddr, void *kaddr, 292 + unsigned long len, int write) 293 + { 294 + if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { 295 + unsigned long addr = (unsigned long)kaddr; 296 + __cpuc_coherent_kern_range(addr, addr + len); 297 + } 298 + } 286 299 #else 287 300 extern void flush_cache_mm(struct mm_struct *mm); 288 301 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 289 302 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn); 303 + extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, 304 + unsigned long uaddr, void *kaddr, 305 + unsigned long len, int write); 290 306 #endif 291 307 292 308 /*
+15 -1
include/asm-arm/spinlock.h
··· 199 199 : "cc"); 200 200 } 201 201 202 - #define __raw_read_trylock(lock) generic__raw_read_trylock(lock) 202 + static inline int __raw_read_trylock(raw_rwlock_t *rw) 203 + { 204 + unsigned long tmp tmp2 = 1; 205 + 206 + __asm__ __volatile__( 207 + "1: ldrex %0, [%2]\n" 208 + " adds %0, %0, #1\n" 209 + " strexpl %1, %0, [%2]\n" 210 + : "=&r" (tmp), "+r" (tmp2) 211 + : "r" (&rw->lock) 212 + : "cc"); 213 + 214 + smp_mb(); 215 + return tmp2 == 0; 216 + } 203 217 204 218 /* read_can_lock - would read_trylock() succeed? */ 205 219 #define __raw_read_can_lock(x) ((x)->lock < 0x80000000)