Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'octeopntx2-LMTST-regions'
Geetha sowjanya says:
====================
Dynamic LMTST region setup
This patch series allows RVU PF/VF to allocate memory for
LMTST operations instead of using memory reserved by firmware
which is mapped as device memory.
The LMTST mapping table contains the RVU PF/VF LMTST memory base
address entries. This table is used by hardware for LMTST operations.
Patch1 introduces new mailbox message to update the LMTST table with
the new allocated memory address.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
+284
-77
+10
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+10
drivers/net/ethernet/marvell/octeontx2/af/mbox.h
···
134
134
M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
135
135
M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
136
136
M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
137
+
M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
138
+
msg_rsp) \
137
139
M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \
138
140
/* CGX mbox IDs (range 0x200 - 0x3FF) */ \
139
141
M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
···
1278
1276
#define RESET_VF_PERM BIT_ULL(0)
1279
1277
#define VF_TRUSTED BIT_ULL(1)
1280
1278
u64 flags;
1279
+
};
1280
+
1281
+
struct lmtst_tbl_setup_req {
1282
+
struct mbox_msghdr hdr;
1283
+
u16 base_pcifunc;
1284
+
u8 use_local_lmt_region;
1285
+
u64 lmt_iova;
1286
+
u64 rsvd[4];
1281
1287
};
1282
1288
1283
1289
/* CPT mailbox error codes
+1
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
+1
drivers/net/ethernet/marvell/octeontx2/af/rvu.c
···
2333
2333
rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW);
2334
2334
rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO);
2335
2335
rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA);
2336
+
rvu_reset_lmt_map_tbl(rvu, pcifunc);
2336
2337
rvu_detach_rsrcs(rvu, NULL, pcifunc);
2337
2338
mutex_unlock(&rvu->flr_lock);
2338
2339
}
+4
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+4
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
···
243
243
u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
244
244
u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */
245
245
u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */
246
+
u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/
246
247
unsigned long flags;
247
248
};
248
249
···
754
753
/* CN10K RVU */
755
754
int rvu_set_channels_base(struct rvu *rvu);
756
755
void rvu_program_channels(struct rvu *rvu);
756
+
757
+
/* CN10K RVU - LMT*/
758
+
void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);
757
759
758
760
#ifdef CONFIG_DEBUG_FS
759
761
void rvu_dbg_init(struct rvu *rvu);
+200
drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
+200
drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
···
10
10
#include "cgx.h"
11
11
#include "rvu_reg.h"
12
12
13
+
/* RVU LMTST */
14
+
#define LMT_TBL_OP_READ 0
15
+
#define LMT_TBL_OP_WRITE 1
16
+
#define LMT_MAP_TABLE_SIZE (128 * 1024)
17
+
#define LMT_MAPTBL_ENTRY_SIZE 16
18
+
19
+
/* Function to perform operations (read/write) on lmtst map table */
20
+
static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val,
21
+
int lmt_tbl_op)
22
+
{
23
+
void __iomem *lmt_map_base;
24
+
u64 tbl_base;
25
+
26
+
tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE);
27
+
28
+
lmt_map_base = ioremap_wc(tbl_base, LMT_MAP_TABLE_SIZE);
29
+
if (!lmt_map_base) {
30
+
dev_err(rvu->dev, "Failed to setup lmt map table mapping!!\n");
31
+
return -ENOMEM;
32
+
}
33
+
34
+
if (lmt_tbl_op == LMT_TBL_OP_READ) {
35
+
*val = readq(lmt_map_base + index);
36
+
} else {
37
+
writeq((*val), (lmt_map_base + index));
38
+
/* Flushing the AP interceptor cache to make APR_LMT_MAP_ENTRY_S
39
+
* changes effective. Write 1 for flush and read is being used as a
40
+
* barrier and sets up a data dependency. Write to 0 after a write
41
+
* to 1 to complete the flush.
42
+
*/
43
+
rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CTL, BIT_ULL(0));
44
+
rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CTL);
45
+
rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CTL, 0x00);
46
+
}
47
+
48
+
iounmap(lmt_map_base);
49
+
return 0;
50
+
}
51
+
52
+
static u32 rvu_get_lmtst_tbl_index(struct rvu *rvu, u16 pcifunc)
53
+
{
54
+
return ((rvu_get_pf(pcifunc) * rvu->hw->total_vfs) +
55
+
(pcifunc & RVU_PFVF_FUNC_MASK)) * LMT_MAPTBL_ENTRY_SIZE;
56
+
}
57
+
58
+
static int rvu_get_lmtaddr(struct rvu *rvu, u16 pcifunc,
59
+
u64 iova, u64 *lmt_addr)
60
+
{
61
+
u64 pa, val, pf;
62
+
int err;
63
+
64
+
if (!iova) {
65
+
dev_err(rvu->dev, "%s Requested Null address for transulation\n", __func__);
66
+
return -EINVAL;
67
+
}
68
+
69
+
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_REQ, iova);
70
+
pf = rvu_get_pf(pcifunc) & 0x1F;
71
+
val = BIT_ULL(63) | BIT_ULL(14) | BIT_ULL(13) | pf << 8 |
72
+
((pcifunc & RVU_PFVF_FUNC_MASK) & 0xFF);
73
+
rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TXN_REQ, val);
74
+
75
+
err = rvu_poll_reg(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_RSP_STS, BIT_ULL(0), false);
76
+
if (err) {
77
+
dev_err(rvu->dev, "%s LMTLINE iova transulation failed\n", __func__);
78
+
return err;
79
+
}
80
+
val = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_RSP_STS);
81
+
if (val & ~0x1ULL) {
82
+
dev_err(rvu->dev, "%s LMTLINE iova transulation failed err:%llx\n", __func__, val);
83
+
return -EIO;
84
+
}
85
+
/* PA[51:12] = RVU_AF_SMMU_TLN_FLIT1[60:21]
86
+
* PA[11:0] = IOVA[11:0]
87
+
*/
88
+
pa = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TLN_FLIT1) >> 21;
89
+
pa &= GENMASK_ULL(39, 0);
90
+
*lmt_addr = (pa << 12) | (iova & 0xFFF);
91
+
92
+
return 0;
93
+
}
94
+
95
+
static int rvu_update_lmtaddr(struct rvu *rvu, u16 pcifunc, u64 lmt_addr)
96
+
{
97
+
struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
98
+
u32 tbl_idx;
99
+
int err = 0;
100
+
u64 val;
101
+
102
+
/* Read the current lmt addr of pcifunc */
103
+
tbl_idx = rvu_get_lmtst_tbl_index(rvu, pcifunc);
104
+
err = lmtst_map_table_ops(rvu, tbl_idx, &val, LMT_TBL_OP_READ);
105
+
if (err) {
106
+
dev_err(rvu->dev,
107
+
"Failed to read LMT map table: index 0x%x err %d\n",
108
+
tbl_idx, err);
109
+
return err;
110
+
}
111
+
112
+
/* Storing the seondary's lmt base address as this needs to be
113
+
* reverted in FLR. Also making sure this default value doesn't
114
+
* get overwritten on multiple calls to this mailbox.
115
+
*/
116
+
if (!pfvf->lmt_base_addr)
117
+
pfvf->lmt_base_addr = val;
118
+
119
+
/* Update the LMT table with new addr */
120
+
err = lmtst_map_table_ops(rvu, tbl_idx, &lmt_addr, LMT_TBL_OP_WRITE);
121
+
if (err) {
122
+
dev_err(rvu->dev,
123
+
"Failed to update LMT map table: index 0x%x err %d\n",
124
+
tbl_idx, err);
125
+
return err;
126
+
}
127
+
return 0;
128
+
}
129
+
130
+
int rvu_mbox_handler_lmtst_tbl_setup(struct rvu *rvu,
131
+
struct lmtst_tbl_setup_req *req,
132
+
struct msg_rsp *rsp)
133
+
{
134
+
u64 lmt_addr, val;
135
+
u32 pri_tbl_idx;
136
+
int err = 0;
137
+
138
+
/* Check if PF_FUNC wants to use it's own local memory as LMTLINE
139
+
* region, if so, convert that IOVA to physical address and
140
+
* populate LMT table with that address
141
+
*/
142
+
if (req->use_local_lmt_region) {
143
+
err = rvu_get_lmtaddr(rvu, req->hdr.pcifunc,
144
+
req->lmt_iova, &lmt_addr);
145
+
if (err < 0)
146
+
return err;
147
+
148
+
/* Update the lmt addr for this PFFUNC in the LMT table */
149
+
err = rvu_update_lmtaddr(rvu, req->hdr.pcifunc, lmt_addr);
150
+
if (err)
151
+
return err;
152
+
}
153
+
154
+
/* Reconfiguring lmtst map table in lmt region shared mode i.e. make
155
+
* multiple PF_FUNCs to share an LMTLINE region, so primary/base
156
+
* pcifunc (which is passed as an argument to mailbox) is the one
157
+
* whose lmt base address will be shared among other secondary
158
+
* pcifunc (will be the one who is calling this mailbox).
159
+
*/
160
+
if (req->base_pcifunc) {
161
+
/* Calculating the LMT table index equivalent to primary
162
+
* pcifunc.
163
+
*/
164
+
pri_tbl_idx = rvu_get_lmtst_tbl_index(rvu, req->base_pcifunc);
165
+
166
+
/* Read the base lmt addr of the primary pcifunc */
167
+
err = lmtst_map_table_ops(rvu, pri_tbl_idx, &val,
168
+
LMT_TBL_OP_READ);
169
+
if (err) {
170
+
dev_err(rvu->dev,
171
+
"Failed to read LMT map table: index 0x%x err %d\n",
172
+
pri_tbl_idx, err);
173
+
return err;
174
+
}
175
+
176
+
/* Update the base lmt addr of secondary with primary's base
177
+
* lmt addr.
178
+
*/
179
+
err = rvu_update_lmtaddr(rvu, req->hdr.pcifunc, val);
180
+
if (err)
181
+
return err;
182
+
}
183
+
184
+
return 0;
185
+
}
186
+
187
+
/* Resetting the lmtst map table to original base addresses */
188
+
void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc)
189
+
{
190
+
struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
191
+
u32 tbl_idx;
192
+
int err;
193
+
194
+
if (is_rvu_otx2(rvu))
195
+
return;
196
+
197
+
if (pfvf->lmt_base_addr) {
198
+
/* This corresponds to lmt map table index */
199
+
tbl_idx = rvu_get_lmtst_tbl_index(rvu, pcifunc);
200
+
/* Reverting back original lmt base addr for respective
201
+
* pcifunc.
202
+
*/
203
+
err = lmtst_map_table_ops(rvu, tbl_idx, &pfvf->lmt_base_addr,
204
+
LMT_TBL_OP_WRITE);
205
+
if (err)
206
+
dev_err(rvu->dev,
207
+
"Failed to update LMT map table: index 0x%x err %d\n",
208
+
tbl_idx, err);
209
+
pfvf->lmt_base_addr = 0;
210
+
}
211
+
}
212
+
13
213
int rvu_set_channels_base(struct rvu *rvu)
14
214
{
15
215
struct rvu_hwinfo *hw = rvu->hw;
+10
drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
+10
drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
···
49
49
#define RVU_AF_PFX_VF_BAR4_ADDR (0x5400 | (a) << 4)
50
50
#define RVU_AF_PFX_VF_BAR4_CFG (0x5600 | (a) << 4)
51
51
#define RVU_AF_PFX_LMTLINE_ADDR (0x5800 | (a) << 4)
52
+
#define RVU_AF_SMMU_ADDR_REQ (0x6000)
53
+
#define RVU_AF_SMMU_TXN_REQ (0x6008)
54
+
#define RVU_AF_SMMU_ADDR_RSP_STS (0x6010)
55
+
#define RVU_AF_SMMU_ADDR_TLN (0x6018)
56
+
#define RVU_AF_SMMU_TLN_FLIT1 (0x6030)
52
57
53
58
/* Admin function's privileged PF/VF registers */
54
59
#define RVU_PRIV_CONST (0x8000000)
···
696
691
#define LBK_LINK_CFG_RANGE_MASK GENMASK_ULL(19, 16)
697
692
#define LBK_LINK_CFG_ID_MASK GENMASK_ULL(11, 6)
698
693
#define LBK_LINK_CFG_BASE_MASK GENMASK_ULL(5, 0)
694
+
695
+
/* APR */
696
+
#define APR_AF_LMT_CFG (0x000ull)
697
+
#define APR_AF_LMT_MAP_BASE (0x008ull)
698
+
#define APR_AF_LMT_CTL (0x010ull)
699
699
700
700
#endif /* RVU_REG_H */
+2
-1
drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
+2
-1
drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
+38
-55
drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c
+38
-55
drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c
···
22
22
.refill_pool_ptrs = cn10k_refill_pool_ptrs,
23
23
};
24
24
25
-
int cn10k_pf_lmtst_init(struct otx2_nic *pf)
25
+
int cn10k_lmtst_init(struct otx2_nic *pfvf)
26
26
{
27
-
int size, num_lines;
28
-
u64 base;
29
27
30
-
if (!test_bit(CN10K_LMTST, &pf->hw.cap_flag)) {
31
-
pf->hw_ops = &otx2_hw_ops;
28
+
struct lmtst_tbl_setup_req *req;
29
+
int qcount, err;
30
+
31
+
if (!test_bit(CN10K_LMTST, &pfvf->hw.cap_flag)) {
32
+
pfvf->hw_ops = &otx2_hw_ops;
32
33
return 0;
33
34
}
34
35
35
-
pf->hw_ops = &cn10k_hw_ops;
36
-
base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) +
37
-
(MBOX_SIZE * (pf->total_vfs + 1));
36
+
pfvf->hw_ops = &cn10k_hw_ops;
37
+
qcount = pfvf->hw.max_queues;
38
+
/* LMTST lines allocation
39
+
* qcount = num_online_cpus();
40
+
* NPA = TX + RX + XDP.
41
+
* NIX = TX * 32 (For Burst SQE flush).
42
+
*/
43
+
pfvf->tot_lmt_lines = (qcount * 3) + (qcount * 32);
44
+
pfvf->npa_lmt_lines = qcount * 3;
45
+
pfvf->nix_lmt_size = LMT_BURST_SIZE * LMT_LINE_SIZE;
38
46
39
-
size = pci_resource_len(pf->pdev, PCI_MBOX_BAR_NUM) -
40
-
(MBOX_SIZE * (pf->total_vfs + 1));
41
-
42
-
pf->hw.lmt_base = ioremap(base, size);
43
-
44
-
if (!pf->hw.lmt_base) {
45
-
dev_err(pf->dev, "Unable to map PF LMTST region\n");
47
+
mutex_lock(&pfvf->mbox.lock);
48
+
req = otx2_mbox_alloc_msg_lmtst_tbl_setup(&pfvf->mbox);
49
+
if (!req) {
50
+
mutex_unlock(&pfvf->mbox.lock);
46
51
return -ENOMEM;
47
52
}
48
53
49
-
/* FIXME: Get the num of LMTST lines from LMT table */
50
-
pf->tot_lmt_lines = size / LMT_LINE_SIZE;
51
-
num_lines = (pf->tot_lmt_lines - NIX_LMTID_BASE) /
52
-
pf->hw.tx_queues;
53
-
/* Number of LMT lines per SQ queues */
54
-
pf->nix_lmt_lines = num_lines > 32 ? 32 : num_lines;
54
+
req->use_local_lmt_region = true;
55
55
56
-
pf->nix_lmt_size = pf->nix_lmt_lines * LMT_LINE_SIZE;
56
+
err = qmem_alloc(pfvf->dev, &pfvf->dync_lmt, pfvf->tot_lmt_lines,
57
+
LMT_LINE_SIZE);
58
+
if (err) {
59
+
mutex_unlock(&pfvf->mbox.lock);
60
+
return err;
61
+
}
62
+
pfvf->hw.lmt_base = (u64 *)pfvf->dync_lmt->base;
63
+
req->lmt_iova = (u64)pfvf->dync_lmt->iova;
64
+
65
+
err = otx2_sync_mbox_msg(&pfvf->mbox);
66
+
mutex_unlock(&pfvf->mbox.lock);
67
+
57
68
return 0;
58
69
}
59
-
60
-
int cn10k_vf_lmtst_init(struct otx2_nic *vf)
61
-
{
62
-
int size, num_lines;
63
-
64
-
if (!test_bit(CN10K_LMTST, &vf->hw.cap_flag)) {
65
-
vf->hw_ops = &otx2_hw_ops;
66
-
return 0;
67
-
}
68
-
69
-
vf->hw_ops = &cn10k_hw_ops;
70
-
size = pci_resource_len(vf->pdev, PCI_MBOX_BAR_NUM);
71
-
vf->hw.lmt_base = ioremap_wc(pci_resource_start(vf->pdev,
72
-
PCI_MBOX_BAR_NUM),
73
-
size);
74
-
if (!vf->hw.lmt_base) {
75
-
dev_err(vf->dev, "Unable to map VF LMTST region\n");
76
-
return -ENOMEM;
77
-
}
78
-
79
-
vf->tot_lmt_lines = size / LMT_LINE_SIZE;
80
-
/* LMTST lines per SQ */
81
-
num_lines = (vf->tot_lmt_lines - NIX_LMTID_BASE) /
82
-
vf->hw.tx_queues;
83
-
vf->nix_lmt_lines = num_lines > 32 ? 32 : num_lines;
84
-
vf->nix_lmt_size = vf->nix_lmt_lines * LMT_LINE_SIZE;
85
-
return 0;
86
-
}
87
-
EXPORT_SYMBOL(cn10k_vf_lmtst_init);
70
+
EXPORT_SYMBOL(cn10k_lmtst_init);
88
71
89
72
int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura)
90
73
{
···
76
93
struct otx2_snd_queue *sq;
77
94
78
95
sq = &pfvf->qset.sq[qidx];
79
-
sq->lmt_addr = (__force u64 *)((u64)pfvf->hw.nix_lmt_base +
96
+
sq->lmt_addr = (u64 *)((u64)pfvf->hw.nix_lmt_base +
80
97
(qidx * pfvf->nix_lmt_size));
98
+
99
+
sq->lmt_id = pfvf->npa_lmt_lines + (qidx * LMT_BURST_SIZE);
81
100
82
101
/* Get memory to put this msg */
83
102
aq = otx2_mbox_alloc_msg_nix_cn10k_aq_enq(&pfvf->mbox);
···
143
158
144
159
void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx)
145
160
{
146
-
struct otx2_nic *pfvf = dev;
147
-
int lmt_id = NIX_LMTID_BASE + (qidx * pfvf->nix_lmt_lines);
148
161
u64 val = 0, tar_addr = 0;
149
162
150
163
/* FIXME: val[0:10] LMT_ID.
151
164
* [12:15] no of LMTST - 1 in the burst.
152
165
* [19:63] data size of each LMTST in the burst except first.
153
166
*/
154
-
val = (lmt_id & 0x7FF);
167
+
val = (sq->lmt_id & 0x7FF);
155
168
/* Target address for LMTST flush tells HW how many 128bit
156
169
* words are present.
157
170
* tar_addr[6:4] size of first LMTST - 1 in units of 128b.
+1
-2
drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h
+1
-2
drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h
···
12
12
void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
13
13
void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx);
14
14
int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);
15
-
int cn10k_pf_lmtst_init(struct otx2_nic *pf);
16
-
int cn10k_vf_lmtst_init(struct otx2_nic *vf);
15
+
int cn10k_lmtst_init(struct otx2_nic *pfvf);
17
16
int cn10k_free_all_ipolicers(struct otx2_nic *pfvf);
18
17
int cn10k_alloc_matchall_ipolicer(struct otx2_nic *pfvf);
19
18
int cn10k_free_matchall_ipolicer(struct otx2_nic *pfvf);
+4
-3
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
+4
-3
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
···
218
218
unsigned long cap_flag;
219
219
220
220
#define LMT_LINE_SIZE 128
221
-
#define NIX_LMTID_BASE 72 /* RX + TX + XDP */
222
-
void __iomem *lmt_base;
221
+
#define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */
222
+
u64 *lmt_base;
223
223
u64 *npa_lmt_base;
224
224
u64 *nix_lmt_base;
225
225
};
···
363
363
/* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */
364
364
int nix_blkaddr;
365
365
/* LMTST Lines info */
366
+
struct qmem *dync_lmt;
366
367
u16 tot_lmt_lines;
367
-
u16 nix_lmt_lines;
368
+
u16 npa_lmt_lines;
368
369
u32 nix_lmt_size;
369
370
370
371
struct otx2_ptp *ptp;
+8
-9
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
+8
-9
drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c
···
1533
1533
1534
1534
if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) {
1535
1535
/* Reserve LMT lines for NPA AURA batch free */
1536
-
pf->hw.npa_lmt_base = (__force u64 *)pf->hw.lmt_base;
1536
+
pf->hw.npa_lmt_base = pf->hw.lmt_base;
1537
1537
/* Reserve LMT lines for NIX TX */
1538
-
pf->hw.nix_lmt_base = (__force u64 *)((u64)pf->hw.npa_lmt_base +
1539
-
(NIX_LMTID_BASE * LMT_LINE_SIZE));
1538
+
pf->hw.nix_lmt_base = (u64 *)((u64)pf->hw.npa_lmt_base +
1539
+
(pf->npa_lmt_lines * LMT_LINE_SIZE));
1540
1540
}
1541
1541
1542
1542
err = otx2_init_hw_resources(pf);
···
2526
2526
if (err)
2527
2527
goto err_detach_rsrc;
2528
2528
2529
-
err = cn10k_pf_lmtst_init(pf);
2529
+
err = cn10k_lmtst_init(pf);
2530
2530
if (err)
2531
2531
goto err_detach_rsrc;
2532
2532
···
2630
2630
err_ptp_destroy:
2631
2631
otx2_ptp_destroy(pf);
2632
2632
err_detach_rsrc:
2633
-
if (hw->lmt_base)
2634
-
iounmap(hw->lmt_base);
2633
+
if (test_bit(CN10K_LMTST, &pf->hw.cap_flag))
2634
+
qmem_free(pf->dev, pf->dync_lmt);
2635
2635
otx2_detach_resources(&pf->mbox);
2636
2636
err_disable_mbox_intr:
2637
2637
otx2_disable_mbox_intr(pf);
···
2772
2772
otx2_mcam_flow_del(pf);
2773
2773
otx2_shutdown_tc(pf);
2774
2774
otx2_detach_resources(&pf->mbox);
2775
-
if (pf->hw.lmt_base)
2776
-
iounmap(pf->hw.lmt_base);
2777
-
2775
+
if (test_bit(CN10K_LMTST, &pf->hw.cap_flag))
2776
+
qmem_free(pf->dev, pf->dync_lmt);
2778
2777
otx2_disable_mbox_intr(pf);
2779
2778
otx2_pfaf_mbox_destroy(pf);
2780
2779
pci_free_irq_vectors(pf->pdev);
+1
drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h
+1
drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h
+5
-7
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
+5
-7
drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c
···
609
609
if (err)
610
610
goto err_detach_rsrc;
611
611
612
-
err = cn10k_vf_lmtst_init(vf);
612
+
err = cn10k_lmtst_init(vf);
613
613
if (err)
614
614
goto err_detach_rsrc;
615
615
···
667
667
err_unreg_netdev:
668
668
unregister_netdev(netdev);
669
669
err_detach_rsrc:
670
-
if (hw->lmt_base)
671
-
iounmap(hw->lmt_base);
670
+
if (test_bit(CN10K_LMTST, &vf->hw.cap_flag))
671
+
qmem_free(vf->dev, vf->dync_lmt);
672
672
otx2_detach_resources(&vf->mbox);
673
673
err_disable_mbox_intr:
674
674
otx2vf_disable_mbox_intr(vf);
···
700
700
destroy_workqueue(vf->otx2_wq);
701
701
otx2vf_disable_mbox_intr(vf);
702
702
otx2_detach_resources(&vf->mbox);
703
-
704
-
if (vf->hw.lmt_base)
705
-
iounmap(vf->hw.lmt_base);
706
-
703
+
if (test_bit(CN10K_LMTST, &vf->hw.cap_flag))
704
+
qmem_free(vf->dev, vf->dync_lmt);
707
705
otx2vf_vfaf_mbox_destroy(vf);
708
706
pci_free_irq_vectors(vf->pdev);
709
707
pci_set_drvdata(pdev, NULL);