Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle:
"More 3.18 fixes for MIPS:
- backtraces were not quite working on on 64-bit kernels
- loongson needs a different cache coherency setting
- Loongson 3 is a MIPS64 R2 version but due to erratum we treat is an
older architecture revision.
- fix build errors due to undefined references to __node_distances
for certain configurations.
- fix instruction decodig in the jump label code.
- for certain configurations copy_{from,to}_user destroy the content
of $3 so that register needs to be marked as clobbed by the calling
code.
- Hardware Table Walker fixes.
- fill the delay slot of the last instruction of memcpy otherwise
whatever ends up there randomly might have undesirable effects.
- ensure get_user/__get_user always zero the variable to be read even
in case of an error"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: jump_label.c: Handle the microMIPS J instruction encoding
MIPS: jump_label.c: Correct the span of the J instruction
MIPS: Zero variable read by get_user / __get_user in case of an error.
MIPS: lib: memcpy: Restore NOP on delay slot before returning to caller
MIPS: tlb-r4k: Add missing HTW stop/start sequences
MIPS: asm: uaccess: Add v1 register to clobber list on EVA
MIPS: oprofile: Fix backtrace on 64-bit kernel
MIPS: Loongson: Set Loongson-3's ISA level to MIPS64R1
MIPS: Loongson: Fix the write-combine CCA value setting
MIPS: IP27: Fix __node_distances undefined error
MIPS: Loongson3: Fix __node_distances undefined error
+60
-20
+7
-1
arch/mips/include/asm/jump_label.h
+7
-1
arch/mips/include/asm/jump_label.h
···
20
20
#define WORD_INSN ".word"
21
21
#endif
22
22
23
+
#ifdef CONFIG_CPU_MICROMIPS
24
+
#define NOP_INSN "nop32"
25
+
#else
26
+
#define NOP_INSN "nop"
27
+
#endif
28
+
23
29
static __always_inline bool arch_static_branch(struct static_key *key)
24
30
{
25
-
asm_volatile_goto("1:\tnop\n\t"
31
+
asm_volatile_goto("1:\t" NOP_INSN "\n\t"
26
32
"nop\n\t"
27
33
".pushsection __jump_table, \"aw\"\n\t"
28
34
WORD_INSN " 1b, %l[l_yes], %0\n\t"
-2
arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
-2
arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
···
41
41
#define cpu_has_mcheck 0
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#define cpu_has_mdmx 0
43
43
#define cpu_has_mips16 0
44
-
#define cpu_has_mips32r1 0
45
44
#define cpu_has_mips32r2 0
46
45
#define cpu_has_mips3d 0
47
-
#define cpu_has_mips64r1 0
48
46
#define cpu_has_mips64r2 0
49
47
#define cpu_has_mipsmt 0
50
48
#define cpu_has_prefetch 0
+8
-4
arch/mips/include/asm/uaccess.h
+8
-4
arch/mips/include/asm/uaccess.h
···
301
301
__get_kernel_common((x), size, __gu_ptr); \
302
302
else \
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__get_user_common((x), size, __gu_ptr); \
304
-
} \
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+
} else \
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+
(x) = 0; \
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\
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__gu_err; \
307
308
})
···
317
316
" .insn \n" \
318
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" .section .fixup,\"ax\" \n" \
319
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"3: li %0, %4 \n" \
319
+
" move %1, $0 \n" \
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" j 2b \n" \
321
321
" .previous \n" \
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" .section __ex_table,\"a\" \n" \
···
632
630
" .insn \n" \
633
631
" .section .fixup,\"ax\" \n" \
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"3: li %0, %4 \n" \
633
+
" move %1, $0 \n" \
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" j 2b \n" \
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" .previous \n" \
637
636
" .section __ex_table,\"a\" \n" \
···
776
773
"jal\t" #destination "\n\t"
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#endif
778
775
779
-
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
780
-
#define DADDI_SCRATCH "$0"
781
-
#else
776
+
#if defined(CONFIG_CPU_DADDI_WORKAROUNDS) || (defined(CONFIG_EVA) && \
777
+
defined(CONFIG_CPU_HAS_PREFETCH))
782
778
#define DADDI_SCRATCH "$3"
779
+
#else
780
+
#define DADDI_SCRATCH "$0"
783
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#endif
784
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785
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extern size_t __copy_user(void *__to, const void *__from, size_t __n);
+5
-2
arch/mips/kernel/cpu-probe.c
+5
-2
arch/mips/kernel/cpu-probe.c
···
757
757
c->cputype = CPU_LOONGSON2;
758
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__cpu_name[cpu] = "ICT Loongson-2";
759
759
set_elf_platform(cpu, "loongson2e");
760
+
set_isa(c, MIPS_CPU_ISA_III);
760
761
break;
761
762
case PRID_REV_LOONGSON2F:
762
763
c->cputype = CPU_LOONGSON2;
763
764
__cpu_name[cpu] = "ICT Loongson-2";
764
765
set_elf_platform(cpu, "loongson2f");
766
+
set_isa(c, MIPS_CPU_ISA_III);
765
767
break;
766
768
case PRID_REV_LOONGSON3A:
767
769
c->cputype = CPU_LOONGSON3;
768
-
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
769
770
__cpu_name[cpu] = "ICT Loongson-3";
770
771
set_elf_platform(cpu, "loongson3a");
772
+
set_isa(c, MIPS_CPU_ISA_M64R1);
771
773
break;
772
774
case PRID_REV_LOONGSON3B_R1:
773
775
case PRID_REV_LOONGSON3B_R2:
774
776
c->cputype = CPU_LOONGSON3;
775
777
__cpu_name[cpu] = "ICT Loongson-3";
776
778
set_elf_platform(cpu, "loongson3b");
779
+
set_isa(c, MIPS_CPU_ISA_M64R1);
777
780
break;
778
781
}
779
782
780
-
set_isa(c, MIPS_CPU_ISA_III);
781
783
c->options = R4K_OPTS |
782
784
MIPS_CPU_FPU | MIPS_CPU_LLSC |
783
785
MIPS_CPU_32FPR;
784
786
c->tlbsize = 64;
787
+
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
785
788
break;
786
789
case PRID_IMP_LOONGSON_32: /* Loongson-1 */
787
790
decode_configs(c);
+32
-10
arch/mips/kernel/jump_label.c
+32
-10
arch/mips/kernel/jump_label.c
···
18
18
19
19
#ifdef HAVE_JUMP_LABEL
20
20
21
-
#define J_RANGE_MASK ((1ul << 28) - 1)
21
+
/*
22
+
* Define parameters for the standard MIPS and the microMIPS jump
23
+
* instruction encoding respectively:
24
+
*
25
+
* - the ISA bit of the target, either 0 or 1 respectively,
26
+
*
27
+
* - the amount the jump target address is shifted right to fit in the
28
+
* immediate field of the machine instruction, either 2 or 1,
29
+
*
30
+
* - the mask determining the size of the jump region relative to the
31
+
* delay-slot instruction, either 256MB or 128MB,
32
+
*
33
+
* - the jump target alignment, either 4 or 2 bytes.
34
+
*/
35
+
#define J_ISA_BIT IS_ENABLED(CONFIG_CPU_MICROMIPS)
36
+
#define J_RANGE_SHIFT (2 - J_ISA_BIT)
37
+
#define J_RANGE_MASK ((1ul << (26 + J_RANGE_SHIFT)) - 1)
38
+
#define J_ALIGN_MASK ((1ul << J_RANGE_SHIFT) - 1)
22
39
23
40
void arch_jump_label_transform(struct jump_entry *e,
24
41
enum jump_label_type type)
25
42
{
43
+
union mips_instruction *insn_p;
26
44
union mips_instruction insn;
27
-
union mips_instruction *insn_p =
28
-
(union mips_instruction *)(unsigned long)e->code;
29
45
30
-
/* Jump only works within a 256MB aligned region. */
31
-
BUG_ON((e->target & ~J_RANGE_MASK) != (e->code & ~J_RANGE_MASK));
46
+
insn_p = (union mips_instruction *)msk_isa16_mode(e->code);
32
47
33
-
/* Target must have 4 byte alignment. */
34
-
BUG_ON((e->target & 3) != 0);
48
+
/* Jump only works within an aligned region its delay slot is in. */
49
+
BUG_ON((e->target & ~J_RANGE_MASK) != ((e->code + 4) & ~J_RANGE_MASK));
50
+
51
+
/* Target must have the right alignment and ISA must be preserved. */
52
+
BUG_ON((e->target & J_ALIGN_MASK) != J_ISA_BIT);
35
53
36
54
if (type == JUMP_LABEL_ENABLE) {
37
-
insn.j_format.opcode = j_op;
38
-
insn.j_format.target = (e->target & J_RANGE_MASK) >> 2;
55
+
insn.j_format.opcode = J_ISA_BIT ? mm_j32_op : j_op;
56
+
insn.j_format.target = e->target >> J_RANGE_SHIFT;
39
57
} else {
40
58
insn.word = 0; /* nop */
41
59
}
42
60
43
61
get_online_cpus();
44
62
mutex_lock(&text_mutex);
45
-
*insn_p = insn;
63
+
if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) {
64
+
insn_p->halfword[0] = insn.word >> 16;
65
+
insn_p->halfword[1] = insn.word;
66
+
} else
67
+
*insn_p = insn;
46
68
47
69
flush_icache_range((unsigned long)insn_p,
48
70
(unsigned long)insn_p + sizeof(*insn_p));
+1
arch/mips/lib/memcpy.S
+1
arch/mips/lib/memcpy.S
+1
arch/mips/loongson/loongson-3/numa.c
+1
arch/mips/loongson/loongson-3/numa.c
+4
arch/mips/mm/tlb-r4k.c
+4
arch/mips/mm/tlb-r4k.c
···
299
299
300
300
local_irq_save(flags);
301
301
302
+
htw_stop();
302
303
pid = read_c0_entryhi() & ASID_MASK;
303
304
address &= (PAGE_MASK << 1);
304
305
write_c0_entryhi(address | pid);
···
347
346
tlb_write_indexed();
348
347
}
349
348
tlbw_use_hazard();
349
+
htw_start();
350
350
flush_itlb_vm(vma);
351
351
local_irq_restore(flags);
352
352
}
···
424
422
425
423
local_irq_save(flags);
426
424
/* Save old context and create impossible VPN2 value */
425
+
htw_stop();
427
426
old_ctx = read_c0_entryhi();
428
427
old_pagemask = read_c0_pagemask();
429
428
wired = read_c0_wired();
···
446
443
447
444
write_c0_entryhi(old_ctx);
448
445
write_c0_pagemask(old_pagemask);
446
+
htw_start();
449
447
out:
450
448
local_irq_restore(flags);
451
449
return ret;
+1
-1
arch/mips/oprofile/backtrace.c
+1
-1
arch/mips/oprofile/backtrace.c
···
92
92
/* This marks the end of the previous function,
93
93
which means we overran. */
94
94
break;
95
-
stack_size = (unsigned) stack_adjustment;
95
+
stack_size = (unsigned long) stack_adjustment;
96
96
} else if (is_ra_save_ins(&ip)) {
97
97
int ra_slot = ip.i_format.simmediate;
98
98
if (ra_slot < 0)