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drm/msm/dpu: try multirect based on mdp clock limits

It's certainly possible that for large resolutions a single DPU SSPP
cannot process the image without exceeding the MDP clock limits but
it can still process it in multirect mode because the source rectangles
will get divided and can fall within the MDP clock limits.

If the SSPP cannot process the image even in multirect mode, then it
will be rejected in dpu_plane_atomic_check_pipe().

Hence try using multirect for resolutions which cannot be processed
by a single SSPP without exceeding the MDP clock limits.

changes in v2:
- use crtc_state's adjusted_mode instead of mode
- fix the UBWC condition to check maxlinewidth

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/556817/
Link: https://lore.kernel.org/r/20230911221627.9569-2-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

authored by

Abhinav Kumar and committed by
Dmitry Baryshkov e6c0de5f 07e6de73

+6 -2
+6 -2
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
··· 824 824 plane); 825 825 int ret = 0, min_scale; 826 826 struct dpu_plane *pdpu = to_dpu_plane(plane); 827 + struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 828 + u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; 827 829 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 828 830 struct dpu_sw_pipe *pipe = &pstate->pipe; 829 831 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; ··· 894 892 895 893 max_linewidth = pdpu->catalog->caps->max_linewidth; 896 894 897 - if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { 895 + if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || 896 + _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { 898 897 /* 899 898 * In parallel multirect case only the half of the usual width 900 899 * is supported for tiled formats. If we are here, we know that 901 900 * full width is more than max_linewidth, thus each rect is 902 901 * wider than allowed. 903 902 */ 904 - if (DPU_FORMAT_IS_UBWC(fmt)) { 903 + if (DPU_FORMAT_IS_UBWC(fmt) && 904 + drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { 905 905 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n", 906 906 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 907 907 return -E2BIG;