tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/amd/display: Move all DCCG RCG into HWSS root_clock_control

[why & how]
Enabling/disabling DCCG RCG should be done as a last-level step when
enabling/disable blocks. This is handled by HWSS root_clock_control
already during optimize_bandwidth.
However, dccg35_dpp_root_clock_control was missing the RCG enable
call on the disable path.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Ovidiu Bunea and committed by
Alex Deucher e6c0e853 d745900b

+2 -8
+2 -3
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
··· 1184 1184 dcn35_set_dppclk_enable(dccg, dpp_inst, true); 1185 1185 } else { 1186 1186 dcn35_set_dppclk_enable(dccg, dpp_inst, false); 1187 - /*we have this in hwss: disable_plane*/ 1188 - //dccg35_set_dppclk_rcg(dccg, dpp_inst, true); 1187 + dccg35_set_dppclk_rcg(dccg, dpp_inst, true); 1189 1188 } 1190 1189 udelay(10); 1191 1190 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; ··· 1694 1695 DPPCLK0_DTO_PHASE, 0, 1695 1696 DPPCLK0_DTO_MODULO, 1); 1696 1697 /*we have this in hwss: disable_plane*/ 1697 - //dccg35_set_dppclk_rcg(dccg, dpp_inst, true); 1698 + dccg35_set_dppclk_rcg(dccg, dpp_inst, true); 1698 1699 } 1699 1700 1700 1701 // wait for clock to fully ramp
-5
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
··· 817 817 struct dc_state *context) 818 818 { 819 819 struct dpp *dpp = pipe_ctx->plane_res.dpp; 820 - struct dccg *dccg = dc->res_pool->dccg; 821 - 822 820 823 821 /* enable DCFCLK current DCHUB */ 824 822 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); ··· 824 826 /* initialize HUBP on power up */ 825 827 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 826 828 /*make sure DPPCLK is on*/ 827 - dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, true); 828 829 dpp->funcs->dpp_dppclk_control(dpp, false, true); 829 830 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 830 831 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( ··· 857 860 { 858 861 struct hubp *hubp = pipe_ctx->plane_res.hubp; 859 862 struct dpp *dpp = pipe_ctx->plane_res.dpp; 860 - struct dccg *dccg = dc->res_pool->dccg; 861 863 862 864 863 865 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); ··· 875 879 hubp->funcs->hubp_clk_cntl(hubp, false); 876 880 877 881 dpp->funcs->dpp_dppclk_control(dpp, false, false); 878 - dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, false); 879 882 880 883 hubp->power_gated = true; 881 884