Merge master.kernel.org:/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6

+3 -2

Documentation/DocBook/libata.tmpl

··· 456 456 457 457 <sect2><title>SATA phy read/write</title> 458 458 <programlisting> 459 - u32 (*scr_read) (struct ata_port *ap, unsigned int sc_reg); 460 - void (*scr_write) (struct ata_port *ap, unsigned int sc_reg, 459 + int (*scr_read) (struct ata_port *ap, unsigned int sc_reg, 460 + u32 *val); 461 + int (*scr_write) (struct ata_port *ap, unsigned int sc_reg, 461 462 u32 val); 462 463 </programlisting> 463 464

+1 -1

block/Kconfig

··· 53 53 54 54 config BLK_DEV_BSG 55 55 bool "Block layer SG support v4 (EXPERIMENTAL)" 56 - depends on (SCSI=y) && EXPERIMENTAL 56 + depends on EXPERIMENTAL 57 57 ---help--- 58 58 Saying Y here will enable generic SG (SCSI generic) v4 support 59 59 for any block device.

+23 -38

block/bsg.c

··· 932 932 { 933 933 struct bsg_class_device *bcd = &q->bsg_dev; 934 934 935 - WARN_ON(!bcd->class_dev); 935 + if (!bcd->class_dev) 936 + return; 936 937 937 938 mutex_lock(&bsg_mutex); 938 939 sysfs_remove_link(&q->kobj, "bsg"); 939 - class_device_destroy(bsg_class, MKDEV(bsg_major, bcd->minor)); 940 + class_device_unregister(bcd->class_dev); 941 + put_device(bcd->dev); 940 942 bcd->class_dev = NULL; 943 + bcd->dev = NULL; 941 944 list_del_init(&bcd->list); 942 945 bsg_device_nr--; 943 946 mutex_unlock(&bsg_mutex); 944 947 } 945 948 EXPORT_SYMBOL_GPL(bsg_unregister_queue); 946 949 947 - int bsg_register_queue(struct request_queue *q, const char *name) 950 + int bsg_register_queue(struct request_queue *q, struct device *gdev, 951 + const char *name) 948 952 { 949 953 struct bsg_class_device *bcd, *__bcd; 950 954 dev_t dev; 951 955 int ret = -EMFILE; 952 956 struct class_device *class_dev = NULL; 957 + const char *devname; 958 + 959 + if (name) 960 + devname = name; 961 + else 962 + devname = gdev->bus_id; 953 963 954 964 /* 955 965 * we need a proper transport to send commands, not a stacked device ··· 992 982 bsg_minor_idx = 0; 993 983 994 984 bcd->queue = q; 985 + bcd->dev = get_device(gdev); 995 986 dev = MKDEV(bsg_major, bcd->minor); 996 - class_dev = class_device_create(bsg_class, NULL, dev, bcd->dev, "%s", name); 987 + class_dev = class_device_create(bsg_class, NULL, dev, gdev, "%s", 988 + devname); 997 989 if (IS_ERR(class_dev)) { 998 990 ret = PTR_ERR(class_dev); 999 - goto err; 991 + goto err_put; 1000 992 } 1001 993 bcd->class_dev = class_dev; 1002 994 1003 995 if (q->kobj.sd) { 1004 996 ret = sysfs_create_link(&q->kobj, &bcd->class_dev->kobj, "bsg"); 1005 997 if (ret) 1006 - goto err; 998 + goto err_unregister; 1007 999 } 1008 1000 1009 1001 list_add_tail(&bcd->list, &bsg_class_list); ··· 1013 1001 1014 1002 mutex_unlock(&bsg_mutex); 1015 1003 return 0; 1004 + 1005 + err_unregister: 1006 + class_device_unregister(class_dev); 1007 + err_put: 1008 + put_device(gdev); 1016 1009 err: 1017 - if (class_dev) 1018 - class_device_destroy(bsg_class, MKDEV(bsg_major, bcd->minor)); 1019 1010 mutex_unlock(&bsg_mutex); 1020 1011 return ret; 1021 1012 } 1022 1013 EXPORT_SYMBOL_GPL(bsg_register_queue); 1023 - 1024 - static int bsg_add(struct class_device *cl_dev, struct class_interface *cl_intf) 1025 - { 1026 - int ret; 1027 - struct scsi_device *sdp = to_scsi_device(cl_dev->dev); 1028 - struct request_queue *rq = sdp->request_queue; 1029 - 1030 - if (rq->kobj.parent) 1031 - ret = bsg_register_queue(rq, kobject_name(rq->kobj.parent)); 1032 - else 1033 - ret = bsg_register_queue(rq, kobject_name(&sdp->sdev_gendev.kobj)); 1034 - return ret; 1035 - } 1036 - 1037 - static void bsg_remove(struct class_device *cl_dev, struct class_interface *cl_intf) 1038 - { 1039 - bsg_unregister_queue(to_scsi_device(cl_dev->dev)->request_queue); 1040 - } 1041 - 1042 - static struct class_interface bsg_intf = { 1043 - .add = bsg_add, 1044 - .remove = bsg_remove, 1045 - }; 1046 1014 1047 1015 static struct cdev bsg_cdev = { 1048 1016 .kobj = {.name = "bsg", }, ··· 1061 1069 if (ret) 1062 1070 goto unregister_chrdev; 1063 1071 1064 - ret = scsi_register_interface(&bsg_intf); 1065 - if (ret) 1066 - goto remove_cdev; 1067 - 1068 1072 printk(KERN_INFO BSG_DESCRIPTION " version " BSG_VERSION 1069 1073 " loaded (major %d)\n", bsg_major); 1070 1074 return 0; 1071 - remove_cdev: 1072 - printk(KERN_ERR "bsg: failed register scsi interface %d\n", ret); 1073 - cdev_del(&bsg_cdev); 1074 1075 unregister_chrdev: 1075 1076 unregister_chrdev_region(MKDEV(bsg_major, 0), BSG_MAX_DEVS); 1076 1077 destroy_bsg_class:

+5 -8

block/scsi_ioctl.c

··· 214 214 } 215 215 EXPORT_SYMBOL_GPL(blk_verify_command); 216 216 217 - int blk_fill_sghdr_rq(request_queue_t *q, struct request *rq, 218 - struct sg_io_hdr *hdr, int has_write_perm) 217 + static int blk_fill_sghdr_rq(request_queue_t *q, struct request *rq, 218 + struct sg_io_hdr *hdr, int has_write_perm) 219 219 { 220 220 memset(rq->cmd, 0, BLK_MAX_CDB); /* ATAPI hates garbage after CDB */ 221 221 ··· 238 238 239 239 return 0; 240 240 } 241 - EXPORT_SYMBOL_GPL(blk_fill_sghdr_rq); 242 241 243 242 /* 244 243 * unmap a request that was previously mapped to this sg_io_hdr. handles 245 244 * both sg and non-sg sg_io_hdr. 246 245 */ 247 - int blk_unmap_sghdr_rq(struct request *rq, struct sg_io_hdr *hdr) 246 + static int blk_unmap_sghdr_rq(struct request *rq, struct sg_io_hdr *hdr) 248 247 { 249 248 blk_rq_unmap_user(rq->bio); 250 249 blk_put_request(rq); 251 250 return 0; 252 251 } 253 - EXPORT_SYMBOL_GPL(blk_unmap_sghdr_rq); 254 252 255 - int blk_complete_sghdr_rq(struct request *rq, struct sg_io_hdr *hdr, 256 - struct bio *bio) 253 + static int blk_complete_sghdr_rq(struct request *rq, struct sg_io_hdr *hdr, 254 + struct bio *bio) 257 255 { 258 256 int r, ret = 0; 259 257 ··· 285 287 286 288 return r; 287 289 } 288 - EXPORT_SYMBOL_GPL(blk_complete_sghdr_rq); 289 290 290 291 static int sg_io(struct file *file, request_queue_t *q, 291 292 struct gendisk *bd_disk, struct sg_io_hdr *hdr)

+1 -1

drivers/firewire/fw-sbp2.c

··· 1160 1160 static struct scsi_host_template scsi_driver_template = { 1161 1161 .module = THIS_MODULE, 1162 1162 .name = "SBP-2 IEEE-1394", 1163 - .proc_name = (char *)sbp2_driver_name, 1163 + .proc_name = sbp2_driver_name, 1164 1164 .queuecommand = sbp2_scsi_queuecommand, 1165 1165 .slave_alloc = sbp2_scsi_slave_alloc, 1166 1166 .slave_configure = sbp2_scsi_slave_configure,

+1

drivers/message/fusion/Kconfig

··· 37 37 LSIFC929 38 38 LSIFC929X 39 39 LSIFC929XL 40 + Brocade FC 410/420 40 41 41 42 config FUSION_SAS 42 43 tristate "Fusion MPT ScsiHost drivers for SAS"

+320 -62

drivers/message/fusion/mptbase.c

··· 161 161 static void mpt_read_ioc_pg_1(MPT_ADAPTER *ioc); 162 162 static void mpt_read_ioc_pg_4(MPT_ADAPTER *ioc); 163 163 static void mpt_timer_expired(unsigned long data); 164 + static void mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc); 164 165 static int SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch); 165 166 static int SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp); 166 167 static int mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag); ··· 1132 1131 return -1; 1133 1132 } 1134 1133 1134 + /** 1135 + * mpt_get_product_name - returns product string 1136 + * @vendor: pci vendor id 1137 + * @device: pci device id 1138 + * @revision: pci revision id 1139 + * @prod_name: string returned 1140 + * 1141 + * Returns product string displayed when driver loads, 1142 + * in /proc/mpt/summary and /sysfs/class/scsi_host/host<X>/version_product 1143 + * 1144 + **/ 1145 + static void 1146 + mpt_get_product_name(u16 vendor, u16 device, u8 revision, char *prod_name) 1147 + { 1148 + char *product_str = NULL; 1149 + 1150 + if (vendor == PCI_VENDOR_ID_BROCADE) { 1151 + switch (device) 1152 + { 1153 + case MPI_MANUFACTPAGE_DEVICEID_FC949E: 1154 + switch (revision) 1155 + { 1156 + case 0x00: 1157 + product_str = "BRE040 A0"; 1158 + break; 1159 + case 0x01: 1160 + product_str = "BRE040 A1"; 1161 + break; 1162 + default: 1163 + product_str = "BRE040"; 1164 + break; 1165 + } 1166 + break; 1167 + } 1168 + goto out; 1169 + } 1170 + 1171 + switch (device) 1172 + { 1173 + case MPI_MANUFACTPAGE_DEVICEID_FC909: 1174 + product_str = "LSIFC909 B1"; 1175 + break; 1176 + case MPI_MANUFACTPAGE_DEVICEID_FC919: 1177 + product_str = "LSIFC919 B0"; 1178 + break; 1179 + case MPI_MANUFACTPAGE_DEVICEID_FC929: 1180 + product_str = "LSIFC929 B0"; 1181 + break; 1182 + case MPI_MANUFACTPAGE_DEVICEID_FC919X: 1183 + if (revision < 0x80) 1184 + product_str = "LSIFC919X A0"; 1185 + else 1186 + product_str = "LSIFC919XL A1"; 1187 + break; 1188 + case MPI_MANUFACTPAGE_DEVICEID_FC929X: 1189 + if (revision < 0x80) 1190 + product_str = "LSIFC929X A0"; 1191 + else 1192 + product_str = "LSIFC929XL A1"; 1193 + break; 1194 + case MPI_MANUFACTPAGE_DEVICEID_FC939X: 1195 + product_str = "LSIFC939X A1"; 1196 + break; 1197 + case MPI_MANUFACTPAGE_DEVICEID_FC949X: 1198 + product_str = "LSIFC949X A1"; 1199 + break; 1200 + case MPI_MANUFACTPAGE_DEVICEID_FC949E: 1201 + switch (revision) 1202 + { 1203 + case 0x00: 1204 + product_str = "LSIFC949E A0"; 1205 + break; 1206 + case 0x01: 1207 + product_str = "LSIFC949E A1"; 1208 + break; 1209 + default: 1210 + product_str = "LSIFC949E"; 1211 + break; 1212 + } 1213 + break; 1214 + case MPI_MANUFACTPAGE_DEVID_53C1030: 1215 + switch (revision) 1216 + { 1217 + case 0x00: 1218 + product_str = "LSI53C1030 A0"; 1219 + break; 1220 + case 0x01: 1221 + product_str = "LSI53C1030 B0"; 1222 + break; 1223 + case 0x03: 1224 + product_str = "LSI53C1030 B1"; 1225 + break; 1226 + case 0x07: 1227 + product_str = "LSI53C1030 B2"; 1228 + break; 1229 + case 0x08: 1230 + product_str = "LSI53C1030 C0"; 1231 + break; 1232 + case 0x80: 1233 + product_str = "LSI53C1030T A0"; 1234 + break; 1235 + case 0x83: 1236 + product_str = "LSI53C1030T A2"; 1237 + break; 1238 + case 0x87: 1239 + product_str = "LSI53C1030T A3"; 1240 + break; 1241 + case 0xc1: 1242 + product_str = "LSI53C1020A A1"; 1243 + break; 1244 + default: 1245 + product_str = "LSI53C1030"; 1246 + break; 1247 + } 1248 + break; 1249 + case MPI_MANUFACTPAGE_DEVID_1030_53C1035: 1250 + switch (revision) 1251 + { 1252 + case 0x03: 1253 + product_str = "LSI53C1035 A2"; 1254 + break; 1255 + case 0x04: 1256 + product_str = "LSI53C1035 B0"; 1257 + break; 1258 + default: 1259 + product_str = "LSI53C1035"; 1260 + break; 1261 + } 1262 + break; 1263 + case MPI_MANUFACTPAGE_DEVID_SAS1064: 1264 + switch (revision) 1265 + { 1266 + case 0x00: 1267 + product_str = "LSISAS1064 A1"; 1268 + break; 1269 + case 0x01: 1270 + product_str = "LSISAS1064 A2"; 1271 + break; 1272 + case 0x02: 1273 + product_str = "LSISAS1064 A3"; 1274 + break; 1275 + case 0x03: 1276 + product_str = "LSISAS1064 A4"; 1277 + break; 1278 + default: 1279 + product_str = "LSISAS1064"; 1280 + break; 1281 + } 1282 + break; 1283 + case MPI_MANUFACTPAGE_DEVID_SAS1064E: 1284 + switch (revision) 1285 + { 1286 + case 0x00: 1287 + product_str = "LSISAS1064E A0"; 1288 + break; 1289 + case 0x01: 1290 + product_str = "LSISAS1064E B0"; 1291 + break; 1292 + case 0x02: 1293 + product_str = "LSISAS1064E B1"; 1294 + break; 1295 + case 0x04: 1296 + product_str = "LSISAS1064E B2"; 1297 + break; 1298 + case 0x08: 1299 + product_str = "LSISAS1064E B3"; 1300 + break; 1301 + default: 1302 + product_str = "LSISAS1064E"; 1303 + break; 1304 + } 1305 + break; 1306 + case MPI_MANUFACTPAGE_DEVID_SAS1068: 1307 + switch (revision) 1308 + { 1309 + case 0x00: 1310 + product_str = "LSISAS1068 A0"; 1311 + break; 1312 + case 0x01: 1313 + product_str = "LSISAS1068 B0"; 1314 + break; 1315 + case 0x02: 1316 + product_str = "LSISAS1068 B1"; 1317 + break; 1318 + default: 1319 + product_str = "LSISAS1068"; 1320 + break; 1321 + } 1322 + break; 1323 + case MPI_MANUFACTPAGE_DEVID_SAS1068E: 1324 + switch (revision) 1325 + { 1326 + case 0x00: 1327 + product_str = "LSISAS1068E A0"; 1328 + break; 1329 + case 0x01: 1330 + product_str = "LSISAS1068E B0"; 1331 + break; 1332 + case 0x02: 1333 + product_str = "LSISAS1068E B1"; 1334 + break; 1335 + case 0x04: 1336 + product_str = "LSISAS1068E B2"; 1337 + break; 1338 + case 0x08: 1339 + product_str = "LSISAS1068E B3"; 1340 + break; 1341 + default: 1342 + product_str = "LSISAS1068E"; 1343 + break; 1344 + } 1345 + break; 1346 + case MPI_MANUFACTPAGE_DEVID_SAS1078: 1347 + switch (revision) 1348 + { 1349 + case 0x00: 1350 + product_str = "LSISAS1078 A0"; 1351 + break; 1352 + case 0x01: 1353 + product_str = "LSISAS1078 B0"; 1354 + break; 1355 + case 0x02: 1356 + product_str = "LSISAS1078 C0"; 1357 + break; 1358 + case 0x03: 1359 + product_str = "LSISAS1078 C1"; 1360 + break; 1361 + case 0x04: 1362 + product_str = "LSISAS1078 C2"; 1363 + break; 1364 + default: 1365 + product_str = "LSISAS1078"; 1366 + break; 1367 + } 1368 + break; 1369 + } 1370 + 1371 + out: 1372 + if (product_str) 1373 + sprintf(prod_name, "%s", product_str); 1374 + } 1375 + 1135 1376 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1136 1377 /** 1137 1378 * mpt_attach - Install a PCI intelligent MPT adapter. ··· 1517 1274 ioc->pio_chip = (SYSIF_REGS __iomem *)pmem; 1518 1275 } 1519 1276 1520 - if (pdev->device == MPI_MANUFACTPAGE_DEVICEID_FC909) { 1521 - ioc->prod_name = "LSIFC909"; 1277 + pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision); 1278 + mpt_get_product_name(pdev->vendor, pdev->device, revision, ioc->prod_name); 1279 + 1280 + switch (pdev->device) 1281 + { 1282 + case MPI_MANUFACTPAGE_DEVICEID_FC939X: 1283 + case MPI_MANUFACTPAGE_DEVICEID_FC949X: 1284 + ioc->errata_flag_1064 = 1; 1285 + case MPI_MANUFACTPAGE_DEVICEID_FC909: 1286 + case MPI_MANUFACTPAGE_DEVICEID_FC929: 1287 + case MPI_MANUFACTPAGE_DEVICEID_FC919: 1288 + case MPI_MANUFACTPAGE_DEVICEID_FC949E: 1522 1289 ioc->bus_type = FC; 1523 - } 1524 - else if (pdev->device == MPI_MANUFACTPAGE_DEVICEID_FC929) { 1525 - ioc->prod_name = "LSIFC929"; 1526 - ioc->bus_type = FC; 1527 - } 1528 - else if (pdev->device == MPI_MANUFACTPAGE_DEVICEID_FC919) { 1529 - ioc->prod_name = "LSIFC919"; 1530 - ioc->bus_type = FC; 1531 - } 1532 - else if (pdev->device == MPI_MANUFACTPAGE_DEVICEID_FC929X) { 1533 - pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision); 1534 - ioc->bus_type = FC; 1290 + break; 1291 + 1292 + case MPI_MANUFACTPAGE_DEVICEID_FC929X: 1535 1293 if (revision < XL_929) { 1536 - ioc->prod_name = "LSIFC929X"; 1537 1294 /* 929X Chip Fix. Set Split transactions level 1538 1295 * for PCIX. Set MOST bits to zero. 1539 1296 */ ··· 1541 1298 pcixcmd &= 0x8F; 1542 1299 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1543 1300 } else { 1544 - ioc->prod_name = "LSIFC929XL"; 1545 1301 /* 929XL Chip Fix. Set MMRBC to 0x08. 1546 1302 */ 1547 1303 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1548 1304 pcixcmd |= 0x08; 1549 1305 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1550 1306 } 1551 - } 1552 - else if (pdev->device == MPI_MANUFACTPAGE_DEVICEID_FC919X) { 1553 - ioc->prod_name = "LSIFC919X"; 1554 1307 ioc->bus_type = FC; 1308 + break; 1309 + 1310 + case MPI_MANUFACTPAGE_DEVICEID_FC919X: 1555 1311 /* 919X Chip Fix. Set Split transactions level 1556 1312 * for PCIX. Set MOST bits to zero. 1557 1313 */ 1558 1314 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1559 1315 pcixcmd &= 0x8F; 1560 1316 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1561 - } 1562 - else if (pdev->device == MPI_MANUFACTPAGE_DEVICEID_FC939X) { 1563 - ioc->prod_name = "LSIFC939X"; 1564 1317 ioc->bus_type = FC; 1565 - ioc->errata_flag_1064 = 1; 1566 - } 1567 - else if (pdev->device == MPI_MANUFACTPAGE_DEVICEID_FC949X) { 1568 - ioc->prod_name = "LSIFC949X"; 1569 - ioc->bus_type = FC; 1570 - ioc->errata_flag_1064 = 1; 1571 - } 1572 - else if (pdev->device == MPI_MANUFACTPAGE_DEVICEID_FC949E) { 1573 - ioc->prod_name = "LSIFC949E"; 1574 - ioc->bus_type = FC; 1575 - } 1576 - else if (pdev->device == MPI_MANUFACTPAGE_DEVID_53C1030) { 1577 - ioc->prod_name = "LSI53C1030"; 1578 - ioc->bus_type = SPI; 1318 + break; 1319 + 1320 + case MPI_MANUFACTPAGE_DEVID_53C1030: 1579 1321 /* 1030 Chip Fix. Disable Split transactions 1580 1322 * for PCIX. Set MOST bits to zero if Rev < C0( = 8). 1581 1323 */ 1582 - pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision); 1583 1324 if (revision < C0_1030) { 1584 1325 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1585 1326 pcixcmd &= 0x8F; 1586 1327 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1587 1328 } 1588 - } 1589 - else if (pdev->device == MPI_MANUFACTPAGE_DEVID_1030_53C1035) { 1590 - ioc->prod_name = "LSI53C1035"; 1329 + 1330 + case MPI_MANUFACTPAGE_DEVID_1030_53C1035: 1591 1331 ioc->bus_type = SPI; 1592 - } 1593 - else if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1064) { 1594 - ioc->prod_name = "LSISAS1064"; 1595 - ioc->bus_type = SAS; 1332 + break; 1333 + 1334 + case MPI_MANUFACTPAGE_DEVID_SAS1064: 1335 + case MPI_MANUFACTPAGE_DEVID_SAS1068: 1596 1336 ioc->errata_flag_1064 = 1; 1597 - } 1598 - else if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1068) { 1599 - ioc->prod_name = "LSISAS1068"; 1600 - ioc->bus_type = SAS; 1601 - ioc->errata_flag_1064 = 1; 1602 - } 1603 - else if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1064E) { 1604 - ioc->prod_name = "LSISAS1064E"; 1605 - ioc->bus_type = SAS; 1606 - } 1607 - else if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1068E) { 1608 - ioc->prod_name = "LSISAS1068E"; 1609 - ioc->bus_type = SAS; 1610 - } 1611 - else if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) { 1612 - ioc->prod_name = "LSISAS1078"; 1337 + 1338 + case MPI_MANUFACTPAGE_DEVID_SAS1064E: 1339 + case MPI_MANUFACTPAGE_DEVID_SAS1068E: 1340 + case MPI_MANUFACTPAGE_DEVID_SAS1078: 1613 1341 ioc->bus_type = SAS; 1614 1342 } 1615 1343 ··· 2094 1880 } 2095 1881 2096 1882 GetIoUnitPage2(ioc); 1883 + mpt_get_manufacturing_pg_0(ioc); 2097 1884 } 2098 1885 2099 1886 /* ··· 2353 2138 int i = 0; 2354 2139 2355 2140 printk(KERN_INFO "%s: ", ioc->name); 2356 - if (ioc->prod_name && strlen(ioc->prod_name) > 3) 2357 - printk("%s: ", ioc->prod_name+3); 2141 + if (ioc->prod_name) 2142 + printk("%s: ", ioc->prod_name); 2358 2143 printk("Capabilities={"); 2359 2144 2360 2145 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) { ··· 5403 5188 pci_free_consistent(ioc->pcidev, iocpage1sz, pIoc1, ioc1_dma); 5404 5189 5405 5190 return; 5191 + } 5192 + 5193 + static void 5194 + mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc) 5195 + { 5196 + CONFIGPARMS cfg; 5197 + ConfigPageHeader_t hdr; 5198 + dma_addr_t buf_dma; 5199 + ManufacturingPage0_t *pbuf = NULL; 5200 + 5201 + memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5202 + memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5203 + 5204 + hdr.PageType = MPI_CONFIG_PAGETYPE_MANUFACTURING; 5205 + cfg.cfghdr.hdr = &hdr; 5206 + cfg.physAddr = -1; 5207 + cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5208 + cfg.timeout = 10; 5209 + 5210 + if (mpt_config(ioc, &cfg) != 0) 5211 + goto out; 5212 + 5213 + if (!cfg.cfghdr.hdr->PageLength) 5214 + goto out; 5215 + 5216 + cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5217 + pbuf = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, &buf_dma); 5218 + if (!pbuf) 5219 + goto out; 5220 + 5221 + cfg.physAddr = buf_dma; 5222 + 5223 + if (mpt_config(ioc, &cfg) != 0) 5224 + goto out; 5225 + 5226 + memcpy(ioc->board_name, pbuf->BoardName, sizeof(ioc->board_name)); 5227 + memcpy(ioc->board_assembly, pbuf->BoardAssembly, sizeof(ioc->board_assembly)); 5228 + memcpy(ioc->board_tracer, pbuf->BoardTracerNumber, sizeof(ioc->board_tracer)); 5229 + 5230 + out: 5231 + 5232 + if (pbuf) 5233 + pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, pbuf, buf_dma); 5406 5234 } 5407 5235 5408 5236 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/

+8 -1

drivers/message/fusion/mptbase.h

··· 537 537 int id; /* Unique adapter id N {0,1,2,...} */ 538 538 int pci_irq; /* This irq */ 539 539 char name[MPT_NAME_LENGTH]; /* "iocN" */ 540 - char *prod_name; /* "LSIFC9x9" */ 540 + char prod_name[MPT_NAME_LENGTH]; /* "LSIFC9x9" */ 541 + char board_name[16]; 542 + char board_assembly[16]; 543 + char board_tracer[16]; 544 + u16 nvdata_version_persistent; 545 + u16 nvdata_version_default; 546 + u8 io_missing_delay; 547 + u8 device_missing_delay; 541 548 SYSIF_REGS __iomem *chip; /* == c8817000 (mmap) */ 542 549 SYSIF_REGS __iomem *pio_chip; /* Programmed IO (downloadboot) */ 543 550 u8 bus_type;

+3

drivers/message/fusion/mptfc.c

··· 130 130 .max_sectors = 8192, 131 131 .cmd_per_lun = 7, 132 132 .use_clustering = ENABLE_CLUSTERING, 133 + .shost_attrs = mptscsih_host_attrs, 133 134 }; 134 135 135 136 /**************************************************************************** ··· 153 152 { PCI_VENDOR_ID_LSI_LOGIC, MPI_MANUFACTPAGE_DEVICEID_FC949X, 154 153 PCI_ANY_ID, PCI_ANY_ID }, 155 154 { PCI_VENDOR_ID_LSI_LOGIC, MPI_MANUFACTPAGE_DEVICEID_FC949E, 155 + PCI_ANY_ID, PCI_ANY_ID }, 156 + { PCI_VENDOR_ID_BROCADE, MPI_MANUFACTPAGE_DEVICEID_FC949E, 156 157 PCI_ANY_ID, PCI_ANY_ID }, 157 158 {0} /* Terminating entry */ 158 159 };

+71 -1

drivers/message/fusion/mptsas.c

··· 1119 1119 .max_sectors = 8192, 1120 1120 .cmd_per_lun = 7, 1121 1121 .use_clustering = ENABLE_CLUSTERING, 1122 + .shost_attrs = mptscsih_host_attrs, 1122 1123 }; 1123 1124 1124 1125 static int mptsas_get_linkerrors(struct sas_phy *phy) ··· 1391 1390 goto out_free_consistent; 1392 1391 } 1393 1392 1393 + ioc->nvdata_version_persistent = 1394 + le16_to_cpu(buffer->NvdataVersionPersistent); 1395 + ioc->nvdata_version_default = 1396 + le16_to_cpu(buffer->NvdataVersionDefault); 1397 + 1394 1398 for (i = 0; i < port_info->num_phys; i++) { 1395 1399 mptsas_print_phy_data(&buffer->PhyData[i]); 1396 1400 port_info->phy_info[i].phy_id = i; ··· 1407 1401 port_info->phy_info[i].handle = 1408 1402 le16_to_cpu(buffer->PhyData[i].ControllerDevHandle); 1409 1403 } 1404 + 1405 + out_free_consistent: 1406 + pci_free_consistent(ioc->pcidev, hdr.ExtPageLength * 4, 1407 + buffer, dma_handle); 1408 + out: 1409 + return error; 1410 + } 1411 + 1412 + static int 1413 + mptsas_sas_io_unit_pg1(MPT_ADAPTER *ioc) 1414 + { 1415 + ConfigExtendedPageHeader_t hdr; 1416 + CONFIGPARMS cfg; 1417 + SasIOUnitPage1_t *buffer; 1418 + dma_addr_t dma_handle; 1419 + int error; 1420 + u16 device_missing_delay; 1421 + 1422 + memset(&hdr, 0, sizeof(ConfigExtendedPageHeader_t)); 1423 + memset(&cfg, 0, sizeof(CONFIGPARMS)); 1424 + 1425 + cfg.cfghdr.ehdr = &hdr; 1426 + cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 1427 + cfg.timeout = 10; 1428 + cfg.cfghdr.ehdr->PageType = MPI_CONFIG_PAGETYPE_EXTENDED; 1429 + cfg.cfghdr.ehdr->ExtPageType = MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT; 1430 + cfg.cfghdr.ehdr->PageVersion = MPI_SASIOUNITPAGE1_PAGEVERSION; 1431 + cfg.cfghdr.ehdr->PageNumber = 1; 1432 + 1433 + error = mpt_config(ioc, &cfg); 1434 + if (error) 1435 + goto out; 1436 + if (!hdr.ExtPageLength) { 1437 + error = -ENXIO; 1438 + goto out; 1439 + } 1440 + 1441 + buffer = pci_alloc_consistent(ioc->pcidev, hdr.ExtPageLength * 4, 1442 + &dma_handle); 1443 + if (!buffer) { 1444 + error = -ENOMEM; 1445 + goto out; 1446 + } 1447 + 1448 + cfg.physAddr = dma_handle; 1449 + cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 1450 + 1451 + error = mpt_config(ioc, &cfg); 1452 + if (error) 1453 + goto out_free_consistent; 1454 + 1455 + ioc->io_missing_delay = 1456 + le16_to_cpu(buffer->IODeviceMissingDelay); 1457 + device_missing_delay = le16_to_cpu(buffer->ReportDeviceMissingDelay); 1458 + ioc->device_missing_delay = (device_missing_delay & MPI_SAS_IOUNIT1_REPORT_MISSING_UNIT_16) ? 1459 + (device_missing_delay & MPI_SAS_IOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16 : 1460 + device_missing_delay & MPI_SAS_IOUNIT1_REPORT_MISSING_TIMEOUT_MASK; 1410 1461 1411 1462 out_free_consistent: 1412 1463 pci_free_consistent(ioc->pcidev, hdr.ExtPageLength * 4, ··· 2053 1990 if (error) 2054 1991 goto out_free_port_info; 2055 1992 1993 + mptsas_sas_io_unit_pg1(ioc); 2056 1994 mutex_lock(&ioc->sas_topology_mutex); 2057 1995 ioc->handle = hba->phy_info[0].handle; 2058 1996 port_info = mptsas_find_portinfo_by_handle(ioc, ioc->handle); ··· 3301 3237 static int __init 3302 3238 mptsas_init(void) 3303 3239 { 3240 + int error; 3241 + 3304 3242 show_mptmod_ver(my_NAME, my_VERSION); 3305 3243 3306 3244 mptsas_transport_template = ··· 3326 3260 ": Registered for IOC reset notifications\n")); 3327 3261 } 3328 3262 3329 - return pci_register_driver(&mptsas_driver); 3263 + error = pci_register_driver(&mptsas_driver); 3264 + if (error) 3265 + sas_release_transport(mptsas_transport_template); 3266 + 3267 + return error; 3330 3268 } 3331 3269 3332 3270 static void __exit

+153

drivers/message/fusion/mptscsih.c

··· 3187 3187 mptscsih_do_cmd(hd, &iocmd); 3188 3188 } 3189 3189 3190 + static ssize_t 3191 + mptscsih_version_fw_show(struct class_device *cdev, char *buf) 3192 + { 3193 + struct Scsi_Host *host = class_to_shost(cdev); 3194 + MPT_SCSI_HOST *hd = (MPT_SCSI_HOST *)host->hostdata; 3195 + MPT_ADAPTER *ioc = hd->ioc; 3196 + 3197 + return snprintf(buf, PAGE_SIZE, "%02d.%02d.%02d.%02d\n", 3198 + (ioc->facts.FWVersion.Word & 0xFF000000) >> 24, 3199 + (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16, 3200 + (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8, 3201 + ioc->facts.FWVersion.Word & 0x000000FF); 3202 + } 3203 + static CLASS_DEVICE_ATTR(version_fw, S_IRUGO, mptscsih_version_fw_show, NULL); 3204 + 3205 + static ssize_t 3206 + mptscsih_version_bios_show(struct class_device *cdev, char *buf) 3207 + { 3208 + struct Scsi_Host *host = class_to_shost(cdev); 3209 + MPT_SCSI_HOST *hd = (MPT_SCSI_HOST *)host->hostdata; 3210 + MPT_ADAPTER *ioc = hd->ioc; 3211 + 3212 + return snprintf(buf, PAGE_SIZE, "%02x.%02x.%02x.%02x\n", 3213 + (ioc->biosVersion & 0xFF000000) >> 24, 3214 + (ioc->biosVersion & 0x00FF0000) >> 16, 3215 + (ioc->biosVersion & 0x0000FF00) >> 8, 3216 + ioc->biosVersion & 0x000000FF); 3217 + } 3218 + static CLASS_DEVICE_ATTR(version_bios, S_IRUGO, mptscsih_version_bios_show, NULL); 3219 + 3220 + static ssize_t 3221 + mptscsih_version_mpi_show(struct class_device *cdev, char *buf) 3222 + { 3223 + struct Scsi_Host *host = class_to_shost(cdev); 3224 + MPT_SCSI_HOST *hd = (MPT_SCSI_HOST *)host->hostdata; 3225 + MPT_ADAPTER *ioc = hd->ioc; 3226 + 3227 + return snprintf(buf, PAGE_SIZE, "%03x\n", ioc->facts.MsgVersion); 3228 + } 3229 + static CLASS_DEVICE_ATTR(version_mpi, S_IRUGO, mptscsih_version_mpi_show, NULL); 3230 + 3231 + static ssize_t 3232 + mptscsih_version_product_show(struct class_device *cdev, char *buf) 3233 + { 3234 + struct Scsi_Host *host = class_to_shost(cdev); 3235 + MPT_SCSI_HOST *hd = (MPT_SCSI_HOST *)host->hostdata; 3236 + MPT_ADAPTER *ioc = hd->ioc; 3237 + 3238 + return snprintf(buf, PAGE_SIZE, "%s\n", ioc->prod_name); 3239 + } 3240 + static CLASS_DEVICE_ATTR(version_product, S_IRUGO, 3241 + mptscsih_version_product_show, NULL); 3242 + 3243 + static ssize_t 3244 + mptscsih_version_nvdata_persistent_show(struct class_device *cdev, char *buf) 3245 + { 3246 + struct Scsi_Host *host = class_to_shost(cdev); 3247 + MPT_SCSI_HOST *hd = (MPT_SCSI_HOST *)host->hostdata; 3248 + MPT_ADAPTER *ioc = hd->ioc; 3249 + 3250 + return snprintf(buf, PAGE_SIZE, "%02xh\n", 3251 + ioc->nvdata_version_persistent); 3252 + } 3253 + static CLASS_DEVICE_ATTR(version_nvdata_persistent, S_IRUGO, 3254 + mptscsih_version_nvdata_persistent_show, NULL); 3255 + 3256 + static ssize_t 3257 + mptscsih_version_nvdata_default_show(struct class_device *cdev, char *buf) 3258 + { 3259 + struct Scsi_Host *host = class_to_shost(cdev); 3260 + MPT_SCSI_HOST *hd = (MPT_SCSI_HOST *)host->hostdata; 3261 + MPT_ADAPTER *ioc = hd->ioc; 3262 + 3263 + return snprintf(buf, PAGE_SIZE, "%02xh\n",ioc->nvdata_version_default); 3264 + } 3265 + static CLASS_DEVICE_ATTR(version_nvdata_default, S_IRUGO, 3266 + mptscsih_version_nvdata_default_show, NULL); 3267 + 3268 + static ssize_t 3269 + mptscsih_board_name_show(struct class_device *cdev, char *buf) 3270 + { 3271 + struct Scsi_Host *host = class_to_shost(cdev); 3272 + MPT_SCSI_HOST *hd = (MPT_SCSI_HOST *)host->hostdata; 3273 + MPT_ADAPTER *ioc = hd->ioc; 3274 + 3275 + return snprintf(buf, PAGE_SIZE, "%s\n", ioc->board_name); 3276 + } 3277 + static CLASS_DEVICE_ATTR(board_name, S_IRUGO, mptscsih_board_name_show, NULL); 3278 + 3279 + static ssize_t 3280 + mptscsih_board_assembly_show(struct class_device *cdev, char *buf) 3281 + { 3282 + struct Scsi_Host *host = class_to_shost(cdev); 3283 + MPT_SCSI_HOST *hd = (MPT_SCSI_HOST *)host->hostdata; 3284 + MPT_ADAPTER *ioc = hd->ioc; 3285 + 3286 + return snprintf(buf, PAGE_SIZE, "%s\n", ioc->board_assembly); 3287 + } 3288 + static CLASS_DEVICE_ATTR(board_assembly, S_IRUGO, 3289 + mptscsih_board_assembly_show, NULL); 3290 + 3291 + static ssize_t 3292 + mptscsih_board_tracer_show(struct class_device *cdev, char *buf) 3293 + { 3294 + struct Scsi_Host *host = class_to_shost(cdev); 3295 + MPT_SCSI_HOST *hd = (MPT_SCSI_HOST *)host->hostdata; 3296 + MPT_ADAPTER *ioc = hd->ioc; 3297 + 3298 + return snprintf(buf, PAGE_SIZE, "%s\n", ioc->board_tracer); 3299 + } 3300 + static CLASS_DEVICE_ATTR(board_tracer, S_IRUGO, 3301 + mptscsih_board_tracer_show, NULL); 3302 + 3303 + static ssize_t 3304 + mptscsih_io_delay_show(struct class_device *cdev, char *buf) 3305 + { 3306 + struct Scsi_Host *host = class_to_shost(cdev); 3307 + MPT_SCSI_HOST *hd = (MPT_SCSI_HOST *)host->hostdata; 3308 + MPT_ADAPTER *ioc = hd->ioc; 3309 + 3310 + return snprintf(buf, PAGE_SIZE, "%02d\n", ioc->io_missing_delay); 3311 + } 3312 + static CLASS_DEVICE_ATTR(io_delay, S_IRUGO, 3313 + mptscsih_io_delay_show, NULL); 3314 + 3315 + static ssize_t 3316 + mptscsih_device_delay_show(struct class_device *cdev, char *buf) 3317 + { 3318 + struct Scsi_Host *host = class_to_shost(cdev); 3319 + MPT_SCSI_HOST *hd = (MPT_SCSI_HOST *)host->hostdata; 3320 + MPT_ADAPTER *ioc = hd->ioc; 3321 + 3322 + return snprintf(buf, PAGE_SIZE, "%02d\n", ioc->device_missing_delay); 3323 + } 3324 + static CLASS_DEVICE_ATTR(device_delay, S_IRUGO, 3325 + mptscsih_device_delay_show, NULL); 3326 + 3327 + struct class_device_attribute *mptscsih_host_attrs[] = { 3328 + &class_device_attr_version_fw, 3329 + &class_device_attr_version_bios, 3330 + &class_device_attr_version_mpi, 3331 + &class_device_attr_version_product, 3332 + &class_device_attr_version_nvdata_persistent, 3333 + &class_device_attr_version_nvdata_default, 3334 + &class_device_attr_board_name, 3335 + &class_device_attr_board_assembly, 3336 + &class_device_attr_board_tracer, 3337 + &class_device_attr_io_delay, 3338 + &class_device_attr_device_delay, 3339 + NULL, 3340 + }; 3341 + EXPORT_SYMBOL(mptscsih_host_attrs); 3342 + 3190 3343 EXPORT_SYMBOL(mptscsih_remove); 3191 3344 EXPORT_SYMBOL(mptscsih_shutdown); 3192 3345 #ifdef CONFIG_PM

+1

drivers/message/fusion/mptscsih.h

··· 129 129 extern int mptscsih_TMHandler(MPT_SCSI_HOST *hd, u8 type, u8 channel, u8 id, int lun, int ctx2abort, ulong timeout); 130 130 extern u8 mptscsih_raid_id_to_num(MPT_ADAPTER *ioc, u8 channel, u8 id); 131 131 extern int mptscsih_is_phys_disk(MPT_ADAPTER *ioc, u8 channel, u8 id); 132 + extern struct class_device_attribute *mptscsih_host_attrs[];

+8 -1

drivers/message/fusion/mptspi.c

··· 821 821 .max_sectors = 8192, 822 822 .cmd_per_lun = 7, 823 823 .use_clustering = ENABLE_CLUSTERING, 824 + .shost_attrs = mptscsih_host_attrs, 824 825 }; 825 826 826 827 static int mptspi_write_spi_device_pg1(struct scsi_target *starget, ··· 1524 1523 static int __init 1525 1524 mptspi_init(void) 1526 1525 { 1526 + int error; 1527 + 1527 1528 show_mptmod_ver(my_NAME, my_VERSION); 1528 1529 1529 1530 mptspi_transport_template = spi_attach_transport(&mptspi_transport_functions); ··· 1546 1543 ": Registered for IOC reset notifications\n")); 1547 1544 } 1548 1545 1549 - return pci_register_driver(&mptspi_driver); 1546 + error = pci_register_driver(&mptspi_driver); 1547 + if (error) 1548 + spi_release_transport(mptspi_transport_template); 1549 + 1550 + return error; 1550 1551 } 1551 1552 1552 1553 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/

+3 -6

drivers/s390/scsi/zfcp_aux.c

··· 1526 1526 * zfcp_gid_pn_buffers_free - free buffers for GID_PN nameserver request 1527 1527 * @gid_pn: pointer to struct zfcp_gid_pn_data which has to be freed 1528 1528 */ 1529 - static void 1530 - zfcp_gid_pn_buffers_free(struct zfcp_gid_pn_data *gid_pn) 1529 + static void zfcp_gid_pn_buffers_free(struct zfcp_gid_pn_data *gid_pn) 1531 1530 { 1532 - if ((gid_pn->ct.pool != 0)) 1531 + if (gid_pn->ct.pool) 1533 1532 mempool_free(gid_pn, gid_pn->ct.pool); 1534 1533 else 1535 - kfree(gid_pn); 1536 - 1537 - return; 1534 + kfree(gid_pn); 1538 1535 } 1539 1536 1540 1537 /**

+1

drivers/s390/scsi/zfcp_def.h

··· 126 126 #define ZFCP_MIN_OUTPUT_THRESHOLD 1 /* ignored by QDIO layer */ 127 127 128 128 #define QDIO_SCSI_QFMT 1 /* 1 for FSF */ 129 + #define QBUFF_PER_PAGE (PAGE_SIZE / sizeof(struct qdio_buffer)) 129 130 130 131 /********************* FSF SPECIFIC DEFINES *********************************/ 131 132

+1 -2

drivers/s390/scsi/zfcp_erp.c

··· 1626 1626 { 1627 1627 struct zfcp_erp_add_work *p; 1628 1628 1629 - p = kmalloc(sizeof(*p), GFP_KERNEL); 1629 + p = kzalloc(sizeof(*p), GFP_KERNEL); 1630 1630 if (!p) { 1631 1631 ZFCP_LOG_NORMAL("error: Out of resources. Could not register " 1632 1632 "the FCP-LUN 0x%Lx connected to " ··· 1639 1639 } 1640 1640 1641 1641 zfcp_unit_get(unit); 1642 - memset(p, 0, sizeof(*p)); 1643 1642 atomic_set_mask(ZFCP_STATUS_UNIT_SCSI_WORK_PENDING, &unit->status); 1644 1643 INIT_WORK(&p->work, zfcp_erp_scsi_scan); 1645 1644 p->unit = unit;

+1 -1

drivers/s390/scsi/zfcp_fsf.c

··· 1930 1930 skip_fsfstatus: 1931 1931 send_els->status = retval; 1932 1932 1933 - if (send_els->handler != 0) 1933 + if (send_els->handler) 1934 1934 send_els->handler(send_els->handler_data); 1935 1935 1936 1936 return retval;

+37 -86

drivers/s390/scsi/zfcp_qdio.c

··· 47 47 #define ZFCP_LOG_AREA ZFCP_LOG_AREA_QDIO 48 48 49 49 /* 50 - * Allocates BUFFER memory to each of the pointers of the qdio_buffer_t 51 - * array in the adapter struct. 52 - * Cur_buf is the pointer array and count can be any number of required 53 - * buffers, the page-fitting arithmetic is done entirely within this funciton. 54 - * 55 - * returns: number of buffers allocated 56 - * locks: must only be called with zfcp_data.config_sema taken 57 - */ 58 - static int 59 - zfcp_qdio_buffers_enqueue(struct qdio_buffer **cur_buf, int count) 60 - { 61 - int buf_pos; 62 - int qdio_buffers_per_page; 63 - int page_pos = 0; 64 - struct qdio_buffer *first_in_page = NULL; 65 - 66 - qdio_buffers_per_page = PAGE_SIZE / sizeof (struct qdio_buffer); 67 - ZFCP_LOG_TRACE("buffers_per_page=%d\n", qdio_buffers_per_page); 68 - 69 - for (buf_pos = 0; buf_pos < count; buf_pos++) { 70 - if (page_pos == 0) { 71 - cur_buf[buf_pos] = (struct qdio_buffer *) 72 - get_zeroed_page(GFP_KERNEL); 73 - if (cur_buf[buf_pos] == NULL) { 74 - ZFCP_LOG_INFO("error: allocation of " 75 - "QDIO buffer failed \n"); 76 - goto out; 77 - } 78 - first_in_page = cur_buf[buf_pos]; 79 - } else { 80 - cur_buf[buf_pos] = first_in_page + page_pos; 81 - 82 - } 83 - /* was initialised to zero */ 84 - page_pos++; 85 - page_pos %= qdio_buffers_per_page; 86 - } 87 - out: 88 - return buf_pos; 89 - } 90 - 91 - /* 92 50 * Frees BUFFER memory for each of the pointers of the struct qdio_buffer array 93 - * in the adapter struct cur_buf is the pointer array and count can be any 94 - * number of buffers in the array that should be freed starting from buffer 0 51 + * in the adapter struct sbuf is the pointer array. 95 52 * 96 53 * locks: must only be called with zfcp_data.config_sema taken 97 54 */ 98 55 static void 99 - zfcp_qdio_buffers_dequeue(struct qdio_buffer **cur_buf, int count) 56 + zfcp_qdio_buffers_dequeue(struct qdio_buffer **sbuf) 100 57 { 101 - int buf_pos; 102 - int qdio_buffers_per_page; 58 + int pos; 103 59 104 - qdio_buffers_per_page = PAGE_SIZE / sizeof (struct qdio_buffer); 105 - ZFCP_LOG_TRACE("buffers_per_page=%d\n", qdio_buffers_per_page); 60 + for (pos = 0; pos < QDIO_MAX_BUFFERS_PER_Q; pos += QBUFF_PER_PAGE) 61 + free_page((unsigned long) sbuf[pos]); 62 + } 106 63 107 - for (buf_pos = 0; buf_pos < count; buf_pos += qdio_buffers_per_page) 108 - free_page((unsigned long) cur_buf[buf_pos]); 109 - return; 64 + /* 65 + * Allocates BUFFER memory to each of the pointers of the qdio_buffer_t 66 + * array in the adapter struct. 67 + * Cur_buf is the pointer array 68 + * 69 + * returns: zero on success else -ENOMEM 70 + * locks: must only be called with zfcp_data.config_sema taken 71 + */ 72 + static int 73 + zfcp_qdio_buffers_enqueue(struct qdio_buffer **sbuf) 74 + { 75 + int pos; 76 + 77 + for (pos = 0; pos < QDIO_MAX_BUFFERS_PER_Q; pos += QBUFF_PER_PAGE) { 78 + sbuf[pos] = (struct qdio_buffer *) get_zeroed_page(GFP_KERNEL); 79 + if (!sbuf[pos]) { 80 + zfcp_qdio_buffers_dequeue(sbuf); 81 + return -ENOMEM; 82 + } 83 + } 84 + for (pos = 0; pos < QDIO_MAX_BUFFERS_PER_Q; pos++) 85 + if (pos % QBUFF_PER_PAGE) 86 + sbuf[pos] = sbuf[pos - 1] + 1; 87 + return 0; 110 88 } 111 89 112 90 /* locks: must only be called with zfcp_data.config_sema taken */ 113 91 int 114 92 zfcp_qdio_allocate_queues(struct zfcp_adapter *adapter) 115 93 { 116 - int buffer_count; 117 - int retval = 0; 94 + int ret; 118 95 119 - buffer_count = 120 - zfcp_qdio_buffers_enqueue(&(adapter->request_queue.buffer[0]), 121 - QDIO_MAX_BUFFERS_PER_Q); 122 - if (buffer_count < QDIO_MAX_BUFFERS_PER_Q) { 123 - ZFCP_LOG_DEBUG("only %d QDIO buffers allocated for request " 124 - "queue\n", buffer_count); 125 - zfcp_qdio_buffers_dequeue(&(adapter->request_queue.buffer[0]), 126 - buffer_count); 127 - retval = -ENOMEM; 128 - goto out; 129 - } 130 - 131 - buffer_count = 132 - zfcp_qdio_buffers_enqueue(&(adapter->response_queue.buffer[0]), 133 - QDIO_MAX_BUFFERS_PER_Q); 134 - if (buffer_count < QDIO_MAX_BUFFERS_PER_Q) { 135 - ZFCP_LOG_DEBUG("only %d QDIO buffers allocated for response " 136 - "queue", buffer_count); 137 - zfcp_qdio_buffers_dequeue(&(adapter->response_queue.buffer[0]), 138 - buffer_count); 139 - ZFCP_LOG_TRACE("freeing request_queue buffers\n"); 140 - zfcp_qdio_buffers_dequeue(&(adapter->request_queue.buffer[0]), 141 - QDIO_MAX_BUFFERS_PER_Q); 142 - retval = -ENOMEM; 143 - goto out; 144 - } 145 - out: 146 - return retval; 96 + ret = zfcp_qdio_buffers_enqueue(adapter->request_queue.buffer); 97 + if (ret) 98 + return ret; 99 + return zfcp_qdio_buffers_enqueue(adapter->response_queue.buffer); 147 100 } 148 101 149 102 /* locks: must only be called with zfcp_data.config_sema taken */ ··· 104 151 zfcp_qdio_free_queues(struct zfcp_adapter *adapter) 105 152 { 106 153 ZFCP_LOG_TRACE("freeing request_queue buffers\n"); 107 - zfcp_qdio_buffers_dequeue(&(adapter->request_queue.buffer[0]), 108 - QDIO_MAX_BUFFERS_PER_Q); 154 + zfcp_qdio_buffers_dequeue(adapter->request_queue.buffer); 109 155 110 156 ZFCP_LOG_TRACE("freeing response_queue buffers\n"); 111 - zfcp_qdio_buffers_dequeue(&(adapter->response_queue.buffer[0]), 112 - QDIO_MAX_BUFFERS_PER_Q); 157 + zfcp_qdio_buffers_dequeue(adapter->response_queue.buffer); 113 158 } 114 159 115 160 int

+41 -26

drivers/scsi/3w-9xxx.c

··· 4 4 Written By: Adam Radford <linuxraid@amcc.com> 5 5 Modifications By: Tom Couch <linuxraid@amcc.com> 6 6 7 - Copyright (C) 2004-2006 Applied Micro Circuits Corporation. 7 + Copyright (C) 2004-2007 Applied Micro Circuits Corporation. 8 8 9 9 This program is free software; you can redistribute it and/or modify 10 10 it under the terms of the GNU General Public License as published by ··· 69 69 2.26.02.008 - Free irq handler in __twa_shutdown(). 70 70 Serialize reset code. 71 71 Add support for 9650SE controllers. 72 + 2.26.02.009 - Fix dma mask setting to fallback to 32-bit if 64-bit fails. 73 + 2.26.02.010 - Add support for 9690SA controllers. 72 74 */ 73 75 74 76 #include <linux/module.h> ··· 94 92 #include "3w-9xxx.h" 95 93 96 94 /* Globals */ 97 - #define TW_DRIVER_VERSION "2.26.02.008" 95 + #define TW_DRIVER_VERSION "2.26.02.010" 98 96 static TW_Device_Extension *twa_device_extension_list[TW_MAX_SLOT]; 99 97 static unsigned int twa_device_extension_count; 100 98 static int twa_major = -1; ··· 126 124 unsigned short *fw_on_ctlr_branch, 127 125 unsigned short *fw_on_ctlr_build, 128 126 u32 *init_connect_result); 129 - static void twa_load_sgl(TW_Command_Full *full_command_packet, int request_id, dma_addr_t dma_handle, int length); 127 + static void twa_load_sgl(TW_Device_Extension *tw_dev, TW_Command_Full *full_command_packet, int request_id, dma_addr_t dma_handle, int length); 130 128 static int twa_poll_response(TW_Device_Extension *tw_dev, int request_id, int seconds); 131 129 static int twa_poll_status_gone(TW_Device_Extension *tw_dev, u32 flag, int seconds); 132 130 static int twa_post_command_packet(TW_Device_Extension *tw_dev, int request_id, char internal); 133 - static int twa_reset_device_extension(TW_Device_Extension *tw_dev, int ioctl_reset); 131 + static int twa_reset_device_extension(TW_Device_Extension *tw_dev); 134 132 static int twa_reset_sequence(TW_Device_Extension *tw_dev, int soft_reset); 135 133 static int twa_scsiop_execute_scsi(TW_Device_Extension *tw_dev, int request_id, char *cdb, int use_sg, TW_SG_Entry *sglistarg); 136 134 static void twa_scsiop_execute_scsi_complete(TW_Device_Extension *tw_dev, int request_id); ··· 685 683 full_command_packet = &tw_ioctl->firmware_command; 686 684 687 685 /* Load request id and sglist for both command types */ 688 - twa_load_sgl(full_command_packet, request_id, dma_handle, data_buffer_length_adjusted); 686 + twa_load_sgl(tw_dev, full_command_packet, request_id, dma_handle, data_buffer_length_adjusted); 689 687 690 688 memcpy(tw_dev->command_packet_virt[request_id], &(tw_ioctl->firmware_command), sizeof(TW_Command_Full)); 691 689 ··· 702 700 if (tw_dev->chrdev_request_id != TW_IOCTL_CHRDEV_FREE) { 703 701 /* Now we need to reset the board */ 704 702 printk(KERN_WARNING "3w-9xxx: scsi%d: WARNING: (0x%02X:0x%04X): Character ioctl (0x%x) timed out, resetting card.\n", 705 - tw_dev->host->host_no, TW_DRIVER, 0xc, 703 + tw_dev->host->host_no, TW_DRIVER, 0x37, 706 704 cmd); 707 705 retval = TW_IOCTL_ERROR_OS_EIO; 708 - twa_reset_device_extension(tw_dev, 1); 706 + twa_reset_device_extension(tw_dev); 709 707 goto out3; 710 708 } 711 709 ··· 892 890 } 893 891 894 892 if (status_reg_value & TW_STATUS_QUEUE_ERROR) { 895 - if ((tw_dev->tw_pci_dev->device != PCI_DEVICE_ID_3WARE_9650SE) || (!test_bit(TW_IN_RESET, &tw_dev->flags))) 893 + if (((tw_dev->tw_pci_dev->device != PCI_DEVICE_ID_3WARE_9650SE) && 894 + (tw_dev->tw_pci_dev->device != PCI_DEVICE_ID_3WARE_9690SA)) || 895 + (!test_bit(TW_IN_RESET, &tw_dev->flags))) 896 896 TW_PRINTK(tw_dev->host, TW_DRIVER, 0xe, "Controller Queue Error: clearing"); 897 897 writel(TW_CONTROL_CLEAR_QUEUE_ERROR, TW_CONTROL_REG_ADDR(tw_dev)); 898 898 } ··· 939 935 unsigned long before; 940 936 int retval = 1; 941 937 942 - if ((tw_dev->tw_pci_dev->device == PCI_DEVICE_ID_3WARE_9550SX) || 943 - (tw_dev->tw_pci_dev->device == PCI_DEVICE_ID_3WARE_9650SE)) { 938 + if (tw_dev->tw_pci_dev->device != PCI_DEVICE_ID_3WARE_9000) { 944 939 before = jiffies; 945 940 while ((response_que_value & TW_9550SX_DRAIN_COMPLETED) != TW_9550SX_DRAIN_COMPLETED) { 946 941 response_que_value = readl(TW_RESPONSE_QUEUE_REG_ADDR_LARGE(tw_dev)); ··· 1198 1195 u32 status_reg_value; 1199 1196 TW_Response_Queue response_que; 1200 1197 TW_Command_Full *full_command_packet; 1201 - TW_Command *command_packet; 1202 1198 TW_Device_Extension *tw_dev = (TW_Device_Extension *)dev_instance; 1203 1199 int handled = 0; 1204 1200 ··· 1275 1273 request_id = TW_RESID_OUT(response_que.response_id); 1276 1274 full_command_packet = tw_dev->command_packet_virt[request_id]; 1277 1275 error = 0; 1278 - command_packet = &full_command_packet->command.oldcommand; 1279 1276 /* Check for command packet errors */ 1280 1277 if (full_command_packet->command.newcommand.status != 0) { 1281 1278 if (tw_dev->srb[request_id] != 0) { ··· 1353 1352 } /* End twa_interrupt() */ 1354 1353 1355 1354 /* This function will load the request id and various sgls for ioctls */ 1356 - static void twa_load_sgl(TW_Command_Full *full_command_packet, int request_id, dma_addr_t dma_handle, int length) 1355 + static void twa_load_sgl(TW_Device_Extension *tw_dev, TW_Command_Full *full_command_packet, int request_id, dma_addr_t dma_handle, int length) 1357 1356 { 1358 1357 TW_Command *oldcommand; 1359 1358 TW_Command_Apache *newcommand; 1360 1359 TW_SG_Entry *sgl; 1360 + unsigned int pae = 0; 1361 + 1362 + if ((sizeof(long) < 8) && (sizeof(dma_addr_t) > 4)) 1363 + pae = 1; 1361 1364 1362 1365 if (TW_OP_OUT(full_command_packet->command.newcommand.opcode__reserved) == TW_OP_EXECUTE_SCSI) { 1363 1366 newcommand = &full_command_packet->command.newcommand; ··· 1377 1372 1378 1373 if (TW_SGL_OUT(oldcommand->opcode__sgloffset)) { 1379 1374 /* Load the sg list */ 1380 - sgl = (TW_SG_Entry *)((u32 *)oldcommand+TW_SGL_OUT(oldcommand->opcode__sgloffset)); 1375 + if (tw_dev->tw_pci_dev->device == PCI_DEVICE_ID_3WARE_9690SA) 1376 + sgl = (TW_SG_Entry *)((u32 *)oldcommand+oldcommand->size - (sizeof(TW_SG_Entry)/4) + pae); 1377 + else 1378 + sgl = (TW_SG_Entry *)((u32 *)oldcommand+TW_SGL_OUT(oldcommand->opcode__sgloffset)); 1381 1379 sgl->address = TW_CPU_TO_SGL(dma_handle + sizeof(TW_Ioctl_Buf_Apache) - 1); 1382 1380 sgl->length = cpu_to_le32(length); 1383 1381 1384 - if ((sizeof(long) < 8) && (sizeof(dma_addr_t) > 4)) 1385 - oldcommand->size += 1; 1382 + oldcommand->size += pae; 1386 1383 } 1387 1384 } 1388 1385 } /* End twa_load_sgl() */ ··· 1513 1506 command_que_value = tw_dev->command_packet_phys[request_id]; 1514 1507 1515 1508 /* For 9650SE write low 4 bytes first */ 1516 - if (tw_dev->tw_pci_dev->device == PCI_DEVICE_ID_3WARE_9650SE) { 1509 + if ((tw_dev->tw_pci_dev->device == PCI_DEVICE_ID_3WARE_9650SE) || 1510 + (tw_dev->tw_pci_dev->device == PCI_DEVICE_ID_3WARE_9690SA)) { 1517 1511 command_que_value += TW_COMMAND_OFFSET; 1518 1512 writel((u32)command_que_value, TW_COMMAND_QUEUE_REG_ADDR_LARGE(tw_dev)); 1519 1513 } ··· 1545 1537 TW_UNMASK_COMMAND_INTERRUPT(tw_dev); 1546 1538 goto out; 1547 1539 } else { 1548 - if (tw_dev->tw_pci_dev->device == PCI_DEVICE_ID_3WARE_9650SE) { 1540 + if ((tw_dev->tw_pci_dev->device == PCI_DEVICE_ID_3WARE_9650SE) || 1541 + (tw_dev->tw_pci_dev->device == PCI_DEVICE_ID_3WARE_9690SA)) { 1549 1542 /* Now write upper 4 bytes */ 1550 1543 writel((u32)((u64)command_que_value >> 32), TW_COMMAND_QUEUE_REG_ADDR_LARGE(tw_dev) + 0x4); 1551 1544 } else { ··· 1570 1561 } /* End twa_post_command_packet() */ 1571 1562 1572 1563 /* This function will reset a device extension */ 1573 - static int twa_reset_device_extension(TW_Device_Extension *tw_dev, int ioctl_reset) 1564 + static int twa_reset_device_extension(TW_Device_Extension *tw_dev) 1574 1565 { 1575 1566 int i = 0; 1576 1567 int retval = 1; ··· 1728 1719 mutex_lock(&tw_dev->ioctl_lock); 1729 1720 1730 1721 /* Now reset the card and some of the device extension data */ 1731 - if (twa_reset_device_extension(tw_dev, 0)) { 1722 + if (twa_reset_device_extension(tw_dev)) { 1732 1723 TW_PRINTK(tw_dev->host, TW_DRIVER, 0x2b, "Controller reset failed during scsi host reset"); 1733 1724 goto out; 1734 1725 } ··· 2010 2001 2011 2002 pci_set_master(pdev); 2012 2003 2013 - retval = pci_set_dma_mask(pdev, sizeof(dma_addr_t) > 4 ? DMA_64BIT_MASK : DMA_32BIT_MASK); 2014 - if (retval) { 2015 - TW_PRINTK(host, TW_DRIVER, 0x23, "Failed to set dma mask"); 2016 - goto out_disable_device; 2017 - } 2004 + if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) 2005 + || pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) 2006 + if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) 2007 + || pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) { 2008 + TW_PRINTK(host, TW_DRIVER, 0x23, "Failed to set dma mask"); 2009 + retval = -ENODEV; 2010 + goto out_disable_device; 2011 + } 2018 2012 2019 2013 host = scsi_host_alloc(&driver_template, sizeof(TW_Device_Extension)); 2020 2014 if (!host) { ··· 2065 2053 goto out_iounmap; 2066 2054 2067 2055 /* Set host specific parameters */ 2068 - if (pdev->device == PCI_DEVICE_ID_3WARE_9650SE) 2056 + if ((pdev->device == PCI_DEVICE_ID_3WARE_9650SE) || 2057 + (pdev->device == PCI_DEVICE_ID_3WARE_9690SA)) 2069 2058 host->max_id = TW_MAX_UNITS_9650SE; 2070 2059 else 2071 2060 host->max_id = TW_MAX_UNITS; ··· 2172 2159 { PCI_VENDOR_ID_3WARE, PCI_DEVICE_ID_3WARE_9550SX, 2173 2160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2174 2161 { PCI_VENDOR_ID_3WARE, PCI_DEVICE_ID_3WARE_9650SE, 2162 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2163 + { PCI_VENDOR_ID_3WARE, PCI_DEVICE_ID_3WARE_9690SA, 2175 2164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2176 2165 { } 2177 2166 };

+4 -1

drivers/scsi/3w-9xxx.h

··· 4 4 Written By: Adam Radford <linuxraid@amcc.com> 5 5 Modifications By: Tom Couch <linuxraid@amcc.com> 6 6 7 - Copyright (C) 2004-2006 Applied Micro Circuits Corporation. 7 + Copyright (C) 2004-2007 Applied Micro Circuits Corporation. 8 8 9 9 This program is free software; you can redistribute it and/or modify 10 10 it under the terms of the GNU General Public License as published by ··· 418 418 #endif 419 419 #ifndef PCI_DEVICE_ID_3WARE_9650SE 420 420 #define PCI_DEVICE_ID_3WARE_9650SE 0x1004 421 + #endif 422 + #ifndef PCI_DEVICE_ID_3WARE_9690SA 423 + #define PCI_DEVICE_ID_3WARE_9690SA 0x1005 421 424 #endif 422 425 423 426 /* Bitmask macros to eliminate bitfields */

+7 -3

drivers/scsi/Kconfig

··· 282 282 283 283 config SCSI_SAS_ATTRS 284 284 tristate "SAS Transport Attributes" 285 - depends on SCSI 285 + depends on SCSI && BLK_DEV_BSG 286 286 help 287 287 If you wish to export transport-specific information about 288 288 each attached SAS device to sysfs, say Y. ··· 291 291 292 292 endmenu 293 293 294 - menu "SCSI low-level drivers" 294 + menuconfig SCSI_LOWLEVEL 295 + bool "SCSI low-level drivers" 295 296 depends on SCSI!=n 297 + default y 298 + 299 + if SCSI_LOWLEVEL 296 300 297 301 config ISCSI_TCP 298 302 tristate "iSCSI Initiator over TCP/IP" ··· 1804 1800 To compile this driver as a module, choose M here: the 1805 1801 module will be called libsrp. 1806 1802 1807 - endmenu 1803 + endif # SCSI_LOWLEVEL 1808 1804 1809 1805 source "drivers/scsi/pcmcia/Kconfig" 1810 1806

+2 -1

drivers/scsi/a4000t.c

··· 79 79 goto out_put_host; 80 80 } 81 81 82 + dev_set_drvdata(dev, host); 82 83 scsi_scan_host(host); 83 84 84 85 return 0; ··· 96 95 97 96 static __devexit int a4000t_device_remove(struct device *dev) 98 97 { 99 - struct Scsi_Host *host = dev_to_shost(dev); 98 + struct Scsi_Host *host = dev_get_drvdata(dev); 100 99 struct NCR_700_Host_Parameters *hostdata = shost_priv(host); 101 100 102 101 scsi_remove_host(host);

+139 -1

drivers/scsi/aacraid/aachba.c

··· 751 751 inqstrcpy ("V1.0", str->prl); 752 752 } 753 753 754 + static void get_container_serial_callback(void *context, struct fib * fibptr) 755 + { 756 + struct aac_get_serial_resp * get_serial_reply; 757 + struct scsi_cmnd * scsicmd; 758 + 759 + BUG_ON(fibptr == NULL); 760 + 761 + scsicmd = (struct scsi_cmnd *) context; 762 + if (!aac_valid_context(scsicmd, fibptr)) 763 + return; 764 + 765 + get_serial_reply = (struct aac_get_serial_resp *) fib_data(fibptr); 766 + /* Failure is irrelevant, using default value instead */ 767 + if (le32_to_cpu(get_serial_reply->status) == CT_OK) { 768 + char sp[13]; 769 + /* EVPD bit set */ 770 + sp[0] = INQD_PDT_DA; 771 + sp[1] = scsicmd->cmnd[2]; 772 + sp[2] = 0; 773 + sp[3] = snprintf(sp+4, sizeof(sp)-4, "%08X", 774 + le32_to_cpu(get_serial_reply->uid)); 775 + aac_internal_transfer(scsicmd, sp, 0, sizeof(sp)); 776 + } 777 + 778 + scsicmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8 | SAM_STAT_GOOD; 779 + 780 + aac_fib_complete(fibptr); 781 + aac_fib_free(fibptr); 782 + scsicmd->scsi_done(scsicmd); 783 + } 784 + 785 + /** 786 + * aac_get_container_serial - get container serial, none blocking. 787 + */ 788 + static int aac_get_container_serial(struct scsi_cmnd * scsicmd) 789 + { 790 + int status; 791 + struct aac_get_serial *dinfo; 792 + struct fib * cmd_fibcontext; 793 + struct aac_dev * dev; 794 + 795 + dev = (struct aac_dev *)scsicmd->device->host->hostdata; 796 + 797 + if (!(cmd_fibcontext = aac_fib_alloc(dev))) 798 + return -ENOMEM; 799 + 800 + aac_fib_init(cmd_fibcontext); 801 + dinfo = (struct aac_get_serial *) fib_data(cmd_fibcontext); 802 + 803 + dinfo->command = cpu_to_le32(VM_ContainerConfig); 804 + dinfo->type = cpu_to_le32(CT_CID_TO_32BITS_UID); 805 + dinfo->cid = cpu_to_le32(scmd_id(scsicmd)); 806 + 807 + status = aac_fib_send(ContainerCommand, 808 + cmd_fibcontext, 809 + sizeof (struct aac_get_serial), 810 + FsaNormal, 811 + 0, 1, 812 + (fib_callback) get_container_serial_callback, 813 + (void *) scsicmd); 814 + 815 + /* 816 + * Check that the command queued to the controller 817 + */ 818 + if (status == -EINPROGRESS) { 819 + scsicmd->SCp.phase = AAC_OWNER_FIRMWARE; 820 + return 0; 821 + } 822 + 823 + printk(KERN_WARNING "aac_get_container_serial: aac_fib_send failed with status: %d.\n", status); 824 + aac_fib_complete(cmd_fibcontext); 825 + aac_fib_free(cmd_fibcontext); 826 + return -1; 827 + } 828 + 829 + /* Function: setinqserial 830 + * 831 + * Arguments: [1] pointer to void [1] int 832 + * 833 + * Purpose: Sets SCSI Unit Serial number. 834 + * This is a fake. We should read a proper 835 + * serial number from the container. <SuSE>But 836 + * without docs it's quite hard to do it :-) 837 + * So this will have to do in the meantime.</SuSE> 838 + */ 839 + 840 + static int setinqserial(struct aac_dev *dev, void *data, int cid) 841 + { 842 + /* 843 + * This breaks array migration. 844 + */ 845 + return snprintf((char *)(data), sizeof(struct scsi_inq) - 4, "%08X%02X", 846 + le32_to_cpu(dev->adapter_info.serial[0]), cid); 847 + } 848 + 754 849 static void set_sense(u8 *sense_buf, u8 sense_key, u8 sense_code, 755 850 u8 a_sense_code, u8 incorrect_length, 756 851 u8 bit_pointer, u16 field_pointer, ··· 1893 1798 dprintk((KERN_DEBUG "INQUIRY command, ID: %d.\n", cid)); 1894 1799 memset(&inq_data, 0, sizeof (struct inquiry_data)); 1895 1800 1801 + if (scsicmd->cmnd[1] & 0x1 ) { 1802 + char *arr = (char *)&inq_data; 1803 + 1804 + /* EVPD bit set */ 1805 + arr[0] = (scmd_id(scsicmd) == host->this_id) ? 1806 + INQD_PDT_PROC : INQD_PDT_DA; 1807 + if (scsicmd->cmnd[2] == 0) { 1808 + /* supported vital product data pages */ 1809 + arr[3] = 2; 1810 + arr[4] = 0x0; 1811 + arr[5] = 0x80; 1812 + arr[1] = scsicmd->cmnd[2]; 1813 + aac_internal_transfer(scsicmd, &inq_data, 0, 1814 + sizeof(inq_data)); 1815 + scsicmd->result = DID_OK << 16 | 1816 + COMMAND_COMPLETE << 8 | SAM_STAT_GOOD; 1817 + } else if (scsicmd->cmnd[2] == 0x80) { 1818 + /* unit serial number page */ 1819 + arr[3] = setinqserial(dev, &arr[4], 1820 + scmd_id(scsicmd)); 1821 + arr[1] = scsicmd->cmnd[2]; 1822 + aac_internal_transfer(scsicmd, &inq_data, 0, 1823 + sizeof(inq_data)); 1824 + return aac_get_container_serial(scsicmd); 1825 + } else { 1826 + /* vpd page not implemented */ 1827 + scsicmd->result = DID_OK << 16 | 1828 + COMMAND_COMPLETE << 8 | 1829 + SAM_STAT_CHECK_CONDITION; 1830 + set_sense((u8 *) &dev->fsa_dev[cid].sense_data, 1831 + ILLEGAL_REQUEST, 1832 + SENCODE_INVALID_CDB_FIELD, 1833 + ASENCODE_NO_SENSE, 0, 7, 2, 0); 1834 + memcpy(scsicmd->sense_buffer, 1835 + &dev->fsa_dev[cid].sense_data, 1836 + (sizeof(dev->fsa_dev[cid].sense_data) > 1837 + sizeof(scsicmd->sense_buffer)) 1838 + ? sizeof(scsicmd->sense_buffer) 1839 + : sizeof(dev->fsa_dev[cid].sense_data)); 1840 + } 1841 + scsicmd->scsi_done(scsicmd); 1842 + return 0; 1843 + } 1896 1844 inq_data.inqd_ver = 2; /* claim compliance to SCSI-2 */ 1897 1845 inq_data.inqd_rdf = 2; /* A response data format value of two indicates that the data shall be in the format specified in SCSI-2 */ 1898 1846 inq_data.inqd_len = 31; ··· 2208 2070 } 2209 2071 else return -EINVAL; 2210 2072 2211 - qd.valid = fsa_dev_ptr[qd.cnum].valid; 2073 + qd.valid = fsa_dev_ptr[qd.cnum].valid != 0; 2212 2074 qd.locked = fsa_dev_ptr[qd.cnum].locked; 2213 2075 qd.deleted = fsa_dev_ptr[qd.cnum].deleted; 2214 2076

+14

drivers/scsi/aacraid/aacraid.h

··· 1567 1567 u8 data[16]; 1568 1568 }; 1569 1569 1570 + #define CT_CID_TO_32BITS_UID 165 1571 + struct aac_get_serial { 1572 + __le32 command; /* VM_ContainerConfig */ 1573 + __le32 type; /* CT_CID_TO_32BITS_UID */ 1574 + __le32 cid; 1575 + }; 1576 + 1577 + struct aac_get_serial_resp { 1578 + __le32 dummy0; 1579 + __le32 dummy1; 1580 + __le32 status; /* CT_OK */ 1581 + __le32 uid; 1582 + }; 1583 + 1570 1584 /* 1571 1585 * The following command is sent to shut down each container. 1572 1586 */

+9 -7

drivers/scsi/aacraid/commsup.c

··· 80 80 81 81 void aac_fib_map_free(struct aac_dev *dev) 82 82 { 83 - pci_free_consistent(dev->pdev, dev->max_fib_size * (dev->scsi_host_ptr->can_queue + AAC_NUM_MGT_FIB), dev->hw_fib_va, dev->hw_fib_pa); 83 + pci_free_consistent(dev->pdev, 84 + dev->max_fib_size * (dev->scsi_host_ptr->can_queue + AAC_NUM_MGT_FIB), 85 + dev->hw_fib_va, dev->hw_fib_pa); 86 + dev->hw_fib_va = NULL; 87 + dev->hw_fib_pa = 0; 84 88 } 85 89 86 90 /** ··· 1091 1087 * case. 1092 1088 */ 1093 1089 aac_fib_map_free(aac); 1094 - aac->hw_fib_va = NULL; 1095 - aac->hw_fib_pa = 0; 1096 1090 pci_free_consistent(aac->pdev, aac->comm_size, aac->comm_addr, aac->comm_phys); 1097 1091 aac->comm_addr = NULL; 1098 1092 aac->comm_phys = 0; ··· 1100 1098 kfree(aac->fsa_dev); 1101 1099 aac->fsa_dev = NULL; 1102 1100 if (aac_get_driver_ident(index)->quirks & AAC_QUIRK_31BIT) { 1103 - if (((retval = pci_set_dma_mask(aac->pdev, DMA_32BIT_MASK))) || 1104 - ((retval = pci_set_consistent_dma_mask(aac->pdev, DMA_32BIT_MASK)))) 1101 + if (((retval = pci_set_dma_mask(aac->pdev, DMA_31BIT_MASK))) || 1102 + ((retval = pci_set_consistent_dma_mask(aac->pdev, DMA_31BIT_MASK)))) 1105 1103 goto out; 1106 1104 } else { 1107 - if (((retval = pci_set_dma_mask(aac->pdev, 0x7FFFFFFFULL))) || 1108 - ((retval = pci_set_consistent_dma_mask(aac->pdev, 0x7FFFFFFFULL)))) 1105 + if (((retval = pci_set_dma_mask(aac->pdev, DMA_32BIT_MASK))) || 1106 + ((retval = pci_set_consistent_dma_mask(aac->pdev, DMA_32BIT_MASK)))) 1109 1107 goto out; 1110 1108 } 1111 1109 if ((retval = (*(aac_get_driver_ident(index)->init))(aac)))

+1 -1

drivers/scsi/aic94xx/aic94xx_dev.c

··· 126 126 if (w76 & 0x100) /* NCQ? */ 127 127 qdepth = (w75 & 0x1F) + 1; 128 128 asd_ddbsite_write_dword(asd_ha, ddb, SATA_TAG_ALLOC_MASK, 129 - (1<<qdepth)-1); 129 + (1ULL<<qdepth)-1); 130 130 asd_ddbsite_write_byte(asd_ha, ddb, NUM_SATA_TAGS, qdepth); 131 131 } 132 132 if (dev->dev_type == SATA_DEV || dev->dev_type == SATA_PM ||

+3

drivers/scsi/aic94xx/aic94xx_init.c

··· 81 81 .use_clustering = ENABLE_CLUSTERING, 82 82 .eh_device_reset_handler = sas_eh_device_reset_handler, 83 83 .eh_bus_reset_handler = sas_eh_bus_reset_handler, 84 + .slave_alloc = sas_slave_alloc, 85 + .target_destroy = sas_target_destroy, 86 + .ioctl = sas_ioctl, 84 87 }; 85 88 86 89 static int __devinit asd_map_memio(struct asd_ha_struct *asd_ha)

+13 -7

drivers/scsi/aic94xx/aic94xx_task.c

··· 74 74 return 0; 75 75 } 76 76 77 - num_sg = pci_map_sg(asd_ha->pcidev, task->scatter, task->num_scatter, 78 - task->data_dir); 77 + /* STP tasks come from libata which has already mapped 78 + * the SG list */ 79 + if (sas_protocol_ata(task->task_proto)) 80 + num_sg = task->num_scatter; 81 + else 82 + num_sg = pci_map_sg(asd_ha->pcidev, task->scatter, 83 + task->num_scatter, task->data_dir); 79 84 if (num_sg == 0) 80 85 return -ENOMEM; 81 86 ··· 125 120 126 121 return 0; 127 122 err_unmap: 128 - pci_unmap_sg(asd_ha->pcidev, task->scatter, task->num_scatter, 129 - task->data_dir); 123 + if (sas_protocol_ata(task->task_proto)) 124 + pci_unmap_sg(asd_ha->pcidev, task->scatter, task->num_scatter, 125 + task->data_dir); 130 126 return res; 131 127 } 132 128 ··· 148 142 } 149 143 150 144 asd_free_coherent(asd_ha, ascb->sg_arr); 151 - pci_unmap_sg(asd_ha->pcidev, task->scatter, task->num_scatter, 152 - task->data_dir); 145 + if (task->task_proto != SAS_PROTOCOL_STP) 146 + pci_unmap_sg(asd_ha->pcidev, task->scatter, task->num_scatter, 147 + task->data_dir); 153 148 } 154 149 155 150 /* ---------- Task complete tasklet ---------- */ ··· 398 391 399 392 scb->ata_task.total_xfer_len = cpu_to_le32(task->total_xfer_len); 400 393 scb->ata_task.fis = task->ata_task.fis; 401 - scb->ata_task.fis.fis_type = 0x27; 402 394 if (likely(!task->ata_task.device_control_reg_update)) 403 395 scb->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 404 396 scb->ata_task.fis.flags &= 0xF0; /* PM_PORT field shall be 0 */

+2 -1

drivers/scsi/bvme6000_scsi.c

··· 74 74 goto out_put_host; 75 75 } 76 76 77 + dev_set_drvdata(dev, host); 77 78 scsi_scan_host(host); 78 79 79 80 return 0; ··· 90 89 static __devexit int 91 90 bvme6000_device_remove(struct device *dev) 92 91 { 93 - struct Scsi_Host *host = dev_to_shost(dev); 92 + struct Scsi_Host *host = dev_get_drvdata(dev); 94 93 struct NCR_700_Host_Parameters *hostdata = shost_priv(host); 95 94 96 95 scsi_remove_host(host);

+1 -1

drivers/scsi/esp_scsi.h

··· 220 220 #define ESP_BUSID_RESELID 0x10 221 221 #define ESP_BUSID_CTR32BIT 0x40 222 222 223 - #define ESP_BUS_TIMEOUT 250 /* In milli-seconds */ 223 + #define ESP_BUS_TIMEOUT 275 /* In milli-seconds */ 224 224 #define ESP_TIMEO_CONST 8192 225 225 #define ESP_NEG_DEFP(mhz, cfact) \ 226 226 ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))

+7

drivers/scsi/libsas/Kconfig

··· 30 30 This provides transport specific helpers for SAS drivers which 31 31 use the domain device construct (like the aic94xxx). 32 32 33 + config SCSI_SAS_ATA 34 + bool "ATA support for libsas (requires libata)" 35 + depends on SCSI_SAS_LIBSAS && ATA 36 + help 37 + Builds in ATA support into libsas. Will necessitate 38 + the loading of libata along with libsas. 39 + 33 40 config SCSI_SAS_LIBSAS_DEBUG 34 41 bool "Compile the SAS Domain Transport Attributes in debug mode" 35 42 default y

+1

drivers/scsi/libsas/Makefile

··· 34 34 sas_discover.o \ 35 35 sas_expander.o \ 36 36 sas_scsi_host.o 37 + libsas-$(CONFIG_SCSI_SAS_ATA) += sas_ata.o

+817

drivers/scsi/libsas/sas_ata.c

··· 1 + /* 2 + * Support for SATA devices on Serial Attached SCSI (SAS) controllers 3 + * 4 + * Copyright (C) 2006 IBM Corporation 5 + * 6 + * Written by: Darrick J. Wong <djwong@us.ibm.com>, IBM Corporation 7 + * 8 + * This program is free software; you can redistribute it and/or 9 + * modify it under the terms of the GNU General Public License as 10 + * published by the Free Software Foundation; either version 2 of the 11 + * License, or (at your option) any later version. 12 + * 13 + * This program is distributed in the hope that it will be useful, but 14 + * WITHOUT ANY WARRANTY; without even the implied warranty of 15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 + * General Public License for more details. 17 + * 18 + * You should have received a copy of the GNU General Public License 19 + * along with this program; if not, write to the Free Software 20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 21 + * USA 22 + */ 23 + 24 + #include <linux/scatterlist.h> 25 + 26 + #include <scsi/sas_ata.h> 27 + #include "sas_internal.h" 28 + #include <scsi/scsi_host.h> 29 + #include <scsi/scsi_device.h> 30 + #include <scsi/scsi_tcq.h> 31 + #include <scsi/scsi.h> 32 + #include <scsi/scsi_transport.h> 33 + #include <scsi/scsi_transport_sas.h> 34 + #include "../scsi_sas_internal.h" 35 + #include "../scsi_transport_api.h" 36 + #include <scsi/scsi_eh.h> 37 + 38 + static enum ata_completion_errors sas_to_ata_err(struct task_status_struct *ts) 39 + { 40 + /* Cheesy attempt to translate SAS errors into ATA. Hah! */ 41 + 42 + /* transport error */ 43 + if (ts->resp == SAS_TASK_UNDELIVERED) 44 + return AC_ERR_ATA_BUS; 45 + 46 + /* ts->resp == SAS_TASK_COMPLETE */ 47 + /* task delivered, what happened afterwards? */ 48 + switch (ts->stat) { 49 + case SAS_DEV_NO_RESPONSE: 50 + return AC_ERR_TIMEOUT; 51 + 52 + case SAS_INTERRUPTED: 53 + case SAS_PHY_DOWN: 54 + case SAS_NAK_R_ERR: 55 + return AC_ERR_ATA_BUS; 56 + 57 + 58 + case SAS_DATA_UNDERRUN: 59 + /* 60 + * Some programs that use the taskfile interface 61 + * (smartctl in particular) can cause underrun 62 + * problems. Ignore these errors, perhaps at our 63 + * peril. 64 + */ 65 + return 0; 66 + 67 + case SAS_DATA_OVERRUN: 68 + case SAS_QUEUE_FULL: 69 + case SAS_DEVICE_UNKNOWN: 70 + case SAS_SG_ERR: 71 + return AC_ERR_INVALID; 72 + 73 + case SAM_CHECK_COND: 74 + case SAS_OPEN_TO: 75 + case SAS_OPEN_REJECT: 76 + SAS_DPRINTK("%s: Saw error %d. What to do?\n", 77 + __FUNCTION__, ts->stat); 78 + return AC_ERR_OTHER; 79 + 80 + case SAS_ABORTED_TASK: 81 + return AC_ERR_DEV; 82 + 83 + case SAS_PROTO_RESPONSE: 84 + /* This means the ending_fis has the error 85 + * value; return 0 here to collect it */ 86 + return 0; 87 + default: 88 + return 0; 89 + } 90 + } 91 + 92 + static void sas_ata_task_done(struct sas_task *task) 93 + { 94 + struct ata_queued_cmd *qc = task->uldd_task; 95 + struct domain_device *dev; 96 + struct task_status_struct *stat = &task->task_status; 97 + struct ata_task_resp *resp = (struct ata_task_resp *)stat->buf; 98 + struct sas_ha_struct *sas_ha; 99 + enum ata_completion_errors ac; 100 + unsigned long flags; 101 + 102 + if (!qc) 103 + goto qc_already_gone; 104 + 105 + dev = qc->ap->private_data; 106 + sas_ha = dev->port->ha; 107 + 108 + spin_lock_irqsave(dev->sata_dev.ap->lock, flags); 109 + if (stat->stat == SAS_PROTO_RESPONSE || stat->stat == SAM_GOOD) { 110 + ata_tf_from_fis(resp->ending_fis, &dev->sata_dev.tf); 111 + qc->err_mask |= ac_err_mask(dev->sata_dev.tf.command); 112 + dev->sata_dev.sstatus = resp->sstatus; 113 + dev->sata_dev.serror = resp->serror; 114 + dev->sata_dev.scontrol = resp->scontrol; 115 + } else if (stat->stat != SAM_STAT_GOOD) { 116 + ac = sas_to_ata_err(stat); 117 + if (ac) { 118 + SAS_DPRINTK("%s: SAS error %x\n", __FUNCTION__, 119 + stat->stat); 120 + /* We saw a SAS error. Send a vague error. */ 121 + qc->err_mask = ac; 122 + dev->sata_dev.tf.feature = 0x04; /* status err */ 123 + dev->sata_dev.tf.command = ATA_ERR; 124 + } 125 + } 126 + 127 + qc->lldd_task = NULL; 128 + if (qc->scsicmd) 129 + ASSIGN_SAS_TASK(qc->scsicmd, NULL); 130 + ata_qc_complete(qc); 131 + spin_unlock_irqrestore(dev->sata_dev.ap->lock, flags); 132 + 133 + /* 134 + * If the sas_task has an ata qc, a scsi_cmnd and the aborted 135 + * flag is set, then we must have come in via the libsas EH 136 + * functions. When we exit this function, we need to put the 137 + * scsi_cmnd on the list of finished errors. The ata_qc_complete 138 + * call cleans up the libata side of things but we're protected 139 + * from the scsi_cmnd going away because the scsi_cmnd is owned 140 + * by the EH, making libata's call to scsi_done a NOP. 141 + */ 142 + spin_lock_irqsave(&task->task_state_lock, flags); 143 + if (qc->scsicmd && task->task_state_flags & SAS_TASK_STATE_ABORTED) 144 + scsi_eh_finish_cmd(qc->scsicmd, &sas_ha->eh_done_q); 145 + spin_unlock_irqrestore(&task->task_state_lock, flags); 146 + 147 + qc_already_gone: 148 + list_del_init(&task->list); 149 + sas_free_task(task); 150 + } 151 + 152 + static unsigned int sas_ata_qc_issue(struct ata_queued_cmd *qc) 153 + { 154 + int res; 155 + struct sas_task *task; 156 + struct domain_device *dev = qc->ap->private_data; 157 + struct sas_ha_struct *sas_ha = dev->port->ha; 158 + struct Scsi_Host *host = sas_ha->core.shost; 159 + struct sas_internal *i = to_sas_internal(host->transportt); 160 + struct scatterlist *sg; 161 + unsigned int num = 0; 162 + unsigned int xfer = 0; 163 + 164 + task = sas_alloc_task(GFP_ATOMIC); 165 + if (!task) 166 + return AC_ERR_SYSTEM; 167 + task->dev = dev; 168 + task->task_proto = SAS_PROTOCOL_STP; 169 + task->task_done = sas_ata_task_done; 170 + 171 + if (qc->tf.command == ATA_CMD_FPDMA_WRITE || 172 + qc->tf.command == ATA_CMD_FPDMA_READ) { 173 + /* Need to zero out the tag libata assigned us */ 174 + qc->tf.nsect = 0; 175 + } 176 + 177 + ata_tf_to_fis(&qc->tf, 1, 0, (u8*)&task->ata_task.fis); 178 + task->uldd_task = qc; 179 + if (is_atapi_taskfile(&qc->tf)) { 180 + memcpy(task->ata_task.atapi_packet, qc->cdb, qc->dev->cdb_len); 181 + task->total_xfer_len = qc->nbytes + qc->pad_len; 182 + task->num_scatter = qc->pad_len ? qc->n_elem + 1 : qc->n_elem; 183 + } else { 184 + ata_for_each_sg(sg, qc) { 185 + num++; 186 + xfer += sg->length; 187 + } 188 + 189 + task->total_xfer_len = xfer; 190 + task->num_scatter = num; 191 + } 192 + 193 + task->data_dir = qc->dma_dir; 194 + task->scatter = qc->__sg; 195 + task->ata_task.retry_count = 1; 196 + task->task_state_flags = SAS_TASK_STATE_PENDING; 197 + qc->lldd_task = task; 198 + 199 + switch (qc->tf.protocol) { 200 + case ATA_PROT_NCQ: 201 + task->ata_task.use_ncq = 1; 202 + /* fall through */ 203 + case ATA_PROT_ATAPI_DMA: 204 + case ATA_PROT_DMA: 205 + task->ata_task.dma_xfer = 1; 206 + break; 207 + } 208 + 209 + if (qc->scsicmd) 210 + ASSIGN_SAS_TASK(qc->scsicmd, task); 211 + 212 + if (sas_ha->lldd_max_execute_num < 2) 213 + res = i->dft->lldd_execute_task(task, 1, GFP_ATOMIC); 214 + else 215 + res = sas_queue_up(task); 216 + 217 + /* Examine */ 218 + if (res) { 219 + SAS_DPRINTK("lldd_execute_task returned: %d\n", res); 220 + 221 + if (qc->scsicmd) 222 + ASSIGN_SAS_TASK(qc->scsicmd, NULL); 223 + sas_free_task(task); 224 + return AC_ERR_SYSTEM; 225 + } 226 + 227 + return 0; 228 + } 229 + 230 + static u8 sas_ata_check_status(struct ata_port *ap) 231 + { 232 + struct domain_device *dev = ap->private_data; 233 + return dev->sata_dev.tf.command; 234 + } 235 + 236 + static void sas_ata_phy_reset(struct ata_port *ap) 237 + { 238 + struct domain_device *dev = ap->private_data; 239 + struct sas_internal *i = 240 + to_sas_internal(dev->port->ha->core.shost->transportt); 241 + int res = 0; 242 + 243 + if (i->dft->lldd_I_T_nexus_reset) 244 + res = i->dft->lldd_I_T_nexus_reset(dev); 245 + 246 + if (res) 247 + SAS_DPRINTK("%s: Unable to reset I T nexus?\n", __FUNCTION__); 248 + 249 + switch (dev->sata_dev.command_set) { 250 + case ATA_COMMAND_SET: 251 + SAS_DPRINTK("%s: Found ATA device.\n", __FUNCTION__); 252 + ap->device[0].class = ATA_DEV_ATA; 253 + break; 254 + case ATAPI_COMMAND_SET: 255 + SAS_DPRINTK("%s: Found ATAPI device.\n", __FUNCTION__); 256 + ap->device[0].class = ATA_DEV_ATAPI; 257 + break; 258 + default: 259 + SAS_DPRINTK("%s: Unknown SATA command set: %d.\n", 260 + __FUNCTION__, 261 + dev->sata_dev.command_set); 262 + ap->device[0].class = ATA_DEV_UNKNOWN; 263 + break; 264 + } 265 + 266 + ap->cbl = ATA_CBL_SATA; 267 + } 268 + 269 + static void sas_ata_post_internal(struct ata_queued_cmd *qc) 270 + { 271 + if (qc->flags & ATA_QCFLAG_FAILED) 272 + qc->err_mask |= AC_ERR_OTHER; 273 + 274 + if (qc->err_mask) { 275 + /* 276 + * Find the sas_task and kill it. By this point, 277 + * libata has decided to kill the qc, so we needn't 278 + * bother with sas_ata_task_done. But we still 279 + * ought to abort the task. 280 + */ 281 + struct sas_task *task = qc->lldd_task; 282 + unsigned long flags; 283 + 284 + qc->lldd_task = NULL; 285 + if (task) { 286 + /* Should this be a AT(API) device reset? */ 287 + spin_lock_irqsave(&task->task_state_lock, flags); 288 + task->task_state_flags |= SAS_TASK_NEED_DEV_RESET; 289 + spin_unlock_irqrestore(&task->task_state_lock, flags); 290 + 291 + task->uldd_task = NULL; 292 + __sas_task_abort(task); 293 + } 294 + } 295 + } 296 + 297 + static void sas_ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 298 + { 299 + struct domain_device *dev = ap->private_data; 300 + memcpy(tf, &dev->sata_dev.tf, sizeof (*tf)); 301 + } 302 + 303 + static int sas_ata_scr_write(struct ata_port *ap, unsigned int sc_reg_in, 304 + u32 val) 305 + { 306 + struct domain_device *dev = ap->private_data; 307 + 308 + SAS_DPRINTK("STUB %s\n", __FUNCTION__); 309 + switch (sc_reg_in) { 310 + case SCR_STATUS: 311 + dev->sata_dev.sstatus = val; 312 + break; 313 + case SCR_CONTROL: 314 + dev->sata_dev.scontrol = val; 315 + break; 316 + case SCR_ERROR: 317 + dev->sata_dev.serror = val; 318 + break; 319 + case SCR_ACTIVE: 320 + dev->sata_dev.ap->sactive = val; 321 + break; 322 + default: 323 + return -EINVAL; 324 + } 325 + return 0; 326 + } 327 + 328 + static int sas_ata_scr_read(struct ata_port *ap, unsigned int sc_reg_in, 329 + u32 *val) 330 + { 331 + struct domain_device *dev = ap->private_data; 332 + 333 + SAS_DPRINTK("STUB %s\n", __FUNCTION__); 334 + switch (sc_reg_in) { 335 + case SCR_STATUS: 336 + *val = dev->sata_dev.sstatus; 337 + return 0; 338 + case SCR_CONTROL: 339 + *val = dev->sata_dev.scontrol; 340 + return 0; 341 + case SCR_ERROR: 342 + *val = dev->sata_dev.serror; 343 + return 0; 344 + case SCR_ACTIVE: 345 + *val = dev->sata_dev.ap->sactive; 346 + return 0; 347 + default: 348 + return -EINVAL; 349 + } 350 + } 351 + 352 + static struct ata_port_operations sas_sata_ops = { 353 + .port_disable = ata_port_disable, 354 + .check_status = sas_ata_check_status, 355 + .check_altstatus = sas_ata_check_status, 356 + .dev_select = ata_noop_dev_select, 357 + .phy_reset = sas_ata_phy_reset, 358 + .post_internal_cmd = sas_ata_post_internal, 359 + .tf_read = sas_ata_tf_read, 360 + .qc_prep = ata_noop_qc_prep, 361 + .qc_issue = sas_ata_qc_issue, 362 + .port_start = ata_sas_port_start, 363 + .port_stop = ata_sas_port_stop, 364 + .scr_read = sas_ata_scr_read, 365 + .scr_write = sas_ata_scr_write 366 + }; 367 + 368 + static struct ata_port_info sata_port_info = { 369 + .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | ATA_FLAG_SATA_RESET | 370 + ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NCQ, 371 + .pio_mask = 0x1f, /* PIO0-4 */ 372 + .mwdma_mask = 0x07, /* MWDMA0-2 */ 373 + .udma_mask = ATA_UDMA6, 374 + .port_ops = &sas_sata_ops 375 + }; 376 + 377 + int sas_ata_init_host_and_port(struct domain_device *found_dev, 378 + struct scsi_target *starget) 379 + { 380 + struct Scsi_Host *shost = dev_to_shost(&starget->dev); 381 + struct sas_ha_struct *ha = SHOST_TO_SAS_HA(shost); 382 + struct ata_port *ap; 383 + 384 + ata_host_init(&found_dev->sata_dev.ata_host, 385 + &ha->pcidev->dev, 386 + sata_port_info.flags, 387 + &sas_sata_ops); 388 + ap = ata_sas_port_alloc(&found_dev->sata_dev.ata_host, 389 + &sata_port_info, 390 + shost); 391 + if (!ap) { 392 + SAS_DPRINTK("ata_sas_port_alloc failed.\n"); 393 + return -ENODEV; 394 + } 395 + 396 + ap->private_data = found_dev; 397 + ap->cbl = ATA_CBL_SATA; 398 + ap->scsi_host = shost; 399 + found_dev->sata_dev.ap = ap; 400 + 401 + return 0; 402 + } 403 + 404 + void sas_ata_task_abort(struct sas_task *task) 405 + { 406 + struct ata_queued_cmd *qc = task->uldd_task; 407 + struct completion *waiting; 408 + 409 + /* Bounce SCSI-initiated commands to the SCSI EH */ 410 + if (qc->scsicmd) { 411 + scsi_req_abort_cmd(qc->scsicmd); 412 + scsi_schedule_eh(qc->scsicmd->device->host); 413 + return; 414 + } 415 + 416 + /* Internal command, fake a timeout and complete. */ 417 + qc->flags &= ~ATA_QCFLAG_ACTIVE; 418 + qc->flags |= ATA_QCFLAG_FAILED; 419 + qc->err_mask |= AC_ERR_TIMEOUT; 420 + waiting = qc->private_data; 421 + complete(waiting); 422 + } 423 + 424 + static void sas_task_timedout(unsigned long _task) 425 + { 426 + struct sas_task *task = (void *) _task; 427 + unsigned long flags; 428 + 429 + spin_lock_irqsave(&task->task_state_lock, flags); 430 + if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) 431 + task->task_state_flags |= SAS_TASK_STATE_ABORTED; 432 + spin_unlock_irqrestore(&task->task_state_lock, flags); 433 + 434 + complete(&task->completion); 435 + } 436 + 437 + static void sas_disc_task_done(struct sas_task *task) 438 + { 439 + if (!del_timer(&task->timer)) 440 + return; 441 + complete(&task->completion); 442 + } 443 + 444 + #define SAS_DEV_TIMEOUT 10 445 + 446 + /** 447 + * sas_execute_task -- Basic task processing for discovery 448 + * @task: the task to be executed 449 + * @buffer: pointer to buffer to do I/O 450 + * @size: size of @buffer 451 + * @pci_dma_dir: PCI_DMA_... 452 + */ 453 + static int sas_execute_task(struct sas_task *task, void *buffer, int size, 454 + int pci_dma_dir) 455 + { 456 + int res = 0; 457 + struct scatterlist *scatter = NULL; 458 + struct task_status_struct *ts = &task->task_status; 459 + int num_scatter = 0; 460 + int retries = 0; 461 + struct sas_internal *i = 462 + to_sas_internal(task->dev->port->ha->core.shost->transportt); 463 + 464 + if (pci_dma_dir != PCI_DMA_NONE) { 465 + scatter = kzalloc(sizeof(*scatter), GFP_KERNEL); 466 + if (!scatter) 467 + goto out; 468 + 469 + sg_init_one(scatter, buffer, size); 470 + num_scatter = 1; 471 + } 472 + 473 + task->task_proto = task->dev->tproto; 474 + task->scatter = scatter; 475 + task->num_scatter = num_scatter; 476 + task->total_xfer_len = size; 477 + task->data_dir = pci_dma_dir; 478 + task->task_done = sas_disc_task_done; 479 + if (pci_dma_dir != PCI_DMA_NONE && 480 + sas_protocol_ata(task->task_proto)) { 481 + task->num_scatter = pci_map_sg(task->dev->port->ha->pcidev, 482 + task->scatter, 483 + task->num_scatter, 484 + task->data_dir); 485 + } 486 + 487 + for (retries = 0; retries < 5; retries++) { 488 + task->task_state_flags = SAS_TASK_STATE_PENDING; 489 + init_completion(&task->completion); 490 + 491 + task->timer.data = (unsigned long) task; 492 + task->timer.function = sas_task_timedout; 493 + task->timer.expires = jiffies + SAS_DEV_TIMEOUT*HZ; 494 + add_timer(&task->timer); 495 + 496 + res = i->dft->lldd_execute_task(task, 1, GFP_KERNEL); 497 + if (res) { 498 + del_timer(&task->timer); 499 + SAS_DPRINTK("executing SAS discovery task failed:%d\n", 500 + res); 501 + goto ex_err; 502 + } 503 + wait_for_completion(&task->completion); 504 + res = -ETASK; 505 + if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 506 + int res2; 507 + SAS_DPRINTK("task aborted, flags:0x%x\n", 508 + task->task_state_flags); 509 + res2 = i->dft->lldd_abort_task(task); 510 + SAS_DPRINTK("came back from abort task\n"); 511 + if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) { 512 + if (res2 == TMF_RESP_FUNC_COMPLETE) 513 + continue; /* Retry the task */ 514 + else 515 + goto ex_err; 516 + } 517 + } 518 + if (task->task_status.stat == SAM_BUSY || 519 + task->task_status.stat == SAM_TASK_SET_FULL || 520 + task->task_status.stat == SAS_QUEUE_FULL) { 521 + SAS_DPRINTK("task: q busy, sleeping...\n"); 522 + schedule_timeout_interruptible(HZ); 523 + } else if (task->task_status.stat == SAM_CHECK_COND) { 524 + struct scsi_sense_hdr shdr; 525 + 526 + if (!scsi_normalize_sense(ts->buf, ts->buf_valid_size, 527 + &shdr)) { 528 + SAS_DPRINTK("couldn't normalize sense\n"); 529 + continue; 530 + } 531 + if ((shdr.sense_key == 6 && shdr.asc == 0x29) || 532 + (shdr.sense_key == 2 && shdr.asc == 4 && 533 + shdr.ascq == 1)) { 534 + SAS_DPRINTK("device %016llx LUN: %016llx " 535 + "powering up or not ready yet, " 536 + "sleeping...\n", 537 + SAS_ADDR(task->dev->sas_addr), 538 + SAS_ADDR(task->ssp_task.LUN)); 539 + 540 + schedule_timeout_interruptible(5*HZ); 541 + } else if (shdr.sense_key == 1) { 542 + res = 0; 543 + break; 544 + } else if (shdr.sense_key == 5) { 545 + break; 546 + } else { 547 + SAS_DPRINTK("dev %016llx LUN: %016llx " 548 + "sense key:0x%x ASC:0x%x ASCQ:0x%x" 549 + "\n", 550 + SAS_ADDR(task->dev->sas_addr), 551 + SAS_ADDR(task->ssp_task.LUN), 552 + shdr.sense_key, 553 + shdr.asc, shdr.ascq); 554 + } 555 + } else if (task->task_status.resp != SAS_TASK_COMPLETE || 556 + task->task_status.stat != SAM_GOOD) { 557 + SAS_DPRINTK("task finished with resp:0x%x, " 558 + "stat:0x%x\n", 559 + task->task_status.resp, 560 + task->task_status.stat); 561 + goto ex_err; 562 + } else { 563 + res = 0; 564 + break; 565 + } 566 + } 567 + ex_err: 568 + if (pci_dma_dir != PCI_DMA_NONE) { 569 + if (sas_protocol_ata(task->task_proto)) 570 + pci_unmap_sg(task->dev->port->ha->pcidev, 571 + task->scatter, task->num_scatter, 572 + task->data_dir); 573 + kfree(scatter); 574 + } 575 + out: 576 + return res; 577 + } 578 + 579 + /* ---------- SATA ---------- */ 580 + 581 + static void sas_get_ata_command_set(struct domain_device *dev) 582 + { 583 + struct dev_to_host_fis *fis = 584 + (struct dev_to_host_fis *) dev->frame_rcvd; 585 + 586 + if ((fis->sector_count == 1 && /* ATA */ 587 + fis->lbal == 1 && 588 + fis->lbam == 0 && 589 + fis->lbah == 0 && 590 + fis->device == 0) 591 + || 592 + (fis->sector_count == 0 && /* CE-ATA (mATA) */ 593 + fis->lbal == 0 && 594 + fis->lbam == 0xCE && 595 + fis->lbah == 0xAA && 596 + (fis->device & ~0x10) == 0)) 597 + 598 + dev->sata_dev.command_set = ATA_COMMAND_SET; 599 + 600 + else if ((fis->interrupt_reason == 1 && /* ATAPI */ 601 + fis->lbal == 1 && 602 + fis->byte_count_low == 0x14 && 603 + fis->byte_count_high == 0xEB && 604 + (fis->device & ~0x10) == 0)) 605 + 606 + dev->sata_dev.command_set = ATAPI_COMMAND_SET; 607 + 608 + else if ((fis->sector_count == 1 && /* SEMB */ 609 + fis->lbal == 1 && 610 + fis->lbam == 0x3C && 611 + fis->lbah == 0xC3 && 612 + fis->device == 0) 613 + || 614 + (fis->interrupt_reason == 1 && /* SATA PM */ 615 + fis->lbal == 1 && 616 + fis->byte_count_low == 0x69 && 617 + fis->byte_count_high == 0x96 && 618 + (fis->device & ~0x10) == 0)) 619 + 620 + /* Treat it as a superset? */ 621 + dev->sata_dev.command_set = ATAPI_COMMAND_SET; 622 + } 623 + 624 + /** 625 + * sas_issue_ata_cmd -- Basic SATA command processing for discovery 626 + * @dev: the device to send the command to 627 + * @command: the command register 628 + * @features: the features register 629 + * @buffer: pointer to buffer to do I/O 630 + * @size: size of @buffer 631 + * @pci_dma_dir: PCI_DMA_... 632 + */ 633 + static int sas_issue_ata_cmd(struct domain_device *dev, u8 command, 634 + u8 features, void *buffer, int size, 635 + int pci_dma_dir) 636 + { 637 + int res = 0; 638 + struct sas_task *task; 639 + struct dev_to_host_fis *d2h_fis = (struct dev_to_host_fis *) 640 + &dev->frame_rcvd[0]; 641 + 642 + res = -ENOMEM; 643 + task = sas_alloc_task(GFP_KERNEL); 644 + if (!task) 645 + goto out; 646 + 647 + task->dev = dev; 648 + 649 + task->ata_task.fis.fis_type = 0x27; 650 + task->ata_task.fis.command = command; 651 + task->ata_task.fis.features = features; 652 + task->ata_task.fis.device = d2h_fis->device; 653 + task->ata_task.retry_count = 1; 654 + 655 + res = sas_execute_task(task, buffer, size, pci_dma_dir); 656 + 657 + sas_free_task(task); 658 + out: 659 + return res; 660 + } 661 + 662 + static void sas_sata_propagate_sas_addr(struct domain_device *dev) 663 + { 664 + unsigned long flags; 665 + struct asd_sas_port *port = dev->port; 666 + struct asd_sas_phy *phy; 667 + 668 + BUG_ON(dev->parent); 669 + 670 + memcpy(port->attached_sas_addr, dev->sas_addr, SAS_ADDR_SIZE); 671 + spin_lock_irqsave(&port->phy_list_lock, flags); 672 + list_for_each_entry(phy, &port->phy_list, port_phy_el) 673 + memcpy(phy->attached_sas_addr, dev->sas_addr, SAS_ADDR_SIZE); 674 + spin_unlock_irqrestore(&port->phy_list_lock, flags); 675 + } 676 + 677 + #define ATA_IDENTIFY_DEV 0xEC 678 + #define ATA_IDENTIFY_PACKET_DEV 0xA1 679 + #define ATA_SET_FEATURES 0xEF 680 + #define ATA_FEATURE_PUP_STBY_SPIN_UP 0x07 681 + 682 + /** 683 + * sas_discover_sata_dev -- discover a STP/SATA device (SATA_DEV) 684 + * @dev: STP/SATA device of interest (ATA/ATAPI) 685 + * 686 + * The LLDD has already been notified of this device, so that we can 687 + * send FISes to it. Here we try to get IDENTIFY DEVICE or IDENTIFY 688 + * PACKET DEVICE, if ATAPI device, so that the LLDD can fine-tune its 689 + * performance for this device. 690 + */ 691 + static int sas_discover_sata_dev(struct domain_device *dev) 692 + { 693 + int res; 694 + __le16 *identify_x; 695 + u8 command; 696 + 697 + identify_x = kzalloc(512, GFP_KERNEL); 698 + if (!identify_x) 699 + return -ENOMEM; 700 + 701 + if (dev->sata_dev.command_set == ATA_COMMAND_SET) { 702 + dev->sata_dev.identify_device = identify_x; 703 + command = ATA_IDENTIFY_DEV; 704 + } else { 705 + dev->sata_dev.identify_packet_device = identify_x; 706 + command = ATA_IDENTIFY_PACKET_DEV; 707 + } 708 + 709 + res = sas_issue_ata_cmd(dev, command, 0, identify_x, 512, 710 + PCI_DMA_FROMDEVICE); 711 + if (res) 712 + goto out_err; 713 + 714 + /* lives on the media? */ 715 + if (le16_to_cpu(identify_x[0]) & 4) { 716 + /* incomplete response */ 717 + SAS_DPRINTK("sending SET FEATURE/PUP_STBY_SPIN_UP to " 718 + "dev %llx\n", SAS_ADDR(dev->sas_addr)); 719 + if (!le16_to_cpu(identify_x[83] & (1<<6))) 720 + goto cont1; 721 + res = sas_issue_ata_cmd(dev, ATA_SET_FEATURES, 722 + ATA_FEATURE_PUP_STBY_SPIN_UP, 723 + NULL, 0, PCI_DMA_NONE); 724 + if (res) 725 + goto cont1; 726 + 727 + schedule_timeout_interruptible(5*HZ); /* More time? */ 728 + res = sas_issue_ata_cmd(dev, command, 0, identify_x, 512, 729 + PCI_DMA_FROMDEVICE); 730 + if (res) 731 + goto out_err; 732 + } 733 + cont1: 734 + /* Get WWN */ 735 + if (dev->port->oob_mode != SATA_OOB_MODE) { 736 + memcpy(dev->sas_addr, dev->sata_dev.rps_resp.rps.stp_sas_addr, 737 + SAS_ADDR_SIZE); 738 + } else if (dev->sata_dev.command_set == ATA_COMMAND_SET && 739 + (le16_to_cpu(dev->sata_dev.identify_device[108]) & 0xF000) 740 + == 0x5000) { 741 + int i; 742 + 743 + for (i = 0; i < 4; i++) { 744 + dev->sas_addr[2*i] = 745 + (le16_to_cpu(dev->sata_dev.identify_device[108+i]) & 0xFF00) >> 8; 746 + dev->sas_addr[2*i+1] = 747 + le16_to_cpu(dev->sata_dev.identify_device[108+i]) & 0x00FF; 748 + } 749 + } 750 + sas_hash_addr(dev->hashed_sas_addr, dev->sas_addr); 751 + if (!dev->parent) 752 + sas_sata_propagate_sas_addr(dev); 753 + 754 + /* XXX Hint: register this SATA device with SATL. 755 + When this returns, dev->sata_dev->lu is alive and 756 + present. 757 + sas_satl_register_dev(dev); 758 + */ 759 + 760 + sas_fill_in_rphy(dev, dev->rphy); 761 + 762 + return 0; 763 + out_err: 764 + dev->sata_dev.identify_packet_device = NULL; 765 + dev->sata_dev.identify_device = NULL; 766 + kfree(identify_x); 767 + return res; 768 + } 769 + 770 + static int sas_discover_sata_pm(struct domain_device *dev) 771 + { 772 + return -ENODEV; 773 + } 774 + 775 + /** 776 + * sas_discover_sata -- discover an STP/SATA domain device 777 + * @dev: pointer to struct domain_device of interest 778 + * 779 + * First we notify the LLDD of this device, so we can send frames to 780 + * it. Then depending on the type of device we call the appropriate 781 + * discover functions. Once device discover is done, we notify the 782 + * LLDD so that it can fine-tune its parameters for the device, by 783 + * removing it and then adding it. That is, the second time around, 784 + * the driver would have certain fields, that it is looking at, set. 785 + * Finally we initialize the kobj so that the device can be added to 786 + * the system at registration time. Devices directly attached to a HA 787 + * port, have no parents. All other devices do, and should have their 788 + * "parent" pointer set appropriately before calling this function. 789 + */ 790 + int sas_discover_sata(struct domain_device *dev) 791 + { 792 + int res; 793 + 794 + sas_get_ata_command_set(dev); 795 + 796 + res = sas_notify_lldd_dev_found(dev); 797 + if (res) 798 + return res; 799 + 800 + switch (dev->dev_type) { 801 + case SATA_DEV: 802 + res = sas_discover_sata_dev(dev); 803 + break; 804 + case SATA_PM: 805 + res = sas_discover_sata_pm(dev); 806 + break; 807 + default: 808 + break; 809 + } 810 + sas_notify_lldd_dev_gone(dev); 811 + if (!res) { 812 + sas_notify_lldd_dev_found(dev); 813 + res = sas_rphy_add(dev->rphy); 814 + } 815 + 816 + return res; 817 + }

+8 -394

drivers/scsi/libsas/sas_discover.c

··· 55 55 } 56 56 } 57 57 58 - static void sas_task_timedout(unsigned long _task) 59 - { 60 - struct sas_task *task = (void *) _task; 61 - unsigned long flags; 62 - 63 - spin_lock_irqsave(&task->task_state_lock, flags); 64 - if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) 65 - task->task_state_flags |= SAS_TASK_STATE_ABORTED; 66 - spin_unlock_irqrestore(&task->task_state_lock, flags); 67 - 68 - complete(&task->completion); 69 - } 70 - 71 - static void sas_disc_task_done(struct sas_task *task) 72 - { 73 - if (!del_timer(&task->timer)) 74 - return; 75 - complete(&task->completion); 76 - } 77 - 78 - #define SAS_DEV_TIMEOUT 10 79 - 80 - /** 81 - * sas_execute_task -- Basic task processing for discovery 82 - * @task: the task to be executed 83 - * @buffer: pointer to buffer to do I/O 84 - * @size: size of @buffer 85 - * @pci_dma_dir: PCI_DMA_... 86 - */ 87 - static int sas_execute_task(struct sas_task *task, void *buffer, int size, 88 - int pci_dma_dir) 89 - { 90 - int res = 0; 91 - struct scatterlist *scatter = NULL; 92 - struct task_status_struct *ts = &task->task_status; 93 - int num_scatter = 0; 94 - int retries = 0; 95 - struct sas_internal *i = 96 - to_sas_internal(task->dev->port->ha->core.shost->transportt); 97 - 98 - if (pci_dma_dir != PCI_DMA_NONE) { 99 - scatter = kzalloc(sizeof(*scatter), GFP_KERNEL); 100 - if (!scatter) 101 - goto out; 102 - 103 - sg_init_one(scatter, buffer, size); 104 - num_scatter = 1; 105 - } 106 - 107 - task->task_proto = task->dev->tproto; 108 - task->scatter = scatter; 109 - task->num_scatter = num_scatter; 110 - task->total_xfer_len = size; 111 - task->data_dir = pci_dma_dir; 112 - task->task_done = sas_disc_task_done; 113 - 114 - for (retries = 0; retries < 5; retries++) { 115 - task->task_state_flags = SAS_TASK_STATE_PENDING; 116 - init_completion(&task->completion); 117 - 118 - task->timer.data = (unsigned long) task; 119 - task->timer.function = sas_task_timedout; 120 - task->timer.expires = jiffies + SAS_DEV_TIMEOUT*HZ; 121 - add_timer(&task->timer); 122 - 123 - res = i->dft->lldd_execute_task(task, 1, GFP_KERNEL); 124 - if (res) { 125 - del_timer(&task->timer); 126 - SAS_DPRINTK("executing SAS discovery task failed:%d\n", 127 - res); 128 - goto ex_err; 129 - } 130 - wait_for_completion(&task->completion); 131 - res = -ETASK; 132 - if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 133 - int res2; 134 - SAS_DPRINTK("task aborted, flags:0x%x\n", 135 - task->task_state_flags); 136 - res2 = i->dft->lldd_abort_task(task); 137 - SAS_DPRINTK("came back from abort task\n"); 138 - if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) { 139 - if (res2 == TMF_RESP_FUNC_COMPLETE) 140 - continue; /* Retry the task */ 141 - else 142 - goto ex_err; 143 - } 144 - } 145 - if (task->task_status.stat == SAM_BUSY || 146 - task->task_status.stat == SAM_TASK_SET_FULL || 147 - task->task_status.stat == SAS_QUEUE_FULL) { 148 - SAS_DPRINTK("task: q busy, sleeping...\n"); 149 - schedule_timeout_interruptible(HZ); 150 - } else if (task->task_status.stat == SAM_CHECK_COND) { 151 - struct scsi_sense_hdr shdr; 152 - 153 - if (!scsi_normalize_sense(ts->buf, ts->buf_valid_size, 154 - &shdr)) { 155 - SAS_DPRINTK("couldn't normalize sense\n"); 156 - continue; 157 - } 158 - if ((shdr.sense_key == 6 && shdr.asc == 0x29) || 159 - (shdr.sense_key == 2 && shdr.asc == 4 && 160 - shdr.ascq == 1)) { 161 - SAS_DPRINTK("device %016llx LUN: %016llx " 162 - "powering up or not ready yet, " 163 - "sleeping...\n", 164 - SAS_ADDR(task->dev->sas_addr), 165 - SAS_ADDR(task->ssp_task.LUN)); 166 - 167 - schedule_timeout_interruptible(5*HZ); 168 - } else if (shdr.sense_key == 1) { 169 - res = 0; 170 - break; 171 - } else if (shdr.sense_key == 5) { 172 - break; 173 - } else { 174 - SAS_DPRINTK("dev %016llx LUN: %016llx " 175 - "sense key:0x%x ASC:0x%x ASCQ:0x%x" 176 - "\n", 177 - SAS_ADDR(task->dev->sas_addr), 178 - SAS_ADDR(task->ssp_task.LUN), 179 - shdr.sense_key, 180 - shdr.asc, shdr.ascq); 181 - } 182 - } else if (task->task_status.resp != SAS_TASK_COMPLETE || 183 - task->task_status.stat != SAM_GOOD) { 184 - SAS_DPRINTK("task finished with resp:0x%x, " 185 - "stat:0x%x\n", 186 - task->task_status.resp, 187 - task->task_status.stat); 188 - goto ex_err; 189 - } else { 190 - res = 0; 191 - break; 192 - } 193 - } 194 - ex_err: 195 - if (pci_dma_dir != PCI_DMA_NONE) 196 - kfree(scatter); 197 - out: 198 - return res; 199 - } 200 - 201 58 /* ---------- Domain device discovery ---------- */ 202 59 203 60 /** ··· 112 255 113 256 switch (dev->dev_type) { 114 257 case SAS_END_DEV: 258 + case SATA_DEV: 115 259 rphy = sas_end_device_alloc(port->port); 116 260 break; 117 261 case EDGE_DEV: ··· 123 265 rphy = sas_expander_alloc(port->port, 124 266 SAS_FANOUT_EXPANDER_DEVICE); 125 267 break; 126 - case SATA_DEV: 127 268 default: 128 269 printk("ERROR: Unidentified device type %d\n", dev->dev_type); 129 270 rphy = NULL; ··· 149 292 port->disc.max_level = 0; 150 293 151 294 dev->rphy = rphy; 152 - spin_lock(&port->dev_list_lock); 295 + spin_lock_irq(&port->dev_list_lock); 153 296 list_add_tail(&dev->dev_list_node, &port->dev_list); 154 - spin_unlock(&port->dev_list_lock); 297 + spin_unlock_irq(&port->dev_list_lock); 155 298 156 299 return 0; 157 300 } 158 301 159 302 /* ---------- Discover and Revalidate ---------- */ 160 - 161 - /* ---------- SATA ---------- */ 162 - 163 - static void sas_get_ata_command_set(struct domain_device *dev) 164 - { 165 - struct dev_to_host_fis *fis = 166 - (struct dev_to_host_fis *) dev->frame_rcvd; 167 - 168 - if ((fis->sector_count == 1 && /* ATA */ 169 - fis->lbal == 1 && 170 - fis->lbam == 0 && 171 - fis->lbah == 0 && 172 - fis->device == 0) 173 - || 174 - (fis->sector_count == 0 && /* CE-ATA (mATA) */ 175 - fis->lbal == 0 && 176 - fis->lbam == 0xCE && 177 - fis->lbah == 0xAA && 178 - (fis->device & ~0x10) == 0)) 179 - 180 - dev->sata_dev.command_set = ATA_COMMAND_SET; 181 - 182 - else if ((fis->interrupt_reason == 1 && /* ATAPI */ 183 - fis->lbal == 1 && 184 - fis->byte_count_low == 0x14 && 185 - fis->byte_count_high == 0xEB && 186 - (fis->device & ~0x10) == 0)) 187 - 188 - dev->sata_dev.command_set = ATAPI_COMMAND_SET; 189 - 190 - else if ((fis->sector_count == 1 && /* SEMB */ 191 - fis->lbal == 1 && 192 - fis->lbam == 0x3C && 193 - fis->lbah == 0xC3 && 194 - fis->device == 0) 195 - || 196 - (fis->interrupt_reason == 1 && /* SATA PM */ 197 - fis->lbal == 1 && 198 - fis->byte_count_low == 0x69 && 199 - fis->byte_count_high == 0x96 && 200 - (fis->device & ~0x10) == 0)) 201 - 202 - /* Treat it as a superset? */ 203 - dev->sata_dev.command_set = ATAPI_COMMAND_SET; 204 - } 205 - 206 - /** 207 - * sas_issue_ata_cmd -- Basic SATA command processing for discovery 208 - * @dev: the device to send the command to 209 - * @command: the command register 210 - * @features: the features register 211 - * @buffer: pointer to buffer to do I/O 212 - * @size: size of @buffer 213 - * @pci_dma_dir: PCI_DMA_... 214 - */ 215 - static int sas_issue_ata_cmd(struct domain_device *dev, u8 command, 216 - u8 features, void *buffer, int size, 217 - int pci_dma_dir) 218 - { 219 - int res = 0; 220 - struct sas_task *task; 221 - struct dev_to_host_fis *d2h_fis = (struct dev_to_host_fis *) 222 - &dev->frame_rcvd[0]; 223 - 224 - res = -ENOMEM; 225 - task = sas_alloc_task(GFP_KERNEL); 226 - if (!task) 227 - goto out; 228 - 229 - task->dev = dev; 230 - 231 - task->ata_task.fis.command = command; 232 - task->ata_task.fis.features = features; 233 - task->ata_task.fis.device = d2h_fis->device; 234 - task->ata_task.retry_count = 1; 235 - 236 - res = sas_execute_task(task, buffer, size, pci_dma_dir); 237 - 238 - sas_free_task(task); 239 - out: 240 - return res; 241 - } 242 - 243 - static void sas_sata_propagate_sas_addr(struct domain_device *dev) 244 - { 245 - unsigned long flags; 246 - struct asd_sas_port *port = dev->port; 247 - struct asd_sas_phy *phy; 248 - 249 - BUG_ON(dev->parent); 250 - 251 - memcpy(port->attached_sas_addr, dev->sas_addr, SAS_ADDR_SIZE); 252 - spin_lock_irqsave(&port->phy_list_lock, flags); 253 - list_for_each_entry(phy, &port->phy_list, port_phy_el) 254 - memcpy(phy->attached_sas_addr, dev->sas_addr, SAS_ADDR_SIZE); 255 - spin_unlock_irqrestore(&port->phy_list_lock, flags); 256 - } 257 - 258 - #define ATA_IDENTIFY_DEV 0xEC 259 - #define ATA_IDENTIFY_PACKET_DEV 0xA1 260 - #define ATA_SET_FEATURES 0xEF 261 - #define ATA_FEATURE_PUP_STBY_SPIN_UP 0x07 262 - 263 - /** 264 - * sas_discover_sata_dev -- discover a STP/SATA device (SATA_DEV) 265 - * @dev: STP/SATA device of interest (ATA/ATAPI) 266 - * 267 - * The LLDD has already been notified of this device, so that we can 268 - * send FISes to it. Here we try to get IDENTIFY DEVICE or IDENTIFY 269 - * PACKET DEVICE, if ATAPI device, so that the LLDD can fine-tune its 270 - * performance for this device. 271 - */ 272 - static int sas_discover_sata_dev(struct domain_device *dev) 273 - { 274 - int res; 275 - __le16 *identify_x; 276 - u8 command; 277 - 278 - identify_x = kzalloc(512, GFP_KERNEL); 279 - if (!identify_x) 280 - return -ENOMEM; 281 - 282 - if (dev->sata_dev.command_set == ATA_COMMAND_SET) { 283 - dev->sata_dev.identify_device = identify_x; 284 - command = ATA_IDENTIFY_DEV; 285 - } else { 286 - dev->sata_dev.identify_packet_device = identify_x; 287 - command = ATA_IDENTIFY_PACKET_DEV; 288 - } 289 - 290 - res = sas_issue_ata_cmd(dev, command, 0, identify_x, 512, 291 - PCI_DMA_FROMDEVICE); 292 - if (res) 293 - goto out_err; 294 - 295 - /* lives on the media? */ 296 - if (le16_to_cpu(identify_x[0]) & 4) { 297 - /* incomplete response */ 298 - SAS_DPRINTK("sending SET FEATURE/PUP_STBY_SPIN_UP to " 299 - "dev %llx\n", SAS_ADDR(dev->sas_addr)); 300 - if (!le16_to_cpu(identify_x[83] & (1<<6))) 301 - goto cont1; 302 - res = sas_issue_ata_cmd(dev, ATA_SET_FEATURES, 303 - ATA_FEATURE_PUP_STBY_SPIN_UP, 304 - NULL, 0, PCI_DMA_NONE); 305 - if (res) 306 - goto cont1; 307 - 308 - schedule_timeout_interruptible(5*HZ); /* More time? */ 309 - res = sas_issue_ata_cmd(dev, command, 0, identify_x, 512, 310 - PCI_DMA_FROMDEVICE); 311 - if (res) 312 - goto out_err; 313 - } 314 - cont1: 315 - /* Get WWN */ 316 - if (dev->port->oob_mode != SATA_OOB_MODE) { 317 - memcpy(dev->sas_addr, dev->sata_dev.rps_resp.rps.stp_sas_addr, 318 - SAS_ADDR_SIZE); 319 - } else if (dev->sata_dev.command_set == ATA_COMMAND_SET && 320 - (le16_to_cpu(dev->sata_dev.identify_device[108]) & 0xF000) 321 - == 0x5000) { 322 - int i; 323 - 324 - for (i = 0; i < 4; i++) { 325 - dev->sas_addr[2*i] = 326 - (le16_to_cpu(dev->sata_dev.identify_device[108+i]) & 0xFF00) >> 8; 327 - dev->sas_addr[2*i+1] = 328 - le16_to_cpu(dev->sata_dev.identify_device[108+i]) & 0x00FF; 329 - } 330 - } 331 - sas_hash_addr(dev->hashed_sas_addr, dev->sas_addr); 332 - if (!dev->parent) 333 - sas_sata_propagate_sas_addr(dev); 334 - 335 - /* XXX Hint: register this SATA device with SATL. 336 - When this returns, dev->sata_dev->lu is alive and 337 - present. 338 - sas_satl_register_dev(dev); 339 - */ 340 - return 0; 341 - out_err: 342 - dev->sata_dev.identify_packet_device = NULL; 343 - dev->sata_dev.identify_device = NULL; 344 - kfree(identify_x); 345 - return res; 346 - } 347 - 348 - static int sas_discover_sata_pm(struct domain_device *dev) 349 - { 350 - return -ENODEV; 351 - } 352 303 353 304 int sas_notify_lldd_dev_found(struct domain_device *dev) 354 305 { ··· 190 525 191 526 /* ---------- Common/dispatchers ---------- */ 192 527 193 - /** 194 - * sas_discover_sata -- discover an STP/SATA domain device 195 - * @dev: pointer to struct domain_device of interest 196 - * 197 - * First we notify the LLDD of this device, so we can send frames to 198 - * it. Then depending on the type of device we call the appropriate 199 - * discover functions. Once device discover is done, we notify the 200 - * LLDD so that it can fine-tune its parameters for the device, by 201 - * removing it and then adding it. That is, the second time around, 202 - * the driver would have certain fields, that it is looking at, set. 203 - * Finally we initialize the kobj so that the device can be added to 204 - * the system at registration time. Devices directly attached to a HA 205 - * port, have no parents. All other devices do, and should have their 206 - * "parent" pointer set appropriately before calling this function. 207 - */ 208 - int sas_discover_sata(struct domain_device *dev) 209 - { 210 - int res; 211 - 212 - sas_get_ata_command_set(dev); 213 - 214 - res = sas_notify_lldd_dev_found(dev); 215 - if (res) 216 - goto out_err2; 217 - 218 - switch (dev->dev_type) { 219 - case SATA_DEV: 220 - res = sas_discover_sata_dev(dev); 221 - break; 222 - case SATA_PM: 223 - res = sas_discover_sata_pm(dev); 224 - break; 225 - default: 226 - break; 227 - } 228 - if (res) 229 - goto out_err; 230 - 231 - sas_notify_lldd_dev_gone(dev); 232 - res = sas_notify_lldd_dev_found(dev); 233 - if (res) 234 - goto out_err2; 235 - 236 - res = sas_rphy_add(dev->rphy); 237 - if (res) 238 - goto out_err; 239 - 240 - return res; 241 - 242 - out_err: 243 - sas_notify_lldd_dev_gone(dev); 244 - out_err2: 245 - return res; 246 - } 247 528 248 529 /** 249 530 * sas_discover_end_dev -- discover an end device (SSP, etc) ··· 296 685 case FANOUT_DEV: 297 686 error = sas_discover_root_expander(dev); 298 687 break; 688 + #ifdef CONFIG_SCSI_SAS_ATA 299 689 case SATA_DEV: 300 690 case SATA_PM: 301 691 error = sas_discover_sata(dev); 302 692 break; 693 + #endif 303 694 default: 695 + error = -ENXIO; 304 696 SAS_DPRINTK("unhandled device %d\n", dev->dev_type); 305 697 break; 306 698 } ··· 312 698 sas_rphy_free(dev->rphy); 313 699 dev->rphy = NULL; 314 700 315 - spin_lock(&port->dev_list_lock); 701 + spin_lock_irq(&port->dev_list_lock); 316 702 list_del_init(&dev->dev_list_node); 317 - spin_unlock(&port->dev_list_lock); 703 + spin_unlock_irq(&port->dev_list_lock); 318 704 319 705 kfree(dev); /* not kobject_register-ed yet */ 320 706 port->port_dev = NULL;

+122 -118

drivers/scsi/libsas/sas_expander.c

··· 23 23 */ 24 24 25 25 #include <linux/scatterlist.h> 26 + #include <linux/blkdev.h> 26 27 27 28 #include "sas_internal.h" 28 29 ··· 36 35 static int sas_configure_phy(struct domain_device *dev, int phy_id, 37 36 u8 *sas_addr, int include); 38 37 static int sas_disable_routing(struct domain_device *dev, u8 *sas_addr); 39 - 40 - #if 0 41 - /* FIXME: smp needs to migrate into the sas class */ 42 - static ssize_t smp_portal_read(struct kobject *, struct bin_attribute *, 43 - char *, loff_t, size_t); 44 - static ssize_t smp_portal_write(struct kobject *, struct bin_attribute *, 45 - char *, loff_t, size_t); 46 - #endif 47 38 48 39 /* ---------- SMP task management ---------- */ 49 40 ··· 213 220 #define DISCOVER_REQ_SIZE 16 214 221 #define DISCOVER_RESP_SIZE 56 215 222 223 + static int sas_ex_phy_discover_helper(struct domain_device *dev, u8 *disc_req, 224 + u8 *disc_resp, int single) 225 + { 226 + int i, res; 227 + 228 + disc_req[9] = single; 229 + for (i = 1 ; i < 3; i++) { 230 + struct discover_resp *dr; 231 + 232 + res = smp_execute_task(dev, disc_req, DISCOVER_REQ_SIZE, 233 + disc_resp, DISCOVER_RESP_SIZE); 234 + if (res) 235 + return res; 236 + /* This is detecting a failure to transmit inital 237 + * dev to host FIS as described in section G.5 of 238 + * sas-2 r 04b */ 239 + dr = &((struct smp_resp *)disc_resp)->disc; 240 + if (!(dr->attached_dev_type == 0 && 241 + dr->attached_sata_dev)) 242 + break; 243 + /* In order to generate the dev to host FIS, we 244 + * send a link reset to the expander port */ 245 + sas_smp_phy_control(dev, single, PHY_FUNC_LINK_RESET, NULL); 246 + /* Wait for the reset to trigger the negotiation */ 247 + msleep(500); 248 + } 249 + sas_set_ex_phy(dev, single, disc_resp); 250 + return 0; 251 + } 252 + 216 253 static int sas_ex_phy_discover(struct domain_device *dev, int single) 217 254 { 218 255 struct expander_device *ex = &dev->ex_dev; ··· 263 240 disc_req[1] = SMP_DISCOVER; 264 241 265 242 if (0 <= single && single < ex->num_phys) { 266 - disc_req[9] = single; 267 - res = smp_execute_task(dev, disc_req, DISCOVER_REQ_SIZE, 268 - disc_resp, DISCOVER_RESP_SIZE); 269 - if (res) 270 - goto out_err; 271 - sas_set_ex_phy(dev, single, disc_resp); 243 + res = sas_ex_phy_discover_helper(dev, disc_req, disc_resp, single); 272 244 } else { 273 245 int i; 274 246 275 247 for (i = 0; i < ex->num_phys; i++) { 276 - disc_req[9] = i; 277 - res = smp_execute_task(dev, disc_req, 278 - DISCOVER_REQ_SIZE, disc_resp, 279 - DISCOVER_RESP_SIZE); 248 + res = sas_ex_phy_discover_helper(dev, disc_req, 249 + disc_resp, i); 280 250 if (res) 281 251 goto out_err; 282 - sas_set_ex_phy(dev, i, disc_resp); 283 252 } 284 253 } 285 254 out_err: ··· 535 520 536 521 } 537 522 523 + #ifdef CONFIG_SCSI_SAS_ATA 524 + 538 525 #define RPS_REQ_SIZE 16 539 526 #define RPS_RESP_SIZE 60 540 527 ··· 546 529 { 547 530 int res; 548 531 u8 *rps_req = alloc_smp_req(RPS_REQ_SIZE); 532 + u8 *resp = (u8 *)rps_resp; 549 533 550 534 if (!rps_req) 551 535 return -ENOMEM; ··· 557 539 res = smp_execute_task(dev, rps_req, RPS_REQ_SIZE, 558 540 rps_resp, RPS_RESP_SIZE); 559 541 542 + /* 0x34 is the FIS type for the D2H fis. There's a potential 543 + * standards cockup here. sas-2 explicitly specifies the FIS 544 + * should be encoded so that FIS type is in resp[24]. 545 + * However, some expanders endian reverse this. Undo the 546 + * reversal here */ 547 + if (!res && resp[27] == 0x34 && resp[24] != 0x34) { 548 + int i; 549 + 550 + for (i = 0; i < 5; i++) { 551 + int j = 24 + (i*4); 552 + u8 a, b; 553 + a = resp[j + 0]; 554 + b = resp[j + 1]; 555 + resp[j + 0] = resp[j + 3]; 556 + resp[j + 1] = resp[j + 2]; 557 + resp[j + 2] = b; 558 + resp[j + 3] = a; 559 + } 560 + } 561 + 560 562 kfree(rps_req); 561 - return 0; 563 + return res; 562 564 } 565 + #endif 563 566 564 567 static void sas_ex_get_linkrate(struct domain_device *parent, 565 568 struct domain_device *child, ··· 648 609 } 649 610 sas_ex_get_linkrate(parent, child, phy); 650 611 612 + #ifdef CONFIG_SCSI_SAS_ATA 651 613 if ((phy->attached_tproto & SAS_PROTO_STP) || phy->attached_sata_dev) { 652 614 child->dev_type = SATA_DEV; 653 615 if (phy->attached_tproto & SAS_PROTO_STP) ··· 665 625 } 666 626 memcpy(child->frame_rcvd, &child->sata_dev.rps_resp.rps.fis, 667 627 sizeof(struct dev_to_host_fis)); 628 + 629 + rphy = sas_end_device_alloc(phy->port); 630 + if (unlikely(!rphy)) 631 + goto out_free; 632 + 668 633 sas_init_dev(child); 634 + 635 + child->rphy = rphy; 636 + 637 + spin_lock_irq(&parent->port->dev_list_lock); 638 + list_add_tail(&child->dev_list_node, &parent->port->dev_list); 639 + spin_unlock_irq(&parent->port->dev_list_lock); 640 + 669 641 res = sas_discover_sata(child); 670 642 if (res) { 671 643 SAS_DPRINTK("sas_discover_sata() for device %16llx at " 672 644 "%016llx:0x%x returned 0x%x\n", 673 645 SAS_ADDR(child->sas_addr), 674 646 SAS_ADDR(parent->sas_addr), phy_id, res); 675 - goto out_free; 647 + goto out_list_del; 676 648 } 677 - } else if (phy->attached_tproto & SAS_PROTO_SSP) { 649 + } else 650 + #endif 651 + if (phy->attached_tproto & SAS_PROTO_SSP) { 678 652 child->dev_type = SAS_END_DEV; 679 653 rphy = sas_end_device_alloc(phy->port); 680 654 /* FIXME: error handling */ ··· 700 646 child->rphy = rphy; 701 647 sas_fill_in_rphy(child, rphy); 702 648 703 - spin_lock(&parent->port->dev_list_lock); 649 + spin_lock_irq(&parent->port->dev_list_lock); 704 650 list_add_tail(&child->dev_list_node, &parent->port->dev_list); 705 - spin_unlock(&parent->port->dev_list_lock); 651 + spin_unlock_irq(&parent->port->dev_list_lock); 706 652 707 653 res = sas_discover_end_dev(child); 708 654 if (res) { ··· 716 662 SAS_DPRINTK("target proto 0x%x at %016llx:0x%x not handled\n", 717 663 phy->attached_tproto, SAS_ADDR(parent->sas_addr), 718 664 phy_id); 665 + goto out_free; 719 666 } 720 667 721 668 list_add_tail(&child->siblings, &parent_ex->children); ··· 816 761 sas_fill_in_rphy(child, rphy); 817 762 sas_rphy_add(rphy); 818 763 819 - spin_lock(&parent->port->dev_list_lock); 764 + spin_lock_irq(&parent->port->dev_list_lock); 820 765 list_add_tail(&child->dev_list_node, &parent->port->dev_list); 821 - spin_unlock(&parent->port->dev_list_lock); 766 + spin_unlock_irq(&parent->port->dev_list_lock); 822 767 823 768 res = sas_discover_expander(child); 824 769 if (res) { ··· 1414 1359 return 0; 1415 1360 } 1416 1361 1417 - #if 0 1418 - #define SMP_BIN_ATTR_NAME "smp_portal" 1419 - 1420 - static void sas_ex_smp_hook(struct domain_device *dev) 1421 - { 1422 - struct expander_device *ex_dev = &dev->ex_dev; 1423 - struct bin_attribute *bin_attr = &ex_dev->smp_bin_attr; 1424 - 1425 - memset(bin_attr, 0, sizeof(*bin_attr)); 1426 - 1427 - bin_attr->attr.name = SMP_BIN_ATTR_NAME; 1428 - bin_attr->attr.mode = 0600; 1429 - 1430 - bin_attr->size = 0; 1431 - bin_attr->private = NULL; 1432 - bin_attr->read = smp_portal_read; 1433 - bin_attr->write= smp_portal_write; 1434 - bin_attr->mmap = NULL; 1435 - 1436 - ex_dev->smp_portal_pid = -1; 1437 - init_MUTEX(&ex_dev->smp_sema); 1438 - } 1439 - #endif 1440 - 1441 1362 /** 1442 1363 * sas_discover_expander -- expander discovery 1443 1364 * @ex: pointer to expander domain device ··· 1875 1844 return res; 1876 1845 } 1877 1846 1878 - #if 0 1879 - /* ---------- SMP portal ---------- */ 1880 - 1881 - static ssize_t smp_portal_write(struct kobject *kobj, 1882 - struct bin_attribute *bin_attr, 1883 - char *buf, loff_t offs, size_t size) 1847 + int sas_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy, 1848 + struct request *req) 1884 1849 { 1885 - struct domain_device *dev = to_dom_device(kobj); 1886 - struct expander_device *ex = &dev->ex_dev; 1850 + struct domain_device *dev; 1851 + int ret, type = rphy->identify.device_type; 1852 + struct request *rsp = req->next_rq; 1887 1853 1888 - if (offs != 0) 1889 - return -EFBIG; 1890 - else if (size == 0) 1891 - return 0; 1892 - 1893 - down_interruptible(&ex->smp_sema); 1894 - if (ex->smp_req) 1895 - kfree(ex->smp_req); 1896 - ex->smp_req = kzalloc(size, GFP_USER); 1897 - if (!ex->smp_req) { 1898 - up(&ex->smp_sema); 1899 - return -ENOMEM; 1900 - } 1901 - memcpy(ex->smp_req, buf, size); 1902 - ex->smp_req_size = size; 1903 - ex->smp_portal_pid = current->pid; 1904 - up(&ex->smp_sema); 1905 - 1906 - return size; 1907 - } 1908 - 1909 - static ssize_t smp_portal_read(struct kobject *kobj, 1910 - struct bin_attribute *bin_attr, 1911 - char *buf, loff_t offs, size_t size) 1912 - { 1913 - struct domain_device *dev = to_dom_device(kobj); 1914 - struct expander_device *ex = &dev->ex_dev; 1915 - u8 *smp_resp; 1916 - int res = -EINVAL; 1917 - 1918 - /* XXX: sysfs gives us an offset of 0x10 or 0x8 while in fact 1919 - * it should be 0. 1920 - */ 1921 - 1922 - down_interruptible(&ex->smp_sema); 1923 - if (!ex->smp_req || ex->smp_portal_pid != current->pid) 1924 - goto out; 1925 - 1926 - res = 0; 1927 - if (size == 0) 1928 - goto out; 1929 - 1930 - res = -ENOMEM; 1931 - smp_resp = alloc_smp_resp(size); 1932 - if (!smp_resp) 1933 - goto out; 1934 - res = smp_execute_task(dev, ex->smp_req, ex->smp_req_size, 1935 - smp_resp, size); 1936 - if (!res) { 1937 - memcpy(buf, smp_resp, size); 1938 - res = size; 1854 + if (!rsp) { 1855 + printk("%s: space for a smp response is missing\n", 1856 + __FUNCTION__); 1857 + return -EINVAL; 1939 1858 } 1940 1859 1941 - kfree(smp_resp); 1942 - out: 1943 - kfree(ex->smp_req); 1944 - ex->smp_req = NULL; 1945 - ex->smp_req_size = 0; 1946 - ex->smp_portal_pid = -1; 1947 - up(&ex->smp_sema); 1948 - return res; 1860 + /* seems aic94xx doesn't support */ 1861 + if (!rphy) { 1862 + printk("%s: can we send a smp request to a host?\n", 1863 + __FUNCTION__); 1864 + return -EINVAL; 1865 + } 1866 + 1867 + if (type != SAS_EDGE_EXPANDER_DEVICE && 1868 + type != SAS_FANOUT_EXPANDER_DEVICE) { 1869 + printk("%s: can we send a smp request to a device?\n", 1870 + __FUNCTION__); 1871 + return -EINVAL; 1872 + } 1873 + 1874 + dev = sas_find_dev_by_rphy(rphy); 1875 + if (!dev) { 1876 + printk("%s: fail to find a domain_device?\n", __FUNCTION__); 1877 + return -EINVAL; 1878 + } 1879 + 1880 + /* do we need to support multiple segments? */ 1881 + if (req->bio->bi_vcnt > 1 || rsp->bio->bi_vcnt > 1) { 1882 + printk("%s: multiple segments req %u %u, rsp %u %u\n", 1883 + __FUNCTION__, req->bio->bi_vcnt, req->data_len, 1884 + rsp->bio->bi_vcnt, rsp->data_len); 1885 + return -EINVAL; 1886 + } 1887 + 1888 + ret = smp_execute_task(dev, bio_data(req->bio), req->data_len, 1889 + bio_data(rsp->bio), rsp->data_len); 1890 + 1891 + return ret; 1949 1892 } 1950 - #endif

+1

drivers/scsi/libsas/sas_init.c

··· 259 259 .phy_reset = sas_phy_reset, 260 260 .set_phy_speed = sas_set_phy_speed, 261 261 .get_linkerrors = sas_get_linkerrors, 262 + .smp_handler = sas_smp_handler, 262 263 }; 263 264 264 265 struct scsi_transport_template *

+3

drivers/scsi/libsas/sas_internal.h

··· 39 39 #define SAS_DPRINTK(fmt, ...) 40 40 #endif 41 41 42 + #define TO_SAS_TASK(_scsi_cmd) ((void *)(_scsi_cmd)->host_scribble) 43 + #define ASSIGN_SAS_TASK(_sc, _t) do { (_sc)->host_scribble = (void *) _t; } while (0) 44 + 42 45 void sas_scsi_recover_host(struct Scsi_Host *shost); 43 46 44 47 int sas_show_class(enum sas_class class, char *buf);

+70 -4

drivers/scsi/libsas/sas_scsi_host.c

··· 34 34 #include <scsi/scsi_eh.h> 35 35 #include <scsi/scsi_transport.h> 36 36 #include <scsi/scsi_transport_sas.h> 37 + #include <scsi/sas_ata.h> 37 38 #include "../scsi_sas_internal.h" 38 39 #include "../scsi_transport_api.h" 39 40 #include "../scsi_priv.h" ··· 43 42 #include <linux/blkdev.h> 44 43 #include <linux/freezer.h> 45 44 #include <linux/scatterlist.h> 45 + #include <linux/libata.h> 46 46 47 47 /* ---------- SCSI Host glue ---------- */ 48 - 49 - #define TO_SAS_TASK(_scsi_cmd) ((void *)(_scsi_cmd)->host_scribble) 50 - #define ASSIGN_SAS_TASK(_sc, _t) do { (_sc)->host_scribble = (void *) _t; } while (0) 51 48 52 49 static void sas_scsi_task_done(struct sas_task *task) 53 50 { ··· 171 172 return task; 172 173 } 173 174 174 - static int sas_queue_up(struct sas_task *task) 175 + int sas_queue_up(struct sas_task *task) 175 176 { 176 177 struct sas_ha_struct *sas_ha = task->dev->port->ha; 177 178 struct scsi_core *core = &sas_ha->core; ··· 211 212 { 212 213 struct sas_ha_struct *sas_ha = dev->port->ha; 213 214 struct sas_task *task; 215 + 216 + if (dev_is_sata(dev)) { 217 + unsigned long flags; 218 + 219 + spin_lock_irqsave(dev->sata_dev.ap->lock, flags); 220 + res = ata_sas_queuecmd(cmd, scsi_done, 221 + dev->sata_dev.ap); 222 + spin_unlock_irqrestore(dev->sata_dev.ap->lock, flags); 223 + goto out; 224 + } 214 225 215 226 res = -ENOMEM; 216 227 task = sas_create_task(cmd, dev, GFP_ATOMIC); ··· 693 684 return EH_NOT_HANDLED; 694 685 } 695 686 687 + int sas_ioctl(struct scsi_device *sdev, int cmd, void __user *arg) 688 + { 689 + struct domain_device *dev = sdev_to_domain_dev(sdev); 690 + 691 + if (dev_is_sata(dev)) 692 + return ata_scsi_ioctl(sdev, cmd, arg); 693 + 694 + return -EINVAL; 695 + } 696 + 696 697 struct domain_device *sas_find_dev_by_rphy(struct sas_rphy *rphy) 697 698 { 698 699 struct Scsi_Host *shost = dev_to_shost(rphy->dev.parent); ··· 742 723 int sas_target_alloc(struct scsi_target *starget) 743 724 { 744 725 struct domain_device *found_dev = sas_find_target(starget); 726 + int res; 745 727 746 728 if (!found_dev) 747 729 return -ENODEV; 730 + 731 + if (dev_is_sata(found_dev)) { 732 + res = sas_ata_init_host_and_port(found_dev, starget); 733 + if (res) 734 + return res; 735 + } 748 736 749 737 starget->hostdata = found_dev; 750 738 return 0; ··· 766 740 struct sas_ha_struct *sas_ha; 767 741 768 742 BUG_ON(dev->rphy->identify.device_type != SAS_END_DEVICE); 743 + 744 + if (dev_is_sata(dev)) { 745 + ata_sas_slave_configure(scsi_dev, dev->sata_dev.ap); 746 + return 0; 747 + } 769 748 770 749 sas_ha = dev->port->ha; 771 750 ··· 795 764 796 765 void sas_slave_destroy(struct scsi_device *scsi_dev) 797 766 { 767 + struct domain_device *dev = sdev_to_domain_dev(scsi_dev); 768 + 769 + if (dev_is_sata(dev)) 770 + ata_port_disable(dev->sata_dev.ap); 798 771 } 799 772 800 773 int sas_change_queue_depth(struct scsi_device *scsi_dev, int new_depth) ··· 1015 980 return; 1016 981 } 1017 982 983 + if (dev_is_sata(task->dev)) { 984 + sas_ata_task_abort(task); 985 + return; 986 + } 987 + 1018 988 scsi_req_abort_cmd(sc); 1019 989 scsi_schedule_eh(sc->device->host); 990 + } 991 + 992 + int sas_slave_alloc(struct scsi_device *scsi_dev) 993 + { 994 + struct domain_device *dev = sdev_to_domain_dev(scsi_dev); 995 + 996 + if (dev_is_sata(dev)) 997 + return ata_sas_port_init(dev->sata_dev.ap); 998 + 999 + return 0; 1000 + } 1001 + 1002 + void sas_target_destroy(struct scsi_target *starget) 1003 + { 1004 + struct domain_device *found_dev = sas_find_target(starget); 1005 + 1006 + if (!found_dev) 1007 + return; 1008 + 1009 + if (dev_is_sata(found_dev)) 1010 + ata_sas_port_destroy(found_dev->sata_dev.ap); 1011 + 1012 + return; 1020 1013 } 1021 1014 1022 1015 EXPORT_SYMBOL_GPL(sas_queuecommand); ··· 1060 997 EXPORT_SYMBOL_GPL(sas_phy_enable); 1061 998 EXPORT_SYMBOL_GPL(sas_eh_device_reset_handler); 1062 999 EXPORT_SYMBOL_GPL(sas_eh_bus_reset_handler); 1000 + EXPORT_SYMBOL_GPL(sas_slave_alloc); 1001 + EXPORT_SYMBOL_GPL(sas_target_destroy); 1002 + EXPORT_SYMBOL_GPL(sas_ioctl);

+2 -1

drivers/scsi/mvme16x_scsi.c

··· 89 89 out_be32(0xfff4202c, v); 90 90 } 91 91 92 + dev_set_drvdata(dev, host); 92 93 scsi_scan_host(host); 93 94 94 95 return 0; ··· 105 104 static __devexit int 106 105 mvme16x_device_remove(struct device *dev) 107 106 { 108 - struct Scsi_Host *host = dev_to_shost(dev); 107 + struct Scsi_Host *host = dev_get_drvdata(dev); 109 108 struct NCR_700_Host_Parameters *hostdata = shost_priv(host); 110 109 111 110 /* Disable scsi chip ints */

+5 -2

drivers/scsi/pcmcia/Kconfig

··· 2 2 # PCMCIA SCSI adapter configuration 3 3 # 4 4 5 - menu "PCMCIA SCSI adapter support" 5 + menuconfig SCSI_LOWLEVEL_PCMCIA 6 + bool "PCMCIA SCSI adapter support" 6 7 depends on SCSI!=n && PCMCIA!=n 8 + 9 + if SCSI_LOWLEVEL_PCMCIA && SCSI && PCMCIA 7 10 8 11 config PCMCIA_AHA152X 9 12 tristate "Adaptec AHA152X PCMCIA support" ··· 80 77 To compile this driver as a module, choose M here: the 81 78 module will be called sym53c500_cs. 82 79 83 - endmenu 80 + endif # SCSI_LOWLEVEL_PCMCIA

+17 -16

drivers/scsi/qla2xxx/qla_attr.c

··· 98 98 99 99 /* Read NVRAM. */ 100 100 spin_lock_irqsave(&ha->hardware_lock, flags); 101 - ha->isp_ops.read_nvram(ha, (uint8_t *)buf, ha->nvram_base, 101 + ha->isp_ops->read_nvram(ha, (uint8_t *)buf, ha->nvram_base, 102 102 ha->nvram_size); 103 103 spin_unlock_irqrestore(&ha->hardware_lock, flags); 104 104 ··· 119 119 return 0; 120 120 121 121 /* Checksum NVRAM. */ 122 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 122 + if (IS_FWI2_CAPABLE(ha)) { 123 123 uint32_t *iter; 124 124 uint32_t chksum; 125 125 ··· 143 143 144 144 /* Write NVRAM. */ 145 145 spin_lock_irqsave(&ha->hardware_lock, flags); 146 - ha->isp_ops.write_nvram(ha, (uint8_t *)buf, ha->nvram_base, count); 146 + ha->isp_ops->write_nvram(ha, (uint8_t *)buf, ha->nvram_base, count); 147 147 spin_unlock_irqrestore(&ha->hardware_lock, flags); 148 148 149 149 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); ··· 206 206 .name = "optrom", 207 207 .mode = S_IRUSR | S_IWUSR, 208 208 }, 209 - .size = OPTROM_SIZE_24XX, 209 + .size = 0, 210 210 .read = qla2x00_sysfs_read_optrom, 211 211 .write = qla2x00_sysfs_write_optrom, 212 212 }; ··· 252 252 } 253 253 254 254 memset(ha->optrom_buffer, 0, ha->optrom_size); 255 - ha->isp_ops.read_optrom(ha, ha->optrom_buffer, 0, 255 + ha->isp_ops->read_optrom(ha, ha->optrom_buffer, 0, 256 256 ha->optrom_size); 257 257 break; 258 258 case 2: ··· 275 275 if (ha->optrom_state != QLA_SWRITING) 276 276 break; 277 277 278 - ha->isp_ops.write_optrom(ha, ha->optrom_buffer, 0, 278 + ha->isp_ops->write_optrom(ha, ha->optrom_buffer, 0, 279 279 ha->optrom_size); 280 280 break; 281 281 } ··· 305 305 306 306 /* Read NVRAM. */ 307 307 spin_lock_irqsave(&ha->hardware_lock, flags); 308 - ha->isp_ops.read_nvram(ha, (uint8_t *)buf, ha->vpd_base, ha->vpd_size); 308 + ha->isp_ops->read_nvram(ha, (uint8_t *)buf, ha->vpd_base, 309 + ha->vpd_size); 309 310 spin_unlock_irqrestore(&ha->hardware_lock, flags); 310 311 311 312 return ha->vpd_size; ··· 326 325 327 326 /* Write NVRAM. */ 328 327 spin_lock_irqsave(&ha->hardware_lock, flags); 329 - ha->isp_ops.write_nvram(ha, (uint8_t *)buf, ha->vpd_base, count); 328 + ha->isp_ops->write_nvram(ha, (uint8_t *)buf, ha->vpd_base, count); 330 329 spin_unlock_irqrestore(&ha->hardware_lock, flags); 331 330 332 331 return count; ··· 411 410 int ret; 412 411 413 412 for (iter = bin_file_entries; iter->name; iter++) { 414 - if (iter->is4GBp_only && (!IS_QLA24XX(ha) && !IS_QLA54XX(ha))) 413 + if (iter->is4GBp_only && !IS_FWI2_CAPABLE(ha)) 415 414 continue; 416 415 417 416 ret = sysfs_create_bin_file(&host->shost_gendev.kobj, ··· 430 429 struct sysfs_entry *iter; 431 430 432 431 for (iter = bin_file_entries; iter->name; iter++) { 433 - if (iter->is4GBp_only && (!IS_QLA24XX(ha) && !IS_QLA54XX(ha))) 432 + if (iter->is4GBp_only && !IS_FWI2_CAPABLE(ha)) 434 433 continue; 435 434 436 435 sysfs_remove_bin_file(&host->shost_gendev.kobj, ··· 438 437 } 439 438 440 439 if (ha->beacon_blink_led == 1) 441 - ha->isp_ops.beacon_off(ha); 440 + ha->isp_ops->beacon_off(ha); 442 441 } 443 442 444 443 /* Scsi_Host attributes. */ ··· 456 455 char fw_str[30]; 457 456 458 457 return snprintf(buf, PAGE_SIZE, "%s\n", 459 - ha->isp_ops.fw_version_str(ha, fw_str)); 458 + ha->isp_ops->fw_version_str(ha, fw_str)); 460 459 } 461 460 462 461 static ssize_t ··· 508 507 char pci_info[30]; 509 508 510 509 return snprintf(buf, PAGE_SIZE, "%s\n", 511 - ha->isp_ops.pci_info_str(ha, pci_info)); 510 + ha->isp_ops->pci_info_str(ha, pci_info)); 512 511 } 513 512 514 513 static ssize_t ··· 653 652 return -EINVAL; 654 653 655 654 if (val) 656 - rval = ha->isp_ops.beacon_on(ha); 655 + rval = ha->isp_ops->beacon_on(ha); 657 656 else 658 - rval = ha->isp_ops.beacon_off(ha); 657 + rval = ha->isp_ops->beacon_off(ha); 659 658 660 659 if (rval != QLA_SUCCESS) 661 660 count = 0; ··· 899 898 pfc_host_stat = &ha->fc_host_stat; 900 899 memset(pfc_host_stat, -1, sizeof(struct fc_host_statistics)); 901 900 902 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 901 + if (IS_FWI2_CAPABLE(ha)) { 903 902 rval = qla24xx_get_isp_stats(ha, (uint32_t *)&stat_buf, 904 903 sizeof(stat_buf) / 4, mb_stat); 905 904 } else if (atomic_read(&ha->loop_state) == LOOP_READY &&

+925 -219

drivers/scsi/qla2xxx/qla_dbg.c

··· 37 37 return ptr + (ha->response_q_length * sizeof(response_t)); 38 38 } 39 39 40 + static int 41 + qla2xxx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram, 42 + uint32_t cram_size, uint32_t *ext_mem, void **nxt) 43 + { 44 + int rval; 45 + uint32_t cnt, stat, timer, risc_address, ext_mem_cnt; 46 + uint16_t mb[4]; 47 + struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 48 + 49 + rval = QLA_SUCCESS; 50 + risc_address = ext_mem_cnt = 0; 51 + memset(mb, 0, sizeof(mb)); 52 + 53 + /* Code RAM. */ 54 + risc_address = 0x20000; 55 + WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED); 56 + clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 57 + 58 + for (cnt = 0; cnt < cram_size / 4 && rval == QLA_SUCCESS; 59 + cnt++, risc_address++) { 60 + WRT_REG_WORD(&reg->mailbox1, LSW(risc_address)); 61 + WRT_REG_WORD(&reg->mailbox8, MSW(risc_address)); 62 + RD_REG_WORD(&reg->mailbox8); 63 + WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); 64 + 65 + for (timer = 6000000; timer; timer--) { 66 + /* Check for pending interrupts. */ 67 + stat = RD_REG_DWORD(&reg->host_status); 68 + if (stat & HSRX_RISC_INT) { 69 + stat &= 0xff; 70 + 71 + if (stat == 0x1 || stat == 0x2 || 72 + stat == 0x10 || stat == 0x11) { 73 + set_bit(MBX_INTERRUPT, 74 + &ha->mbx_cmd_flags); 75 + 76 + mb[0] = RD_REG_WORD(&reg->mailbox0); 77 + mb[2] = RD_REG_WORD(&reg->mailbox2); 78 + mb[3] = RD_REG_WORD(&reg->mailbox3); 79 + 80 + WRT_REG_DWORD(&reg->hccr, 81 + HCCRX_CLR_RISC_INT); 82 + RD_REG_DWORD(&reg->hccr); 83 + break; 84 + } 85 + 86 + /* Clear this intr; it wasn't a mailbox intr */ 87 + WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); 88 + RD_REG_DWORD(&reg->hccr); 89 + } 90 + udelay(5); 91 + } 92 + 93 + if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 94 + rval = mb[0] & MBS_MASK; 95 + code_ram[cnt] = htonl((mb[3] << 16) | mb[2]); 96 + } else { 97 + rval = QLA_FUNCTION_FAILED; 98 + } 99 + } 100 + 101 + if (rval == QLA_SUCCESS) { 102 + /* External Memory. */ 103 + risc_address = 0x100000; 104 + ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1; 105 + WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED); 106 + clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 107 + } 108 + for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS; 109 + cnt++, risc_address++) { 110 + WRT_REG_WORD(&reg->mailbox1, LSW(risc_address)); 111 + WRT_REG_WORD(&reg->mailbox8, MSW(risc_address)); 112 + RD_REG_WORD(&reg->mailbox8); 113 + WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); 114 + 115 + for (timer = 6000000; timer; timer--) { 116 + /* Check for pending interrupts. */ 117 + stat = RD_REG_DWORD(&reg->host_status); 118 + if (stat & HSRX_RISC_INT) { 119 + stat &= 0xff; 120 + 121 + if (stat == 0x1 || stat == 0x2 || 122 + stat == 0x10 || stat == 0x11) { 123 + set_bit(MBX_INTERRUPT, 124 + &ha->mbx_cmd_flags); 125 + 126 + mb[0] = RD_REG_WORD(&reg->mailbox0); 127 + mb[2] = RD_REG_WORD(&reg->mailbox2); 128 + mb[3] = RD_REG_WORD(&reg->mailbox3); 129 + 130 + WRT_REG_DWORD(&reg->hccr, 131 + HCCRX_CLR_RISC_INT); 132 + RD_REG_DWORD(&reg->hccr); 133 + break; 134 + } 135 + 136 + /* Clear this intr; it wasn't a mailbox intr */ 137 + WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); 138 + RD_REG_DWORD(&reg->hccr); 139 + } 140 + udelay(5); 141 + } 142 + 143 + if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 144 + rval = mb[0] & MBS_MASK; 145 + ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]); 146 + } else { 147 + rval = QLA_FUNCTION_FAILED; 148 + } 149 + } 150 + 151 + *nxt = rval == QLA_SUCCESS ? &ext_mem[cnt]: NULL; 152 + return rval; 153 + } 154 + 40 155 /** 41 156 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. 42 157 * @ha: HA context ··· 748 633 qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) 749 634 { 750 635 int rval; 751 - uint32_t cnt, timer; 636 + uint32_t cnt; 752 637 uint32_t risc_address; 753 - uint16_t mb[4], wd; 638 + uint16_t mb0, wd; 754 639 755 - uint32_t stat; 756 640 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 757 641 uint32_t __iomem *dmp_reg; 758 642 uint32_t *iter_reg; ··· 759 645 unsigned long flags; 760 646 struct qla24xx_fw_dump *fw; 761 647 uint32_t ext_mem_cnt; 762 - void *eft; 648 + void *nxt; 763 649 764 650 risc_address = ext_mem_cnt = 0; 765 - memset(mb, 0, sizeof(mb)); 766 651 flags = 0; 767 652 768 653 if (!hardware_locked) ··· 814 701 /* Shadow registers. */ 815 702 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 816 703 RD_REG_DWORD(&reg->iobase_addr); 817 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 818 - WRT_REG_DWORD(dmp_reg, 0xB0000000); 819 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 820 - fw->shadow_reg[0] = htonl(RD_REG_DWORD(dmp_reg)); 704 + WRT_REG_DWORD(&reg->iobase_select, 0xB0000000); 705 + fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 821 706 822 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 823 - WRT_REG_DWORD(dmp_reg, 0xB0100000); 824 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 825 - fw->shadow_reg[1] = htonl(RD_REG_DWORD(dmp_reg)); 707 + WRT_REG_DWORD(&reg->iobase_select, 0xB0100000); 708 + fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 826 709 827 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 828 - WRT_REG_DWORD(dmp_reg, 0xB0200000); 829 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 830 - fw->shadow_reg[2] = htonl(RD_REG_DWORD(dmp_reg)); 710 + WRT_REG_DWORD(&reg->iobase_select, 0xB0200000); 711 + fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 831 712 832 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 833 - WRT_REG_DWORD(dmp_reg, 0xB0300000); 834 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 835 - fw->shadow_reg[3] = htonl(RD_REG_DWORD(dmp_reg)); 713 + WRT_REG_DWORD(&reg->iobase_select, 0xB0300000); 714 + fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 836 715 837 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 838 - WRT_REG_DWORD(dmp_reg, 0xB0400000); 839 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 840 - fw->shadow_reg[4] = htonl(RD_REG_DWORD(dmp_reg)); 716 + WRT_REG_DWORD(&reg->iobase_select, 0xB0400000); 717 + fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 841 718 842 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 843 - WRT_REG_DWORD(dmp_reg, 0xB0500000); 844 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 845 - fw->shadow_reg[5] = htonl(RD_REG_DWORD(dmp_reg)); 719 + WRT_REG_DWORD(&reg->iobase_select, 0xB0500000); 720 + fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 846 721 847 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0); 848 - WRT_REG_DWORD(dmp_reg, 0xB0600000); 849 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC); 850 - fw->shadow_reg[6] = htonl(RD_REG_DWORD(dmp_reg)); 722 + WRT_REG_DWORD(&reg->iobase_select, 0xB0600000); 723 + fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 851 724 852 725 /* Mailbox registers. */ 853 - mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80); 726 + mbx_reg = &reg->mailbox0; 854 727 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 855 728 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 856 729 857 730 /* Transfer sequence registers. */ 858 731 iter_reg = fw->xseq_gp_reg; 859 732 WRT_REG_DWORD(&reg->iobase_addr, 0xBF00); 860 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 733 + dmp_reg = &reg->iobase_window; 861 734 for (cnt = 0; cnt < 16; cnt++) 862 735 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 863 736 864 737 WRT_REG_DWORD(&reg->iobase_addr, 0xBF10); 865 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 738 + dmp_reg = &reg->iobase_window; 866 739 for (cnt = 0; cnt < 16; cnt++) 867 740 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 868 741 869 742 WRT_REG_DWORD(&reg->iobase_addr, 0xBF20); 870 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 743 + dmp_reg = &reg->iobase_window; 871 744 for (cnt = 0; cnt < 16; cnt++) 872 745 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 873 746 874 747 WRT_REG_DWORD(&reg->iobase_addr, 0xBF30); 875 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 748 + dmp_reg = &reg->iobase_window; 876 749 for (cnt = 0; cnt < 16; cnt++) 877 750 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 878 751 879 752 WRT_REG_DWORD(&reg->iobase_addr, 0xBF40); 880 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 753 + dmp_reg = &reg->iobase_window; 881 754 for (cnt = 0; cnt < 16; cnt++) 882 755 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 883 756 884 757 WRT_REG_DWORD(&reg->iobase_addr, 0xBF50); 885 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 758 + dmp_reg = &reg->iobase_window; 886 759 for (cnt = 0; cnt < 16; cnt++) 887 760 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 888 761 889 762 WRT_REG_DWORD(&reg->iobase_addr, 0xBF60); 890 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 763 + dmp_reg = &reg->iobase_window; 891 764 for (cnt = 0; cnt < 16; cnt++) 892 765 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 893 766 894 767 WRT_REG_DWORD(&reg->iobase_addr, 0xBF70); 895 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 768 + dmp_reg = &reg->iobase_window; 896 769 for (cnt = 0; cnt < 16; cnt++) 897 770 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 898 771 899 772 WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0); 900 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 773 + dmp_reg = &reg->iobase_window; 901 774 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) 902 775 fw->xseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 903 776 904 777 WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0); 905 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 778 + dmp_reg = &reg->iobase_window; 906 779 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) 907 780 fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 908 781 909 782 /* Receive sequence registers. */ 910 783 iter_reg = fw->rseq_gp_reg; 911 784 WRT_REG_DWORD(&reg->iobase_addr, 0xFF00); 912 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 785 + dmp_reg = &reg->iobase_window; 913 786 for (cnt = 0; cnt < 16; cnt++) 914 787 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 915 788 916 789 WRT_REG_DWORD(&reg->iobase_addr, 0xFF10); 917 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 790 + dmp_reg = &reg->iobase_window; 918 791 for (cnt = 0; cnt < 16; cnt++) 919 792 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 920 793 921 794 WRT_REG_DWORD(&reg->iobase_addr, 0xFF20); 922 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 795 + dmp_reg = &reg->iobase_window; 923 796 for (cnt = 0; cnt < 16; cnt++) 924 797 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 925 798 926 799 WRT_REG_DWORD(&reg->iobase_addr, 0xFF30); 927 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 800 + dmp_reg = &reg->iobase_window; 928 801 for (cnt = 0; cnt < 16; cnt++) 929 802 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 930 803 931 804 WRT_REG_DWORD(&reg->iobase_addr, 0xFF40); 932 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 805 + dmp_reg = &reg->iobase_window; 933 806 for (cnt = 0; cnt < 16; cnt++) 934 807 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 935 808 936 809 WRT_REG_DWORD(&reg->iobase_addr, 0xFF50); 937 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 810 + dmp_reg = &reg->iobase_window; 938 811 for (cnt = 0; cnt < 16; cnt++) 939 812 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 940 813 941 814 WRT_REG_DWORD(&reg->iobase_addr, 0xFF60); 942 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 815 + dmp_reg = &reg->iobase_window; 943 816 for (cnt = 0; cnt < 16; cnt++) 944 817 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 945 818 946 819 WRT_REG_DWORD(&reg->iobase_addr, 0xFF70); 947 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 820 + dmp_reg = &reg->iobase_window; 948 821 for (cnt = 0; cnt < 16; cnt++) 949 822 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 950 823 951 824 WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0); 952 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 825 + dmp_reg = &reg->iobase_window; 953 826 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) 954 827 fw->rseq_0_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 955 828 956 829 WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0); 957 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 830 + dmp_reg = &reg->iobase_window; 958 831 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) 959 832 fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 960 833 961 834 WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0); 962 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 835 + dmp_reg = &reg->iobase_window; 963 836 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) 964 837 fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 965 838 966 839 /* Command DMA registers. */ 967 840 WRT_REG_DWORD(&reg->iobase_addr, 0x7100); 968 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 841 + dmp_reg = &reg->iobase_window; 969 842 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) 970 843 fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 971 844 972 845 /* Queues. */ 973 846 iter_reg = fw->req0_dma_reg; 974 847 WRT_REG_DWORD(&reg->iobase_addr, 0x7200); 975 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 848 + dmp_reg = &reg->iobase_window; 976 849 for (cnt = 0; cnt < 8; cnt++) 977 850 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 978 851 979 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); 852 + dmp_reg = &reg->iobase_q; 980 853 for (cnt = 0; cnt < 7; cnt++) 981 854 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 982 855 983 856 iter_reg = fw->resp0_dma_reg; 984 857 WRT_REG_DWORD(&reg->iobase_addr, 0x7300); 985 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 858 + dmp_reg = &reg->iobase_window; 986 859 for (cnt = 0; cnt < 8; cnt++) 987 860 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 988 861 989 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); 862 + dmp_reg = &reg->iobase_q; 990 863 for (cnt = 0; cnt < 7; cnt++) 991 864 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 992 865 993 866 iter_reg = fw->req1_dma_reg; 994 867 WRT_REG_DWORD(&reg->iobase_addr, 0x7400); 995 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 868 + dmp_reg = &reg->iobase_window; 996 869 for (cnt = 0; cnt < 8; cnt++) 997 870 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 998 871 999 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4); 872 + dmp_reg = &reg->iobase_q; 1000 873 for (cnt = 0; cnt < 7; cnt++) 1001 874 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1002 875 1003 876 /* Transmit DMA registers. */ 1004 877 iter_reg = fw->xmt0_dma_reg; 1005 878 WRT_REG_DWORD(&reg->iobase_addr, 0x7600); 1006 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 879 + dmp_reg = &reg->iobase_window; 1007 880 for (cnt = 0; cnt < 16; cnt++) 1008 881 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1009 882 1010 883 WRT_REG_DWORD(&reg->iobase_addr, 0x7610); 1011 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 884 + dmp_reg = &reg->iobase_window; 1012 885 for (cnt = 0; cnt < 16; cnt++) 1013 886 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1014 887 1015 888 iter_reg = fw->xmt1_dma_reg; 1016 889 WRT_REG_DWORD(&reg->iobase_addr, 0x7620); 1017 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 890 + dmp_reg = &reg->iobase_window; 1018 891 for (cnt = 0; cnt < 16; cnt++) 1019 892 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1020 893 1021 894 WRT_REG_DWORD(&reg->iobase_addr, 0x7630); 1022 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 895 + dmp_reg = &reg->iobase_window; 1023 896 for (cnt = 0; cnt < 16; cnt++) 1024 897 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1025 898 1026 899 iter_reg = fw->xmt2_dma_reg; 1027 900 WRT_REG_DWORD(&reg->iobase_addr, 0x7640); 1028 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 901 + dmp_reg = &reg->iobase_window; 1029 902 for (cnt = 0; cnt < 16; cnt++) 1030 903 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1031 904 1032 905 WRT_REG_DWORD(&reg->iobase_addr, 0x7650); 1033 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 906 + dmp_reg = &reg->iobase_window; 1034 907 for (cnt = 0; cnt < 16; cnt++) 1035 908 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1036 909 1037 910 iter_reg = fw->xmt3_dma_reg; 1038 911 WRT_REG_DWORD(&reg->iobase_addr, 0x7660); 1039 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 912 + dmp_reg = &reg->iobase_window; 1040 913 for (cnt = 0; cnt < 16; cnt++) 1041 914 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1042 915 1043 916 WRT_REG_DWORD(&reg->iobase_addr, 0x7670); 1044 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 917 + dmp_reg = &reg->iobase_window; 1045 918 for (cnt = 0; cnt < 16; cnt++) 1046 919 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1047 920 1048 921 iter_reg = fw->xmt4_dma_reg; 1049 922 WRT_REG_DWORD(&reg->iobase_addr, 0x7680); 1050 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 923 + dmp_reg = &reg->iobase_window; 1051 924 for (cnt = 0; cnt < 16; cnt++) 1052 925 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1053 926 1054 927 WRT_REG_DWORD(&reg->iobase_addr, 0x7690); 1055 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 928 + dmp_reg = &reg->iobase_window; 1056 929 for (cnt = 0; cnt < 16; cnt++) 1057 930 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1058 931 1059 932 WRT_REG_DWORD(&reg->iobase_addr, 0x76A0); 1060 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 933 + dmp_reg = &reg->iobase_window; 1061 934 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) 1062 935 fw->xmt_data_dma_reg[cnt] = 1063 936 htonl(RD_REG_DWORD(dmp_reg++)); ··· 1051 952 /* Receive DMA registers. */ 1052 953 iter_reg = fw->rcvt0_data_dma_reg; 1053 954 WRT_REG_DWORD(&reg->iobase_addr, 0x7700); 1054 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 955 + dmp_reg = &reg->iobase_window; 1055 956 for (cnt = 0; cnt < 16; cnt++) 1056 957 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1057 958 1058 959 WRT_REG_DWORD(&reg->iobase_addr, 0x7710); 1059 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 960 + dmp_reg = &reg->iobase_window; 1060 961 for (cnt = 0; cnt < 16; cnt++) 1061 962 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1062 963 1063 964 iter_reg = fw->rcvt1_data_dma_reg; 1064 965 WRT_REG_DWORD(&reg->iobase_addr, 0x7720); 1065 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 966 + dmp_reg = &reg->iobase_window; 1066 967 for (cnt = 0; cnt < 16; cnt++) 1067 968 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1068 969 1069 970 WRT_REG_DWORD(&reg->iobase_addr, 0x7730); 1070 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 971 + dmp_reg = &reg->iobase_window; 1071 972 for (cnt = 0; cnt < 16; cnt++) 1072 973 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1073 974 1074 975 /* RISC registers. */ 1075 976 iter_reg = fw->risc_gp_reg; 1076 977 WRT_REG_DWORD(&reg->iobase_addr, 0x0F00); 1077 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 978 + dmp_reg = &reg->iobase_window; 1078 979 for (cnt = 0; cnt < 16; cnt++) 1079 980 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1080 981 1081 982 WRT_REG_DWORD(&reg->iobase_addr, 0x0F10); 1082 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 983 + dmp_reg = &reg->iobase_window; 1083 984 for (cnt = 0; cnt < 16; cnt++) 1084 985 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1085 986 1086 987 WRT_REG_DWORD(&reg->iobase_addr, 0x0F20); 1087 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 988 + dmp_reg = &reg->iobase_window; 1088 989 for (cnt = 0; cnt < 16; cnt++) 1089 990 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1090 991 1091 992 WRT_REG_DWORD(&reg->iobase_addr, 0x0F30); 1092 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 993 + dmp_reg = &reg->iobase_window; 1093 994 for (cnt = 0; cnt < 16; cnt++) 1094 995 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1095 996 1096 997 WRT_REG_DWORD(&reg->iobase_addr, 0x0F40); 1097 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 998 + dmp_reg = &reg->iobase_window; 1098 999 for (cnt = 0; cnt < 16; cnt++) 1099 1000 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1100 1001 1101 1002 WRT_REG_DWORD(&reg->iobase_addr, 0x0F50); 1102 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1003 + dmp_reg = &reg->iobase_window; 1103 1004 for (cnt = 0; cnt < 16; cnt++) 1104 1005 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1105 1006 1106 1007 WRT_REG_DWORD(&reg->iobase_addr, 0x0F60); 1107 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1008 + dmp_reg = &reg->iobase_window; 1108 1009 for (cnt = 0; cnt < 16; cnt++) 1109 1010 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1110 1011 1111 1012 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 1112 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1013 + dmp_reg = &reg->iobase_window; 1113 1014 for (cnt = 0; cnt < 16; cnt++) 1114 1015 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1115 1016 1116 1017 /* Local memory controller registers. */ 1117 1018 iter_reg = fw->lmc_reg; 1118 1019 WRT_REG_DWORD(&reg->iobase_addr, 0x3000); 1119 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1020 + dmp_reg = &reg->iobase_window; 1120 1021 for (cnt = 0; cnt < 16; cnt++) 1121 1022 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1122 1023 1123 1024 WRT_REG_DWORD(&reg->iobase_addr, 0x3010); 1124 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1025 + dmp_reg = &reg->iobase_window; 1125 1026 for (cnt = 0; cnt < 16; cnt++) 1126 1027 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1127 1028 1128 1029 WRT_REG_DWORD(&reg->iobase_addr, 0x3020); 1129 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1030 + dmp_reg = &reg->iobase_window; 1130 1031 for (cnt = 0; cnt < 16; cnt++) 1131 1032 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1132 1033 1133 1034 WRT_REG_DWORD(&reg->iobase_addr, 0x3030); 1134 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1035 + dmp_reg = &reg->iobase_window; 1135 1036 for (cnt = 0; cnt < 16; cnt++) 1136 1037 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1137 1038 1138 1039 WRT_REG_DWORD(&reg->iobase_addr, 0x3040); 1139 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1040 + dmp_reg = &reg->iobase_window; 1140 1041 for (cnt = 0; cnt < 16; cnt++) 1141 1042 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1142 1043 1143 1044 WRT_REG_DWORD(&reg->iobase_addr, 0x3050); 1144 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1045 + dmp_reg = &reg->iobase_window; 1145 1046 for (cnt = 0; cnt < 16; cnt++) 1146 1047 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1147 1048 1148 1049 WRT_REG_DWORD(&reg->iobase_addr, 0x3060); 1149 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1050 + dmp_reg = &reg->iobase_window; 1150 1051 for (cnt = 0; cnt < 16; cnt++) 1151 1052 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1152 1053 1153 1054 /* Fibre Protocol Module registers. */ 1154 1055 iter_reg = fw->fpm_hdw_reg; 1155 1056 WRT_REG_DWORD(&reg->iobase_addr, 0x4000); 1156 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1057 + dmp_reg = &reg->iobase_window; 1157 1058 for (cnt = 0; cnt < 16; cnt++) 1158 1059 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1159 1060 1160 1061 WRT_REG_DWORD(&reg->iobase_addr, 0x4010); 1161 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1062 + dmp_reg = &reg->iobase_window; 1162 1063 for (cnt = 0; cnt < 16; cnt++) 1163 1064 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1164 1065 1165 1066 WRT_REG_DWORD(&reg->iobase_addr, 0x4020); 1166 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1067 + dmp_reg = &reg->iobase_window; 1167 1068 for (cnt = 0; cnt < 16; cnt++) 1168 1069 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1169 1070 1170 1071 WRT_REG_DWORD(&reg->iobase_addr, 0x4030); 1171 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1072 + dmp_reg = &reg->iobase_window; 1172 1073 for (cnt = 0; cnt < 16; cnt++) 1173 1074 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1174 1075 1175 1076 WRT_REG_DWORD(&reg->iobase_addr, 0x4040); 1176 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1077 + dmp_reg = &reg->iobase_window; 1177 1078 for (cnt = 0; cnt < 16; cnt++) 1178 1079 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1179 1080 1180 1081 WRT_REG_DWORD(&reg->iobase_addr, 0x4050); 1181 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1082 + dmp_reg = &reg->iobase_window; 1182 1083 for (cnt = 0; cnt < 16; cnt++) 1183 1084 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1184 1085 1185 1086 WRT_REG_DWORD(&reg->iobase_addr, 0x4060); 1186 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1087 + dmp_reg = &reg->iobase_window; 1187 1088 for (cnt = 0; cnt < 16; cnt++) 1188 1089 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1189 1090 1190 1091 WRT_REG_DWORD(&reg->iobase_addr, 0x4070); 1191 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1092 + dmp_reg = &reg->iobase_window; 1192 1093 for (cnt = 0; cnt < 16; cnt++) 1193 1094 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1194 1095 1195 1096 WRT_REG_DWORD(&reg->iobase_addr, 0x4080); 1196 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1097 + dmp_reg = &reg->iobase_window; 1197 1098 for (cnt = 0; cnt < 16; cnt++) 1198 1099 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1199 1100 1200 1101 WRT_REG_DWORD(&reg->iobase_addr, 0x4090); 1201 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1102 + dmp_reg = &reg->iobase_window; 1202 1103 for (cnt = 0; cnt < 16; cnt++) 1203 1104 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1204 1105 1205 1106 WRT_REG_DWORD(&reg->iobase_addr, 0x40A0); 1206 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1107 + dmp_reg = &reg->iobase_window; 1207 1108 for (cnt = 0; cnt < 16; cnt++) 1208 1109 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1209 1110 1210 1111 WRT_REG_DWORD(&reg->iobase_addr, 0x40B0); 1211 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1112 + dmp_reg = &reg->iobase_window; 1212 1113 for (cnt = 0; cnt < 16; cnt++) 1213 1114 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1214 1115 1215 1116 /* Frame Buffer registers. */ 1216 1117 iter_reg = fw->fb_hdw_reg; 1217 1118 WRT_REG_DWORD(&reg->iobase_addr, 0x6000); 1218 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1119 + dmp_reg = &reg->iobase_window; 1219 1120 for (cnt = 0; cnt < 16; cnt++) 1220 1121 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1221 1122 1222 1123 WRT_REG_DWORD(&reg->iobase_addr, 0x6010); 1223 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1124 + dmp_reg = &reg->iobase_window; 1224 1125 for (cnt = 0; cnt < 16; cnt++) 1225 1126 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1226 1127 1227 1128 WRT_REG_DWORD(&reg->iobase_addr, 0x6020); 1228 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1129 + dmp_reg = &reg->iobase_window; 1229 1130 for (cnt = 0; cnt < 16; cnt++) 1230 1131 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1231 1132 1232 1133 WRT_REG_DWORD(&reg->iobase_addr, 0x6030); 1233 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1134 + dmp_reg = &reg->iobase_window; 1234 1135 for (cnt = 0; cnt < 16; cnt++) 1235 1136 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1236 1137 1237 1138 WRT_REG_DWORD(&reg->iobase_addr, 0x6040); 1238 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1139 + dmp_reg = &reg->iobase_window; 1239 1140 for (cnt = 0; cnt < 16; cnt++) 1240 1141 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1241 1142 1242 1143 WRT_REG_DWORD(&reg->iobase_addr, 0x6100); 1243 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1144 + dmp_reg = &reg->iobase_window; 1244 1145 for (cnt = 0; cnt < 16; cnt++) 1245 1146 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1246 1147 1247 1148 WRT_REG_DWORD(&reg->iobase_addr, 0x6130); 1248 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1149 + dmp_reg = &reg->iobase_window; 1249 1150 for (cnt = 0; cnt < 16; cnt++) 1250 1151 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1251 1152 1252 1153 WRT_REG_DWORD(&reg->iobase_addr, 0x6150); 1253 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1154 + dmp_reg = &reg->iobase_window; 1254 1155 for (cnt = 0; cnt < 16; cnt++) 1255 1156 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1256 1157 1257 1158 WRT_REG_DWORD(&reg->iobase_addr, 0x6170); 1258 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1159 + dmp_reg = &reg->iobase_window; 1259 1160 for (cnt = 0; cnt < 16; cnt++) 1260 1161 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1261 1162 1262 1163 WRT_REG_DWORD(&reg->iobase_addr, 0x6190); 1263 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1164 + dmp_reg = &reg->iobase_window; 1264 1165 for (cnt = 0; cnt < 16; cnt++) 1265 1166 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1266 1167 1267 1168 WRT_REG_DWORD(&reg->iobase_addr, 0x61B0); 1268 - dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0); 1169 + dmp_reg = &reg->iobase_window; 1269 1170 for (cnt = 0; cnt < 16; cnt++) 1270 1171 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1271 1172 ··· 1286 1187 1287 1188 udelay(100); 1288 1189 /* Wait for firmware to complete NVRAM accesses. */ 1289 - mb[0] = (uint32_t) RD_REG_WORD(&reg->mailbox0); 1290 - for (cnt = 10000 ; cnt && mb[0]; cnt--) { 1190 + mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0); 1191 + for (cnt = 10000 ; cnt && mb0; cnt--) { 1291 1192 udelay(5); 1292 - mb[0] = (uint32_t) RD_REG_WORD(&reg->mailbox0); 1193 + mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0); 1293 1194 barrier(); 1294 1195 } 1295 1196 ··· 1313 1214 rval = QLA_FUNCTION_TIMEOUT; 1314 1215 } 1315 1216 1316 - /* Memory. */ 1317 - if (rval == QLA_SUCCESS) { 1318 - /* Code RAM. */ 1319 - risc_address = 0x20000; 1320 - WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED); 1321 - clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 1322 - } 1323 - for (cnt = 0; cnt < sizeof(fw->code_ram) / 4 && rval == QLA_SUCCESS; 1324 - cnt++, risc_address++) { 1325 - WRT_REG_WORD(&reg->mailbox1, LSW(risc_address)); 1326 - WRT_REG_WORD(&reg->mailbox8, MSW(risc_address)); 1327 - RD_REG_WORD(&reg->mailbox8); 1328 - WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); 1329 - 1330 - for (timer = 6000000; timer; timer--) { 1331 - /* Check for pending interrupts. */ 1332 - stat = RD_REG_DWORD(&reg->host_status); 1333 - if (stat & HSRX_RISC_INT) { 1334 - stat &= 0xff; 1335 - 1336 - if (stat == 0x1 || stat == 0x2 || 1337 - stat == 0x10 || stat == 0x11) { 1338 - set_bit(MBX_INTERRUPT, 1339 - &ha->mbx_cmd_flags); 1340 - 1341 - mb[0] = RD_REG_WORD(&reg->mailbox0); 1342 - mb[2] = RD_REG_WORD(&reg->mailbox2); 1343 - mb[3] = RD_REG_WORD(&reg->mailbox3); 1344 - 1345 - WRT_REG_DWORD(&reg->hccr, 1346 - HCCRX_CLR_RISC_INT); 1347 - RD_REG_DWORD(&reg->hccr); 1348 - break; 1349 - } 1350 - 1351 - /* Clear this intr; it wasn't a mailbox intr */ 1352 - WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); 1353 - RD_REG_DWORD(&reg->hccr); 1354 - } 1355 - udelay(5); 1356 - } 1357 - 1358 - if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 1359 - rval = mb[0] & MBS_MASK; 1360 - fw->code_ram[cnt] = htonl((mb[3] << 16) | mb[2]); 1361 - } else { 1362 - rval = QLA_FUNCTION_FAILED; 1363 - } 1364 - } 1217 + if (rval == QLA_SUCCESS) 1218 + rval = qla2xxx_dump_memory(ha, fw->code_ram, 1219 + sizeof(fw->code_ram), fw->ext_mem, &nxt); 1365 1220 1366 1221 if (rval == QLA_SUCCESS) { 1367 - /* External Memory. */ 1368 - risc_address = 0x100000; 1369 - ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1; 1370 - WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED); 1371 - clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 1372 - } 1373 - for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS; 1374 - cnt++, risc_address++) { 1375 - WRT_REG_WORD(&reg->mailbox1, LSW(risc_address)); 1376 - WRT_REG_WORD(&reg->mailbox8, MSW(risc_address)); 1377 - RD_REG_WORD(&reg->mailbox8); 1378 - WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT); 1379 - 1380 - for (timer = 6000000; timer; timer--) { 1381 - /* Check for pending interrupts. */ 1382 - stat = RD_REG_DWORD(&reg->host_status); 1383 - if (stat & HSRX_RISC_INT) { 1384 - stat &= 0xff; 1385 - 1386 - if (stat == 0x1 || stat == 0x2 || 1387 - stat == 0x10 || stat == 0x11) { 1388 - set_bit(MBX_INTERRUPT, 1389 - &ha->mbx_cmd_flags); 1390 - 1391 - mb[0] = RD_REG_WORD(&reg->mailbox0); 1392 - mb[2] = RD_REG_WORD(&reg->mailbox2); 1393 - mb[3] = RD_REG_WORD(&reg->mailbox3); 1394 - 1395 - WRT_REG_DWORD(&reg->hccr, 1396 - HCCRX_CLR_RISC_INT); 1397 - RD_REG_DWORD(&reg->hccr); 1398 - break; 1399 - } 1400 - 1401 - /* Clear this intr; it wasn't a mailbox intr */ 1402 - WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT); 1403 - RD_REG_DWORD(&reg->hccr); 1404 - } 1405 - udelay(5); 1406 - } 1407 - 1408 - if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 1409 - rval = mb[0] & MBS_MASK; 1410 - fw->ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]); 1411 - } else { 1412 - rval = QLA_FUNCTION_FAILED; 1413 - } 1414 - } 1415 - 1416 - if (rval == QLA_SUCCESS) { 1417 - eft = qla2xxx_copy_queues(ha, &fw->ext_mem[cnt]); 1222 + nxt = qla2xxx_copy_queues(ha, nxt); 1418 1223 if (ha->eft) 1419 - memcpy(eft, ha->eft, ntohl(ha->fw_dump->eft_size)); 1224 + memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size)); 1420 1225 } 1421 1226 1422 1227 if (rval != QLA_SUCCESS) { ··· 1336 1333 } 1337 1334 1338 1335 qla24xx_fw_dump_failed: 1336 + if (!hardware_locked) 1337 + spin_unlock_irqrestore(&ha->hardware_lock, flags); 1338 + } 1339 + 1340 + void 1341 + qla25xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked) 1342 + { 1343 + int rval; 1344 + uint32_t cnt; 1345 + uint32_t risc_address; 1346 + uint16_t mb0, wd; 1347 + 1348 + struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1349 + uint32_t __iomem *dmp_reg; 1350 + uint32_t *iter_reg; 1351 + uint16_t __iomem *mbx_reg; 1352 + unsigned long flags; 1353 + struct qla25xx_fw_dump *fw; 1354 + uint32_t ext_mem_cnt; 1355 + void *nxt; 1356 + 1357 + risc_address = ext_mem_cnt = 0; 1358 + flags = 0; 1359 + 1360 + if (!hardware_locked) 1361 + spin_lock_irqsave(&ha->hardware_lock, flags); 1362 + 1363 + if (!ha->fw_dump) { 1364 + qla_printk(KERN_WARNING, ha, 1365 + "No buffer available for dump!!!\n"); 1366 + goto qla25xx_fw_dump_failed; 1367 + } 1368 + 1369 + if (ha->fw_dumped) { 1370 + qla_printk(KERN_WARNING, ha, 1371 + "Firmware has been previously dumped (%p) -- ignoring " 1372 + "request...\n", ha->fw_dump); 1373 + goto qla25xx_fw_dump_failed; 1374 + } 1375 + fw = &ha->fw_dump->isp.isp25; 1376 + qla2xxx_prep_dump(ha, ha->fw_dump); 1377 + 1378 + rval = QLA_SUCCESS; 1379 + fw->host_status = htonl(RD_REG_DWORD(&reg->host_status)); 1380 + 1381 + /* Pause RISC. */ 1382 + if ((RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0) { 1383 + WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET | 1384 + HCCRX_CLR_HOST_INT); 1385 + RD_REG_DWORD(&reg->hccr); /* PCI Posting. */ 1386 + WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE); 1387 + for (cnt = 30000; 1388 + (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 && 1389 + rval == QLA_SUCCESS; cnt--) { 1390 + if (cnt) 1391 + udelay(100); 1392 + else 1393 + rval = QLA_FUNCTION_TIMEOUT; 1394 + } 1395 + } 1396 + 1397 + if (rval == QLA_SUCCESS) { 1398 + /* Host interface registers. */ 1399 + dmp_reg = (uint32_t __iomem *)(reg + 0); 1400 + for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1401 + fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1402 + 1403 + /* Disable interrupts. */ 1404 + WRT_REG_DWORD(&reg->ictrl, 0); 1405 + RD_REG_DWORD(&reg->ictrl); 1406 + 1407 + /* Shadow registers. */ 1408 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 1409 + RD_REG_DWORD(&reg->iobase_addr); 1410 + WRT_REG_DWORD(&reg->iobase_select, 0xB0000000); 1411 + fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1412 + 1413 + WRT_REG_DWORD(&reg->iobase_select, 0xB0100000); 1414 + fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1415 + 1416 + WRT_REG_DWORD(&reg->iobase_select, 0xB0200000); 1417 + fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1418 + 1419 + WRT_REG_DWORD(&reg->iobase_select, 0xB0300000); 1420 + fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1421 + 1422 + WRT_REG_DWORD(&reg->iobase_select, 0xB0400000); 1423 + fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1424 + 1425 + WRT_REG_DWORD(&reg->iobase_select, 0xB0500000); 1426 + fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1427 + 1428 + WRT_REG_DWORD(&reg->iobase_select, 0xB0600000); 1429 + fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1430 + 1431 + WRT_REG_DWORD(&reg->iobase_select, 0xB0700000); 1432 + fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1433 + 1434 + WRT_REG_DWORD(&reg->iobase_select, 0xB0800000); 1435 + fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1436 + 1437 + WRT_REG_DWORD(&reg->iobase_select, 0xB0900000); 1438 + fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1439 + 1440 + WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000); 1441 + fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata)); 1442 + 1443 + /* RISC I/O register. */ 1444 + WRT_REG_DWORD(&reg->iobase_addr, 0x0010); 1445 + RD_REG_DWORD(&reg->iobase_addr); 1446 + fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window)); 1447 + 1448 + /* Mailbox registers. */ 1449 + mbx_reg = &reg->mailbox0; 1450 + for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1451 + fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1452 + 1453 + /* Transfer sequence registers. */ 1454 + iter_reg = fw->xseq_gp_reg; 1455 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF00); 1456 + dmp_reg = &reg->iobase_window; 1457 + for (cnt = 0; cnt < 16; cnt++) 1458 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1459 + 1460 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF10); 1461 + dmp_reg = &reg->iobase_window; 1462 + for (cnt = 0; cnt < 16; cnt++) 1463 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1464 + 1465 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF20); 1466 + dmp_reg = &reg->iobase_window; 1467 + for (cnt = 0; cnt < 16; cnt++) 1468 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1469 + 1470 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF30); 1471 + dmp_reg = &reg->iobase_window; 1472 + for (cnt = 0; cnt < 16; cnt++) 1473 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1474 + 1475 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF40); 1476 + dmp_reg = &reg->iobase_window; 1477 + for (cnt = 0; cnt < 16; cnt++) 1478 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1479 + 1480 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF50); 1481 + dmp_reg = &reg->iobase_window; 1482 + for (cnt = 0; cnt < 16; cnt++) 1483 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1484 + 1485 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF60); 1486 + dmp_reg = &reg->iobase_window; 1487 + for (cnt = 0; cnt < 16; cnt++) 1488 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1489 + 1490 + WRT_REG_DWORD(&reg->iobase_addr, 0xBF70); 1491 + dmp_reg = &reg->iobase_window; 1492 + for (cnt = 0; cnt < 16; cnt++) 1493 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1494 + 1495 + iter_reg = fw->xseq_0_reg; 1496 + WRT_REG_DWORD(&reg->iobase_addr, 0xBFC0); 1497 + dmp_reg = &reg->iobase_window; 1498 + for (cnt = 0; cnt < 16; cnt++) 1499 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1500 + 1501 + WRT_REG_DWORD(&reg->iobase_addr, 0xBFD0); 1502 + dmp_reg = &reg->iobase_window; 1503 + for (cnt = 0; cnt < 16; cnt++) 1504 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1505 + 1506 + WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0); 1507 + dmp_reg = &reg->iobase_window; 1508 + for (cnt = 0; cnt < 16; cnt++) 1509 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1510 + 1511 + WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0); 1512 + dmp_reg = &reg->iobase_window; 1513 + for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) 1514 + fw->xseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1515 + 1516 + /* Receive sequence registers. */ 1517 + iter_reg = fw->rseq_gp_reg; 1518 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF00); 1519 + dmp_reg = &reg->iobase_window; 1520 + for (cnt = 0; cnt < 16; cnt++) 1521 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1522 + 1523 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF10); 1524 + dmp_reg = &reg->iobase_window; 1525 + for (cnt = 0; cnt < 16; cnt++) 1526 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1527 + 1528 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF20); 1529 + dmp_reg = &reg->iobase_window; 1530 + for (cnt = 0; cnt < 16; cnt++) 1531 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1532 + 1533 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF30); 1534 + dmp_reg = &reg->iobase_window; 1535 + for (cnt = 0; cnt < 16; cnt++) 1536 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1537 + 1538 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF40); 1539 + dmp_reg = &reg->iobase_window; 1540 + for (cnt = 0; cnt < 16; cnt++) 1541 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1542 + 1543 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF50); 1544 + dmp_reg = &reg->iobase_window; 1545 + for (cnt = 0; cnt < 16; cnt++) 1546 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1547 + 1548 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF60); 1549 + dmp_reg = &reg->iobase_window; 1550 + for (cnt = 0; cnt < 16; cnt++) 1551 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1552 + 1553 + WRT_REG_DWORD(&reg->iobase_addr, 0xFF70); 1554 + dmp_reg = &reg->iobase_window; 1555 + for (cnt = 0; cnt < 16; cnt++) 1556 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1557 + 1558 + iter_reg = fw->rseq_0_reg; 1559 + WRT_REG_DWORD(&reg->iobase_addr, 0xFFC0); 1560 + dmp_reg = &reg->iobase_window; 1561 + for (cnt = 0; cnt < 16; cnt++) 1562 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1563 + 1564 + WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0); 1565 + dmp_reg = &reg->iobase_window; 1566 + for (cnt = 0; cnt < 16; cnt++) 1567 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1568 + 1569 + WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0); 1570 + dmp_reg = &reg->iobase_window; 1571 + for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) 1572 + fw->rseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1573 + 1574 + WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0); 1575 + dmp_reg = &reg->iobase_window; 1576 + for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) 1577 + fw->rseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1578 + 1579 + /* Auxiliary sequence registers. */ 1580 + iter_reg = fw->aseq_gp_reg; 1581 + WRT_REG_DWORD(&reg->iobase_addr, 0xB000); 1582 + dmp_reg = &reg->iobase_window; 1583 + for (cnt = 0; cnt < 16; cnt++) 1584 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1585 + 1586 + WRT_REG_DWORD(&reg->iobase_addr, 0xB010); 1587 + dmp_reg = &reg->iobase_window; 1588 + for (cnt = 0; cnt < 16; cnt++) 1589 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1590 + 1591 + WRT_REG_DWORD(&reg->iobase_addr, 0xB020); 1592 + dmp_reg = &reg->iobase_window; 1593 + for (cnt = 0; cnt < 16; cnt++) 1594 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1595 + 1596 + WRT_REG_DWORD(&reg->iobase_addr, 0xB030); 1597 + dmp_reg = &reg->iobase_window; 1598 + for (cnt = 0; cnt < 16; cnt++) 1599 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1600 + 1601 + WRT_REG_DWORD(&reg->iobase_addr, 0xB040); 1602 + dmp_reg = &reg->iobase_window; 1603 + for (cnt = 0; cnt < 16; cnt++) 1604 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1605 + 1606 + WRT_REG_DWORD(&reg->iobase_addr, 0xB050); 1607 + dmp_reg = &reg->iobase_window; 1608 + for (cnt = 0; cnt < 16; cnt++) 1609 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1610 + 1611 + WRT_REG_DWORD(&reg->iobase_addr, 0xB060); 1612 + dmp_reg = &reg->iobase_window; 1613 + for (cnt = 0; cnt < 16; cnt++) 1614 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1615 + 1616 + WRT_REG_DWORD(&reg->iobase_addr, 0xB070); 1617 + dmp_reg = &reg->iobase_window; 1618 + for (cnt = 0; cnt < 16; cnt++) 1619 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1620 + 1621 + iter_reg = fw->aseq_0_reg; 1622 + WRT_REG_DWORD(&reg->iobase_addr, 0xB0C0); 1623 + dmp_reg = &reg->iobase_window; 1624 + for (cnt = 0; cnt < 16; cnt++) 1625 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1626 + 1627 + WRT_REG_DWORD(&reg->iobase_addr, 0xB0D0); 1628 + dmp_reg = &reg->iobase_window; 1629 + for (cnt = 0; cnt < 16; cnt++) 1630 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1631 + 1632 + WRT_REG_DWORD(&reg->iobase_addr, 0xB0E0); 1633 + dmp_reg = &reg->iobase_window; 1634 + for (cnt = 0; cnt < sizeof(fw->aseq_1_reg) / 4; cnt++) 1635 + fw->aseq_1_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1636 + 1637 + WRT_REG_DWORD(&reg->iobase_addr, 0xB0F0); 1638 + dmp_reg = &reg->iobase_window; 1639 + for (cnt = 0; cnt < sizeof(fw->aseq_2_reg) / 4; cnt++) 1640 + fw->aseq_2_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1641 + 1642 + /* Command DMA registers. */ 1643 + WRT_REG_DWORD(&reg->iobase_addr, 0x7100); 1644 + dmp_reg = &reg->iobase_window; 1645 + for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) 1646 + fw->cmd_dma_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1647 + 1648 + /* Queues. */ 1649 + iter_reg = fw->req0_dma_reg; 1650 + WRT_REG_DWORD(&reg->iobase_addr, 0x7200); 1651 + dmp_reg = &reg->iobase_window; 1652 + for (cnt = 0; cnt < 8; cnt++) 1653 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1654 + 1655 + dmp_reg = &reg->iobase_q; 1656 + for (cnt = 0; cnt < 7; cnt++) 1657 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1658 + 1659 + iter_reg = fw->resp0_dma_reg; 1660 + WRT_REG_DWORD(&reg->iobase_addr, 0x7300); 1661 + dmp_reg = &reg->iobase_window; 1662 + for (cnt = 0; cnt < 8; cnt++) 1663 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1664 + 1665 + dmp_reg = &reg->iobase_q; 1666 + for (cnt = 0; cnt < 7; cnt++) 1667 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1668 + 1669 + iter_reg = fw->req1_dma_reg; 1670 + WRT_REG_DWORD(&reg->iobase_addr, 0x7400); 1671 + dmp_reg = &reg->iobase_window; 1672 + for (cnt = 0; cnt < 8; cnt++) 1673 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1674 + 1675 + dmp_reg = &reg->iobase_q; 1676 + for (cnt = 0; cnt < 7; cnt++) 1677 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1678 + 1679 + /* Transmit DMA registers. */ 1680 + iter_reg = fw->xmt0_dma_reg; 1681 + WRT_REG_DWORD(&reg->iobase_addr, 0x7600); 1682 + dmp_reg = &reg->iobase_window; 1683 + for (cnt = 0; cnt < 16; cnt++) 1684 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1685 + 1686 + WRT_REG_DWORD(&reg->iobase_addr, 0x7610); 1687 + dmp_reg = &reg->iobase_window; 1688 + for (cnt = 0; cnt < 16; cnt++) 1689 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1690 + 1691 + iter_reg = fw->xmt1_dma_reg; 1692 + WRT_REG_DWORD(&reg->iobase_addr, 0x7620); 1693 + dmp_reg = &reg->iobase_window; 1694 + for (cnt = 0; cnt < 16; cnt++) 1695 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1696 + 1697 + WRT_REG_DWORD(&reg->iobase_addr, 0x7630); 1698 + dmp_reg = &reg->iobase_window; 1699 + for (cnt = 0; cnt < 16; cnt++) 1700 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1701 + 1702 + iter_reg = fw->xmt2_dma_reg; 1703 + WRT_REG_DWORD(&reg->iobase_addr, 0x7640); 1704 + dmp_reg = &reg->iobase_window; 1705 + for (cnt = 0; cnt < 16; cnt++) 1706 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1707 + 1708 + WRT_REG_DWORD(&reg->iobase_addr, 0x7650); 1709 + dmp_reg = &reg->iobase_window; 1710 + for (cnt = 0; cnt < 16; cnt++) 1711 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1712 + 1713 + iter_reg = fw->xmt3_dma_reg; 1714 + WRT_REG_DWORD(&reg->iobase_addr, 0x7660); 1715 + dmp_reg = &reg->iobase_window; 1716 + for (cnt = 0; cnt < 16; cnt++) 1717 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1718 + 1719 + WRT_REG_DWORD(&reg->iobase_addr, 0x7670); 1720 + dmp_reg = &reg->iobase_window; 1721 + for (cnt = 0; cnt < 16; cnt++) 1722 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1723 + 1724 + iter_reg = fw->xmt4_dma_reg; 1725 + WRT_REG_DWORD(&reg->iobase_addr, 0x7680); 1726 + dmp_reg = &reg->iobase_window; 1727 + for (cnt = 0; cnt < 16; cnt++) 1728 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1729 + 1730 + WRT_REG_DWORD(&reg->iobase_addr, 0x7690); 1731 + dmp_reg = &reg->iobase_window; 1732 + for (cnt = 0; cnt < 16; cnt++) 1733 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1734 + 1735 + WRT_REG_DWORD(&reg->iobase_addr, 0x76A0); 1736 + dmp_reg = &reg->iobase_window; 1737 + for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) 1738 + fw->xmt_data_dma_reg[cnt] = 1739 + htonl(RD_REG_DWORD(dmp_reg++)); 1740 + 1741 + /* Receive DMA registers. */ 1742 + iter_reg = fw->rcvt0_data_dma_reg; 1743 + WRT_REG_DWORD(&reg->iobase_addr, 0x7700); 1744 + dmp_reg = &reg->iobase_window; 1745 + for (cnt = 0; cnt < 16; cnt++) 1746 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1747 + 1748 + WRT_REG_DWORD(&reg->iobase_addr, 0x7710); 1749 + dmp_reg = &reg->iobase_window; 1750 + for (cnt = 0; cnt < 16; cnt++) 1751 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1752 + 1753 + iter_reg = fw->rcvt1_data_dma_reg; 1754 + WRT_REG_DWORD(&reg->iobase_addr, 0x7720); 1755 + dmp_reg = &reg->iobase_window; 1756 + for (cnt = 0; cnt < 16; cnt++) 1757 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1758 + 1759 + WRT_REG_DWORD(&reg->iobase_addr, 0x7730); 1760 + dmp_reg = &reg->iobase_window; 1761 + for (cnt = 0; cnt < 16; cnt++) 1762 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1763 + 1764 + /* RISC registers. */ 1765 + iter_reg = fw->risc_gp_reg; 1766 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F00); 1767 + dmp_reg = &reg->iobase_window; 1768 + for (cnt = 0; cnt < 16; cnt++) 1769 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1770 + 1771 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F10); 1772 + dmp_reg = &reg->iobase_window; 1773 + for (cnt = 0; cnt < 16; cnt++) 1774 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1775 + 1776 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F20); 1777 + dmp_reg = &reg->iobase_window; 1778 + for (cnt = 0; cnt < 16; cnt++) 1779 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1780 + 1781 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F30); 1782 + dmp_reg = &reg->iobase_window; 1783 + for (cnt = 0; cnt < 16; cnt++) 1784 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1785 + 1786 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F40); 1787 + dmp_reg = &reg->iobase_window; 1788 + for (cnt = 0; cnt < 16; cnt++) 1789 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1790 + 1791 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F50); 1792 + dmp_reg = &reg->iobase_window; 1793 + for (cnt = 0; cnt < 16; cnt++) 1794 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1795 + 1796 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F60); 1797 + dmp_reg = &reg->iobase_window; 1798 + for (cnt = 0; cnt < 16; cnt++) 1799 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1800 + 1801 + WRT_REG_DWORD(&reg->iobase_addr, 0x0F70); 1802 + dmp_reg = &reg->iobase_window; 1803 + for (cnt = 0; cnt < 16; cnt++) 1804 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1805 + 1806 + /* Local memory controller registers. */ 1807 + iter_reg = fw->lmc_reg; 1808 + WRT_REG_DWORD(&reg->iobase_addr, 0x3000); 1809 + dmp_reg = &reg->iobase_window; 1810 + for (cnt = 0; cnt < 16; cnt++) 1811 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1812 + 1813 + WRT_REG_DWORD(&reg->iobase_addr, 0x3010); 1814 + dmp_reg = &reg->iobase_window; 1815 + for (cnt = 0; cnt < 16; cnt++) 1816 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1817 + 1818 + WRT_REG_DWORD(&reg->iobase_addr, 0x3020); 1819 + dmp_reg = &reg->iobase_window; 1820 + for (cnt = 0; cnt < 16; cnt++) 1821 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1822 + 1823 + WRT_REG_DWORD(&reg->iobase_addr, 0x3030); 1824 + dmp_reg = &reg->iobase_window; 1825 + for (cnt = 0; cnt < 16; cnt++) 1826 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1827 + 1828 + WRT_REG_DWORD(&reg->iobase_addr, 0x3040); 1829 + dmp_reg = &reg->iobase_window; 1830 + for (cnt = 0; cnt < 16; cnt++) 1831 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1832 + 1833 + WRT_REG_DWORD(&reg->iobase_addr, 0x3050); 1834 + dmp_reg = &reg->iobase_window; 1835 + for (cnt = 0; cnt < 16; cnt++) 1836 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1837 + 1838 + WRT_REG_DWORD(&reg->iobase_addr, 0x3060); 1839 + dmp_reg = &reg->iobase_window; 1840 + for (cnt = 0; cnt < 16; cnt++) 1841 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1842 + 1843 + WRT_REG_DWORD(&reg->iobase_addr, 0x3070); 1844 + dmp_reg = &reg->iobase_window; 1845 + for (cnt = 0; cnt < 16; cnt++) 1846 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1847 + 1848 + /* Fibre Protocol Module registers. */ 1849 + iter_reg = fw->fpm_hdw_reg; 1850 + WRT_REG_DWORD(&reg->iobase_addr, 0x4000); 1851 + dmp_reg = &reg->iobase_window; 1852 + for (cnt = 0; cnt < 16; cnt++) 1853 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1854 + 1855 + WRT_REG_DWORD(&reg->iobase_addr, 0x4010); 1856 + dmp_reg = &reg->iobase_window; 1857 + for (cnt = 0; cnt < 16; cnt++) 1858 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1859 + 1860 + WRT_REG_DWORD(&reg->iobase_addr, 0x4020); 1861 + dmp_reg = &reg->iobase_window; 1862 + for (cnt = 0; cnt < 16; cnt++) 1863 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1864 + 1865 + WRT_REG_DWORD(&reg->iobase_addr, 0x4030); 1866 + dmp_reg = &reg->iobase_window; 1867 + for (cnt = 0; cnt < 16; cnt++) 1868 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1869 + 1870 + WRT_REG_DWORD(&reg->iobase_addr, 0x4040); 1871 + dmp_reg = &reg->iobase_window; 1872 + for (cnt = 0; cnt < 16; cnt++) 1873 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1874 + 1875 + WRT_REG_DWORD(&reg->iobase_addr, 0x4050); 1876 + dmp_reg = &reg->iobase_window; 1877 + for (cnt = 0; cnt < 16; cnt++) 1878 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1879 + 1880 + WRT_REG_DWORD(&reg->iobase_addr, 0x4060); 1881 + dmp_reg = &reg->iobase_window; 1882 + for (cnt = 0; cnt < 16; cnt++) 1883 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1884 + 1885 + WRT_REG_DWORD(&reg->iobase_addr, 0x4070); 1886 + dmp_reg = &reg->iobase_window; 1887 + for (cnt = 0; cnt < 16; cnt++) 1888 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1889 + 1890 + WRT_REG_DWORD(&reg->iobase_addr, 0x4080); 1891 + dmp_reg = &reg->iobase_window; 1892 + for (cnt = 0; cnt < 16; cnt++) 1893 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1894 + 1895 + WRT_REG_DWORD(&reg->iobase_addr, 0x4090); 1896 + dmp_reg = &reg->iobase_window; 1897 + for (cnt = 0; cnt < 16; cnt++) 1898 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1899 + 1900 + WRT_REG_DWORD(&reg->iobase_addr, 0x40A0); 1901 + dmp_reg = &reg->iobase_window; 1902 + for (cnt = 0; cnt < 16; cnt++) 1903 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1904 + 1905 + WRT_REG_DWORD(&reg->iobase_addr, 0x40B0); 1906 + dmp_reg = &reg->iobase_window; 1907 + for (cnt = 0; cnt < 16; cnt++) 1908 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1909 + 1910 + /* Frame Buffer registers. */ 1911 + iter_reg = fw->fb_hdw_reg; 1912 + WRT_REG_DWORD(&reg->iobase_addr, 0x6000); 1913 + dmp_reg = &reg->iobase_window; 1914 + for (cnt = 0; cnt < 16; cnt++) 1915 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1916 + 1917 + WRT_REG_DWORD(&reg->iobase_addr, 0x6010); 1918 + dmp_reg = &reg->iobase_window; 1919 + for (cnt = 0; cnt < 16; cnt++) 1920 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1921 + 1922 + WRT_REG_DWORD(&reg->iobase_addr, 0x6020); 1923 + dmp_reg = &reg->iobase_window; 1924 + for (cnt = 0; cnt < 16; cnt++) 1925 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1926 + 1927 + WRT_REG_DWORD(&reg->iobase_addr, 0x6030); 1928 + dmp_reg = &reg->iobase_window; 1929 + for (cnt = 0; cnt < 16; cnt++) 1930 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1931 + 1932 + WRT_REG_DWORD(&reg->iobase_addr, 0x6040); 1933 + dmp_reg = &reg->iobase_window; 1934 + for (cnt = 0; cnt < 16; cnt++) 1935 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1936 + 1937 + WRT_REG_DWORD(&reg->iobase_addr, 0x6100); 1938 + dmp_reg = &reg->iobase_window; 1939 + for (cnt = 0; cnt < 16; cnt++) 1940 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1941 + 1942 + WRT_REG_DWORD(&reg->iobase_addr, 0x6130); 1943 + dmp_reg = &reg->iobase_window; 1944 + for (cnt = 0; cnt < 16; cnt++) 1945 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1946 + 1947 + WRT_REG_DWORD(&reg->iobase_addr, 0x6150); 1948 + dmp_reg = &reg->iobase_window; 1949 + for (cnt = 0; cnt < 16; cnt++) 1950 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1951 + 1952 + WRT_REG_DWORD(&reg->iobase_addr, 0x6170); 1953 + dmp_reg = &reg->iobase_window; 1954 + for (cnt = 0; cnt < 16; cnt++) 1955 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1956 + 1957 + WRT_REG_DWORD(&reg->iobase_addr, 0x6190); 1958 + dmp_reg = &reg->iobase_window; 1959 + for (cnt = 0; cnt < 16; cnt++) 1960 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1961 + 1962 + WRT_REG_DWORD(&reg->iobase_addr, 0x61B0); 1963 + dmp_reg = &reg->iobase_window; 1964 + for (cnt = 0; cnt < 16; cnt++) 1965 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1966 + 1967 + WRT_REG_DWORD(&reg->iobase_addr, 0x6F00); 1968 + dmp_reg = &reg->iobase_window; 1969 + for (cnt = 0; cnt < 16; cnt++) 1970 + *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1971 + 1972 + /* Reset RISC. */ 1973 + WRT_REG_DWORD(&reg->ctrl_status, 1974 + CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 1975 + for (cnt = 0; cnt < 30000; cnt++) { 1976 + if ((RD_REG_DWORD(&reg->ctrl_status) & 1977 + CSRX_DMA_ACTIVE) == 0) 1978 + break; 1979 + 1980 + udelay(10); 1981 + } 1982 + 1983 + WRT_REG_DWORD(&reg->ctrl_status, 1984 + CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 1985 + pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 1986 + 1987 + udelay(100); 1988 + /* Wait for firmware to complete NVRAM accesses. */ 1989 + mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0); 1990 + for (cnt = 10000 ; cnt && mb0; cnt--) { 1991 + udelay(5); 1992 + mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0); 1993 + barrier(); 1994 + } 1995 + 1996 + /* Wait for soft-reset to complete. */ 1997 + for (cnt = 0; cnt < 30000; cnt++) { 1998 + if ((RD_REG_DWORD(&reg->ctrl_status) & 1999 + CSRX_ISP_SOFT_RESET) == 0) 2000 + break; 2001 + 2002 + udelay(10); 2003 + } 2004 + WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET); 2005 + RD_REG_DWORD(&reg->hccr); /* PCI Posting. */ 2006 + } 2007 + 2008 + for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 && 2009 + rval == QLA_SUCCESS; cnt--) { 2010 + if (cnt) 2011 + udelay(100); 2012 + else 2013 + rval = QLA_FUNCTION_TIMEOUT; 2014 + } 2015 + 2016 + if (rval == QLA_SUCCESS) 2017 + rval = qla2xxx_dump_memory(ha, fw->code_ram, 2018 + sizeof(fw->code_ram), fw->ext_mem, &nxt); 2019 + 2020 + if (rval == QLA_SUCCESS) { 2021 + nxt = qla2xxx_copy_queues(ha, nxt); 2022 + if (ha->eft) 2023 + memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size)); 2024 + } 2025 + 2026 + if (rval != QLA_SUCCESS) { 2027 + qla_printk(KERN_WARNING, ha, 2028 + "Failed to dump firmware (%x)!!!\n", rval); 2029 + ha->fw_dumped = 0; 2030 + 2031 + } else { 2032 + qla_printk(KERN_INFO, ha, 2033 + "Firmware dump saved to temp buffer (%ld/%p).\n", 2034 + ha->host_no, ha->fw_dump); 2035 + ha->fw_dumped = 1; 2036 + } 2037 + 2038 + qla25xx_fw_dump_failed: 1339 2039 if (!hardware_locked) 1340 2040 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1341 2041 }

+38

drivers/scsi/qla2xxx/qla_dbg.h

··· 213 213 uint32_t ext_mem[1]; 214 214 }; 215 215 216 + struct qla25xx_fw_dump { 217 + uint32_t host_status; 218 + uint32_t host_reg[32]; 219 + uint32_t shadow_reg[11]; 220 + uint32_t risc_io_reg; 221 + uint16_t mailbox_reg[32]; 222 + uint32_t xseq_gp_reg[128]; 223 + uint32_t xseq_0_reg[48]; 224 + uint32_t xseq_1_reg[16]; 225 + uint32_t rseq_gp_reg[128]; 226 + uint32_t rseq_0_reg[32]; 227 + uint32_t rseq_1_reg[16]; 228 + uint32_t rseq_2_reg[16]; 229 + uint32_t aseq_gp_reg[128]; 230 + uint32_t aseq_0_reg[32]; 231 + uint32_t aseq_1_reg[16]; 232 + uint32_t aseq_2_reg[16]; 233 + uint32_t cmd_dma_reg[16]; 234 + uint32_t req0_dma_reg[15]; 235 + uint32_t resp0_dma_reg[15]; 236 + uint32_t req1_dma_reg[15]; 237 + uint32_t xmt0_dma_reg[32]; 238 + uint32_t xmt1_dma_reg[32]; 239 + uint32_t xmt2_dma_reg[32]; 240 + uint32_t xmt3_dma_reg[32]; 241 + uint32_t xmt4_dma_reg[32]; 242 + uint32_t xmt_data_dma_reg[16]; 243 + uint32_t rcvt0_data_dma_reg[32]; 244 + uint32_t rcvt1_data_dma_reg[32]; 245 + uint32_t risc_gp_reg[128]; 246 + uint32_t lmc_reg[128]; 247 + uint32_t fpm_hdw_reg[192]; 248 + uint32_t fb_hdw_reg[192]; 249 + uint32_t code_ram[0x2000]; 250 + uint32_t ext_mem[1]; 251 + }; 252 + 216 253 #define EFT_NUM_BUFFERS 4 217 254 #define EFT_BYTES_PER_BUFFER 0x4000 218 255 #define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS)) ··· 283 246 struct qla2100_fw_dump isp21; 284 247 struct qla2300_fw_dump isp23; 285 248 struct qla24xx_fw_dump isp24; 249 + struct qla25xx_fw_dump isp25; 286 250 } isp; 287 251 };

+20 -2

drivers/scsi/qla2xxx/qla_def.h

··· 1711 1711 #define FDMI_PORT_OS_DEVICE_NAME 5 1712 1712 #define FDMI_PORT_HOST_NAME 6 1713 1713 1714 + #define FDMI_PORT_SPEED_1GB 0x1 1715 + #define FDMI_PORT_SPEED_2GB 0x2 1716 + #define FDMI_PORT_SPEED_10GB 0x4 1717 + #define FDMI_PORT_SPEED_4GB 0x8 1718 + #define FDMI_PORT_SPEED_8GB 0x10 1719 + #define FDMI_PORT_SPEED_16GB 0x20 1720 + #define FDMI_PORT_SPEED_UNKNOWN 0x8000 1721 + 1714 1722 struct ct_fdmi_port_attr { 1715 1723 uint16_t type; 1716 1724 uint16_t len; ··· 2209 2201 #define SWITCH_FOUND BIT_3 2210 2202 #define DFLG_NO_CABLE BIT_4 2211 2203 2204 + #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 2212 2205 uint32_t device_type; 2213 2206 #define DT_ISP2100 BIT_0 2214 2207 #define DT_ISP2200 BIT_1 ··· 2222 2213 #define DT_ISP2432 BIT_8 2223 2214 #define DT_ISP5422 BIT_9 2224 2215 #define DT_ISP5432 BIT_10 2225 - #define DT_ISP_LAST (DT_ISP5432 << 1) 2216 + #define DT_ISP2532 BIT_11 2217 + #define DT_ISP_LAST (DT_ISP2532 << 1) 2226 2218 2219 + #define DT_IIDMA BIT_26 2220 + #define DT_FWI2 BIT_27 2227 2221 #define DT_ZIO_SUPPORTED BIT_28 2228 2222 #define DT_OEM_001 BIT_29 2229 2223 #define DT_ISP2200A BIT_30 ··· 2244 2232 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 2245 2233 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 2246 2234 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 2235 + #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 2247 2236 2248 2237 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 2249 2238 IS_QLA6312(ha) || IS_QLA6322(ha)) 2250 2239 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 2251 2240 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 2241 + #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 2252 2242 2243 + #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 2244 + #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 2253 2245 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 2254 2246 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 2255 2247 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) ··· 2290 2274 uint16_t rsp_ring_index; /* Current index. */ 2291 2275 uint16_t response_q_length; 2292 2276 2293 - struct isp_operations isp_ops; 2277 + struct isp_operations *isp_ops; 2294 2278 2295 2279 /* Outstandings ISP commands. */ 2296 2280 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS]; ··· 2314 2298 #define PORT_SPEED_1GB 0x00 2315 2299 #define PORT_SPEED_2GB 0x01 2316 2300 #define PORT_SPEED_4GB 0x03 2301 + #define PORT_SPEED_8GB 0x04 2317 2302 uint16_t link_data_rate; /* F/W operating speed */ 2318 2303 2319 2304 uint8_t current_topology; ··· 2581 2564 #define OPTROM_SIZE_2300 0x20000 2582 2565 #define OPTROM_SIZE_2322 0x100000 2583 2566 #define OPTROM_SIZE_24XX 0x100000 2567 + #define OPTROM_SIZE_25XX 0x200000 2584 2568 2585 2569 #include "qla_gbl.h" 2586 2570 #include "qla_dbg.h"

+33 -3

drivers/scsi/qla2xxx/qla_fw.h

··· 8 8 #define __QLA_FW_H 9 9 10 10 #define MBS_CHECKSUM_ERROR 0x4010 11 + #define MBS_INVALID_PRODUCT_KEY 0x4020 11 12 12 13 /* 13 14 * Firmware Options. 14 15 */ 15 16 #define FO1_ENABLE_PUREX BIT_10 16 17 #define FO1_DISABLE_LED_CTRL BIT_6 18 + #define FO1_ENABLE_8016 BIT_0 17 19 #define FO2_ENABLE_SEL_CLASS2 BIT_5 18 20 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14 21 + #define FO3_HOLD_STS_IOCB BIT_12 19 22 20 23 /* 21 24 * Port Database structure definition for ISP 24xx. ··· 344 341 * BIT 10 = Reserved 345 342 * BIT 11 = Enable FC-SP Security 346 343 * BIT 12 = FC Tape Enable 347 - * BIT 13-31 = Reserved 344 + * BIT 13 = Reserved 345 + * BIT 14 = Enable Target PRLI Control 346 + * BIT 15-31 = Reserved 348 347 */ 349 348 uint32_t firmware_options_2; 350 349 ··· 368 363 * BIT 13 = Data Rate bit 0 369 364 * BIT 14 = Data Rate bit 1 370 365 * BIT 15 = Data Rate bit 2 371 - * BIT 16-31 = Reserved 366 + * BIT 16 = Enable 75 ohm Termination Select 367 + * BIT 17-31 = Reserved 372 368 */ 373 369 uint32_t firmware_options_3; 374 370 ··· 441 435 #define TMF_LUN_RESET BIT_12 442 436 #define TMF_CLEAR_TASK_SET BIT_10 443 437 #define TMF_ABORT_TASK_SET BIT_9 438 + #define TMF_DSD_LIST_ENABLE BIT_2 444 439 #define TMF_READ_DATA BIT_1 445 440 #define TMF_WRITE_DATA BIT_0 446 441 ··· 596 589 #define EST_SOFI3 (1 << 4) 597 590 #define EST_SOFI2 (3 << 4) 598 591 599 - uint32_t rx_xchg_address[2]; /* Receive exchange address. */ 592 + uint32_t rx_xchg_address; /* Receive exchange address. */ 600 593 uint16_t rx_dsd_count; 601 594 602 595 uint8_t opcode; ··· 657 650 658 651 uint16_t control_flags; /* Control flags. */ 659 652 /* Modifiers. */ 653 + #define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */ 660 654 #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */ 661 655 #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */ 662 656 #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */ ··· 787 779 #define FA_RISC_CODE_ADDR 0x20000 788 780 #define FA_RISC_CODE_SEGMENTS 2 789 781 782 + #define FA_FW_AREA_ADDR 0x40000 783 + #define FA_VPD_NVRAM_ADDR 0x48000 784 + #define FA_FEATURE_ADDR 0x4C000 785 + #define FA_FLASH_DESCR_ADDR 0x50000 786 + #define FA_HW_EVENT_ADDR 0x54000 787 + #define FA_BOOT_LOG_ADDR 0x58000 788 + #define FA_FW_DUMP0_ADDR 0x60000 789 + #define FA_FW_DUMP1_ADDR 0x70000 790 + 790 791 uint32_t flash_data; /* Flash/NVRAM BIOS data. */ 791 792 792 793 uint32_t ctrl_status; /* Control/Status. */ ··· 876 859 #define HCCRX_CLR_RISC_INT 0xA0000000 877 860 878 861 uint32_t gpiod; /* GPIO Data register. */ 862 + 879 863 /* LED update mask. */ 880 864 #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18) 881 865 /* Data update mask. */ 882 866 #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16) 867 + /* Data update mask. */ 868 + #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 883 869 /* LED control mask. */ 884 870 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2) 885 871 /* LED bit values. Color names as ··· 897 877 uint32_t gpioe; /* GPIO Enable register. */ 898 878 /* Enable update mask. */ 899 879 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16) 880 + /* Enable update mask. */ 881 + #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 900 882 /* Enable. */ 901 883 #define GPEX_ENABLE (BIT_1|BIT_0) 902 884 ··· 938 916 uint16_t mailbox29; 939 917 uint16_t mailbox30; 940 918 uint16_t mailbox31; 919 + 920 + uint32_t iobase_window; 921 + uint32_t unused_4[8]; /* Gap. */ 922 + uint32_t iobase_q; 923 + uint32_t unused_5[2]; /* Gap. */ 924 + uint32_t iobase_select; 925 + uint32_t unused_6[2]; /* Gap. */ 926 + uint32_t iobase_sdata; 941 927 }; 942 928 943 929 /* MID Support ***************************************************************/

+6

drivers/scsi/qla2xxx/qla_gbl.h

··· 17 17 extern int qla2100_pci_config(struct scsi_qla_host *); 18 18 extern int qla2300_pci_config(struct scsi_qla_host *); 19 19 extern int qla24xx_pci_config(scsi_qla_host_t *); 20 + extern int qla25xx_pci_config(scsi_qla_host_t *); 20 21 extern void qla2x00_reset_chip(struct scsi_qla_host *); 21 22 extern void qla24xx_reset_chip(struct scsi_qla_host *); 22 23 extern int qla2x00_chip_diag(struct scsi_qla_host *); ··· 282 281 uint32_t); 283 282 extern int qla24xx_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t, 284 283 uint32_t); 284 + extern uint8_t *qla25xx_read_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t, 285 + uint32_t); 286 + extern int qla25xx_write_nvram_data(scsi_qla_host_t *, uint8_t *, uint32_t, 287 + uint32_t); 285 288 286 289 extern int qla2x00_beacon_on(struct scsi_qla_host *); 287 290 extern int qla2x00_beacon_off(struct scsi_qla_host *); ··· 312 307 extern void qla2100_fw_dump(scsi_qla_host_t *, int); 313 308 extern void qla2300_fw_dump(scsi_qla_host_t *, int); 314 309 extern void qla24xx_fw_dump(scsi_qla_host_t *, int); 310 + extern void qla25xx_fw_dump(scsi_qla_host_t *, int); 315 311 extern void qla2x00_dump_regs(scsi_qla_host_t *); 316 312 extern void qla2x00_dump_buffer(uint8_t *, uint32_t); 317 313 extern void qla2x00_print_scsi_cmd(struct scsi_cmnd *);

+53 -29

drivers/scsi/qla2xxx/qla_gs.c

··· 127 127 DEBUG2_3(printk("scsi(%ld): %s failed, error status (%x).\n", 128 128 ha->host_no, routine, ms_pkt->entry_status)); 129 129 } else { 130 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 130 + if (IS_FWI2_CAPABLE(ha)) 131 131 comp_status = le16_to_cpu( 132 132 ((struct ct_entry_24xx *)ms_pkt)->comp_status); 133 133 else ··· 180 180 181 181 /* Issue GA_NXT */ 182 182 /* Prepare common MS IOCB */ 183 - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, GA_NXT_REQ_SIZE, GA_NXT_RSP_SIZE); 183 + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, GA_NXT_REQ_SIZE, 184 + GA_NXT_RSP_SIZE); 184 185 185 186 /* Prepare CT request */ 186 187 ct_req = qla2x00_prep_ct_req(&ha->ct_sns->p.req, GA_NXT_CMD, ··· 267 266 268 267 /* Issue GID_PT */ 269 268 /* Prepare common MS IOCB */ 270 - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, GID_PT_REQ_SIZE, GID_PT_RSP_SIZE); 269 + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, GID_PT_REQ_SIZE, 270 + GID_PT_RSP_SIZE); 271 271 272 272 /* Prepare CT request */ 273 273 ct_req = qla2x00_prep_ct_req(&ha->ct_sns->p.req, GID_PT_CMD, ··· 340 338 for (i = 0; i < MAX_FIBRE_DEVICES; i++) { 341 339 /* Issue GPN_ID */ 342 340 /* Prepare common MS IOCB */ 343 - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, GPN_ID_REQ_SIZE, 341 + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, GPN_ID_REQ_SIZE, 344 342 GPN_ID_RSP_SIZE); 345 343 346 344 /* Prepare CT request */ ··· 401 399 for (i = 0; i < MAX_FIBRE_DEVICES; i++) { 402 400 /* Issue GNN_ID */ 403 401 /* Prepare common MS IOCB */ 404 - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, GNN_ID_REQ_SIZE, 402 + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, GNN_ID_REQ_SIZE, 405 403 GNN_ID_RSP_SIZE); 406 404 407 405 /* Prepare CT request */ ··· 475 473 476 474 /* Issue RFT_ID */ 477 475 /* Prepare common MS IOCB */ 478 - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, RFT_ID_REQ_SIZE, RFT_ID_RSP_SIZE); 476 + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, RFT_ID_REQ_SIZE, 477 + RFT_ID_RSP_SIZE); 479 478 480 479 /* Prepare CT request */ 481 480 ct_req = qla2x00_prep_ct_req(&ha->ct_sns->p.req, RFT_ID_CMD, ··· 531 528 532 529 /* Issue RFF_ID */ 533 530 /* Prepare common MS IOCB */ 534 - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, RFF_ID_REQ_SIZE, RFF_ID_RSP_SIZE); 531 + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, RFF_ID_REQ_SIZE, 532 + RFF_ID_RSP_SIZE); 535 533 536 534 /* Prepare CT request */ 537 535 ct_req = qla2x00_prep_ct_req(&ha->ct_sns->p.req, RFF_ID_CMD, ··· 586 582 587 583 /* Issue RNN_ID */ 588 584 /* Prepare common MS IOCB */ 589 - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, RNN_ID_REQ_SIZE, RNN_ID_RSP_SIZE); 585 + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, RNN_ID_REQ_SIZE, 586 + RNN_ID_RSP_SIZE); 590 587 591 588 /* Prepare CT request */ 592 589 ct_req = qla2x00_prep_ct_req(&ha->ct_sns->p.req, RNN_ID_CMD, ··· 650 645 /* Issue RSNN_NN */ 651 646 /* Prepare common MS IOCB */ 652 647 /* Request size adjusted after CT preparation */ 653 - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, 0, RSNN_NN_RSP_SIZE); 648 + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, 0, RSNN_NN_RSP_SIZE); 654 649 655 650 /* Prepare CT request */ 656 651 ct_req = qla2x00_prep_ct_req(&ha->ct_sns->p.req, RSNN_NN_CMD, ··· 1107 1102 if (ha->flags.management_server_logged_in) 1108 1103 return ret; 1109 1104 1110 - ha->isp_ops.fabric_login(ha, ha->mgmt_svr_loop_id, 0xff, 0xff, 0xfa, 1105 + ha->isp_ops->fabric_login(ha, ha->mgmt_svr_loop_id, 0xff, 0xff, 0xfa, 1111 1106 mb, BIT_1); 1112 1107 if (mb[0] != MBS_COMMAND_COMPLETE) { 1113 1108 DEBUG2_13(printk("%s(%ld): Failed MANAGEMENT_SERVER login: " ··· 1203 1198 ms_iocb_entry_t *ms_pkt = ha->ms_iocb; 1204 1199 struct ct_entry_24xx *ct_pkt = (struct ct_entry_24xx *)ha->ms_iocb; 1205 1200 1206 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 1201 + if (IS_FWI2_CAPABLE(ha)) { 1207 1202 ct_pkt->cmd_byte_count = cpu_to_le32(req_size); 1208 1203 ct_pkt->dseg_0_len = ct_pkt->cmd_byte_count; 1209 1204 } else { ··· 1258 1253 /* Issue RHBA */ 1259 1254 /* Prepare common MS IOCB */ 1260 1255 /* Request size adjusted after CT preparation */ 1261 - ms_pkt = ha->isp_ops.prep_ms_fdmi_iocb(ha, 0, RHBA_RSP_SIZE); 1256 + ms_pkt = ha->isp_ops->prep_ms_fdmi_iocb(ha, 0, RHBA_RSP_SIZE); 1262 1257 1263 1258 /* Prepare CT request */ 1264 1259 ct_req = qla2x00_prep_ct_fdmi_req(&ha->ct_sns->p.req, RHBA_CMD, ··· 1378 1373 /* Firmware version */ 1379 1374 eiter = (struct ct_fdmi_hba_attr *) (entries + size); 1380 1375 eiter->type = __constant_cpu_to_be16(FDMI_HBA_FIRMWARE_VERSION); 1381 - ha->isp_ops.fw_version_str(ha, eiter->a.fw_version); 1376 + ha->isp_ops->fw_version_str(ha, eiter->a.fw_version); 1382 1377 alen = strlen(eiter->a.fw_version); 1383 1378 alen += (alen & 3) ? (4 - (alen & 3)) : 4; 1384 1379 eiter->len = cpu_to_be16(4 + alen); ··· 1444 1439 1445 1440 /* Issue RPA */ 1446 1441 /* Prepare common MS IOCB */ 1447 - ms_pkt = ha->isp_ops.prep_ms_fdmi_iocb(ha, DHBA_REQ_SIZE, 1442 + ms_pkt = ha->isp_ops->prep_ms_fdmi_iocb(ha, DHBA_REQ_SIZE, 1448 1443 DHBA_RSP_SIZE); 1449 1444 1450 1445 /* Prepare CT request */ ··· 1502 1497 /* Issue RPA */ 1503 1498 /* Prepare common MS IOCB */ 1504 1499 /* Request size adjusted after CT preparation */ 1505 - ms_pkt = ha->isp_ops.prep_ms_fdmi_iocb(ha, 0, RPA_RSP_SIZE); 1500 + ms_pkt = ha->isp_ops->prep_ms_fdmi_iocb(ha, 0, RPA_RSP_SIZE); 1506 1501 1507 1502 /* Prepare CT request */ 1508 1503 ct_req = qla2x00_prep_ct_fdmi_req(&ha->ct_sns->p.req, RPA_CMD, ··· 1532 1527 eiter = (struct ct_fdmi_port_attr *) (entries + size); 1533 1528 eiter->type = __constant_cpu_to_be16(FDMI_PORT_SUPPORT_SPEED); 1534 1529 eiter->len = __constant_cpu_to_be16(4 + 4); 1535 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 1536 - eiter->a.sup_speed = __constant_cpu_to_be32(4); 1530 + if (IS_QLA25XX(ha)) 1531 + eiter->a.sup_speed = __constant_cpu_to_be32( 1532 + FDMI_PORT_SPEED_1GB|FDMI_PORT_SPEED_2GB| 1533 + FDMI_PORT_SPEED_4GB|FDMI_PORT_SPEED_8GB); 1534 + else if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 1535 + eiter->a.sup_speed = __constant_cpu_to_be32( 1536 + FDMI_PORT_SPEED_1GB|FDMI_PORT_SPEED_2GB| 1537 + FDMI_PORT_SPEED_4GB); 1537 1538 else if (IS_QLA23XX(ha)) 1538 - eiter->a.sup_speed = __constant_cpu_to_be32(2); 1539 + eiter->a.sup_speed =__constant_cpu_to_be32( 1540 + FDMI_PORT_SPEED_1GB|FDMI_PORT_SPEED_2GB); 1539 1541 else 1540 - eiter->a.sup_speed = __constant_cpu_to_be32(1); 1542 + eiter->a.sup_speed = __constant_cpu_to_be32( 1543 + FDMI_PORT_SPEED_1GB); 1541 1544 size += 4 + 4; 1542 1545 1543 1546 DEBUG13(printk("%s(%ld): SUPPORTED_SPEED=%x.\n", __func__, ha->host_no, ··· 1556 1543 eiter->type = __constant_cpu_to_be16(FDMI_PORT_CURRENT_SPEED); 1557 1544 eiter->len = __constant_cpu_to_be16(4 + 4); 1558 1545 switch (ha->link_data_rate) { 1559 - case 0: 1560 - eiter->a.cur_speed = __constant_cpu_to_be32(1); 1546 + case PORT_SPEED_1GB: 1547 + eiter->a.cur_speed = 1548 + __constant_cpu_to_be32(FDMI_PORT_SPEED_1GB); 1561 1549 break; 1562 - case 1: 1563 - eiter->a.cur_speed = __constant_cpu_to_be32(2); 1550 + case PORT_SPEED_2GB: 1551 + eiter->a.cur_speed = 1552 + __constant_cpu_to_be32(FDMI_PORT_SPEED_2GB); 1564 1553 break; 1565 - case 3: 1566 - eiter->a.cur_speed = __constant_cpu_to_be32(4); 1554 + case PORT_SPEED_4GB: 1555 + eiter->a.cur_speed = 1556 + __constant_cpu_to_be32(FDMI_PORT_SPEED_4GB); 1557 + break; 1558 + case PORT_SPEED_8GB: 1559 + eiter->a.cur_speed = 1560 + __constant_cpu_to_be32(FDMI_PORT_SPEED_8GB); 1561 + break; 1562 + default: 1563 + eiter->a.cur_speed = 1564 + __constant_cpu_to_be32(FDMI_PORT_SPEED_UNKNOWN); 1567 1565 break; 1568 1566 } 1569 1567 size += 4 + 4; ··· 1586 1562 eiter = (struct ct_fdmi_port_attr *) (entries + size); 1587 1563 eiter->type = __constant_cpu_to_be16(FDMI_PORT_MAX_FRAME_SIZE); 1588 1564 eiter->len = __constant_cpu_to_be16(4 + 4); 1589 - max_frame_size = IS_QLA24XX(ha) || IS_QLA54XX(ha) ? 1565 + max_frame_size = IS_FWI2_CAPABLE(ha) ? 1590 1566 (uint32_t) icb24->frame_payload_size: 1591 1567 (uint32_t) ha->init_cb->frame_payload_size; 1592 1568 eiter->a.max_frame_size = cpu_to_be32(max_frame_size); ··· 1702 1678 struct ct_sns_req *ct_req; 1703 1679 struct ct_sns_rsp *ct_rsp; 1704 1680 1705 - if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha)) 1681 + if (!IS_IIDMA_CAPABLE(ha)) 1706 1682 return QLA_FUNCTION_FAILED; 1707 1683 1708 1684 for (i = 0; i < MAX_FIBRE_DEVICES; i++) { ··· 1710 1686 memset(list[i].fabric_port_name, 0, WWN_SIZE); 1711 1687 1712 1688 /* Prepare common MS IOCB */ 1713 - ms_pkt = ha->isp_ops.prep_ms_iocb(ha, GFPN_ID_REQ_SIZE, 1689 + ms_pkt = ha->isp_ops->prep_ms_iocb(ha, GFPN_ID_REQ_SIZE, 1714 1690 GFPN_ID_RSP_SIZE); 1715 1691 1716 1692 /* Prepare CT request */ ··· 1810 1786 struct ct_sns_req *ct_req; 1811 1787 struct ct_sns_rsp *ct_rsp; 1812 1788 1813 - if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha)) 1789 + if (!IS_IIDMA_CAPABLE(ha)) 1814 1790 return QLA_FUNCTION_FAILED; 1815 1791 if (!ha->flags.gpsc_supported) 1816 1792 return QLA_FUNCTION_FAILED;

+76 -60

drivers/scsi/qla2xxx/qla_init.c

··· 79 79 set_bit(REGISTER_FDMI_NEEDED, &ha->dpc_flags); 80 80 81 81 qla_printk(KERN_INFO, ha, "Configuring PCI space...\n"); 82 - rval = ha->isp_ops.pci_config(ha); 82 + rval = ha->isp_ops->pci_config(ha); 83 83 if (rval) { 84 84 DEBUG2(printk("scsi(%ld): Unable to configure PCI space.\n", 85 85 ha->host_no)); 86 86 return (rval); 87 87 } 88 88 89 - ha->isp_ops.reset_chip(ha); 89 + ha->isp_ops->reset_chip(ha); 90 90 91 - ha->isp_ops.get_flash_version(ha, ha->request_ring); 91 + ha->isp_ops->get_flash_version(ha, ha->request_ring); 92 92 93 93 qla_printk(KERN_INFO, ha, "Configure NVRAM parameters...\n"); 94 94 95 - ha->isp_ops.nvram_config(ha); 95 + ha->isp_ops->nvram_config(ha); 96 96 97 97 if (ha->flags.disable_serdes) { 98 98 /* Mask HBA via NVRAM settings? */ ··· 108 108 qla_printk(KERN_INFO, ha, "Verifying loaded RISC code...\n"); 109 109 110 110 if (qla2x00_isp_firmware(ha) != QLA_SUCCESS) { 111 - rval = ha->isp_ops.chip_diag(ha); 111 + rval = ha->isp_ops->chip_diag(ha); 112 112 if (rval) 113 113 return (rval); 114 114 rval = qla2x00_setup_chip(ha); ··· 129 129 int 130 130 qla2100_pci_config(scsi_qla_host_t *ha) 131 131 { 132 - int ret; 133 132 uint16_t w; 134 133 uint32_t d; 135 134 unsigned long flags; 136 135 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 137 136 138 137 pci_set_master(ha->pdev); 139 - ret = pci_set_mwi(ha->pdev); 138 + pci_try_set_mwi(ha->pdev); 140 139 141 140 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 142 141 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); ··· 163 164 int 164 165 qla2300_pci_config(scsi_qla_host_t *ha) 165 166 { 166 - int ret; 167 167 uint16_t w; 168 168 uint32_t d; 169 169 unsigned long flags = 0; ··· 170 172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 171 173 172 174 pci_set_master(ha->pdev); 173 - ret = pci_set_mwi(ha->pdev); 175 + pci_try_set_mwi(ha->pdev); 174 176 175 177 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 176 178 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); ··· 248 250 int 249 251 qla24xx_pci_config(scsi_qla_host_t *ha) 250 252 { 251 - int ret; 252 253 uint16_t w; 253 254 uint32_t d; 254 255 unsigned long flags = 0; 255 256 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 256 - int pcix_cmd_reg, pcie_dctl_reg; 257 257 258 258 pci_set_master(ha->pdev); 259 - ret = pci_set_mwi(ha->pdev); 259 + pci_try_set_mwi(ha->pdev); 260 260 261 261 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 262 262 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); ··· 264 268 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 265 269 266 270 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ 267 - pcix_cmd_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX); 268 - if (pcix_cmd_reg) { 269 - uint16_t pcix_cmd; 270 - 271 - pcix_cmd_reg += PCI_X_CMD; 272 - pci_read_config_word(ha->pdev, pcix_cmd_reg, &pcix_cmd); 273 - pcix_cmd &= ~PCI_X_CMD_MAX_READ; 274 - pcix_cmd |= 0x0008; 275 - pci_write_config_word(ha->pdev, pcix_cmd_reg, pcix_cmd); 276 - } 271 + if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX)) 272 + pcix_set_mmrbc(ha->pdev, 2048); 277 273 278 274 /* PCIe -- adjust Maximum Read Request Size (2048). */ 279 - pcie_dctl_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 280 - if (pcie_dctl_reg) { 281 - uint16_t pcie_dctl; 282 - 283 - pcie_dctl_reg += PCI_EXP_DEVCTL; 284 - pci_read_config_word(ha->pdev, pcie_dctl_reg, &pcie_dctl); 285 - pcie_dctl &= ~PCI_EXP_DEVCTL_READRQ; 286 - pcie_dctl |= 0x4000; 287 - pci_write_config_word(ha->pdev, pcie_dctl_reg, pcie_dctl); 288 - } 275 + if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP)) 276 + pcie_set_readrq(ha->pdev, 2048); 289 277 290 278 /* Reset expansion ROM address decode enable */ 291 279 pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d); ··· 282 302 spin_lock_irqsave(&ha->hardware_lock, flags); 283 303 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status); 284 304 spin_unlock_irqrestore(&ha->hardware_lock, flags); 305 + 306 + return QLA_SUCCESS; 307 + } 308 + 309 + /** 310 + * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers. 311 + * @ha: HA context 312 + * 313 + * Returns 0 on success. 314 + */ 315 + int 316 + qla25xx_pci_config(scsi_qla_host_t *ha) 317 + { 318 + uint16_t w; 319 + uint32_t d; 320 + 321 + pci_set_master(ha->pdev); 322 + pci_try_set_mwi(ha->pdev); 323 + 324 + pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 325 + w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 326 + w &= ~PCI_COMMAND_INTX_DISABLE; 327 + pci_write_config_word(ha->pdev, PCI_COMMAND, w); 328 + 329 + /* PCIe -- adjust Maximum Read Request Size (2048). */ 330 + if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP)) 331 + pcie_set_readrq(ha->pdev, 2048); 332 + 333 + /* Reset expansion ROM address decode enable */ 334 + pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d); 335 + d &= ~PCI_ROM_ADDRESS_ENABLE; 336 + pci_write_config_dword(ha->pdev, PCI_ROM_ADDRESS, d); 337 + 338 + ha->chip_revision = ha->pdev->revision; 285 339 286 340 return QLA_SUCCESS; 287 341 } ··· 365 351 uint32_t cnt; 366 352 uint16_t cmd; 367 353 368 - ha->isp_ops.disable_intrs(ha); 354 + ha->isp_ops->disable_intrs(ha); 369 355 370 356 spin_lock_irqsave(&ha->hardware_lock, flags); 371 357 ··· 565 551 void 566 552 qla24xx_reset_chip(scsi_qla_host_t *ha) 567 553 { 568 - ha->isp_ops.disable_intrs(ha); 554 + ha->isp_ops->disable_intrs(ha); 569 555 570 556 /* Perform RISC reset. */ 571 557 qla24xx_reset_risc(ha); ··· 750 736 fixed_size = offsetof(struct qla2300_fw_dump, data_ram); 751 737 mem_size = (ha->fw_memory_size - 0x11000 + 1) * 752 738 sizeof(uint16_t); 753 - } else if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 754 - fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem); 739 + } else if (IS_FWI2_CAPABLE(ha)) { 740 + fixed_size = IS_QLA25XX(ha) ? 741 + offsetof(struct qla25xx_fw_dump, ext_mem): 742 + offsetof(struct qla24xx_fw_dump, ext_mem); 755 743 mem_size = (ha->fw_memory_size - 0x100000 + 1) * 756 744 sizeof(uint32_t); 757 745 ··· 895 879 uint32_t srisc_address = 0; 896 880 897 881 /* Load firmware sequences */ 898 - rval = ha->isp_ops.load_risc(ha, &srisc_address); 882 + rval = ha->isp_ops->load_risc(ha, &srisc_address); 899 883 if (rval == QLA_SUCCESS) { 900 884 DEBUG(printk("scsi(%ld): Verifying Checksum of loaded RISC " 901 885 "code.\n", ha->host_no)); ··· 1146 1130 /* Initialize response queue entries */ 1147 1131 qla2x00_init_response_q_entries(ha); 1148 1132 1149 - ha->isp_ops.config_rings(ha); 1133 + ha->isp_ops->config_rings(ha); 1150 1134 1151 1135 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1152 1136 1153 1137 /* Update any ISP specific firmware options before initialization. */ 1154 - ha->isp_ops.update_fw_options(ha); 1138 + ha->isp_ops->update_fw_options(ha); 1155 1139 1156 1140 DEBUG(printk("scsi(%ld): Issue init firmware.\n", ha->host_no)); 1157 1141 ··· 1475 1459 ha->nvram_base = 0x80; 1476 1460 1477 1461 /* Get NVRAM data and calculate checksum. */ 1478 - ha->isp_ops.read_nvram(ha, ptr, ha->nvram_base, ha->nvram_size); 1462 + ha->isp_ops->read_nvram(ha, ptr, ha->nvram_base, ha->nvram_size); 1479 1463 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++) 1480 1464 chksum += *ptr++; 1481 1465 ··· 2135 2119 int rval; 2136 2120 uint16_t port_speed, mb[6]; 2137 2121 2138 - if (!IS_QLA24XX(ha)) 2122 + if (!IS_IIDMA_CAPABLE(ha)) 2139 2123 return; 2140 2124 2141 2125 switch (be16_to_cpu(fcport->fp_speed)) { ··· 2283 2267 scsi_qla_host_t *pha = to_qla_parent(ha); 2284 2268 2285 2269 /* If FL port exists, then SNS is present */ 2286 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 2270 + if (IS_FWI2_CAPABLE(ha)) 2287 2271 loop_id = NPH_F_PORT; 2288 2272 else 2289 2273 loop_id = SNS_FL_PORT; ··· 2310 2294 qla2x00_fdmi_register(ha); 2311 2295 2312 2296 /* Ensure we are logged into the SNS. */ 2313 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 2297 + if (IS_FWI2_CAPABLE(ha)) 2314 2298 loop_id = NPH_SNS; 2315 2299 else 2316 2300 loop_id = SIMPLE_NAME_SERVER; 2317 - ha->isp_ops.fabric_login(ha, loop_id, 0xff, 0xff, 2301 + ha->isp_ops->fabric_login(ha, loop_id, 0xff, 0xff, 2318 2302 0xfc, mb, BIT_1 | BIT_0); 2319 2303 if (mb[0] != MBS_COMMAND_COMPLETE) { 2320 2304 DEBUG2(qla_printk(KERN_INFO, ha, ··· 2371 2355 (fcport->flags & FCF_TAPE_PRESENT) == 0 && 2372 2356 fcport->port_type != FCT_INITIATOR && 2373 2357 fcport->port_type != FCT_BROADCAST) { 2374 - ha->isp_ops.fabric_logout(ha, 2358 + ha->isp_ops->fabric_logout(ha, 2375 2359 fcport->loop_id, 2376 2360 fcport->d_id.b.domain, 2377 2361 fcport->d_id.b.area, ··· 2680 2664 (fcport->flags & FCF_TAPE_PRESENT) == 0 && 2681 2665 fcport->port_type != FCT_INITIATOR && 2682 2666 fcport->port_type != FCT_BROADCAST) { 2683 - ha->isp_ops.fabric_logout(ha, fcport->loop_id, 2667 + ha->isp_ops->fabric_logout(ha, fcport->loop_id, 2684 2668 fcport->d_id.b.domain, fcport->d_id.b.area, 2685 2669 fcport->d_id.b.al_pa); 2686 2670 fcport->loop_id = FC_NO_LOOP_ID; ··· 2935 2919 opts |= BIT_1; 2936 2920 rval = qla2x00_get_port_database(ha, fcport, opts); 2937 2921 if (rval != QLA_SUCCESS) { 2938 - ha->isp_ops.fabric_logout(ha, fcport->loop_id, 2922 + ha->isp_ops->fabric_logout(ha, fcport->loop_id, 2939 2923 fcport->d_id.b.domain, fcport->d_id.b.area, 2940 2924 fcport->d_id.b.al_pa); 2941 2925 qla2x00_mark_device_lost(ha, fcport, 1, 0); ··· 2980 2964 fcport->d_id.b.area, fcport->d_id.b.al_pa)); 2981 2965 2982 2966 /* Login fcport on switch. */ 2983 - ha->isp_ops.fabric_login(ha, fcport->loop_id, 2967 + ha->isp_ops->fabric_login(ha, fcport->loop_id, 2984 2968 fcport->d_id.b.domain, fcport->d_id.b.area, 2985 2969 fcport->d_id.b.al_pa, mb, BIT_0); 2986 2970 if (mb[0] == MBS_PORT_ID_USED) { ··· 3048 3032 * dead. 3049 3033 */ 3050 3034 *next_loopid = fcport->loop_id; 3051 - ha->isp_ops.fabric_logout(ha, fcport->loop_id, 3035 + ha->isp_ops->fabric_logout(ha, fcport->loop_id, 3052 3036 fcport->d_id.b.domain, fcport->d_id.b.area, 3053 3037 fcport->d_id.b.al_pa); 3054 3038 qla2x00_mark_device_lost(ha, fcport, 1, 0); ··· 3066 3050 fcport->d_id.b.al_pa, fcport->loop_id, jiffies)); 3067 3051 3068 3052 *next_loopid = fcport->loop_id; 3069 - ha->isp_ops.fabric_logout(ha, fcport->loop_id, 3053 + ha->isp_ops->fabric_logout(ha, fcport->loop_id, 3070 3054 fcport->d_id.b.domain, fcport->d_id.b.area, 3071 3055 fcport->d_id.b.al_pa); 3072 3056 fcport->loop_id = FC_NO_LOOP_ID; ··· 3222 3206 3223 3207 qla_printk(KERN_INFO, ha, 3224 3208 "Performing ISP error recovery - ha= %p.\n", ha); 3225 - ha->isp_ops.reset_chip(ha); 3209 + ha->isp_ops->reset_chip(ha); 3226 3210 3227 3211 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME); 3228 3212 if (atomic_read(&ha->loop_state) != LOOP_DOWN) { ··· 3248 3232 } 3249 3233 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3250 3234 3251 - ha->isp_ops.get_flash_version(ha, ha->request_ring); 3235 + ha->isp_ops->get_flash_version(ha, ha->request_ring); 3252 3236 3253 - ha->isp_ops.nvram_config(ha); 3237 + ha->isp_ops->nvram_config(ha); 3254 3238 3255 3239 if (!qla2x00_restart_isp(ha)) { 3256 3240 clear_bit(RESET_MARKER_NEEDED, &ha->dpc_flags); ··· 3265 3249 3266 3250 ha->flags.online = 1; 3267 3251 3268 - ha->isp_ops.enable_intrs(ha); 3252 + ha->isp_ops->enable_intrs(ha); 3269 3253 3270 3254 ha->isp_abort_cnt = 0; 3271 3255 clear_bit(ISP_ABORT_RETRY, &ha->dpc_flags); ··· 3290 3274 * The next call disables the board 3291 3275 * completely. 3292 3276 */ 3293 - ha->isp_ops.reset_adapter(ha); 3277 + ha->isp_ops->reset_adapter(ha); 3294 3278 ha->flags.online = 0; 3295 3279 clear_bit(ISP_ABORT_RETRY, 3296 3280 &ha->dpc_flags); ··· 3347 3331 /* If firmware needs to be loaded */ 3348 3332 if (qla2x00_isp_firmware(ha)) { 3349 3333 ha->flags.online = 0; 3350 - if (!(status = ha->isp_ops.chip_diag(ha))) { 3334 + if (!(status = ha->isp_ops->chip_diag(ha))) { 3351 3335 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3352 3336 status = qla2x00_setup_chip(ha); 3353 3337 goto done; ··· 3439 3423 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 3440 3424 3441 3425 ha->flags.online = 0; 3442 - ha->isp_ops.disable_intrs(ha); 3426 + ha->isp_ops->disable_intrs(ha); 3443 3427 3444 3428 spin_lock_irqsave(&ha->hardware_lock, flags); 3445 3429 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC); ··· 3456 3440 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 3457 3441 3458 3442 ha->flags.online = 0; 3459 - ha->isp_ops.disable_intrs(ha); 3443 + ha->isp_ops->disable_intrs(ha); 3460 3444 3461 3445 spin_lock_irqsave(&ha->hardware_lock, flags); 3462 3446 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET); ··· 3514 3498 3515 3499 /* Get NVRAM data and calculate checksum. */ 3516 3500 dptr = (uint32_t *)nv; 3517 - ha->isp_ops.read_nvram(ha, (uint8_t *)dptr, ha->nvram_base, 3501 + ha->isp_ops->read_nvram(ha, (uint8_t *)dptr, ha->nvram_base, 3518 3502 ha->nvram_size); 3519 3503 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++) 3520 3504 chksum += le32_to_cpu(*dptr++); ··· 4028 4012 { 4029 4013 int ret, retries; 4030 4014 4031 - if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha)) 4015 + if (!IS_FWI2_CAPABLE(ha)) 4032 4016 return; 4033 4017 if (!ha->fw_major_version) 4034 4018 return;

+2 -2

drivers/scsi/qla2xxx/qla_inline.h

··· 104 104 static inline void 105 105 qla2x00_poll(scsi_qla_host_t *ha) 106 106 { 107 - ha->isp_ops.intr_handler(0, ha); 107 + ha->isp_ops->intr_handler(0, ha); 108 108 } 109 109 110 110 static __inline__ void qla2x00_check_fabric_devices(scsi_qla_host_t *); ··· 163 163 static inline int 164 164 qla2x00_is_reserved_id(scsi_qla_host_t *ha, uint16_t loop_id) 165 165 { 166 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 166 + if (IS_FWI2_CAPABLE(ha)) 167 167 return (loop_id > NPH_LAST_HANDLE); 168 168 169 169 return ((loop_id > ha->last_loop_id && loop_id < SNS_FIRST_LOOP_ID) ||

+5 -5

drivers/scsi/qla2xxx/qla_iocb.c

··· 326 326 tot_dsds = nseg; 327 327 328 328 /* Calculate the number of request entries needed. */ 329 - req_cnt = ha->isp_ops.calc_req_entries(tot_dsds); 329 + req_cnt = ha->isp_ops->calc_req_entries(tot_dsds); 330 330 if (ha->req_q_cnt < (req_cnt + 2)) { 331 331 cnt = RD_REG_WORD_RELAXED(ISP_REQ_Q_OUT(ha, reg)); 332 332 if (ha->req_ring_index < cnt) ··· 364 364 cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); 365 365 366 366 /* Build IOCB segments */ 367 - ha->isp_ops.build_iocbs(sp, cmd_pkt, tot_dsds); 367 + ha->isp_ops->build_iocbs(sp, cmd_pkt, tot_dsds); 368 368 369 369 /* Set total data segment count. */ 370 370 cmd_pkt->entry_count = (uint8_t)req_cnt; ··· 432 432 mrk->entry_type = MARKER_TYPE; 433 433 mrk->modifier = type; 434 434 if (type != MK_SYNC_ALL) { 435 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 435 + if (IS_FWI2_CAPABLE(ha)) { 436 436 mrk24 = (struct mrk_entry_24xx *) mrk; 437 437 mrk24->nport_handle = cpu_to_le16(loop_id); 438 438 mrk24->lun[1] = LSB(lun); ··· 487 487 for (timer = HZ; timer; timer--) { 488 488 if ((req_cnt + 2) >= ha->req_q_cnt) { 489 489 /* Calculate number of free request entries. */ 490 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 490 + if (IS_FWI2_CAPABLE(ha)) 491 491 cnt = (uint16_t)RD_REG_DWORD( 492 492 &reg->isp24.req_q_out); 493 493 else ··· 561 561 ha->request_ring_ptr++; 562 562 563 563 /* Set chip new ring index. */ 564 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 564 + if (IS_FWI2_CAPABLE(ha)) { 565 565 WRT_REG_DWORD(&reg->isp24.req_q_in, ha->req_ring_index); 566 566 RD_REG_DWORD_RELAXED(&reg->isp24.req_q_in); 567 567 } else {

+37 -18

drivers/scsi/qla2xxx/qla_isr.c

··· 143 143 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC); 144 144 RD_REG_WORD(&reg->hccr); 145 145 146 - ha->isp_ops.fw_dump(ha, 1); 146 + ha->isp_ops->fw_dump(ha, 1); 147 147 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); 148 148 break; 149 149 } else if ((stat & HSR_RISC_INT) == 0) ··· 247 247 qla2x00_async_event(scsi_qla_host_t *ha, uint16_t *mb) 248 248 { 249 249 #define LS_UNKNOWN 2 250 - static char *link_speeds[5] = { "1", "2", "?", "4", "10" }; 250 + static char *link_speeds[5] = { "1", "2", "?", "4", "8" }; 251 251 char *link_speed; 252 252 uint16_t handle_cnt; 253 253 uint16_t cnt; ··· 334 334 "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh.\n", 335 335 mb[1], mb[2], mb[3]); 336 336 337 - ha->isp_ops.fw_dump(ha, 1); 337 + ha->isp_ops->fw_dump(ha, 1); 338 338 339 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 339 + if (IS_FWI2_CAPABLE(ha)) { 340 340 if (mb[1] == 0 && mb[2] == 0) { 341 341 qla_printk(KERN_ERR, ha, 342 342 "Unrecoverable Hardware Error: adapter " ··· 601 601 "scsi(%ld): [R|Z]IO update completion.\n", 602 602 ha->host_no)); 603 603 604 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 604 + if (IS_FWI2_CAPABLE(ha)) 605 605 qla24xx_process_response_queue(ha); 606 606 else 607 607 qla2x00_process_response_queue(ha); ··· 823 823 824 824 sts = (sts_entry_t *) pkt; 825 825 sts24 = (struct sts_entry_24xx *) pkt; 826 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 826 + if (IS_FWI2_CAPABLE(ha)) { 827 827 comp_status = le16_to_cpu(sts24->comp_status); 828 828 scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK; 829 829 } else { ··· 872 872 fcport = sp->fcport; 873 873 874 874 sense_len = rsp_info_len = resid_len = fw_resid_len = 0; 875 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 875 + if (IS_FWI2_CAPABLE(ha)) { 876 876 sense_len = le32_to_cpu(sts24->sense_len); 877 877 rsp_info_len = le32_to_cpu(sts24->rsp_data_len); 878 878 resid_len = le32_to_cpu(sts24->rsp_residual_count); ··· 891 891 /* Check for any FCP transport errors. */ 892 892 if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) { 893 893 /* Sense data lies beyond any FCP RESPONSE data. */ 894 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 894 + if (IS_FWI2_CAPABLE(ha)) 895 895 sense_data += rsp_info_len; 896 896 if (rsp_info_len > 3 && rsp_info[3]) { 897 897 DEBUG2(printk("scsi(%ld:%d:%d:%d) FCP I/O protocol " ··· 990 990 case CS_DATA_UNDERRUN: 991 991 resid = resid_len; 992 992 /* Use F/W calculated residual length. */ 993 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 993 + if (IS_FWI2_CAPABLE(ha)) 994 994 resid = fw_resid_len; 995 995 996 996 if (scsi_status & SS_RESIDUAL_UNDER) { ··· 1061 1061 __func__, ha->host_no, cp->device->channel, 1062 1062 cp->device->id, cp->device->lun, cp, 1063 1063 cp->serial_number)); 1064 + 1065 + /* 1066 + * In case of a Underrun condition, set both the lscsi 1067 + * status and the completion status to appropriate 1068 + * values. 1069 + */ 1070 + if (resid && 1071 + ((unsigned)(cp->request_bufflen - resid) < 1072 + cp->underflow)) { 1073 + DEBUG2(qla_printk(KERN_INFO, ha, 1074 + "scsi(%ld:%d:%d:%d): Mid-layer underflow " 1075 + "detected (%x of %x bytes)...returning " 1076 + "error status.\n", ha->host_no, 1077 + cp->device->channel, cp->device->id, 1078 + cp->device->lun, resid, 1079 + cp->request_bufflen)); 1080 + 1081 + cp->result = DID_ERROR << 16 | lscsi_status; 1082 + } 1064 1083 1065 1084 if (sense_len) 1066 1085 DEBUG5(qla2x00_dump_buffer(cp->sense_buffer, ··· 1185 1166 case CS_TIMEOUT: 1186 1167 cp->result = DID_BUS_BUSY << 16; 1187 1168 1188 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 1169 + if (IS_FWI2_CAPABLE(ha)) { 1189 1170 DEBUG2(printk(KERN_INFO 1190 1171 "scsi(%ld:%d:%d:%d): TIMEOUT status detected " 1191 1172 "0x%x-0x%x\n", ha->host_no, cp->device->channel, ··· 1254 1235 } 1255 1236 1256 1237 /* Move sense data. */ 1257 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 1238 + if (IS_FWI2_CAPABLE(ha)) 1258 1239 host_to_fcp_swap(pkt->data, sizeof(pkt->data)); 1259 1240 memcpy(sp->request_sense_ptr, pkt->data, sense_sz); 1260 1241 DEBUG5(qla2x00_dump_buffer(sp->request_sense_ptr, sense_sz)); ··· 1502 1483 1503 1484 qla_printk(KERN_INFO, ha, "RISC paused -- HCCR=%x, " 1504 1485 "Dumping firmware!\n", hccr); 1505 - ha->isp_ops.fw_dump(ha, 1); 1486 + ha->isp_ops->fw_dump(ha, 1); 1506 1487 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); 1507 1488 break; 1508 1489 } else if ((stat & HSRX_RISC_INT) == 0) ··· 1636 1617 1637 1618 qla_printk(KERN_INFO, ha, "RISC paused -- HCCR=%x, " 1638 1619 "Dumping firmware!\n", hccr); 1639 - ha->isp_ops.fw_dump(ha, 1); 1620 + ha->isp_ops->fw_dump(ha, 1); 1640 1621 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); 1641 1622 break; 1642 1623 } else if ((stat & HSRX_RISC_INT) == 0) ··· 1758 1739 int ret; 1759 1740 1760 1741 /* If possible, enable MSI-X. */ 1761 - if (!IS_QLA2432(ha)) 1742 + if (!IS_QLA2432(ha) && !IS_QLA2532(ha)) 1762 1743 goto skip_msix; 1763 1744 1764 - if (ha->chip_revision < QLA_MSIX_CHIP_REV_24XX || 1765 - !QLA_MSIX_FW_MODE_1(ha->fw_attributes)) { 1745 + if (IS_QLA2432(ha) && (ha->chip_revision < QLA_MSIX_CHIP_REV_24XX || 1746 + !QLA_MSIX_FW_MODE_1(ha->fw_attributes))) { 1766 1747 DEBUG2(qla_printk(KERN_WARNING, ha, 1767 1748 "MSI-X: Unsupported ISP2432 (0x%X, 0x%X).\n", 1768 1749 ha->chip_revision, ha->fw_attributes)); ··· 1781 1762 "MSI-X: Falling back-to INTa mode -- %d.\n", ret); 1782 1763 skip_msix: 1783 1764 1784 - if (!IS_QLA24XX(ha)) 1765 + if (!IS_QLA24XX(ha) && !IS_QLA2532(ha)) 1785 1766 goto skip_msi; 1786 1767 1787 1768 ret = pci_enable_msi(ha->pdev); ··· 1791 1772 } 1792 1773 skip_msi: 1793 1774 1794 - ret = request_irq(ha->pdev->irq, ha->isp_ops.intr_handler, 1775 + ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler, 1795 1776 IRQF_DISABLED|IRQF_SHARED, QLA2XXX_DRIVER_NAME, ha); 1796 1777 if (!ret) { 1797 1778 ha->flags.inta_enabled = 1;

+29 -29

drivers/scsi/qla2xxx/qla_mbx.c

··· 90 90 spin_lock_irqsave(&ha->hardware_lock, flags); 91 91 92 92 /* Load mailbox registers. */ 93 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 93 + if (IS_FWI2_CAPABLE(ha)) 94 94 optr = (uint16_t __iomem *)&reg->isp24.mailbox0; 95 95 else 96 96 optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0); ··· 154 154 155 155 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 156 156 157 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 157 + if (IS_FWI2_CAPABLE(ha)) 158 158 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT); 159 159 else 160 160 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT); ··· 175 175 DEBUG3_11(printk("%s(%ld): cmd=%x POLLING MODE.\n", __func__, 176 176 ha->host_no, command)); 177 177 178 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 178 + if (IS_FWI2_CAPABLE(ha)) 179 179 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT); 180 180 else 181 181 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT); ··· 228 228 uint16_t mb0; 229 229 uint32_t ictrl; 230 230 231 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 231 + if (IS_FWI2_CAPABLE(ha)) { 232 232 mb0 = RD_REG_WORD(&reg->isp24.mailbox0); 233 233 ictrl = RD_REG_DWORD(&reg->isp24.ictrl); 234 234 } else { ··· 322 322 323 323 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); 324 324 325 - if (MSW(risc_addr) || IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 325 + if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) { 326 326 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED; 327 327 mcp->mb[8] = MSW(risc_addr); 328 328 mcp->out_mb = MBX_8|MBX_0; ··· 336 336 mcp->mb[6] = MSW(MSD(req_dma)); 337 337 mcp->mb[7] = LSW(MSD(req_dma)); 338 338 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1; 339 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 339 + if (IS_FWI2_CAPABLE(ha)) { 340 340 mcp->mb[4] = MSW(risc_code_size); 341 341 mcp->mb[5] = LSW(risc_code_size); 342 342 mcp->out_mb |= MBX_5|MBX_4; ··· 387 387 mcp->mb[0] = MBC_EXECUTE_FIRMWARE; 388 388 mcp->out_mb = MBX_0; 389 389 mcp->in_mb = MBX_0; 390 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 390 + if (IS_FWI2_CAPABLE(ha)) { 391 391 mcp->mb[1] = MSW(risc_addr); 392 392 mcp->mb[2] = LSW(risc_addr); 393 393 mcp->mb[3] = 0; ··· 410 410 DEBUG2_3_11(printk("%s(%ld): failed=%x mb[0]=%x.\n", __func__, 411 411 ha->host_no, rval, mcp->mb[0])); 412 412 } else { 413 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 413 + if (IS_FWI2_CAPABLE(ha)) { 414 414 DEBUG11(printk("%s(%ld): done exchanges=%x.\n", 415 415 __func__, ha->host_no, mcp->mb[1])); 416 416 } else { ··· 551 551 mcp->mb[3] = fwopts[3]; 552 552 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; 553 553 mcp->in_mb = MBX_0; 554 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 554 + if (IS_FWI2_CAPABLE(ha)) { 555 555 mcp->in_mb |= MBX_1; 556 556 } else { 557 557 mcp->mb[10] = fwopts[10]; ··· 664 664 mcp->mb[0] = MBC_VERIFY_CHECKSUM; 665 665 mcp->out_mb = MBX_0; 666 666 mcp->in_mb = MBX_0; 667 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 667 + if (IS_FWI2_CAPABLE(ha)) { 668 668 mcp->mb[1] = MSW(risc_addr); 669 669 mcp->mb[2] = LSW(risc_addr); 670 670 mcp->out_mb |= MBX_2|MBX_1; ··· 681 681 682 682 if (rval != QLA_SUCCESS) { 683 683 DEBUG2_3_11(printk("%s(%ld): failed=%x chk sum=%x.\n", __func__, 684 - ha->host_no, rval, (IS_QLA24XX(ha) || IS_QLA54XX(ha) ? 685 - (mcp->mb[2] << 16) | mcp->mb[1]: mcp->mb[1]))); 684 + ha->host_no, rval, IS_FWI2_CAPABLE(ha) ? 685 + (mcp->mb[2] << 16) | mcp->mb[1]: mcp->mb[1])); 686 686 } else { 687 687 DEBUG11(printk("%s(%ld): done.\n", __func__, ha->host_no)); 688 688 } ··· 739 739 740 740 /* Mask reserved bits. */ 741 741 sts_entry->entry_status &= 742 - IS_QLA24XX(ha) || IS_QLA54XX(ha) ? RF_MASK_24XX :RF_MASK; 742 + IS_FWI2_CAPABLE(ha) ? RF_MASK_24XX :RF_MASK; 743 743 } 744 744 745 745 return rval; ··· 1085 1085 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE)); 1086 1086 1087 1087 mcp->mb[0] = MBC_GET_PORT_DATABASE; 1088 - if (opt != 0 && !IS_QLA24XX(ha) && !IS_QLA54XX(ha)) 1088 + if (opt != 0 && !IS_FWI2_CAPABLE(ha)) 1089 1089 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE; 1090 1090 mcp->mb[2] = MSW(pd_dma); 1091 1091 mcp->mb[3] = LSW(pd_dma); ··· 1094 1094 mcp->mb[9] = ha->vp_idx; 1095 1095 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 1096 1096 mcp->in_mb = MBX_0; 1097 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 1097 + if (IS_FWI2_CAPABLE(ha)) { 1098 1098 mcp->mb[1] = fcport->loop_id; 1099 1099 mcp->mb[10] = opt; 1100 1100 mcp->out_mb |= MBX_10|MBX_1; ··· 1107 1107 mcp->mb[1] = fcport->loop_id << 8 | opt; 1108 1108 mcp->out_mb |= MBX_1; 1109 1109 } 1110 - mcp->buf_size = (IS_QLA24XX(ha) || IS_QLA54XX(ha) ? 1111 - PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE); 1110 + mcp->buf_size = IS_FWI2_CAPABLE(ha) ? 1111 + PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE; 1112 1112 mcp->flags = MBX_DMA_IN; 1113 1113 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2); 1114 1114 rval = qla2x00_mailbox_command(ha, mcp); 1115 1115 if (rval != QLA_SUCCESS) 1116 1116 goto gpd_error_out; 1117 1117 1118 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 1118 + if (IS_FWI2_CAPABLE(ha)) { 1119 1119 pd24 = (struct port_database_24xx *) pd; 1120 1120 1121 1121 /* Check for logged in state. */ ··· 1333 1333 1334 1334 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); 1335 1335 1336 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 1336 + if (IS_FWI2_CAPABLE(ha)) { 1337 1337 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 1338 1338 mcp->mb[1] = BIT_6; 1339 1339 mcp->mb[2] = 0; ··· 1637 1637 mbx_cmd_t mc; 1638 1638 mbx_cmd_t *mcp = &mc; 1639 1639 1640 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) 1640 + if (IS_FWI2_CAPABLE(ha)) 1641 1641 return qla24xx_login_fabric(ha, fcport->loop_id, 1642 1642 fcport->d_id.b.domain, fcport->d_id.b.area, 1643 1643 fcport->d_id.b.al_pa, mb_ret, opt); ··· 1821 1821 ha->host_no)); 1822 1822 1823 1823 mcp->mb[0] = MBC_LIP_FULL_LOGIN; 1824 - mcp->mb[1] = IS_QLA24XX(ha) || IS_QLA54XX(ha) ? BIT_3: 0; 1824 + mcp->mb[1] = IS_FWI2_CAPABLE(ha) ? BIT_3: 0; 1825 1825 mcp->mb[2] = 0; 1826 1826 mcp->mb[3] = 0; 1827 1827 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0; ··· 1871 1871 1872 1872 mcp->mb[0] = MBC_GET_ID_LIST; 1873 1873 mcp->out_mb = MBX_0; 1874 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 1874 + if (IS_FWI2_CAPABLE(ha)) { 1875 1875 mcp->mb[2] = MSW(id_list_dma); 1876 1876 mcp->mb[3] = LSW(id_list_dma); 1877 1877 mcp->mb[6] = MSW(MSD(id_list_dma)); ··· 2063 2063 mcp->mb[7] = LSW(MSD(stat_buf_dma)); 2064 2064 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0; 2065 2065 mcp->in_mb = MBX_0; 2066 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 2066 + if (IS_FWI2_CAPABLE(ha)) { 2067 2067 mcp->mb[1] = loop_id; 2068 2068 mcp->mb[4] = 0; 2069 2069 mcp->mb[10] = 0; ··· 2334 2334 mbx_cmd_t mc; 2335 2335 mbx_cmd_t *mcp = &mc; 2336 2336 2337 - if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha)) 2337 + if (!IS_FWI2_CAPABLE(ha)) 2338 2338 return QLA_FUNCTION_FAILED; 2339 2339 2340 2340 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); ··· 2444 2444 mbx_cmd_t mc; 2445 2445 mbx_cmd_t *mcp = &mc; 2446 2446 2447 - if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha)) 2447 + if (!IS_FWI2_CAPABLE(ha)) 2448 2448 return QLA_FUNCTION_FAILED; 2449 2449 2450 2450 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); ··· 2474 2474 mbx_cmd_t mc; 2475 2475 mbx_cmd_t *mcp = &mc; 2476 2476 2477 - if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha)) 2477 + if (!IS_FWI2_CAPABLE(ha)) 2478 2478 return QLA_FUNCTION_FAILED; 2479 2479 2480 2480 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); ··· 2514 2514 mbx_cmd_t mc; 2515 2515 mbx_cmd_t *mcp = &mc; 2516 2516 2517 - if (!IS_QLA24XX(ha) && !IS_QLA54XX(ha)) 2517 + if (!IS_FWI2_CAPABLE(ha)) 2518 2518 return QLA_FUNCTION_FAILED; 2519 2519 2520 2520 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); ··· 2552 2552 mbx_cmd_t mc; 2553 2553 mbx_cmd_t *mcp = &mc; 2554 2554 2555 - if (!IS_QLA24XX(ha)) 2555 + if (!IS_IIDMA_CAPABLE(ha)) 2556 2556 return QLA_FUNCTION_FAILED; 2557 2557 2558 2558 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no)); ··· 2595 2595 mbx_cmd_t mc; 2596 2596 mbx_cmd_t *mcp = &mc; 2597 2597 2598 - if (!IS_QLA24XX(ha)) 2598 + if (!IS_IIDMA_CAPABLE(ha)) 2599 2599 return QLA_FUNCTION_FAILED; 2600 2600 2601 2601 DEBUG11(printk("%s(%ld): entered.\n", __func__, ha->host_no));

+247 -133

drivers/scsi/qla2xxx/qla_os.c

··· 265 265 strcpy(str, "PCIe ("); 266 266 if (lspeed == 1) 267 267 strcat(str, "2.5Gb/s "); 268 + else if (lspeed == 2) 269 + strcat(str, "5.0Gb/s "); 268 270 else 269 271 strcat(str, "<unknown> "); 270 272 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); ··· 345 343 strcat(str, "[IP] "); 346 344 if (ha->fw_attributes & BIT_2) 347 345 strcat(str, "[Multi-ID] "); 346 + if (ha->fw_attributes & BIT_3) 347 + strcat(str, "[SB-2] "); 348 + if (ha->fw_attributes & BIT_4) 349 + strcat(str, "[T10 CRC] "); 350 + if (ha->fw_attributes & BIT_5) 351 + strcat(str, "[VI] "); 348 352 if (ha->fw_attributes & BIT_13) 349 353 strcat(str, "[Experimental]"); 350 354 return str; ··· 689 681 DEBUG3(qla2x00_print_scsi_cmd(cmd)); 690 682 691 683 spin_unlock_irqrestore(&pha->hardware_lock, flags); 692 - if (ha->isp_ops.abort_command(ha, sp)) { 684 + if (ha->isp_ops->abort_command(ha, sp)) { 693 685 DEBUG2(printk("%s(%ld): abort_command " 694 686 "mbx failed.\n", __func__, ha->host_no)); 695 687 } else { ··· 821 813 #if defined(LOGOUT_AFTER_DEVICE_RESET) 822 814 if (ret == SUCCESS) { 823 815 if (fcport->flags & FC_FABRIC_DEVICE) { 824 - ha->isp_ops.fabric_logout(ha, fcport->loop_id); 816 + ha->isp_ops->fabric_logout(ha, fcport->loop_id); 825 817 qla2x00_mark_device_lost(ha, fcport, 0, 0); 826 818 } 827 819 } ··· 1113 1105 qla2x00_device_reset(scsi_qla_host_t *ha, fc_port_t *reset_fcport) 1114 1106 { 1115 1107 /* Abort Target command will clear Reservation */ 1116 - return ha->isp_ops.abort_target(reset_fcport); 1108 + return ha->isp_ops->abort_target(reset_fcport); 1117 1109 } 1118 1110 1119 1111 static int ··· 1192 1184 !pci_set_consistent_dma_mask(ha->pdev, DMA_64BIT_MASK)) { 1193 1185 /* Ok, a 64bit DMA mask is applicable. */ 1194 1186 ha->flags.enable_64bit_addressing = 1; 1195 - ha->isp_ops.calc_req_entries = qla2x00_calc_iocbs_64; 1196 - ha->isp_ops.build_iocbs = qla2x00_build_scsi_iocbs_64; 1187 + ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1188 + ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1197 1189 return; 1198 1190 } 1199 1191 } ··· 1201 1193 dma_set_mask(&ha->pdev->dev, DMA_32BIT_MASK); 1202 1194 pci_set_consistent_dma_mask(ha->pdev, DMA_32BIT_MASK); 1203 1195 } 1196 + 1197 + static void 1198 + qla2x00_enable_intrs(scsi_qla_host_t *ha) 1199 + { 1200 + unsigned long flags = 0; 1201 + struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1202 + 1203 + spin_lock_irqsave(&ha->hardware_lock, flags); 1204 + ha->interrupts_on = 1; 1205 + /* enable risc and host interrupts */ 1206 + WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC); 1207 + RD_REG_WORD(&reg->ictrl); 1208 + spin_unlock_irqrestore(&ha->hardware_lock, flags); 1209 + 1210 + } 1211 + 1212 + static void 1213 + qla2x00_disable_intrs(scsi_qla_host_t *ha) 1214 + { 1215 + unsigned long flags = 0; 1216 + struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1217 + 1218 + spin_lock_irqsave(&ha->hardware_lock, flags); 1219 + ha->interrupts_on = 0; 1220 + /* disable risc and host interrupts */ 1221 + WRT_REG_WORD(&reg->ictrl, 0); 1222 + RD_REG_WORD(&reg->ictrl); 1223 + spin_unlock_irqrestore(&ha->hardware_lock, flags); 1224 + } 1225 + 1226 + static void 1227 + qla24xx_enable_intrs(scsi_qla_host_t *ha) 1228 + { 1229 + unsigned long flags = 0; 1230 + struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1231 + 1232 + spin_lock_irqsave(&ha->hardware_lock, flags); 1233 + ha->interrupts_on = 1; 1234 + WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT); 1235 + RD_REG_DWORD(&reg->ictrl); 1236 + spin_unlock_irqrestore(&ha->hardware_lock, flags); 1237 + } 1238 + 1239 + static void 1240 + qla24xx_disable_intrs(scsi_qla_host_t *ha) 1241 + { 1242 + unsigned long flags = 0; 1243 + struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1244 + 1245 + spin_lock_irqsave(&ha->hardware_lock, flags); 1246 + ha->interrupts_on = 0; 1247 + WRT_REG_DWORD(&reg->ictrl, 0); 1248 + RD_REG_DWORD(&reg->ictrl); 1249 + spin_unlock_irqrestore(&ha->hardware_lock, flags); 1250 + } 1251 + 1252 + static struct isp_operations qla2100_isp_ops = { 1253 + .pci_config = qla2100_pci_config, 1254 + .reset_chip = qla2x00_reset_chip, 1255 + .chip_diag = qla2x00_chip_diag, 1256 + .config_rings = qla2x00_config_rings, 1257 + .reset_adapter = qla2x00_reset_adapter, 1258 + .nvram_config = qla2x00_nvram_config, 1259 + .update_fw_options = qla2x00_update_fw_options, 1260 + .load_risc = qla2x00_load_risc, 1261 + .pci_info_str = qla2x00_pci_info_str, 1262 + .fw_version_str = qla2x00_fw_version_str, 1263 + .intr_handler = qla2100_intr_handler, 1264 + .enable_intrs = qla2x00_enable_intrs, 1265 + .disable_intrs = qla2x00_disable_intrs, 1266 + .abort_command = qla2x00_abort_command, 1267 + .abort_target = qla2x00_abort_target, 1268 + .fabric_login = qla2x00_login_fabric, 1269 + .fabric_logout = qla2x00_fabric_logout, 1270 + .calc_req_entries = qla2x00_calc_iocbs_32, 1271 + .build_iocbs = qla2x00_build_scsi_iocbs_32, 1272 + .prep_ms_iocb = qla2x00_prep_ms_iocb, 1273 + .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1274 + .read_nvram = qla2x00_read_nvram_data, 1275 + .write_nvram = qla2x00_write_nvram_data, 1276 + .fw_dump = qla2100_fw_dump, 1277 + .beacon_on = NULL, 1278 + .beacon_off = NULL, 1279 + .beacon_blink = NULL, 1280 + .read_optrom = qla2x00_read_optrom_data, 1281 + .write_optrom = qla2x00_write_optrom_data, 1282 + .get_flash_version = qla2x00_get_flash_version, 1283 + }; 1284 + 1285 + static struct isp_operations qla2300_isp_ops = { 1286 + .pci_config = qla2300_pci_config, 1287 + .reset_chip = qla2x00_reset_chip, 1288 + .chip_diag = qla2x00_chip_diag, 1289 + .config_rings = qla2x00_config_rings, 1290 + .reset_adapter = qla2x00_reset_adapter, 1291 + .nvram_config = qla2x00_nvram_config, 1292 + .update_fw_options = qla2x00_update_fw_options, 1293 + .load_risc = qla2x00_load_risc, 1294 + .pci_info_str = qla2x00_pci_info_str, 1295 + .fw_version_str = qla2x00_fw_version_str, 1296 + .intr_handler = qla2300_intr_handler, 1297 + .enable_intrs = qla2x00_enable_intrs, 1298 + .disable_intrs = qla2x00_disable_intrs, 1299 + .abort_command = qla2x00_abort_command, 1300 + .abort_target = qla2x00_abort_target, 1301 + .fabric_login = qla2x00_login_fabric, 1302 + .fabric_logout = qla2x00_fabric_logout, 1303 + .calc_req_entries = qla2x00_calc_iocbs_32, 1304 + .build_iocbs = qla2x00_build_scsi_iocbs_32, 1305 + .prep_ms_iocb = qla2x00_prep_ms_iocb, 1306 + .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 1307 + .read_nvram = qla2x00_read_nvram_data, 1308 + .write_nvram = qla2x00_write_nvram_data, 1309 + .fw_dump = qla2300_fw_dump, 1310 + .beacon_on = qla2x00_beacon_on, 1311 + .beacon_off = qla2x00_beacon_off, 1312 + .beacon_blink = qla2x00_beacon_blink, 1313 + .read_optrom = qla2x00_read_optrom_data, 1314 + .write_optrom = qla2x00_write_optrom_data, 1315 + .get_flash_version = qla2x00_get_flash_version, 1316 + }; 1317 + 1318 + static struct isp_operations qla24xx_isp_ops = { 1319 + .pci_config = qla24xx_pci_config, 1320 + .reset_chip = qla24xx_reset_chip, 1321 + .chip_diag = qla24xx_chip_diag, 1322 + .config_rings = qla24xx_config_rings, 1323 + .reset_adapter = qla24xx_reset_adapter, 1324 + .nvram_config = qla24xx_nvram_config, 1325 + .update_fw_options = qla24xx_update_fw_options, 1326 + .load_risc = qla24xx_load_risc, 1327 + .pci_info_str = qla24xx_pci_info_str, 1328 + .fw_version_str = qla24xx_fw_version_str, 1329 + .intr_handler = qla24xx_intr_handler, 1330 + .enable_intrs = qla24xx_enable_intrs, 1331 + .disable_intrs = qla24xx_disable_intrs, 1332 + .abort_command = qla24xx_abort_command, 1333 + .abort_target = qla24xx_abort_target, 1334 + .fabric_login = qla24xx_login_fabric, 1335 + .fabric_logout = qla24xx_fabric_logout, 1336 + .calc_req_entries = NULL, 1337 + .build_iocbs = NULL, 1338 + .prep_ms_iocb = qla24xx_prep_ms_iocb, 1339 + .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1340 + .read_nvram = qla24xx_read_nvram_data, 1341 + .write_nvram = qla24xx_write_nvram_data, 1342 + .fw_dump = qla24xx_fw_dump, 1343 + .beacon_on = qla24xx_beacon_on, 1344 + .beacon_off = qla24xx_beacon_off, 1345 + .beacon_blink = qla24xx_beacon_blink, 1346 + .read_optrom = qla24xx_read_optrom_data, 1347 + .write_optrom = qla24xx_write_optrom_data, 1348 + .get_flash_version = qla24xx_get_flash_version, 1349 + }; 1350 + 1351 + static struct isp_operations qla25xx_isp_ops = { 1352 + .pci_config = qla25xx_pci_config, 1353 + .reset_chip = qla24xx_reset_chip, 1354 + .chip_diag = qla24xx_chip_diag, 1355 + .config_rings = qla24xx_config_rings, 1356 + .reset_adapter = qla24xx_reset_adapter, 1357 + .nvram_config = qla24xx_nvram_config, 1358 + .update_fw_options = qla24xx_update_fw_options, 1359 + .load_risc = qla24xx_load_risc, 1360 + .pci_info_str = qla24xx_pci_info_str, 1361 + .fw_version_str = qla24xx_fw_version_str, 1362 + .intr_handler = qla24xx_intr_handler, 1363 + .enable_intrs = qla24xx_enable_intrs, 1364 + .disable_intrs = qla24xx_disable_intrs, 1365 + .abort_command = qla24xx_abort_command, 1366 + .abort_target = qla24xx_abort_target, 1367 + .fabric_login = qla24xx_login_fabric, 1368 + .fabric_logout = qla24xx_fabric_logout, 1369 + .calc_req_entries = NULL, 1370 + .build_iocbs = NULL, 1371 + .prep_ms_iocb = qla24xx_prep_ms_iocb, 1372 + .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 1373 + .read_nvram = qla25xx_read_nvram_data, 1374 + .write_nvram = qla25xx_write_nvram_data, 1375 + .fw_dump = qla25xx_fw_dump, 1376 + .beacon_on = qla24xx_beacon_on, 1377 + .beacon_off = qla24xx_beacon_off, 1378 + .beacon_blink = qla24xx_beacon_blink, 1379 + .read_optrom = qla24xx_read_optrom_data, 1380 + .write_optrom = qla24xx_write_optrom_data, 1381 + .get_flash_version = qla24xx_get_flash_version, 1382 + }; 1204 1383 1205 1384 static inline void 1206 1385 qla2x00_set_isp_flags(scsi_qla_host_t *ha) ··· 1433 1238 case PCI_DEVICE_ID_QLOGIC_ISP2422: 1434 1239 ha->device_type |= DT_ISP2422; 1435 1240 ha->device_type |= DT_ZIO_SUPPORTED; 1241 + ha->device_type |= DT_FWI2; 1242 + ha->device_type |= DT_IIDMA; 1436 1243 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1437 1244 break; 1438 1245 case PCI_DEVICE_ID_QLOGIC_ISP2432: 1439 1246 ha->device_type |= DT_ISP2432; 1440 1247 ha->device_type |= DT_ZIO_SUPPORTED; 1248 + ha->device_type |= DT_FWI2; 1249 + ha->device_type |= DT_IIDMA; 1441 1250 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1442 1251 break; 1443 1252 case PCI_DEVICE_ID_QLOGIC_ISP5422: 1444 1253 ha->device_type |= DT_ISP5422; 1254 + ha->device_type |= DT_FWI2; 1445 1255 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1446 1256 break; 1447 1257 case PCI_DEVICE_ID_QLOGIC_ISP5432: 1448 1258 ha->device_type |= DT_ISP5432; 1259 + ha->device_type |= DT_FWI2; 1260 + ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1261 + break; 1262 + case PCI_DEVICE_ID_QLOGIC_ISP2532: 1263 + ha->device_type |= DT_ISP2532; 1264 + ha->device_type |= DT_ZIO_SUPPORTED; 1265 + ha->device_type |= DT_FWI2; 1266 + ha->device_type |= DT_IIDMA; 1449 1267 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 1450 1268 break; 1451 1269 } ··· 1531 1323 } 1532 1324 1533 1325 static void 1534 - qla2x00_enable_intrs(scsi_qla_host_t *ha) 1535 - { 1536 - unsigned long flags = 0; 1537 - struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1538 - 1539 - spin_lock_irqsave(&ha->hardware_lock, flags); 1540 - ha->interrupts_on = 1; 1541 - /* enable risc and host interrupts */ 1542 - WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC); 1543 - RD_REG_WORD(&reg->ictrl); 1544 - spin_unlock_irqrestore(&ha->hardware_lock, flags); 1545 - 1546 - } 1547 - 1548 - static void 1549 - qla2x00_disable_intrs(scsi_qla_host_t *ha) 1550 - { 1551 - unsigned long flags = 0; 1552 - struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1553 - 1554 - spin_lock_irqsave(&ha->hardware_lock, flags); 1555 - ha->interrupts_on = 0; 1556 - /* disable risc and host interrupts */ 1557 - WRT_REG_WORD(&reg->ictrl, 0); 1558 - RD_REG_WORD(&reg->ictrl); 1559 - spin_unlock_irqrestore(&ha->hardware_lock, flags); 1560 - } 1561 - 1562 - static void 1563 - qla24xx_enable_intrs(scsi_qla_host_t *ha) 1564 - { 1565 - unsigned long flags = 0; 1566 - struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1567 - 1568 - spin_lock_irqsave(&ha->hardware_lock, flags); 1569 - ha->interrupts_on = 1; 1570 - WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT); 1571 - RD_REG_DWORD(&reg->ictrl); 1572 - spin_unlock_irqrestore(&ha->hardware_lock, flags); 1573 - } 1574 - 1575 - static void 1576 - qla24xx_disable_intrs(scsi_qla_host_t *ha) 1577 - { 1578 - unsigned long flags = 0; 1579 - struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1580 - 1581 - spin_lock_irqsave(&ha->hardware_lock, flags); 1582 - ha->interrupts_on = 0; 1583 - WRT_REG_DWORD(&reg->ictrl, 0); 1584 - RD_REG_DWORD(&reg->ictrl); 1585 - spin_unlock_irqrestore(&ha->hardware_lock, flags); 1586 - } 1587 - 1588 - static void 1589 1326 qla2xxx_scan_start(struct Scsi_Host *shost) 1590 1327 { 1591 1328 scsi_qla_host_t *ha = (scsi_qla_host_t *)shost->hostdata; ··· 1575 1422 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 1576 1423 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 1577 1424 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 1578 - pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432) 1425 + pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 1426 + pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532) 1579 1427 sht = &qla24xx_driver_template; 1580 1428 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 1581 1429 if (host == NULL) { ··· 1620 1466 ha->max_q_depth = ql2xmaxqdepth; 1621 1467 1622 1468 /* Assign ISP specific operations. */ 1623 - ha->isp_ops.pci_config = qla2100_pci_config; 1624 - ha->isp_ops.reset_chip = qla2x00_reset_chip; 1625 - ha->isp_ops.chip_diag = qla2x00_chip_diag; 1626 - ha->isp_ops.config_rings = qla2x00_config_rings; 1627 - ha->isp_ops.reset_adapter = qla2x00_reset_adapter; 1628 - ha->isp_ops.nvram_config = qla2x00_nvram_config; 1629 - ha->isp_ops.update_fw_options = qla2x00_update_fw_options; 1630 - ha->isp_ops.load_risc = qla2x00_load_risc; 1631 - ha->isp_ops.pci_info_str = qla2x00_pci_info_str; 1632 - ha->isp_ops.fw_version_str = qla2x00_fw_version_str; 1633 - ha->isp_ops.intr_handler = qla2100_intr_handler; 1634 - ha->isp_ops.enable_intrs = qla2x00_enable_intrs; 1635 - ha->isp_ops.disable_intrs = qla2x00_disable_intrs; 1636 - ha->isp_ops.abort_command = qla2x00_abort_command; 1637 - ha->isp_ops.abort_target = qla2x00_abort_target; 1638 - ha->isp_ops.fabric_login = qla2x00_login_fabric; 1639 - ha->isp_ops.fabric_logout = qla2x00_fabric_logout; 1640 - ha->isp_ops.calc_req_entries = qla2x00_calc_iocbs_32; 1641 - ha->isp_ops.build_iocbs = qla2x00_build_scsi_iocbs_32; 1642 - ha->isp_ops.prep_ms_iocb = qla2x00_prep_ms_iocb; 1643 - ha->isp_ops.prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb; 1644 - ha->isp_ops.read_nvram = qla2x00_read_nvram_data; 1645 - ha->isp_ops.write_nvram = qla2x00_write_nvram_data; 1646 - ha->isp_ops.fw_dump = qla2100_fw_dump; 1647 - ha->isp_ops.read_optrom = qla2x00_read_optrom_data; 1648 - ha->isp_ops.write_optrom = qla2x00_write_optrom_data; 1649 - ha->isp_ops.get_flash_version = qla2x00_get_flash_version; 1650 1469 if (IS_QLA2100(ha)) { 1651 1470 host->max_id = MAX_TARGETS_2100; 1652 1471 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; ··· 1628 1501 ha->last_loop_id = SNS_LAST_LOOP_ID_2100; 1629 1502 host->sg_tablesize = 32; 1630 1503 ha->gid_list_info_size = 4; 1504 + ha->isp_ops = &qla2100_isp_ops; 1631 1505 } else if (IS_QLA2200(ha)) { 1632 1506 host->max_id = MAX_TARGETS_2200; 1633 1507 ha->mbx_count = MAILBOX_REGISTER_COUNT; ··· 1636 1508 ha->response_q_length = RESPONSE_ENTRY_CNT_2100; 1637 1509 ha->last_loop_id = SNS_LAST_LOOP_ID_2100; 1638 1510 ha->gid_list_info_size = 4; 1511 + ha->isp_ops = &qla2100_isp_ops; 1639 1512 } else if (IS_QLA23XX(ha)) { 1640 1513 host->max_id = MAX_TARGETS_2200; 1641 1514 ha->mbx_count = MAILBOX_REGISTER_COUNT; 1642 1515 ha->request_q_length = REQUEST_ENTRY_CNT_2200; 1643 1516 ha->response_q_length = RESPONSE_ENTRY_CNT_2300; 1644 1517 ha->last_loop_id = SNS_LAST_LOOP_ID_2300; 1645 - ha->isp_ops.pci_config = qla2300_pci_config; 1646 - ha->isp_ops.intr_handler = qla2300_intr_handler; 1647 - ha->isp_ops.fw_dump = qla2300_fw_dump; 1648 - ha->isp_ops.beacon_on = qla2x00_beacon_on; 1649 - ha->isp_ops.beacon_off = qla2x00_beacon_off; 1650 - ha->isp_ops.beacon_blink = qla2x00_beacon_blink; 1651 1518 ha->gid_list_info_size = 6; 1652 1519 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 1653 1520 ha->optrom_size = OPTROM_SIZE_2322; 1521 + ha->isp_ops = &qla2300_isp_ops; 1654 1522 } else if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 1655 1523 host->max_id = MAX_TARGETS_2200; 1656 1524 ha->mbx_count = MAILBOX_REGISTER_COUNT; ··· 1655 1531 ha->last_loop_id = SNS_LAST_LOOP_ID_2300; 1656 1532 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 1657 1533 ha->mgmt_svr_loop_id = 10 + ha->vp_idx; 1658 - ha->isp_ops.pci_config = qla24xx_pci_config; 1659 - ha->isp_ops.reset_chip = qla24xx_reset_chip; 1660 - ha->isp_ops.chip_diag = qla24xx_chip_diag; 1661 - ha->isp_ops.config_rings = qla24xx_config_rings; 1662 - ha->isp_ops.reset_adapter = qla24xx_reset_adapter; 1663 - ha->isp_ops.nvram_config = qla24xx_nvram_config; 1664 - ha->isp_ops.update_fw_options = qla24xx_update_fw_options; 1665 - ha->isp_ops.load_risc = qla24xx_load_risc; 1666 - ha->isp_ops.pci_info_str = qla24xx_pci_info_str; 1667 - ha->isp_ops.fw_version_str = qla24xx_fw_version_str; 1668 - ha->isp_ops.intr_handler = qla24xx_intr_handler; 1669 - ha->isp_ops.enable_intrs = qla24xx_enable_intrs; 1670 - ha->isp_ops.disable_intrs = qla24xx_disable_intrs; 1671 - ha->isp_ops.abort_command = qla24xx_abort_command; 1672 - ha->isp_ops.abort_target = qla24xx_abort_target; 1673 - ha->isp_ops.fabric_login = qla24xx_login_fabric; 1674 - ha->isp_ops.fabric_logout = qla24xx_fabric_logout; 1675 - ha->isp_ops.prep_ms_iocb = qla24xx_prep_ms_iocb; 1676 - ha->isp_ops.prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb; 1677 - ha->isp_ops.read_nvram = qla24xx_read_nvram_data; 1678 - ha->isp_ops.write_nvram = qla24xx_write_nvram_data; 1679 - ha->isp_ops.fw_dump = qla24xx_fw_dump; 1680 - ha->isp_ops.read_optrom = qla24xx_read_optrom_data; 1681 - ha->isp_ops.write_optrom = qla24xx_write_optrom_data; 1682 - ha->isp_ops.beacon_on = qla24xx_beacon_on; 1683 - ha->isp_ops.beacon_off = qla24xx_beacon_off; 1684 - ha->isp_ops.beacon_blink = qla24xx_beacon_blink; 1685 - ha->isp_ops.get_flash_version = qla24xx_get_flash_version; 1686 1534 ha->gid_list_info_size = 8; 1687 1535 ha->optrom_size = OPTROM_SIZE_24XX; 1536 + ha->isp_ops = &qla24xx_isp_ops; 1537 + } else if (IS_QLA25XX(ha)) { 1538 + host->max_id = MAX_TARGETS_2200; 1539 + ha->mbx_count = MAILBOX_REGISTER_COUNT; 1540 + ha->request_q_length = REQUEST_ENTRY_CNT_24XX; 1541 + ha->response_q_length = RESPONSE_ENTRY_CNT_2300; 1542 + ha->last_loop_id = SNS_LAST_LOOP_ID_2300; 1543 + ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 1544 + ha->mgmt_svr_loop_id = 10 + ha->vp_idx; 1545 + ha->gid_list_info_size = 8; 1546 + ha->optrom_size = OPTROM_SIZE_25XX; 1547 + ha->isp_ops = &qla25xx_isp_ops; 1688 1548 } 1689 1549 host->can_queue = ha->request_q_length + 128; 1690 1550 ··· 1736 1628 DEBUG2(printk("DEBUG: detect hba %ld at address = %p\n", 1737 1629 ha->host_no, ha)); 1738 1630 1739 - ha->isp_ops.disable_intrs(ha); 1631 + ha->isp_ops->disable_intrs(ha); 1740 1632 1741 1633 spin_lock_irqsave(&ha->hardware_lock, flags); 1742 1634 reg = ha->iobase; 1743 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 1635 + if (IS_FWI2_CAPABLE(ha)) { 1744 1636 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_CLR_HOST_INT); 1745 1637 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_CLR_RISC_INT); 1746 1638 } else { ··· 1762 1654 } 1763 1655 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1764 1656 1765 - ha->isp_ops.enable_intrs(ha); 1657 + ha->isp_ops->enable_intrs(ha); 1766 1658 1767 1659 pci_set_drvdata(pdev, ha); 1768 1660 ··· 1787 1679 " ISP%04X: %s @ %s hdma%c, host#=%ld, fw=%s\n", 1788 1680 qla2x00_version_str, ha->model_number, 1789 1681 ha->model_desc ? ha->model_desc: "", pdev->device, 1790 - ha->isp_ops.pci_info_str(ha, pci_info), pci_name(pdev), 1682 + ha->isp_ops->pci_info_str(ha, pci_info), pci_name(pdev), 1791 1683 ha->flags.enable_64bit_addressing ? '+': '-', ha->host_no, 1792 - ha->isp_ops.fw_version_str(ha, fw_str)); 1684 + ha->isp_ops->fw_version_str(ha, fw_str)); 1793 1685 1794 1686 return 0; 1795 1687 ··· 1855 1747 1856 1748 /* turn-off interrupts on the card */ 1857 1749 if (ha->interrupts_on) 1858 - ha->isp_ops.disable_intrs(ha); 1750 + ha->isp_ops->disable_intrs(ha); 1859 1751 1860 1752 qla2x00_mem_free(ha); 1861 1753 ··· 2133 2025 } 2134 2026 memset(ha->ct_sns, 0, sizeof(struct ct_sns_pkt)); 2135 2027 2136 - if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 2028 + if (IS_FWI2_CAPABLE(ha)) { 2137 2029 /* 2138 2030 * Get consistent memory allocated for SFP 2139 2031 * block. ··· 2413 2305 if (fcport->flags & FCF_FABRIC_DEVICE) { 2414 2306 if (fcport->flags & 2415 2307 FCF_TAPE_PRESENT) 2416 - ha->isp_ops.fabric_logout( 2308 + ha->isp_ops->fabric_logout( 2417 2309 ha, fcport->loop_id, 2418 2310 fcport->d_id.b.domain, 2419 2311 fcport->d_id.b.area, ··· 2493 2385 } 2494 2386 2495 2387 if (!ha->interrupts_on) 2496 - ha->isp_ops.enable_intrs(ha); 2388 + ha->isp_ops->enable_intrs(ha); 2497 2389 2498 2390 if (test_and_clear_bit(BEACON_BLINK_NEEDED, &ha->dpc_flags)) 2499 - ha->isp_ops.beacon_blink(ha); 2391 + ha->isp_ops->beacon_blink(ha); 2500 2392 2501 2393 qla2x00_do_dpc_all_vps(ha); 2502 2394 ··· 2725 2617 2726 2618 /* Firmware interface routines. */ 2727 2619 2728 - #define FW_BLOBS 5 2620 + #define FW_BLOBS 6 2729 2621 #define FW_ISP21XX 0 2730 2622 #define FW_ISP22XX 1 2731 2623 #define FW_ISP2300 2 2732 2624 #define FW_ISP2322 3 2733 2625 #define FW_ISP24XX 4 2626 + #define FW_ISP25XX 5 2734 2627 2735 2628 #define FW_FILE_ISP21XX "ql2100_fw.bin" 2736 2629 #define FW_FILE_ISP22XX "ql2200_fw.bin" 2737 2630 #define FW_FILE_ISP2300 "ql2300_fw.bin" 2738 2631 #define FW_FILE_ISP2322 "ql2322_fw.bin" 2739 2632 #define FW_FILE_ISP24XX "ql2400_fw.bin" 2633 + #define FW_FILE_ISP25XX "ql2500_fw.bin" 2740 2634 2741 2635 static DECLARE_MUTEX(qla_fw_lock); 2742 2636 ··· 2748 2638 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 2749 2639 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 2750 2640 { .name = FW_FILE_ISP24XX, }, 2641 + { .name = FW_FILE_ISP25XX, }, 2751 2642 }; 2752 2643 2753 2644 struct fw_blob * ··· 2767 2656 blob = &qla_fw_blobs[FW_ISP2322]; 2768 2657 } else if (IS_QLA24XX(ha) || IS_QLA54XX(ha)) { 2769 2658 blob = &qla_fw_blobs[FW_ISP24XX]; 2659 + } else if (IS_QLA25XX(ha)) { 2660 + blob = &qla_fw_blobs[FW_ISP25XX]; 2770 2661 } 2771 2662 2772 2663 down(&qla_fw_lock); ··· 2812 2699 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 2813 2700 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 2814 2701 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 2702 + { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 2815 2703 { 0 }, 2816 2704 }; 2817 2705 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);

+29 -6

drivers/scsi/qla2xxx/qla_sup.c

··· 766 766 return ret; 767 767 } 768 768 769 + uint8_t * 770 + qla25xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 771 + uint32_t bytes) 772 + { 773 + uint32_t i; 774 + uint32_t *dwptr; 775 + 776 + /* Dword reads to flash. */ 777 + dwptr = (uint32_t *)buf; 778 + for (i = 0; i < bytes >> 2; i++, naddr++) 779 + dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 780 + flash_data_to_access_addr(FA_VPD_NVRAM_ADDR | naddr))); 781 + 782 + return buf; 783 + } 784 + 785 + int 786 + qla25xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 787 + uint32_t bytes) 788 + { 789 + return qla24xx_write_flash_data(ha, (uint32_t *)buf, 790 + FA_VPD_NVRAM_ADDR | naddr, bytes >> 2); 791 + } 769 792 770 793 static inline void 771 794 qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags) ··· 942 919 else 943 920 ha->beacon_color_state = QLA_LED_GRN_ON; 944 921 945 - ha->isp_ops.beacon_blink(ha); /* This turns green LED off */ 922 + ha->isp_ops->beacon_blink(ha); /* This turns green LED off */ 946 923 947 924 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 948 925 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; ··· 1054 1031 ha->beacon_blink_led = 0; 1055 1032 ha->beacon_color_state = QLA_LED_ALL_ON; 1056 1033 1057 - ha->isp_ops.beacon_blink(ha); /* Will flip to all off. */ 1034 + ha->isp_ops->beacon_blink(ha); /* Will flip to all off. */ 1058 1035 1059 1036 /* Give control back to firmware. */ 1060 1037 spin_lock_irqsave(&ha->hardware_lock, flags); ··· 1442 1419 1443 1420 /* Suspend HBA. */ 1444 1421 scsi_block_requests(ha->host); 1445 - ha->isp_ops.disable_intrs(ha); 1422 + ha->isp_ops->disable_intrs(ha); 1446 1423 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1447 1424 1448 1425 /* Pause RISC. */ ··· 1728 1705 { 1729 1706 /* Suspend HBA. */ 1730 1707 scsi_block_requests(ha->host); 1731 - ha->isp_ops.disable_intrs(ha); 1708 + ha->isp_ops->disable_intrs(ha); 1732 1709 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1733 1710 1734 1711 /* Go with read. */ ··· 1736 1713 1737 1714 /* Resume HBA. */ 1738 1715 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1739 - ha->isp_ops.enable_intrs(ha); 1716 + ha->isp_ops->enable_intrs(ha); 1740 1717 scsi_unblock_requests(ha->host); 1741 1718 1742 1719 return buf; ··· 1750 1727 1751 1728 /* Suspend HBA. */ 1752 1729 scsi_block_requests(ha->host); 1753 - ha->isp_ops.disable_intrs(ha); 1730 + ha->isp_ops->disable_intrs(ha); 1754 1731 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1755 1732 1756 1733 /* Go with write. */

+1 -1

drivers/scsi/qla2xxx/qla_version.h

··· 7 7 /* 8 8 * Driver version 9 9 */ 10 - #define QLA2XXX_VERSION "8.02.00-k1" 10 + #define QLA2XXX_VERSION "8.02.00-k2" 11 11 12 12 #define QLA_DRIVER_MAJOR_VER 8 13 13 #define QLA_DRIVER_MINOR_VER 2

+1 -1

drivers/scsi/scsi_debug.c

··· 2875 2875 2876 2876 init_all_queued(); 2877 2877 2878 - sdebug_driver_template.proc_name = (char *)sdebug_proc_name; 2878 + sdebug_driver_template.proc_name = sdebug_proc_name; 2879 2879 2880 2880 host_to_add = scsi_debug_add_host; 2881 2881 scsi_debug_add_host = 0;

+1

drivers/scsi/scsi_sysctl.c

··· 9 9 #include <linux/sysctl.h> 10 10 11 11 #include "scsi_logging.h" 12 + #include "scsi_priv.h" 12 13 13 14 14 15 static ctl_table scsi_table[] = {

+15 -1

drivers/scsi/scsi_sysfs.c

··· 16 16 #include <scsi/scsi_host.h> 17 17 #include <scsi/scsi_tcq.h> 18 18 #include <scsi/scsi_transport.h> 19 + #include <scsi/scsi_driver.h> 19 20 20 21 #include "scsi_priv.h" 21 22 #include "scsi_logging.h" ··· 715 714 int scsi_sysfs_add_sdev(struct scsi_device *sdev) 716 715 { 717 716 int error, i; 717 + struct request_queue *rq = sdev->request_queue; 718 718 719 719 if ((error = scsi_device_set_state(sdev, SDEV_RUNNING)) != 0) 720 720 return error; ··· 735 733 /* take a reference for the sdev_classdev; this is 736 734 * released by the sdev_class .release */ 737 735 get_device(&sdev->sdev_gendev); 736 + 737 + error = bsg_register_queue(rq, &sdev->sdev_gendev, NULL); 738 + 739 + if (error) 740 + sdev_printk(KERN_INFO, sdev, 741 + "Failed to register bsg queue, errno=%d\n", error); 742 + 743 + /* we're treating error on bsg register as non-fatal, so pretend 744 + * nothing went wrong */ 745 + error = 0; 746 + 738 747 if (sdev->host->hostt->sdev_attrs) { 739 748 for (i = 0; sdev->host->hostt->sdev_attrs[i]; i++) { 740 749 error = attr_add(&sdev->sdev_gendev, ··· 792 779 if (scsi_device_set_state(sdev, SDEV_CANCEL) != 0) 793 780 return; 794 781 782 + bsg_unregister_queue(sdev->request_queue); 795 783 class_device_unregister(&sdev->sdev_classdev); 796 784 transport_remove_device(dev); 797 785 device_del(dev); ··· 817 803 } 818 804 EXPORT_SYMBOL(scsi_remove_device); 819 805 820 - void __scsi_remove_target(struct scsi_target *starget) 806 + static void __scsi_remove_target(struct scsi_target *starget) 821 807 { 822 808 struct Scsi_Host *shost = dev_to_shost(starget->dev.parent); 823 809 unsigned long flags;

+1 -1

drivers/scsi/scsi_transport_fc.c

··· 2358 2358 * Notes: 2359 2359 * This routine assumes no locks are held on entry. 2360 2360 **/ 2361 - struct fc_rport * 2361 + static struct fc_rport * 2362 2362 fc_rport_create(struct Scsi_Host *shost, int channel, 2363 2363 struct fc_rport_identifiers *ids) 2364 2364 {

+124 -1

drivers/scsi/scsi_transport_sas.c

··· 29 29 #include <linux/err.h> 30 30 #include <linux/slab.h> 31 31 #include <linux/string.h> 32 + #include <linux/blkdev.h> 33 + #include <linux/bsg.h> 32 34 33 35 #include <scsi/scsi.h> 34 36 #include <scsi/scsi_device.h> ··· 42 40 struct sas_host_attrs { 43 41 struct list_head rphy_list; 44 42 struct mutex lock; 43 + struct request_queue *q; 45 44 u32 next_target_id; 46 45 u32 next_expander_id; 47 46 int next_port_id; ··· 155 152 sas_bitfield_name_search(linkspeed, sas_linkspeed_names) 156 153 sas_bitfield_name_set(linkspeed, sas_linkspeed_names) 157 154 155 + static void sas_smp_request(struct request_queue *q, struct Scsi_Host *shost, 156 + struct sas_rphy *rphy) 157 + { 158 + struct request *req; 159 + int ret; 160 + int (*handler)(struct Scsi_Host *, struct sas_rphy *, struct request *); 161 + 162 + while (!blk_queue_plugged(q)) { 163 + req = elv_next_request(q); 164 + if (!req) 165 + break; 166 + 167 + blkdev_dequeue_request(req); 168 + 169 + spin_unlock_irq(q->queue_lock); 170 + 171 + handler = to_sas_internal(shost->transportt)->f->smp_handler; 172 + ret = handler(shost, rphy, req); 173 + 174 + spin_lock_irq(q->queue_lock); 175 + 176 + req->end_io(req, ret); 177 + } 178 + } 179 + 180 + static void sas_host_smp_request(struct request_queue *q) 181 + { 182 + sas_smp_request(q, (struct Scsi_Host *)q->queuedata, NULL); 183 + } 184 + 185 + static void sas_non_host_smp_request(struct request_queue *q) 186 + { 187 + struct sas_rphy *rphy = q->queuedata; 188 + sas_smp_request(q, rphy_to_shost(rphy), rphy); 189 + } 190 + 191 + static int sas_bsg_initialize(struct Scsi_Host *shost, struct sas_rphy *rphy) 192 + { 193 + struct request_queue *q; 194 + int error; 195 + struct device *dev; 196 + char namebuf[BUS_ID_SIZE]; 197 + const char *name; 198 + 199 + if (!to_sas_internal(shost->transportt)->f->smp_handler) { 200 + printk("%s can't handle SMP requests\n", shost->hostt->name); 201 + return 0; 202 + } 203 + 204 + if (rphy) { 205 + q = blk_init_queue(sas_non_host_smp_request, NULL); 206 + dev = &rphy->dev; 207 + name = dev->bus_id; 208 + } else { 209 + q = blk_init_queue(sas_host_smp_request, NULL); 210 + dev = &shost->shost_gendev; 211 + snprintf(namebuf, sizeof(namebuf), 212 + "sas_host%d", shost->host_no); 213 + name = namebuf; 214 + } 215 + if (!q) 216 + return -ENOMEM; 217 + 218 + error = bsg_register_queue(q, dev, name); 219 + if (error) { 220 + blk_cleanup_queue(q); 221 + return -ENOMEM; 222 + } 223 + 224 + if (rphy) 225 + rphy->q = q; 226 + else 227 + to_sas_host_attrs(shost)->q = q; 228 + 229 + if (rphy) 230 + q->queuedata = rphy; 231 + else 232 + q->queuedata = shost; 233 + 234 + set_bit(QUEUE_FLAG_BIDI, &q->queue_flags); 235 + 236 + return 0; 237 + } 238 + 239 + static void sas_bsg_remove(struct Scsi_Host *shost, struct sas_rphy *rphy) 240 + { 241 + struct request_queue *q; 242 + 243 + if (rphy) 244 + q = rphy->q; 245 + else 246 + q = to_sas_host_attrs(shost)->q; 247 + 248 + if (!q) 249 + return; 250 + 251 + bsg_unregister_queue(q); 252 + blk_cleanup_queue(q); 253 + } 254 + 158 255 /* 159 256 * SAS host attributes 160 257 */ ··· 270 167 sas_host->next_target_id = 0; 271 168 sas_host->next_expander_id = 0; 272 169 sas_host->next_port_id = 0; 170 + 171 + if (sas_bsg_initialize(shost, NULL)) 172 + dev_printk(KERN_ERR, dev, "fail to a bsg device %d\n", 173 + shost->host_no); 174 + 175 + return 0; 176 + } 177 + 178 + static int sas_host_remove(struct transport_container *tc, struct device *dev, 179 + struct class_device *cdev) 180 + { 181 + struct Scsi_Host *shost = dev_to_shost(dev); 182 + 183 + sas_bsg_remove(shost, NULL); 184 + 273 185 return 0; 274 186 } 275 187 276 188 static DECLARE_TRANSPORT_CLASS(sas_host_class, 277 - "sas_host", sas_host_setup, NULL, NULL); 189 + "sas_host", sas_host_setup, sas_host_remove, NULL); 278 190 279 191 static int sas_host_match(struct attribute_container *cont, 280 192 struct device *dev) ··· 1405 1287 return error; 1406 1288 transport_add_device(&rphy->dev); 1407 1289 transport_configure_device(&rphy->dev); 1290 + if (sas_bsg_initialize(shost, rphy)) 1291 + printk("fail to a bsg device %s\n", rphy->dev.bus_id); 1292 + 1408 1293 1409 1294 mutex_lock(&sas_host->lock); 1410 1295 list_add_tail(&rphy->list, &sas_host->rphy_list); ··· 1449 1328 mutex_lock(&sas_host->lock); 1450 1329 list_del(&rphy->list); 1451 1330 mutex_unlock(&sas_host->lock); 1331 + 1332 + sas_bsg_remove(shost, rphy); 1452 1333 1453 1334 transport_destroy_device(dev); 1454 1335

+1 -1

drivers/scsi/seagate.c

··· 420 420 #define ULOOP( i ) for (clock = i*8;;) 421 421 #define TIMEOUT (!(clock--)) 422 422 423 - int __init seagate_st0x_detect (struct scsi_host_template * tpnt) 423 + static int __init seagate_st0x_detect (struct scsi_host_template * tpnt) 424 424 { 425 425 struct Scsi_Host *instance; 426 426 int i, j;

+2 -1

drivers/scsi/sim710.c

··· 138 138 goto out_put_host; 139 139 } 140 140 141 + dev_set_drvdata(dev, host); 141 142 scsi_scan_host(host); 142 143 143 144 return 0; ··· 156 155 static __devexit int 157 156 sim710_device_remove(struct device *dev) 158 157 { 159 - struct Scsi_Host *host = dev_to_shost(dev); 158 + struct Scsi_Host *host = dev_get_drvdata(dev); 160 159 struct NCR_700_Host_Parameters *hostdata = 161 160 (struct NCR_700_Host_Parameters *)host->hostdata[0]; 162 161

+1 -1

drivers/scsi/sr.c

··· 175 175 * an inode for that to work, and we do not always have one. 176 176 */ 177 177 178 - int sr_media_change(struct cdrom_device_info *cdi, int slot) 178 + static int sr_media_change(struct cdrom_device_info *cdi, int slot) 179 179 { 180 180 struct scsi_cd *cd = cdi->handle; 181 181 int retval;

+3 -1

drivers/scsi/wd33c93.c

··· 89 89 #include <scsi/scsi_device.h> 90 90 #include <scsi/scsi_host.h> 91 91 92 + #include <asm/irq.h> 93 + 92 94 #include "wd33c93.h" 93 95 94 96 #define optimum_sx_per(hostdata) (hostdata)->sx_table[1].period_ns ··· 1764 1762 static char setup_used[MAX_SETUP_ARGS]; 1765 1763 static int done_setup = 0; 1766 1764 1767 - int 1765 + static int 1768 1766 wd33c93_setup(char *str) 1769 1767 { 1770 1768 int i;

+2 -1

drivers/scsi/zorro7xx.c

··· 130 130 goto out_put_host; 131 131 } 132 132 133 + zorro_set_drvdata(z, host); 133 134 scsi_scan_host(host); 134 135 135 136 return 0; ··· 149 148 150 149 static __devexit void zorro7xx_remove_one(struct zorro_dev *z) 151 150 { 152 - struct Scsi_Host *host = dev_to_shost(&z->dev); 151 + struct Scsi_Host *host = zorro_get_drvdata(z); 153 152 struct NCR_700_Host_Parameters *hostdata = shost_priv(host); 154 153 155 154 scsi_remove_host(host);

-5

include/linux/blkdev.h

··· 698 698 struct request *, int); 699 699 extern void blk_execute_rq_nowait(request_queue_t *, struct gendisk *, 700 700 struct request *, int, rq_end_io_fn *); 701 - extern int blk_fill_sghdr_rq(request_queue_t *, struct request *, 702 - struct sg_io_hdr *, int); 703 - extern int blk_unmap_sghdr_rq(struct request *, struct sg_io_hdr *); 704 - extern int blk_complete_sghdr_rq(struct request *, struct sg_io_hdr *, 705 - struct bio *); 706 701 extern int blk_verify_command(unsigned char *, int); 707 702 708 703 static inline request_queue_t *bdev_get_queue(struct block_device *bdev)

+2 -2

include/linux/bsg.h

··· 57 57 struct request_queue *queue; 58 58 }; 59 59 60 - extern int bsg_register_queue(struct request_queue *, const char *); 60 + extern int bsg_register_queue(struct request_queue *, struct device *, const char *); 61 61 extern void bsg_unregister_queue(struct request_queue *); 62 62 #else 63 - #define bsg_register_queue(disk, name) (0) 63 + #define bsg_register_queue(disk, dev, name) (0) 64 64 #define bsg_unregister_queue(disk) do { } while (0) 65 65 #endif 66 66

+1

include/linux/libata.h

··· 412 412 ata_qc_cb_t complete_fn; 413 413 414 414 void *private_data; 415 + void *lldd_task; 415 416 }; 416 417 417 418 struct ata_port_stats {

+2

include/linux/pci_ids.h

··· 2019 2019 2020 2020 #define PCI_VENDOR_ID_ARIMA 0x161f 2021 2021 2022 + #define PCI_VENDOR_ID_BROCADE 0x1657 2023 + 2022 2024 #define PCI_VENDOR_ID_SIBYTE 0x166d 2023 2025 #define PCI_DEVICE_ID_BCM1250_PCI 0x0001 2024 2026 #define PCI_DEVICE_ID_BCM1250_HT 0x0002

+15

include/scsi/libsas.h

··· 30 30 #include <linux/timer.h> 31 31 #include <linux/pci.h> 32 32 #include <scsi/sas.h> 33 + #include <linux/libata.h> 33 34 #include <linux/list.h> 34 35 #include <asm/semaphore.h> 35 36 #include <scsi/scsi_device.h> ··· 166 165 167 166 u8 port_no; /* port number, if this is a PM (Port) */ 168 167 struct list_head children; /* PM Ports if this is a PM */ 168 + 169 + struct ata_port *ap; 170 + struct ata_host ata_host; 171 + struct ata_taskfile tf; 172 + u32 sstatus; 173 + u32 serror; 174 + u32 scontrol; 169 175 }; 170 176 171 177 /* ---------- Domain device ---------- */ ··· 632 624 struct sas_phy_linkrates *rates); 633 625 int sas_phy_enable(struct sas_phy *phy, int enabled); 634 626 int sas_phy_reset(struct sas_phy *phy, int hard_reset); 627 + int sas_queue_up(struct sas_task *task); 635 628 extern int sas_queuecommand(struct scsi_cmnd *, 636 629 void (*scsi_done)(struct scsi_cmnd *)); 637 630 extern int sas_target_alloc(struct scsi_target *); ··· 670 661 int sas_eh_device_reset_handler(struct scsi_cmnd *cmd); 671 662 int sas_eh_bus_reset_handler(struct scsi_cmnd *cmd); 672 663 664 + extern void sas_target_destroy(struct scsi_target *); 665 + extern int sas_slave_alloc(struct scsi_device *); 666 + extern int sas_ioctl(struct scsi_device *sdev, int cmd, void __user *arg); 667 + 668 + extern int sas_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy, 669 + struct request *req); 673 670 #endif /* _SASLIB_H_ */

+60

include/scsi/sas_ata.h

··· 1 + /* 2 + * Support for SATA devices on Serial Attached SCSI (SAS) controllers 3 + * 4 + * Copyright (C) 2006 IBM Corporation 5 + * 6 + * Written by: Darrick J. Wong <djwong@us.ibm.com>, IBM Corporation 7 + * 8 + * This program is free software; you can redistribute it and/or 9 + * modify it under the terms of the GNU General Public License as 10 + * published by the Free Software Foundation; either version 2 of the 11 + * License, or (at your option) any later version. 12 + * 13 + * This program is distributed in the hope that it will be useful, but 14 + * WITHOUT ANY WARRANTY; without even the implied warranty of 15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 + * General Public License for more details. 17 + * 18 + * You should have received a copy of the GNU General Public License 19 + * along with this program; if not, write to the Free Software 20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 21 + * USA 22 + * 23 + */ 24 + 25 + #ifndef _SAS_ATA_H_ 26 + #define _SAS_ATA_H_ 27 + 28 + #include <linux/libata.h> 29 + #include <scsi/libsas.h> 30 + 31 + #ifdef CONFIG_SCSI_SAS_ATA 32 + 33 + static inline int dev_is_sata(struct domain_device *dev) 34 + { 35 + return (dev->rphy->identify.target_port_protocols & SAS_PROTOCOL_SATA); 36 + } 37 + 38 + int sas_ata_init_host_and_port(struct domain_device *found_dev, 39 + struct scsi_target *starget); 40 + 41 + void sas_ata_task_abort(struct sas_task *task); 42 + 43 + #else 44 + 45 + 46 + static inline int dev_is_sata(struct domain_device *dev) 47 + { 48 + return 0; 49 + } 50 + int sas_ata_init_host_and_port(struct domain_device *found_dev, 51 + struct scsi_target *starget) 52 + { 53 + return 0; 54 + } 55 + void sas_ata_task_abort(struct sas_task *task) 56 + { 57 + } 58 + #endif 59 + 60 + #endif /* _SAS_ATA_H_ */

+1 -1

include/scsi/scsi_host.h

··· 341 341 /* 342 342 * Name of proc directory 343 343 */ 344 - char *proc_name; 344 + const char *proc_name; 345 345 346 346 /* 347 347 * Used to store the procfs directory if a driver implements the

+10 -1

include/scsi/scsi_transport_sas.h

··· 7 7 8 8 struct scsi_transport_template; 9 9 struct sas_rphy; 10 - 10 + struct request; 11 11 12 12 enum sas_device_type { 13 13 SAS_PHY_UNUSED, ··· 22 22 SAS_PROTOCOL_STP = 0x04, 23 23 SAS_PROTOCOL_SSP = 0x08, 24 24 }; 25 + 26 + static inline int sas_protocol_ata(enum sas_protocol proto) 27 + { 28 + return ((proto & SAS_PROTOCOL_SATA) || 29 + (proto & SAS_PROTOCOL_STP))? 1 : 0; 30 + } 25 31 26 32 enum sas_linkrate { 27 33 /* These Values are defined in the SAS standard */ ··· 91 85 #define phy_to_shost(phy) \ 92 86 dev_to_shost((phy)->dev.parent) 93 87 88 + struct request_queue; 94 89 struct sas_rphy { 95 90 struct device dev; 96 91 struct sas_identify identify; 97 92 struct list_head list; 93 + struct request_queue *q; 98 94 u32 scsi_target_id; 99 95 }; 100 96 ··· 174 166 int (*phy_reset)(struct sas_phy *, int); 175 167 int (*phy_enable)(struct sas_phy *, int); 176 168 int (*set_phy_speed)(struct sas_phy *, struct sas_phy_linkrates *); 169 + int (*smp_handler)(struct Scsi_Host *, struct sas_rphy *, struct request *); 177 170 }; 178 171 179 172

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