RDMA/bnxt_re: Add support for QP rate limiting

+11 -1

drivers/infiniband/hw/bnxt_re/ib_verbs.c

··· 2089 2089 unsigned int flags; 2090 2090 u8 nw_type; 2091 2091 2092 - if (qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS) 2092 + if (qp_attr_mask & ~(IB_QP_ATTR_STANDARD_BITS | IB_QP_RATE_LIMIT)) 2093 2093 return -EOPNOTSUPP; 2094 2094 2095 2095 qp->qplib_qp.modify_flags = 0; 2096 + qp->qplib_qp.ext_modify_flags = 0; 2096 2097 if (qp_attr_mask & IB_QP_STATE) { 2097 2098 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 2098 2099 new_qp_state = qp_attr->qp_state; ··· 2129 2128 bnxt_qplib_clean_qp(&qp->qplib_qp); 2130 2129 bnxt_re_unlock_cqs(qp, flags); 2131 2130 } 2131 + } 2132 + 2133 + if (qp_attr_mask & IB_QP_RATE_LIMIT) { 2134 + if (qp->qplib_qp.type != IB_QPT_RC || 2135 + !_is_modify_qp_rate_limit_supported(dev_attr->dev_cap_flags2)) 2136 + return -EOPNOTSUPP; 2137 + qp->qplib_qp.ext_modify_flags |= 2138 + CMDQ_MODIFY_QP_EXT_MODIFY_MASK_RATE_LIMIT_VALID; 2139 + qp->qplib_qp.rate_limit = qp_attr->rate_limit; 2132 2140 } 2133 2141 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 2134 2142 qp->qplib_qp.modify_flags |=

+11 -1

drivers/infiniband/hw/bnxt_re/qplib_fp.c

··· 1313 1313 struct bnxt_qplib_cmdqmsg msg = {}; 1314 1314 struct cmdq_modify_qp req = {}; 1315 1315 u16 vlan_pcp_vlan_dei_vlan_id; 1316 + u32 bmask, bmask_ext; 1316 1317 u32 temp32[4]; 1317 - u32 bmask; 1318 1318 int rc; 1319 1319 1320 1320 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, ··· 1329 1329 is_optimized_state_transition(qp)) 1330 1330 bnxt_set_mandatory_attributes(res, qp, &req); 1331 1331 } 1332 + 1332 1333 bmask = qp->modify_flags; 1333 1334 req.modify_mask = cpu_to_le32(qp->modify_flags); 1335 + bmask_ext = qp->ext_modify_flags; 1336 + req.ext_modify_mask = cpu_to_le32(qp->ext_modify_flags); 1334 1337 req.qp_cid = cpu_to_le32(qp->id); 1338 + 1339 + if (bmask_ext & CMDQ_MODIFY_QP_EXT_MODIFY_MASK_RATE_LIMIT_VALID) 1340 + req.rate_limit = cpu_to_le32(qp->rate_limit); 1341 + 1335 1342 if (bmask & CMDQ_MODIFY_QP_MODIFY_MASK_STATE) { 1336 1343 req.network_type_en_sqd_async_notify_new_state = 1337 1344 (qp->state & CMDQ_MODIFY_QP_NEW_STATE_MASK) | ··· 1436 1429 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 1437 1430 if (rc) 1438 1431 return rc; 1432 + 1433 + if (bmask_ext & CMDQ_MODIFY_QP_EXT_MODIFY_MASK_RATE_LIMIT_VALID) 1434 + qp->shaper_allocation_status = resp.shaper_allocation_status; 1439 1435 qp->cur_qp_state = qp->state; 1440 1436 return 0; 1441 1437 }

+3

drivers/infiniband/hw/bnxt_re/qplib_fp.h

··· 280 280 u8 state; 281 281 u8 cur_qp_state; 282 282 u64 modify_flags; 283 + u32 ext_modify_flags; 283 284 u32 max_inline_data; 284 285 u32 mtu; 285 286 u8 path_mtu; ··· 347 346 bool is_host_msn_tbl; 348 347 u8 tos_dscp; 349 348 u32 ugid_index; 349 + u32 rate_limit; 350 + u8 shaper_allocation_status; 350 351 }; 351 352 352 353 #define BNXT_RE_MAX_MSG_SIZE 0x80000000

+6

drivers/infiniband/hw/bnxt_re/qplib_res.h

··· 623 623 return !!(dev_cap_ext_flags_2 & CREQ_QUERY_FUNC_RESP_SB_MAX_SRQ_EXTENDED); 624 624 } 625 625 626 + static inline bool _is_modify_qp_rate_limit_supported(u16 dev_cap_ext_flags2) 627 + { 628 + return dev_cap_ext_flags2 & 629 + CREQ_QUERY_FUNC_RESP_SB_MODIFY_QP_RATE_LIMIT_SUPPORTED; 630 + } 631 + 626 632 #endif /* __BNXT_QPLIB_RES_H__ */

+5

drivers/infiniband/hw/bnxt_re/qplib_sp.c

··· 193 193 attr->max_dpi = le32_to_cpu(sb->max_dpi); 194 194 195 195 attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw); 196 + 197 + if (_is_modify_qp_rate_limit_supported(attr->dev_cap_flags2)) { 198 + attr->rate_limit_min = le16_to_cpu(sb->rate_limit_min); 199 + attr->rate_limit_max = le32_to_cpu(sb->rate_limit_max); 200 + } 196 201 bail: 197 202 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 198 203 sbuf.sb, sbuf.dma_addr);

+2

drivers/infiniband/hw/bnxt_re/qplib_sp.h

··· 76 76 u16 dev_cap_flags; 77 77 u16 dev_cap_flags2; 78 78 u32 max_dpi; 79 + u16 rate_limit_min; 80 + u32 rate_limit_max; 79 81 }; 80 82 81 83 struct bnxt_qplib_pd {

+9 -4

drivers/infiniband/hw/bnxt_re/roce_hsi.h

··· 690 690 __le32 ext_modify_mask; 691 691 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX 0x1UL 692 692 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID 0x2UL 693 + #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_RATE_LIMIT_VALID 0x8UL 693 694 __le32 ext_stats_ctx_id; 694 695 __le16 schq_id; 695 696 __le16 unused_0; 696 - __le32 reserved32; 697 + __le32 rate_limit; 697 698 }; 698 699 699 700 /* creq_modify_qp_resp (size:128b/16B) */ ··· 717 716 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK 0xeUL 718 717 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_SFT 1 719 718 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE 0x10UL 720 - u8 reserved8; 719 + u8 shaper_allocation_status; 720 + #define CREQ_MODIFY_QP_RESP_SHAPER_ALLOCATED 0x1UL 721 721 __le32 lag_src_mac; 722 722 }; 723 723 ··· 2181 2179 u8 reserved48[6]; 2182 2180 }; 2183 2181 2184 - /* creq_query_func_resp_sb (size:1088b/136B) */ 2182 + /* creq_query_func_resp_sb (size:1280b/160B) */ 2185 2183 struct creq_query_func_resp_sb { 2186 2184 u8 opcode; 2187 2185 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 0x83UL ··· 2258 2256 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_LAST \ 2259 2257 CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE 2260 2258 #define CREQ_QUERY_FUNC_RESP_SB_MAX_SRQ_EXTENDED 0x40UL 2259 + #define CREQ_QUERY_FUNC_RESP_SB_MODIFY_QP_RATE_LIMIT_SUPPORTED 0x400UL 2261 2260 #define CREQ_QUERY_FUNC_RESP_SB_MIN_RNR_RTR_RTS_OPT_SUPPORTED 0x1000UL 2262 2261 __le16 max_xp_qp_size; 2263 2262 __le16 create_qp_batch_size; 2264 2263 __le16 destroy_qp_batch_size; 2265 2264 __le16 max_srq_ext; 2266 - __le64 reserved64; 2265 + __le16 reserved16; 2266 + __le16 rate_limit_min; 2267 + __le32 rate_limit_max; 2267 2268 }; 2268 2269 2269 2270 /* cmdq_set_func_resources (size:448b/56B) */

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