Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'spi-fix-v7.0-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"A couple of changes here, one update to MAINTAINERS for the AMD
controller and a chnage from Pei Xiao which in spite of the changelog
is actually a fix - previously the zynq-qspi driver leaked a clock
enable for every flash operation it did which isn't good, these extra
enables were removed when doing the enable cleanup which are probably
a good idea anyway"
* tag 'spi-fix-v7.0-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
MAINTAINERS: Update AMD SPI driver maintainers
spi: zynq-qspi: Simplify clock handling with devm_clk_get_enabled()
+7
-36
+1
MAINTAINERS
+1
MAINTAINERS
+6
-36
drivers/spi/spi-zynq-qspi.c
+6
-36
drivers/spi/spi-zynq-qspi.c
···
381
381
{
382
382
struct spi_controller *ctlr = spi->controller;
383
383
struct zynq_qspi *qspi = spi_controller_get_devdata(ctlr);
384
-
int ret;
385
384
386
385
if (ctlr->busy)
387
386
return -EBUSY;
388
-
389
-
ret = clk_enable(qspi->refclk);
390
-
if (ret)
391
-
return ret;
392
-
393
-
ret = clk_enable(qspi->pclk);
394
-
if (ret) {
395
-
clk_disable(qspi->refclk);
396
-
return ret;
397
-
}
398
387
399
388
zynq_qspi_write(qspi, ZYNQ_QSPI_ENABLE_OFFSET,
400
389
ZYNQ_QSPI_ENABLE_ENABLE_MASK);
···
650
661
goto remove_ctlr;
651
662
}
652
663
653
-
xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
664
+
xqspi->pclk = devm_clk_get_enabled(&pdev->dev, "pclk");
654
665
if (IS_ERR(xqspi->pclk)) {
655
666
dev_err(&pdev->dev, "pclk clock not found.\n");
656
667
ret = PTR_ERR(xqspi->pclk);
···
659
670
660
671
init_completion(&xqspi->data_completion);
661
672
662
-
xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
673
+
xqspi->refclk = devm_clk_get_enabled(&pdev->dev, "ref_clk");
663
674
if (IS_ERR(xqspi->refclk)) {
664
675
dev_err(&pdev->dev, "ref_clk clock not found.\n");
665
676
ret = PTR_ERR(xqspi->refclk);
666
677
goto remove_ctlr;
667
678
}
668
679
669
-
ret = clk_prepare_enable(xqspi->pclk);
670
-
if (ret) {
671
-
dev_err(&pdev->dev, "Unable to enable APB clock.\n");
672
-
goto remove_ctlr;
673
-
}
674
-
675
-
ret = clk_prepare_enable(xqspi->refclk);
676
-
if (ret) {
677
-
dev_err(&pdev->dev, "Unable to enable device clock.\n");
678
-
goto clk_dis_pclk;
679
-
}
680
-
681
680
xqspi->irq = platform_get_irq(pdev, 0);
682
681
if (xqspi->irq < 0) {
683
682
ret = xqspi->irq;
684
-
goto clk_dis_all;
683
+
goto remove_ctlr;
685
684
}
686
685
ret = devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq,
687
686
0, pdev->name, xqspi);
688
687
if (ret != 0) {
689
688
ret = -ENXIO;
690
689
dev_err(&pdev->dev, "request_irq failed\n");
691
-
goto clk_dis_all;
690
+
goto remove_ctlr;
692
691
}
693
692
694
693
ret = of_property_read_u32(np, "num-cs",
···
686
709
} else if (num_cs > ZYNQ_QSPI_MAX_NUM_CS) {
687
710
ret = -EINVAL;
688
711
dev_err(&pdev->dev, "only 2 chip selects are available\n");
689
-
goto clk_dis_all;
712
+
goto remove_ctlr;
690
713
} else {
691
714
ctlr->num_chipselect = num_cs;
692
715
}
···
705
728
ret = devm_spi_register_controller(&pdev->dev, ctlr);
706
729
if (ret) {
707
730
dev_err(&pdev->dev, "devm_spi_register_controller failed\n");
708
-
goto clk_dis_all;
731
+
goto remove_ctlr;
709
732
}
710
733
711
734
return ret;
712
735
713
-
clk_dis_all:
714
-
clk_disable_unprepare(xqspi->refclk);
715
-
clk_dis_pclk:
716
-
clk_disable_unprepare(xqspi->pclk);
717
736
remove_ctlr:
718
737
spi_controller_put(ctlr);
719
738
···
731
758
struct zynq_qspi *xqspi = platform_get_drvdata(pdev);
732
759
733
760
zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);
734
-
735
-
clk_disable_unprepare(xqspi->refclk);
736
-
clk_disable_unprepare(xqspi->pclk);
737
761
}
738
762
739
763
static const struct of_device_id zynq_qspi_of_match[] = {