Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm-fixes-6.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Arnd Bergmann:
"As usual, most of the bug fixes address issues in the devicetree
files, and out of these, most are for the Qualcomm and NXP platforms,
including:
- A missing 'reserved-memory' property on LG G Watch R that is needed
to prevent clashing with firmware
- Annotations for cache coherency on multiple machines
- Corrections for pinctrl, regulator, clock, iommu and power domain
properties for i.MX and Qualcomm to correctly reflect the hardware
settings
- Firmware file names on multiple machines SA8540P Ride board
- An incompatible change to the qcom vadc driver requires adding
individual labels
- Fix EQoS PHY reset GPIO by dropping the deprecated/wrong property
and switch to the new bindings.
- A fix for PCI bus address translation Tegra194 and Tegra234.
There are also a couple of device driver fixes, addressing:
- A race condition in the amdtee driver
- A performance regression in the Qualcomm 'llcc' driver
- An unitialized variable use NXP i.MX 'weim' driver
- Error handling issues in Qualcomm 'rmtfs', and 'scm' drivers and
the Arm scmi firmware driver"
* tag 'arm-fixes-6.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (48 commits)
arm64: dts: qcom: sc8280xp-x13s: mark bob regulator as always-on
arm64: dts: qcom: sc8280xp-x13s: mark s12b regulator as always-on
arm64: dts: qcom: sc8280xp-x13s: mark s10b regulator as always-on
arm64: dts: qcom: sc8280xp-x13s: mark s11b regulator as always-on
arm64: dts: imx93: add missing #address-cells and #size-cells to i2c nodes
bus: imx-weim: fix branch condition evaluates to a garbage value
arm64: dts: imx8mn: specify #sound-dai-cells for SAI nodes
ARM: dts: imx6sl: tolino-shine2hd: fix usbotg1 pinctrl
ARM: dts: imx6sll: e60k02: fix usbotg1 pinctrl
ARM: dts: imx6sll: e70k02: fix usbotg1 pinctrl
arm64: dts: imx93: Fix eqos properties
arm64: dts: imx8mp: Fix LCDIF2 node clock order
arm64: dts: imx8mm-nitrogen-r2: fix WM8960 clock name
arm64: dts: imx8dxl-evk: Fix eqos phy reset gpio
firmware: qcom: scm: fix bogus irq error at probe
arm64: dts: qcom: sm8550: Mark UFS controller as cache coherent
arm64: dts: qcom: sa8540p-ride: correct name of remoteproc_nsp0 firmware
arm64: dts: qcom: sm8450: Mark UFS controller as cache coherent
arm64: dts: qcom: sm8350: Mark UFS controller as cache coherent
arm64: dts: qcom: sm8550: fix LPASS pinctrl slew base address
...
+212
-145
+1
arch/arm/boot/dts/e60k02.dtsi
+1
arch/arm/boot/dts/e60k02.dtsi
+1
arch/arm/boot/dts/e70k02.dtsi
+1
arch/arm/boot/dts/e70k02.dtsi
+1
arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts
+1
arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts
+10
arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts
+10
arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts
···
27
27
};
28
28
29
29
reserved-memory {
30
+
sbl_region: sbl@2f00000 {
31
+
reg = <0x02f00000 0x100000>;
32
+
no-map;
33
+
};
34
+
35
+
external_image_region: external-image@3100000 {
36
+
reg = <0x03100000 0x200000>;
37
+
no-map;
38
+
};
39
+
30
40
adsp_region: adsp@3300000 {
31
41
reg = <0x03300000 0x1400000>;
32
42
no-map;
-12
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts
-12
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts
···
56
56
};
57
57
58
58
&enetc_port2 {
59
-
nvmem-cells = <&base_mac_address 2>;
60
-
nvmem-cell-names = "mac-address";
61
59
status = "okay";
62
60
};
63
61
64
62
&enetc_port3 {
65
-
nvmem-cells = <&base_mac_address 3>;
66
-
nvmem-cell-names = "mac-address";
67
63
status = "okay";
68
64
};
69
65
···
80
84
managed = "in-band-status";
81
85
phy-handle = <&qsgmii_phy0>;
82
86
phy-mode = "qsgmii";
83
-
nvmem-cells = <&base_mac_address 4>;
84
-
nvmem-cell-names = "mac-address";
85
87
status = "okay";
86
88
};
87
89
···
88
94
managed = "in-band-status";
89
95
phy-handle = <&qsgmii_phy1>;
90
96
phy-mode = "qsgmii";
91
-
nvmem-cells = <&base_mac_address 5>;
92
-
nvmem-cell-names = "mac-address";
93
97
status = "okay";
94
98
};
95
99
···
96
104
managed = "in-band-status";
97
105
phy-handle = <&qsgmii_phy2>;
98
106
phy-mode = "qsgmii";
99
-
nvmem-cells = <&base_mac_address 6>;
100
-
nvmem-cell-names = "mac-address";
101
107
status = "okay";
102
108
};
103
109
···
104
114
managed = "in-band-status";
105
115
phy-handle = <&qsgmii_phy3>;
106
116
phy-mode = "qsgmii";
107
-
nvmem-cells = <&base_mac_address 7>;
108
-
nvmem-cell-names = "mac-address";
109
117
status = "okay";
110
118
};
111
119
-2
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
-2
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
-8
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts
-8
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts
···
36
36
};
37
37
38
38
&enetc_port2 {
39
-
nvmem-cells = <&base_mac_address 2>;
40
-
nvmem-cell-names = "mac-address";
41
39
status = "okay";
42
40
};
43
41
44
42
&enetc_port3 {
45
-
nvmem-cells = <&base_mac_address 3>;
46
-
nvmem-cell-names = "mac-address";
47
43
status = "okay";
48
44
};
49
45
···
52
56
managed = "in-band-status";
53
57
phy-handle = <&phy0>;
54
58
phy-mode = "sgmii";
55
-
nvmem-cells = <&base_mac_address 0>;
56
-
nvmem-cell-names = "mac-address";
57
59
status = "okay";
58
60
};
59
61
···
60
66
managed = "in-band-status";
61
67
phy-handle = <&phy1>;
62
68
phy-mode = "sgmii";
63
-
nvmem-cells = <&base_mac_address 1>;
64
-
nvmem-cell-names = "mac-address";
65
69
status = "okay";
66
70
};
67
71
-2
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
-2
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
-17
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
-17
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
···
92
92
phy-handle = <&phy0>;
93
93
phy-mode = "sgmii";
94
94
managed = "in-band-status";
95
-
nvmem-cells = <&base_mac_address 0>;
96
-
nvmem-cell-names = "mac-address";
97
95
status = "okay";
98
96
};
99
97
···
152
154
partition@3e0000 {
153
155
reg = <0x3e0000 0x020000>;
154
156
label = "bootloader environment";
155
-
};
156
-
};
157
-
158
-
otp-1 {
159
-
compatible = "user-otp";
160
-
161
-
nvmem-layout {
162
-
compatible = "kontron,sl28-vpd";
163
-
164
-
serial_number: serial-number {
165
-
};
166
-
167
-
base_mac_address: base-mac-address {
168
-
#nvmem-cell-cells = <1>;
169
-
};
170
157
};
171
158
};
172
159
};
+1
-1
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
···
117
117
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
118
118
clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>,
119
119
<&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>;
120
-
clock-names = "fspi", "fspi_en";
120
+
clock-names = "fspi_en", "fspi";
121
121
power-domains = <&pd IMX_SC_R_FSPI_0>;
122
122
status = "disabled";
123
123
};
+3
-2
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+3
-2
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
···
121
121
phy-handle = <ðphy0>;
122
122
nvmem-cells = <&fec_mac1>;
123
123
nvmem-cell-names = "mac-address";
124
-
snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
125
-
snps,reset-delays-us = <10 20 200000>;
126
124
status = "okay";
127
125
128
126
mdio {
···
134
136
eee-broken-1000t;
135
137
qca,disable-smarteee;
136
138
qca,disable-hibernation-mode;
139
+
reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
140
+
reset-assert-us = <20>;
141
+
reset-deassert-us = <200000>;
137
142
vddio-supply = <&vddio0>;
138
143
139
144
vddio0: vddio-regulator {
+1
-1
arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
+5
arch/arm64/boot/dts/freescale/imx8mn.dtsi
+5
arch/arm64/boot/dts/freescale/imx8mn.dtsi
···
296
296
sai2: sai@30020000 {
297
297
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
298
298
reg = <0x30020000 0x10000>;
299
+
#sound-dai-cells = <0>;
299
300
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
300
301
clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
301
302
<&clk IMX8MN_CLK_DUMMY>,
···
311
310
sai3: sai@30030000 {
312
311
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
313
312
reg = <0x30030000 0x10000>;
313
+
#sound-dai-cells = <0>;
314
314
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
315
315
clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
316
316
<&clk IMX8MN_CLK_DUMMY>,
···
326
324
sai5: sai@30050000 {
327
325
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
328
326
reg = <0x30050000 0x10000>;
327
+
#sound-dai-cells = <0>;
329
328
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
330
329
clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
331
330
<&clk IMX8MN_CLK_DUMMY>,
···
343
340
sai6: sai@30060000 {
344
341
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
345
342
reg = <0x30060000 0x10000>;
343
+
#sound-dai-cells = <0>;
346
344
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
347
345
clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
348
346
<&clk IMX8MN_CLK_DUMMY>,
···
401
397
sai7: sai@300b0000 {
402
398
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
403
399
reg = <0x300b0000 0x10000>;
400
+
#sound-dai-cells = <0>;
404
401
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
405
402
clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
406
403
<&clk IMX8MN_CLK_DUMMY>,
+2
-2
arch/arm64/boot/dts/freescale/imx8mp.dtsi
+2
-2
arch/arm64/boot/dts/freescale/imx8mp.dtsi
···
1131
1131
reg = <0x32e90000 0x238>;
1132
1132
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1133
1133
clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1134
-
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1135
-
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1134
+
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1135
+
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1136
1136
clock-names = "pix", "axi", "disp_axi";
1137
1137
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
1138
1138
<&clk IMX8MP_VIDEO_PLL1>;
+20
-4
arch/arm64/boot/dts/freescale/imx93.dtsi
+20
-4
arch/arm64/boot/dts/freescale/imx93.dtsi
···
164
164
lpi2c1: i2c@44340000 {
165
165
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
166
166
reg = <0x44340000 0x10000>;
167
+
#address-cells = <1>;
168
+
#size-cells = <0>;
167
169
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
168
170
clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
169
171
<&clk IMX93_CLK_BUS_AON>;
···
176
174
lpi2c2: i2c@44350000 {
177
175
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
178
176
reg = <0x44350000 0x10000>;
177
+
#address-cells = <1>;
178
+
#size-cells = <0>;
179
179
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
180
180
clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
181
181
<&clk IMX93_CLK_BUS_AON>;
···
347
343
lpi2c3: i2c@42530000 {
348
344
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
349
345
reg = <0x42530000 0x10000>;
346
+
#address-cells = <1>;
347
+
#size-cells = <0>;
350
348
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
351
349
clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
352
350
<&clk IMX93_CLK_BUS_WAKEUP>;
···
359
353
lpi2c4: i2c@42540000 {
360
354
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
361
355
reg = <0x42540000 0x10000>;
356
+
#address-cells = <1>;
357
+
#size-cells = <0>;
362
358
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
363
359
clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
364
360
<&clk IMX93_CLK_BUS_WAKEUP>;
···
463
455
lpi2c5: i2c@426b0000 {
464
456
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
465
457
reg = <0x426b0000 0x10000>;
458
+
#address-cells = <1>;
459
+
#size-cells = <0>;
466
460
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
467
461
clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
468
462
<&clk IMX93_CLK_BUS_WAKEUP>;
···
475
465
lpi2c6: i2c@426c0000 {
476
466
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
477
467
reg = <0x426c0000 0x10000>;
468
+
#address-cells = <1>;
469
+
#size-cells = <0>;
478
470
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
479
471
clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
480
472
<&clk IMX93_CLK_BUS_WAKEUP>;
···
487
475
lpi2c7: i2c@426d0000 {
488
476
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
489
477
reg = <0x426d0000 0x10000>;
478
+
#address-cells = <1>;
479
+
#size-cells = <0>;
490
480
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
491
481
clocks = <&clk IMX93_CLK_LPI2C7_GATE>,
492
482
<&clk IMX93_CLK_BUS_WAKEUP>;
···
499
485
lpi2c8: i2c@426e0000 {
500
486
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
501
487
reg = <0x426e0000 0x10000>;
488
+
#address-cells = <1>;
489
+
#size-cells = <0>;
502
490
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
503
491
clocks = <&clk IMX93_CLK_LPI2C8_GATE>,
504
492
<&clk IMX93_CLK_BUS_WAKEUP>;
···
596
580
eqos: ethernet@428a0000 {
597
581
compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
598
582
reg = <0x428a0000 0x10000>;
599
-
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
600
-
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
601
-
interrupt-names = "eth_wake_irq", "macirq";
583
+
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
584
+
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
585
+
interrupt-names = "macirq", "eth_wake_irq";
602
586
clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
603
587
<&clk IMX93_CLK_ENET_QOS_GATE>,
604
588
<&clk IMX93_CLK_ENET_TIMER2>,
···
611
595
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
612
596
assigned-clock-rates = <100000000>, <250000000>;
613
597
intf_mode = <&wakeupmix_gpr 0x28>;
614
-
clk_csr = <0>;
598
+
snps,clk-csr = <0>;
615
599
status = "disabled";
616
600
};
617
601
+1
-1
arch/arm64/boot/dts/nvidia/tegra194.dtsi
+1
-1
arch/arm64/boot/dts/nvidia/tegra194.dtsi
+1
-1
arch/arm64/boot/dts/nvidia/tegra234.dtsi
+1
-1
arch/arm64/boot/dts/nvidia/tegra234.dtsi
-4
arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts
-4
arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts
+26
-2
arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts
+26
-2
arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts
···
25
25
gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>;
26
26
};
27
27
28
+
&mpss {
29
+
pinctrl-0 = <&sim_ctrl_default>;
30
+
pinctrl-names = "default";
31
+
};
32
+
28
33
&button_default {
29
34
pins = "gpio37";
30
35
bias-pull-down;
···
39
34
pins = "gpio20", "gpio21", "gpio22";
40
35
};
41
36
42
-
&sim_ctrl_default {
43
-
pins = "gpio1", "gpio2";
37
+
/* This selects the external SIM card slot by default */
38
+
&msmgpio {
39
+
sim_ctrl_default: sim-ctrl-default-state {
40
+
esim-sel-pins {
41
+
pins = "gpio0", "gpio3";
42
+
bias-disable;
43
+
output-low;
44
+
};
45
+
46
+
sim-en-pins {
47
+
pins = "gpio1";
48
+
bias-disable;
49
+
output-low;
50
+
};
51
+
52
+
sim-sel-pins {
53
+
pins = "gpio2";
54
+
bias-disable;
55
+
output-high;
56
+
};
57
+
};
44
58
};
-10
arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi
-10
arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi
···
92
92
};
93
93
94
94
&mpss {
95
-
pinctrl-0 = <&sim_ctrl_default>;
96
-
pinctrl-names = "default";
97
-
98
95
status = "okay";
99
96
};
100
97
···
236
239
function = "gpio";
237
240
drive-strength = <2>;
238
241
bias-disable;
239
-
};
240
-
241
-
sim_ctrl_default: sim-ctrl-default-state {
242
-
function = "gpio";
243
-
drive-strength = <2>;
244
-
bias-disable;
245
-
output-low;
246
242
};
247
243
};
+1
-1
arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+1
-1
arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+2
arch/arm64/boot/dts/qcom/sc7280.dtsi
+2
arch/arm64/boot/dts/qcom/sc7280.dtsi
+22
-5
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+22
-5
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
···
370
370
regulator-min-microvolt = <1800000>;
371
371
regulator-max-microvolt = <1800000>;
372
372
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
373
+
regulator-always-on;
373
374
};
374
375
375
376
vreg_s11b: smps11 {
···
378
377
regulator-min-microvolt = <1272000>;
379
378
regulator-max-microvolt = <1272000>;
380
379
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
380
+
regulator-always-on;
381
381
};
382
382
383
383
vreg_s12b: smps12 {
···
386
384
regulator-min-microvolt = <984000>;
387
385
regulator-max-microvolt = <984000>;
388
386
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
387
+
regulator-always-on;
389
388
};
390
389
391
390
vreg_l3b: ldo3 {
···
444
441
regulator-min-microvolt = <3008000>;
445
442
regulator-max-microvolt = <3960000>;
446
443
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
444
+
regulator-always-on;
447
445
};
448
446
};
449
447
···
776
772
pmic-die-temp@3 {
777
773
reg = <PMK8350_ADC7_DIE_TEMP>;
778
774
qcom,pre-scaling = <1 1>;
775
+
label = "pmk8350_die_temp";
779
776
};
780
777
781
778
xo-therm@44 {
782
779
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
783
780
qcom,hw-settle-time = <200>;
784
781
qcom,ratiometric;
782
+
label = "pmk8350_xo_therm";
785
783
};
786
784
787
785
pmic-die-temp@103 {
788
786
reg = <PM8350_ADC7_DIE_TEMP(1)>;
789
787
qcom,pre-scaling = <1 1>;
788
+
label = "pmc8280_1_die_temp";
790
789
};
791
790
792
791
sys-therm@144 {
793
792
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
794
793
qcom,hw-settle-time = <200>;
795
794
qcom,ratiometric;
795
+
label = "sys_therm1";
796
796
};
797
797
798
798
sys-therm@145 {
799
799
reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
800
800
qcom,hw-settle-time = <200>;
801
801
qcom,ratiometric;
802
+
label = "sys_therm2";
802
803
};
803
804
804
805
sys-therm@146 {
805
806
reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
806
807
qcom,hw-settle-time = <200>;
807
808
qcom,ratiometric;
809
+
label = "sys_therm3";
808
810
};
809
811
810
812
sys-therm@147 {
811
813
reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
812
814
qcom,hw-settle-time = <200>;
813
815
qcom,ratiometric;
816
+
label = "sys_therm4";
814
817
};
815
818
816
819
pmic-die-temp@303 {
817
820
reg = <PM8350_ADC7_DIE_TEMP(3)>;
818
821
qcom,pre-scaling = <1 1>;
822
+
label = "pmc8280_2_die_temp";
819
823
};
820
824
821
825
sys-therm@344 {
822
826
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
823
827
qcom,hw-settle-time = <200>;
824
828
qcom,ratiometric;
829
+
label = "sys_therm5";
825
830
};
826
831
827
832
sys-therm@345 {
828
833
reg = <PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
829
834
qcom,hw-settle-time = <200>;
830
835
qcom,ratiometric;
836
+
label = "sys_therm6";
831
837
};
832
838
833
839
sys-therm@346 {
834
840
reg = <PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
835
841
qcom,hw-settle-time = <200>;
836
842
qcom,ratiometric;
843
+
label = "sys_therm7";
837
844
};
838
845
839
846
sys-therm@347 {
840
847
reg = <PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
841
848
qcom,hw-settle-time = <200>;
842
849
qcom,ratiometric;
850
+
label = "sys_therm8";
843
851
};
844
852
845
853
pmic-die-temp@403 {
846
854
reg = <PMR735A_ADC7_DIE_TEMP>;
847
855
qcom,pre-scaling = <1 1>;
856
+
label = "pmr735a_die_temp";
848
857
};
849
858
};
850
859
···
901
884
"VA DMIC0", "MIC BIAS1",
902
885
"VA DMIC1", "MIC BIAS1",
903
886
"VA DMIC2", "MIC BIAS3",
904
-
"TX DMIC0", "MIC BIAS1",
905
-
"TX DMIC1", "MIC BIAS2",
906
-
"TX DMIC2", "MIC BIAS3",
887
+
"VA DMIC0", "VA MIC BIAS1",
888
+
"VA DMIC1", "VA MIC BIAS1",
889
+
"VA DMIC2", "VA MIC BIAS3",
907
890
"TX SWR_ADC1", "ADC2_OUTPUT";
908
891
909
892
wcd-playback-dai-link {
···
954
937
va-dai-link {
955
938
link-name = "VA Capture";
956
939
cpu {
957
-
sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
940
+
sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
958
941
};
959
942
960
943
platform {
···
1079
1062
1080
1063
vdd-micb-supply = <&vreg_s10b>;
1081
1064
1082
-
qcom,dmic-sample-rate = <600000>;
1065
+
qcom,dmic-sample-rate = <4800000>;
1083
1066
1084
1067
status = "okay";
1085
1068
};
+9
-9
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+9
-9
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
···
2504
2504
qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2505
2505
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2506
2506
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2507
-
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2508
-
qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2507
+
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2508
+
qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2509
2509
qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2510
-
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2510
+
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2511
2511
qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2512
-
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2512
+
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2513
2513
2514
2514
#sound-dai-cells = <1>;
2515
2515
#address-cells = <2>;
···
2600
2600
<&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2601
2601
interrupt-names = "core", "wake";
2602
2602
2603
-
clocks = <&vamacro>;
2603
+
clocks = <&txmacro>;
2604
2604
clock-names = "iface";
2605
2605
label = "TX";
2606
2606
#sound-dai-cells = <1>;
···
2609
2609
2610
2610
qcom,din-ports = <4>;
2611
2611
qcom,dout-ports = <0>;
2612
-
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03 0x03>;
2613
-
qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x01>;
2612
+
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2613
+
qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2614
2614
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2615
2615
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2616
2616
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2617
2617
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2618
-
qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff 0xff>;
2618
+
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2619
2619
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2620
-
qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x00>;
2620
+
qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2621
2621
2622
2622
status = "disabled";
2623
2623
};
+1
arch/arm64/boot/dts/qcom/sm6115.dtsi
+1
arch/arm64/boot/dts/qcom/sm6115.dtsi
+1
arch/arm64/boot/dts/qcom/sm6375.dtsi
+1
arch/arm64/boot/dts/qcom/sm6375.dtsi
+2
-2
arch/arm64/boot/dts/qcom/sm8150.dtsi
+2
-2
arch/arm64/boot/dts/qcom/sm8150.dtsi
···
1826
1826
"slave_q2a",
1827
1827
"tbu";
1828
1828
1829
-
iommus = <&apps_smmu 0x1d80 0x7f>;
1829
+
iommus = <&apps_smmu 0x1d80 0x3f>;
1830
1830
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1831
1831
<0x100 &apps_smmu 0x1d81 0x1>;
1832
1832
···
1925
1925
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1926
1926
assigned-clock-rates = <19200000>;
1927
1927
1928
-
iommus = <&apps_smmu 0x1e00 0x7f>;
1928
+
iommus = <&apps_smmu 0x1e00 0x3f>;
1929
1929
iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1930
1930
<0x100 &apps_smmu 0x1e01 0x1>;
1931
1931
+1
-1
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts
+1
-1
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts
+1
arch/arm64/boot/dts/qcom/sm8350.dtsi
+1
arch/arm64/boot/dts/qcom/sm8350.dtsi
+3
-2
arch/arm64/boot/dts/qcom/sm8450.dtsi
+3
-2
arch/arm64/boot/dts/qcom/sm8450.dtsi
···
2143
2143
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2144
2144
<&vamacro>;
2145
2145
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2146
-
assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2147
-
<&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2146
+
assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2147
+
<&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2148
2148
assigned-clock-rates = <19200000>, <19200000>;
2149
2149
2150
2150
#clock-cells = <0>;
···
4003
4003
power-domains = <&gcc UFS_PHY_GDSC>;
4004
4004
4005
4005
iommus = <&apps_smmu 0xe0 0x0>;
4006
+
dma-coherent;
4006
4007
4007
4008
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4008
4009
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
+25
-24
arch/arm64/boot/dts/qcom/sm8550.dtsi
+25
-24
arch/arm64/boot/dts/qcom/sm8550.dtsi
···
66
66
67
67
CPU0: cpu@0 {
68
68
device_type = "cpu";
69
-
compatible = "qcom,kryo";
69
+
compatible = "arm,cortex-a510";
70
70
reg = <0 0>;
71
71
enable-method = "psci";
72
72
next-level-cache = <&L2_0>;
···
89
89
90
90
CPU1: cpu@100 {
91
91
device_type = "cpu";
92
-
compatible = "qcom,kryo";
92
+
compatible = "arm,cortex-a510";
93
93
reg = <0 0x100>;
94
94
enable-method = "psci";
95
95
next-level-cache = <&L2_100>;
···
108
108
109
109
CPU2: cpu@200 {
110
110
device_type = "cpu";
111
-
compatible = "qcom,kryo";
111
+
compatible = "arm,cortex-a510";
112
112
reg = <0 0x200>;
113
113
enable-method = "psci";
114
114
next-level-cache = <&L2_200>;
···
127
127
128
128
CPU3: cpu@300 {
129
129
device_type = "cpu";
130
-
compatible = "qcom,kryo";
130
+
compatible = "arm,cortex-a715";
131
131
reg = <0 0x300>;
132
132
enable-method = "psci";
133
133
next-level-cache = <&L2_300>;
···
146
146
147
147
CPU4: cpu@400 {
148
148
device_type = "cpu";
149
-
compatible = "qcom,kryo";
149
+
compatible = "arm,cortex-a715";
150
150
reg = <0 0x400>;
151
151
enable-method = "psci";
152
152
next-level-cache = <&L2_400>;
···
165
165
166
166
CPU5: cpu@500 {
167
167
device_type = "cpu";
168
-
compatible = "qcom,kryo";
168
+
compatible = "arm,cortex-a710";
169
169
reg = <0 0x500>;
170
170
enable-method = "psci";
171
171
next-level-cache = <&L2_500>;
···
184
184
185
185
CPU6: cpu@600 {
186
186
device_type = "cpu";
187
-
compatible = "qcom,kryo";
187
+
compatible = "arm,cortex-a710";
188
188
reg = <0 0x600>;
189
189
enable-method = "psci";
190
190
next-level-cache = <&L2_600>;
···
203
203
204
204
CPU7: cpu@700 {
205
205
device_type = "cpu";
206
-
compatible = "qcom,kryo";
206
+
compatible = "arm,cortex-x3";
207
207
reg = <0 0x700>;
208
208
enable-method = "psci";
209
209
next-level-cache = <&L2_700>;
···
1905
1905
required-opps = <&rpmhpd_opp_nom>;
1906
1906
1907
1907
iommus = <&apps_smmu 0x60 0x0>;
1908
+
dma-coherent;
1908
1909
1909
1910
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
1910
1911
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
···
1998
1997
lpass_tlmm: pinctrl@6e80000 {
1999
1998
compatible = "qcom,sm8550-lpass-lpi-pinctrl";
2000
1999
reg = <0 0x06e80000 0 0x20000>,
2001
-
<0 0x0725a000 0 0x10000>;
2000
+
<0 0x07250000 0 0x10000>;
2002
2001
gpio-controller;
2003
2002
#gpio-cells = <2>;
2004
2003
gpio-ranges = <&lpass_tlmm 0 0 23>;
···
2692
2691
pins = "gpio28", "gpio29";
2693
2692
function = "qup1_se0";
2694
2693
drive-strength = <2>;
2695
-
bias-pull-up;
2694
+
bias-pull-up = <2200>;
2696
2695
};
2697
2696
2698
2697
qup_i2c1_data_clk: qup-i2c1-data-clk-state {
···
2700
2699
pins = "gpio32", "gpio33";
2701
2700
function = "qup1_se1";
2702
2701
drive-strength = <2>;
2703
-
bias-pull-up;
2702
+
bias-pull-up = <2200>;
2704
2703
};
2705
2704
2706
2705
qup_i2c2_data_clk: qup-i2c2-data-clk-state {
···
2708
2707
pins = "gpio36", "gpio37";
2709
2708
function = "qup1_se2";
2710
2709
drive-strength = <2>;
2711
-
bias-pull-up;
2710
+
bias-pull-up = <2200>;
2712
2711
};
2713
2712
2714
2713
qup_i2c3_data_clk: qup-i2c3-data-clk-state {
···
2716
2715
pins = "gpio40", "gpio41";
2717
2716
function = "qup1_se3";
2718
2717
drive-strength = <2>;
2719
-
bias-pull-up;
2718
+
bias-pull-up = <2200>;
2720
2719
};
2721
2720
2722
2721
qup_i2c4_data_clk: qup-i2c4-data-clk-state {
···
2724
2723
pins = "gpio44", "gpio45";
2725
2724
function = "qup1_se4";
2726
2725
drive-strength = <2>;
2727
-
bias-pull-up;
2726
+
bias-pull-up = <2200>;
2728
2727
};
2729
2728
2730
2729
qup_i2c5_data_clk: qup-i2c5-data-clk-state {
···
2732
2731
pins = "gpio52", "gpio53";
2733
2732
function = "qup1_se5";
2734
2733
drive-strength = <2>;
2735
-
bias-pull-up;
2734
+
bias-pull-up = <2200>;
2736
2735
};
2737
2736
2738
2737
qup_i2c6_data_clk: qup-i2c6-data-clk-state {
···
2740
2739
pins = "gpio48", "gpio49";
2741
2740
function = "qup1_se6";
2742
2741
drive-strength = <2>;
2743
-
bias-pull-up;
2742
+
bias-pull-up = <2200>;
2744
2743
};
2745
2744
2746
2745
qup_i2c8_data_clk: qup-i2c8-data-clk-state {
···
2748
2747
pins = "gpio57";
2749
2748
function = "qup2_se0_l1_mira";
2750
2749
drive-strength = <2>;
2751
-
bias-pull-up;
2750
+
bias-pull-up = <2200>;
2752
2751
};
2753
2752
2754
2753
sda-pins {
2755
2754
pins = "gpio56";
2756
2755
function = "qup2_se0_l0_mira";
2757
2756
drive-strength = <2>;
2758
-
bias-pull-up;
2757
+
bias-pull-up = <2200>;
2759
2758
};
2760
2759
};
2761
2760
···
2764
2763
pins = "gpio60", "gpio61";
2765
2764
function = "qup2_se1";
2766
2765
drive-strength = <2>;
2767
-
bias-pull-up;
2766
+
bias-pull-up = <2200>;
2768
2767
};
2769
2768
2770
2769
qup_i2c10_data_clk: qup-i2c10-data-clk-state {
···
2772
2771
pins = "gpio64", "gpio65";
2773
2772
function = "qup2_se2";
2774
2773
drive-strength = <2>;
2775
-
bias-pull-up;
2774
+
bias-pull-up = <2200>;
2776
2775
};
2777
2776
2778
2777
qup_i2c11_data_clk: qup-i2c11-data-clk-state {
···
2780
2779
pins = "gpio68", "gpio69";
2781
2780
function = "qup2_se3";
2782
2781
drive-strength = <2>;
2783
-
bias-pull-up;
2782
+
bias-pull-up = <2200>;
2784
2783
};
2785
2784
2786
2785
qup_i2c12_data_clk: qup-i2c12-data-clk-state {
···
2788
2787
pins = "gpio2", "gpio3";
2789
2788
function = "qup2_se4";
2790
2789
drive-strength = <2>;
2791
-
bias-pull-up;
2790
+
bias-pull-up = <2200>;
2792
2791
};
2793
2792
2794
2793
qup_i2c13_data_clk: qup-i2c13-data-clk-state {
···
2796
2795
pins = "gpio80", "gpio81";
2797
2796
function = "qup2_se5";
2798
2797
drive-strength = <2>;
2799
-
bias-pull-up;
2798
+
bias-pull-up = <2200>;
2800
2799
};
2801
2800
2802
2801
qup_i2c15_data_clk: qup-i2c15-data-clk-state {
···
2804
2803
pins = "gpio72", "gpio106";
2805
2804
function = "qup2_se7";
2806
2805
drive-strength = <2>;
2807
-
bias-pull-up;
2806
+
bias-pull-up = <2200>;
2808
2807
};
2809
2808
2810
2809
qup_spi0_cs: qup-spi0-cs-state {
+1
-1
drivers/bus/imx-weim.c
+1
-1
drivers/bus/imx-weim.c
···
204
204
const struct of_device_id *of_id = of_match_device(weim_id_table,
205
205
&pdev->dev);
206
206
const struct imx_weim_devtype *devtype = of_id->data;
207
+
int ret = 0, have_child = 0;
207
208
struct device_node *child;
208
-
int ret, have_child = 0;
209
209
struct weim_priv *priv;
210
210
void __iomem *base;
211
211
u32 reg;
+1
-2
drivers/firmware/arm_scmi/bus.c
+1
-2
drivers/firmware/arm_scmi/bus.c
···
14
14
#include <linux/kernel.h>
15
15
#include <linux/slab.h>
16
16
#include <linux/device.h>
17
-
#include <linux/of.h>
18
17
19
18
#include "common.h"
20
19
···
435
436
/* Nothing to do. */
436
437
if (!phead) {
437
438
mutex_unlock(&scmi_requested_devices_mtx);
438
-
return scmi_dev;
439
+
return NULL;
439
440
}
440
441
441
442
/* Walk the list of requested devices for protocol and create them */
+7
-7
drivers/firmware/arm_scmi/driver.c
+7
-7
drivers/firmware/arm_scmi/driver.c
···
2221
2221
hash_init(info->pending_xfers);
2222
2222
2223
2223
/* Allocate a bitmask sized to hold MSG_TOKEN_MAX tokens */
2224
-
info->xfer_alloc_table = devm_kcalloc(dev, BITS_TO_LONGS(MSG_TOKEN_MAX),
2225
-
sizeof(long), GFP_KERNEL);
2224
+
info->xfer_alloc_table = devm_bitmap_zalloc(dev, MSG_TOKEN_MAX,
2225
+
GFP_KERNEL);
2226
2226
if (!info->xfer_alloc_table)
2227
2227
return -ENOMEM;
2228
2228
···
2657
2657
struct scmi_handle *handle;
2658
2658
const struct scmi_desc *desc;
2659
2659
struct scmi_info *info;
2660
+
bool coex = IS_ENABLED(CONFIG_ARM_SCMI_RAW_MODE_SUPPORT_COEX);
2660
2661
struct device *dev = &pdev->dev;
2661
2662
struct device_node *child, *np = dev->of_node;
2662
2663
···
2732
2731
dev_warn(dev, "Failed to setup SCMI debugfs.\n");
2733
2732
2734
2733
if (IS_ENABLED(CONFIG_ARM_SCMI_RAW_MODE_SUPPORT)) {
2735
-
bool coex =
2736
-
IS_ENABLED(CONFIG_ARM_SCMI_RAW_MODE_SUPPORT_COEX);
2737
-
2738
2734
ret = scmi_debugfs_raw_mode_setup(info);
2739
2735
if (!coex) {
2740
2736
if (ret)
2741
2737
goto clear_dev_req_notifier;
2742
2738
2743
-
/* Bail out anyway when coex enabled */
2744
-
return ret;
2739
+
/* Bail out anyway when coex disabled. */
2740
+
return 0;
2745
2741
}
2746
2742
2747
2743
/* Coex enabled, carry on in any case. */
···
2762
2764
ret = scmi_protocol_acquire(handle, SCMI_PROTOCOL_BASE);
2763
2765
if (ret) {
2764
2766
dev_err(dev, "unable to communicate with SCMI\n");
2767
+
if (coex)
2768
+
return 0;
2765
2769
goto notification_exit;
2766
2770
}
2767
2771
+37
drivers/firmware/arm_scmi/mailbox.c
+37
drivers/firmware/arm_scmi/mailbox.c
···
52
52
"#mbox-cells", idx, NULL);
53
53
}
54
54
55
+
static int mailbox_chan_validate(struct device *cdev)
56
+
{
57
+
int num_mb, num_sh, ret = 0;
58
+
struct device_node *np = cdev->of_node;
59
+
60
+
num_mb = of_count_phandle_with_args(np, "mboxes", "#mbox-cells");
61
+
num_sh = of_count_phandle_with_args(np, "shmem", NULL);
62
+
/* Bail out if mboxes and shmem descriptors are inconsistent */
63
+
if (num_mb <= 0 || num_sh > 2 || num_mb != num_sh) {
64
+
dev_warn(cdev, "Invalid channel descriptor for '%s'\n",
65
+
of_node_full_name(np));
66
+
return -EINVAL;
67
+
}
68
+
69
+
if (num_sh > 1) {
70
+
struct device_node *np_tx, *np_rx;
71
+
72
+
np_tx = of_parse_phandle(np, "shmem", 0);
73
+
np_rx = of_parse_phandle(np, "shmem", 1);
74
+
/* SCMI Tx and Rx shared mem areas have to be distinct */
75
+
if (!np_tx || !np_rx || np_tx == np_rx) {
76
+
dev_warn(cdev, "Invalid shmem descriptor for '%s'\n",
77
+
of_node_full_name(np));
78
+
ret = -EINVAL;
79
+
}
80
+
81
+
of_node_put(np_tx);
82
+
of_node_put(np_rx);
83
+
}
84
+
85
+
return ret;
86
+
}
87
+
55
88
static int mailbox_chan_setup(struct scmi_chan_info *cinfo, struct device *dev,
56
89
bool tx)
57
90
{
···
96
63
struct mbox_client *cl;
97
64
resource_size_t size;
98
65
struct resource res;
66
+
67
+
ret = mailbox_chan_validate(cdev);
68
+
if (ret)
69
+
return ret;
99
70
100
71
smbox = devm_kzalloc(dev, sizeof(*smbox), GFP_KERNEL);
101
72
if (!smbox)
+1
-1
drivers/firmware/qcom_scm.c
+1
-1
drivers/firmware/qcom_scm.c
+3
-3
drivers/soc/qcom/llcc-qcom.c
+3
-3
drivers/soc/qcom/llcc-qcom.c
···
191
191
{ LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
192
192
{ LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 },
193
193
{ LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
194
-
{ LLCC_CVPFW, 32, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
195
-
{ LLCC_CPUSS1, 33, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
196
-
{ LLCC_CPUHWT, 36, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
194
+
{ LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
195
+
{ LLCC_CPUSS1, 3, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
196
+
{ LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
197
197
};
198
198
199
199
static const struct llcc_slice_config sdm845_data[] = {
+7
-3
drivers/soc/qcom/rmtfs_mem.c
+7
-3
drivers/soc/qcom/rmtfs_mem.c
···
176
176
struct reserved_mem *rmem;
177
177
struct qcom_rmtfs_mem *rmtfs_mem;
178
178
u32 client_id;
179
-
u32 num_vmids, vmid[NUM_MAX_VMIDS];
179
+
u32 vmid[NUM_MAX_VMIDS];
180
+
int num_vmids;
180
181
int ret, i;
181
182
182
183
rmem = of_reserved_mem_lookup(node);
···
229
228
}
230
229
231
230
num_vmids = of_property_count_u32_elems(node, "qcom,vmid");
232
-
if (num_vmids < 0) {
233
-
dev_err(&pdev->dev, "failed to count qcom,vmid elements: %d\n", ret);
231
+
if (num_vmids == -EINVAL) {
232
+
/* qcom,vmid is optional */
233
+
num_vmids = 0;
234
+
} else if (num_vmids < 0) {
235
+
dev_err(&pdev->dev, "failed to count qcom,vmid elements: %d\n", num_vmids);
234
236
goto remove_cdev;
235
237
} else if (num_vmids > NUM_MAX_VMIDS) {
236
238
dev_warn(&pdev->dev,
+14
-15
drivers/tee/amdtee/core.c
+14
-15
drivers/tee/amdtee/core.c
···
267
267
goto out;
268
268
}
269
269
270
+
/* Open session with loaded TA */
271
+
handle_open_session(arg, &session_info, param);
272
+
if (arg->ret != TEEC_SUCCESS) {
273
+
pr_err("open_session failed %d\n", arg->ret);
274
+
handle_unload_ta(ta_handle);
275
+
kref_put(&sess->refcount, destroy_session);
276
+
goto out;
277
+
}
278
+
270
279
/* Find an empty session index for the given TA */
271
280
spin_lock(&sess->lock);
272
281
i = find_first_zero_bit(sess->sess_mask, TEE_NUM_SESSIONS);
273
-
if (i < TEE_NUM_SESSIONS)
282
+
if (i < TEE_NUM_SESSIONS) {
283
+
sess->session_info[i] = session_info;
284
+
set_session_id(ta_handle, i, &arg->session);
274
285
set_bit(i, sess->sess_mask);
286
+
}
275
287
spin_unlock(&sess->lock);
276
288
277
289
if (i >= TEE_NUM_SESSIONS) {
278
290
pr_err("reached maximum session count %d\n", TEE_NUM_SESSIONS);
291
+
handle_close_session(ta_handle, session_info);
279
292
handle_unload_ta(ta_handle);
280
293
kref_put(&sess->refcount, destroy_session);
281
294
rc = -ENOMEM;
282
295
goto out;
283
296
}
284
297
285
-
/* Open session with loaded TA */
286
-
handle_open_session(arg, &session_info, param);
287
-
if (arg->ret != TEEC_SUCCESS) {
288
-
pr_err("open_session failed %d\n", arg->ret);
289
-
spin_lock(&sess->lock);
290
-
clear_bit(i, sess->sess_mask);
291
-
spin_unlock(&sess->lock);
292
-
handle_unload_ta(ta_handle);
293
-
kref_put(&sess->refcount, destroy_session);
294
-
goto out;
295
-
}
296
-
297
-
sess->session_info[i] = session_info;
298
-
set_session_id(ta_handle, i, &arg->session);
299
298
out:
300
299
free_pages((u64)ta, get_order(ta_size));
301
300
return rc;