+11

Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml

reviewed

··· 17 17 compatible: 18 18 oneOf: 19 19 - const: allwinner,sun6i-a31-mipi-dphy 20 20 + - const: allwinner,sun50i-a100-mipi-dphy 20 21 - items: 21 22 - const: allwinner,sun50i-a64-mipi-dphy 22 23 - const: allwinner,sun6i-a31-mipi-dphy 24 24 + - items: 25 25 + - const: allwinner,sun20i-d1-mipi-dphy 26 26 + - const: allwinner,sun50i-a100-mipi-dphy 23 27 24 28 reg: 29 29 + maxItems: 1 30 30 + 31 31 + interrupts: 25 32 maxItems: 1 26 33 27 34 clocks: ··· 60 53 - "#phy-cells" 61 54 - compatible 62 55 - reg 56 56 + - interrupts 63 57 - clocks 64 58 - clock-names 65 59 - resets ··· 69 61 70 62 examples: 71 63 - | 64 64 + #include <dt-bindings/interrupt-controller/arm-gic.h> 65 65 + 72 66 dphy0: d-phy@1ca1000 { 73 67 compatible = "allwinner,sun6i-a31-mipi-dphy"; 74 68 reg = <0x01ca1000 0x1000>; 69 69 + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 75 70 clocks = <&ccu 23>, <&ccu 97>; 76 71 clock-names = "bus", "mod"; 77 72 resets = <&ccu 4>;

+26

Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml

reviewed

··· 36 36 - const: pmu3 37 37 38 38 clocks: 39 39 + minItems: 4 39 40 items: 40 41 - description: USB OTG PHY bus clock 41 42 - description: USB Host 0 PHY bus clock 42 43 - description: USB Host 1 PHY bus clock 43 44 - description: USB Host 2 PHY bus clock 45 45 + - description: PMU clock for host port 2 44 46 45 47 clock-names: 48 48 + minItems: 4 46 49 items: 47 50 - const: usb0_phy 48 51 - const: usb1_phy 49 52 - const: usb2_phy 50 53 - const: usb3_phy 54 54 + - const: pmu2_clk 51 55 52 56 resets: 53 57 items: ··· 99 95 - reg-names 100 96 - resets 101 97 - reset-names 98 98 + 99 99 + allOf: 100 100 + - if: 101 101 + properties: 102 102 + compatible: 103 103 + contains: 104 104 + enum: 105 105 + - allwinner,sun50i-h616-usb-phy 106 106 + then: 107 107 + properties: 108 108 + clocks: 109 109 + minItems: 5 110 110 + 111 111 + clock-names: 112 112 + minItems: 5 113 113 + else: 114 114 + properties: 115 115 + clocks: 116 116 + maxItems: 4 117 117 + 118 118 + clock-names: 119 119 + maxItems: 4 102 120 103 121 additionalProperties: false 104 122

+13 -3

Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml

reviewed

··· 16 16 compatible: 17 17 enum: 18 18 - fsl,imx8mm-pcie-phy 19 19 + - fsl,imx8mp-pcie-phy 19 20 20 21 reg: 21 22 maxItems: 1 ··· 29 28 - const: ref 30 29 31 30 resets: 32 32 - maxItems: 1 31 31 + minItems: 1 32 32 + maxItems: 2 33 33 34 34 reset-names: 35 35 - items: 36 36 - - const: pciephy 35 35 + oneOf: 36 36 + - items: # for iMX8MM 37 37 + - const: pciephy 38 38 + - items: # for IMX8MP 39 39 + - const: pciephy 40 40 + - const: perst 37 41 38 42 fsl,refclk-pad-mode: 39 43 description: | ··· 65 59 type: boolean 66 60 description: A boolean property indicating the CLKREQ# signal is 67 61 not supported in the board design (optional) 62 62 + 63 63 + power-domains: 64 64 + description: PCIe PHY power domain (optional). 65 65 + maxItems: 1 68 66 69 67 required: 70 68 - "#phy-cells"

+5 -2

Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 - $id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml# 4 4 + $id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: Qualcomm QMP PHY controller (PCIe) 7 7 + title: Qualcomm QMP PHY controller (PCIe, IPQ8074) 8 8 9 9 maintainers: 10 10 - Vinod Koul <vkoul@kernel.org> ··· 12 12 description: 13 13 QMP PHY controller supports physical layer functionality for a number of 14 14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 15 15 + 16 16 + Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see 17 17 + qcom,sc8280xp-qmp-pcie-phy.yaml. 15 18 16 19 properties: 17 20 compatible:

+9 -8

Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 - $id: http://devicetree.org/schemas/phy/qcom,qmp-ufs-phy.yaml# 4 4 + $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-ufs-phy.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: Qualcomm QMP PHY controller (UFS) 7 7 + title: Qualcomm QMP PHY controller (UFS, MSM8996) 8 8 9 9 maintainers: 10 10 - Vinod Koul <vkoul@kernel.org> ··· 13 13 QMP PHY controller supports physical layer functionality for a number of 14 14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 15 15 16 16 + Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see 17 17 + qcom,sc8280xp-qmp-ufs-phy.yaml. 18 18 + 16 19 properties: 17 20 compatible: 18 21 enum: 19 22 - qcom,msm8996-qmp-ufs-phy 20 23 - qcom,msm8998-qmp-ufs-phy 21 24 - qcom,sc8180x-qmp-ufs-phy 22 22 - - qcom,sc8280xp-qmp-ufs-phy 23 25 - qcom,sdm845-qmp-ufs-phy 24 26 - qcom,sm6115-qmp-ufs-phy 25 27 - qcom,sm6350-qmp-ufs-phy ··· 121 119 enum: 122 120 - qcom,msm8998-qmp-ufs-phy 123 121 - qcom,sc8180x-qmp-ufs-phy 124 124 - - qcom,sc8280xp-qmp-ufs-phy 125 122 - qcom,sdm845-qmp-ufs-phy 126 123 - qcom,sm6115-qmp-ufs-phy 127 124 - qcom,sm6350-qmp-ufs-phy ··· 157 156 contains: 158 157 enum: 159 158 - qcom,msm8998-qmp-ufs-phy 160 160 - - qcom,sc8280xp-qmp-ufs-phy 161 159 - qcom,sdm845-qmp-ufs-phy 162 160 - qcom,sm6350-qmp-ufs-phy 163 161 - qcom,sm8150-qmp-ufs-phy ··· 211 211 212 212 examples: 213 213 - | 214 214 - #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 214 214 + #include <dt-bindings/clock/qcom,gcc-sm8250.h> 215 215 #include <dt-bindings/clock/qcom,rpmh.h> 216 216 + 216 217 phy-wrapper@1d87000 { 217 217 - compatible = "qcom,sc8280xp-qmp-ufs-phy"; 218 218 - reg = <0x01d87000 0xe10>; 218 218 + compatible = "qcom,sm8250-qmp-ufs-phy"; 219 219 + reg = <0x01d87000 0x1c0>; 219 220 #address-cells = <1>; 220 221 #size-cells = <1>; 221 222 ranges = <0x0 0x01d87000 0x1000>;

+5 -15

Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 - $id: http://devicetree.org/schemas/phy/qcom,qmp-usb-phy.yaml# 4 4 + $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-usb3-phy.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: Qualcomm QMP PHY controller (USB) 7 7 + title: Qualcomm QMP PHY controller (USB, MSM8996) 8 8 9 9 maintainers: 10 10 - Vinod Koul <vkoul@kernel.org> ··· 12 12 description: 13 13 QMP PHY controller supports physical layer functionality for a number of 14 14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 15 15 + 16 16 + Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see 17 17 + qcom,sc8280xp-qmp-usb3-uni-phy.yaml. 15 18 16 19 properties: 17 20 compatible: ··· 26 23 - qcom,qcm2290-qmp-usb3-phy 27 24 - qcom,sc7180-qmp-usb3-phy 28 25 - qcom,sc8180x-qmp-usb3-phy 29 29 - - qcom,sc8280xp-qmp-usb3-uni-phy 30 26 - qcom,sdm845-qmp-usb3-phy 31 27 - qcom,sdm845-qmp-usb3-uni-phy 32 28 - qcom,sdx55-qmp-usb3-uni-phy ··· 203 201 compatible: 204 202 contains: 205 203 enum: 206 206 - - qcom,sc8280xp-qmp-usb3-uni-phy 207 204 - qcom,sm8150-qmp-usb3-phy 208 205 - qcom,sm8150-qmp-usb3-uni-phy 209 206 - qcom,sm8250-qmp-usb3-uni-phy ··· 268 267 items: 269 268 - const: phy_phy 270 269 - const: phy 271 271 - 272 272 - - if: 273 273 - properties: 274 274 - compatible: 275 275 - contains: 276 276 - enum: 277 277 - - qcom,sc8280xp-qmp-usb3-uni-phy 278 278 - then: 279 279 - required: 280 280 - - power-domains 281 270 282 271 - if: 283 272 properties: ··· 340 349 contains: 341 350 enum: 342 351 - qcom,msm8996-qmp-usb3-phy 343 343 - - qcom,sc8280xp-qmp-usb3-uni-phy 344 352 - qcom,sm8250-qmp-usb3-uni-phy 345 353 - qcom,sm8350-qmp-usb3-uni-phy 346 354 then:

+10 -15

Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml Documentation/devicetree/bindings/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml

reviewed

··· 2 2 3 3 %YAML 1.2 4 4 --- 5 5 - $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#" 6 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 5 5 + $id: http://devicetree.org/schemas/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 8 - title: Qualcomm QMP USB3 DP PHY controller 8 8 + title: Qualcomm QMP USB3 DP PHY controller (SC7180) 9 9 + 10 10 + description: 11 11 + The QMP PHY controller supports physical layer functionality for a number of 12 12 + controllers on Qualcomm chipsets, such as, PCIe, UFS and USB. 13 13 + 14 14 + Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see 15 15 + qcom,sc8280xp-qmp-usb43dp-phy.yaml. 9 16 10 17 maintainers: 11 18 - Wesley Cheng <quic_wcheng@quicinc.com> ··· 23 16 - qcom,sc7180-qmp-usb3-dp-phy 24 17 - qcom,sc7280-qmp-usb3-dp-phy 25 18 - qcom,sc8180x-qmp-usb3-dp-phy 26 26 - - qcom,sc8280xp-qmp-usb43dp-phy 27 19 - qcom,sdm845-qmp-usb3-dp-phy 28 20 - qcom,sm8250-qmp-usb3-dp-phy 29 21 reg: ··· 167 161 - vdda-pll-supply 168 162 169 163 additionalProperties: false 170 170 - 171 171 - allOf: 172 172 - - if: 173 173 - properties: 174 174 - compatible: 175 175 - contains: 176 176 - enum: 177 177 - - qcom,sc8280xp-qmp-usb43dp-phy 178 178 - then: 179 179 - required: 180 180 - - power-domains 181 164 182 165 examples: 183 166 - |

+165

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Qualcomm QMP PHY controller (PCIe, SC8280XP) 8 8 + 9 9 + maintainers: 10 10 + - Vinod Koul <vkoul@kernel.org> 11 11 + 12 12 + description: 13 13 + The QMP PHY controller supports physical layer functionality for a number of 14 14 + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 15 15 + 16 16 + properties: 17 17 + compatible: 18 18 + enum: 19 19 + - qcom,sc8280xp-qmp-gen3x1-pcie-phy 20 20 + - qcom,sc8280xp-qmp-gen3x2-pcie-phy 21 21 + - qcom,sc8280xp-qmp-gen3x4-pcie-phy 22 22 + 23 23 + reg: 24 24 + minItems: 1 25 25 + maxItems: 2 26 26 + 27 27 + clocks: 28 28 + maxItems: 6 29 29 + 30 30 + clock-names: 31 31 + items: 32 32 + - const: aux 33 33 + - const: cfg_ahb 34 34 + - const: ref 35 35 + - const: rchng 36 36 + - const: pipe 37 37 + - const: pipediv2 38 38 + 39 39 + power-domains: 40 40 + maxItems: 1 41 41 + 42 42 + resets: 43 43 + maxItems: 1 44 44 + 45 45 + reset-names: 46 46 + items: 47 47 + - const: phy 48 48 + 49 49 + vdda-phy-supply: true 50 50 + 51 51 + vdda-pll-supply: true 52 52 + 53 53 + qcom,4ln-config-sel: 54 54 + description: PCIe 4-lane configuration 55 55 + $ref: /schemas/types.yaml#/definitions/phandle-array 56 56 + items: 57 57 + - items: 58 58 + - description: phandle of TCSR syscon 59 59 + - description: offset of PCIe 4-lane configuration register 60 60 + - description: offset of configuration bit for this PHY 61 61 + 62 62 + "#clock-cells": 63 63 + const: 0 64 64 + 65 65 + clock-output-names: 66 66 + maxItems: 1 67 67 + 68 68 + "#phy-cells": 69 69 + const: 0 70 70 + 71 71 + required: 72 72 + - compatible 73 73 + - reg 74 74 + - clocks 75 75 + - clock-names 76 76 + - power-domains 77 77 + - resets 78 78 + - reset-names 79 79 + - vdda-phy-supply 80 80 + - vdda-pll-supply 81 81 + - "#clock-cells" 82 82 + - clock-output-names 83 83 + - "#phy-cells" 84 84 + 85 85 + additionalProperties: false 86 86 + 87 87 + allOf: 88 88 + - if: 89 89 + properties: 90 90 + compatible: 91 91 + contains: 92 92 + enum: 93 93 + - qcom,sc8280xp-qmp-gen3x4-pcie-phy 94 94 + then: 95 95 + properties: 96 96 + reg: 97 97 + items: 98 98 + - description: port a 99 99 + - description: port b 100 100 + required: 101 101 + - qcom,4ln-config-sel 102 102 + else: 103 103 + properties: 104 104 + reg: 105 105 + maxItems: 1 106 106 + 107 107 + examples: 108 108 + - | 109 109 + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 110 110 + 111 111 + pcie2b_phy: phy@1c18000 { 112 112 + compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 113 113 + reg = <0x01c18000 0x2000>; 114 114 + 115 115 + clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 116 116 + <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 117 117 + <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 118 118 + <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 119 119 + <&gcc GCC_PCIE_2B_PIPE_CLK>, 120 120 + <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 121 121 + clock-names = "aux", "cfg_ahb", "ref", "rchng", 122 122 + "pipe", "pipediv2"; 123 123 + 124 124 + power-domains = <&gcc PCIE_2B_GDSC>; 125 125 + 126 126 + resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 127 127 + reset-names = "phy"; 128 128 + 129 129 + vdda-phy-supply = <&vreg_l6d>; 130 130 + vdda-pll-supply = <&vreg_l4d>; 131 131 + 132 132 + #clock-cells = <0>; 133 133 + clock-output-names = "pcie_2b_pipe_clk"; 134 134 + 135 135 + #phy-cells = <0>; 136 136 + }; 137 137 + 138 138 + pcie2a_phy: phy@1c24000 { 139 139 + compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 140 140 + reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>; 141 141 + 142 142 + clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 143 143 + <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 144 144 + <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 145 145 + <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 146 146 + <&gcc GCC_PCIE_2A_PIPE_CLK>, 147 147 + <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 148 148 + clock-names = "aux", "cfg_ahb", "ref", "rchng", 149 149 + "pipe", "pipediv2"; 150 150 + 151 151 + power-domains = <&gcc PCIE_2A_GDSC>; 152 152 + 153 153 + resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 154 154 + reset-names = "phy"; 155 155 + 156 156 + vdda-phy-supply = <&vreg_l6d>; 157 157 + vdda-pll-supply = <&vreg_l4d>; 158 158 + 159 159 + qcom,4ln-config-sel = <&tcsr 0xa044 0>; 160 160 + 161 161 + #clock-cells = <0>; 162 162 + clock-output-names = "pcie_2a_pipe_clk"; 163 163 + 164 164 + #phy-cells = <0>; 165 165 + };

+83

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Qualcomm QMP PHY controller (UFS, SC8280XP) 8 8 + 9 9 + maintainers: 10 10 + - Vinod Koul <vkoul@kernel.org> 11 11 + 12 12 + description: 13 13 + The QMP PHY controller supports physical layer functionality for a number of 14 14 + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 15 15 + 16 16 + properties: 17 17 + compatible: 18 18 + enum: 19 19 + - qcom,sc8280xp-qmp-ufs-phy 20 20 + 21 21 + reg: 22 22 + maxItems: 1 23 23 + 24 24 + clocks: 25 25 + maxItems: 2 26 26 + 27 27 + clock-names: 28 28 + items: 29 29 + - const: ref 30 30 + - const: ref_aux 31 31 + 32 32 + power-domains: 33 33 + maxItems: 1 34 34 + 35 35 + resets: 36 36 + maxItems: 1 37 37 + 38 38 + reset-names: 39 39 + items: 40 40 + - const: ufsphy 41 41 + 42 42 + vdda-phy-supply: true 43 43 + 44 44 + vdda-pll-supply: true 45 45 + 46 46 + "#phy-cells": 47 47 + const: 0 48 48 + 49 49 + required: 50 50 + - compatible 51 51 + - reg 52 52 + - clocks 53 53 + - clock-names 54 54 + - power-domains 55 55 + - resets 56 56 + - reset-names 57 57 + - vdda-phy-supply 58 58 + - vdda-pll-supply 59 59 + - "#phy-cells" 60 60 + 61 61 + additionalProperties: false 62 62 + 63 63 + examples: 64 64 + - | 65 65 + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 66 66 + 67 67 + ufs_mem_phy: phy@1d87000 { 68 68 + compatible = "qcom,sc8280xp-qmp-ufs-phy"; 69 69 + reg = <0x01d87000 0x1000>; 70 70 + 71 71 + clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 72 72 + clock-names = "ref", "ref_aux"; 73 73 + 74 74 + power-domains = <&gcc UFS_PHY_GDSC>; 75 75 + 76 76 + resets = <&ufs_mem_hc 0>; 77 77 + reset-names = "ufsphy"; 78 78 + 79 79 + vdda-phy-supply = <&vreg_l6b>; 80 80 + vdda-pll-supply = <&vreg_l3b>; 81 81 + 82 82 + #phy-cells = <0>; 83 83 + };

+102

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Qualcomm QMP PHY controller (USB, SC8280XP) 8 8 + 9 9 + maintainers: 10 10 + - Vinod Koul <vkoul@kernel.org> 11 11 + 12 12 + description: 13 13 + The QMP PHY controller supports physical layer functionality for a number of 14 14 + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 15 15 + 16 16 + properties: 17 17 + compatible: 18 18 + enum: 19 19 + - qcom,sc8280xp-qmp-usb3-uni-phy 20 20 + 21 21 + reg: 22 22 + maxItems: 1 23 23 + 24 24 + clocks: 25 25 + maxItems: 4 26 26 + 27 27 + clock-names: 28 28 + items: 29 29 + - const: aux 30 30 + - const: ref 31 31 + - const: com_aux 32 32 + - const: pipe 33 33 + 34 34 + power-domains: 35 35 + maxItems: 1 36 36 + 37 37 + resets: 38 38 + maxItems: 2 39 39 + 40 40 + reset-names: 41 41 + items: 42 42 + - const: phy 43 43 + - const: phy_phy 44 44 + 45 45 + vdda-phy-supply: true 46 46 + 47 47 + vdda-pll-supply: true 48 48 + 49 49 + "#clock-cells": 50 50 + const: 0 51 51 + 52 52 + clock-output-names: 53 53 + maxItems: 1 54 54 + 55 55 + "#phy-cells": 56 56 + const: 0 57 57 + 58 58 + required: 59 59 + - compatible 60 60 + - reg 61 61 + - clocks 62 62 + - clock-names 63 63 + - power-domains 64 64 + - resets 65 65 + - reset-names 66 66 + - vdda-phy-supply 67 67 + - vdda-pll-supply 68 68 + - "#clock-cells" 69 69 + - clock-output-names 70 70 + - "#phy-cells" 71 71 + 72 72 + additionalProperties: false 73 73 + 74 74 + examples: 75 75 + - | 76 76 + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 77 77 + #include <dt-bindings/clock/qcom,rpmh.h> 78 78 + 79 79 + phy@88ef000 { 80 80 + compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 81 81 + reg = <0x088ef000 0x2000>; 82 82 + 83 83 + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 84 84 + <&gcc GCC_USB3_MP0_CLKREF_CLK>, 85 85 + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 86 86 + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 87 87 + clock-names = "aux", "ref", "com_aux", "pipe"; 88 88 + 89 89 + power-domains = <&gcc USB30_MP_GDSC>; 90 90 + 91 91 + resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 92 92 + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 93 93 + reset-names = "phy", "phy_phy"; 94 94 + 95 95 + vdda-phy-supply = <&vreg_l3a>; 96 96 + vdda-pll-supply = <&vreg_l5a>; 97 97 + 98 98 + #clock-cells = <0>; 99 99 + clock-output-names = "usb2_phy0_pipe_clk"; 100 100 + 101 101 + #phy-cells = <0>; 102 102 + };

+99

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP) 8 8 + 9 9 + maintainers: 10 10 + - Vinod Koul <vkoul@kernel.org> 11 11 + 12 12 + description: 13 13 + The QMP PHY controller supports physical layer functionality for a number of 14 14 + controllers on Qualcomm chipsets, such as, PCIe, UFS and USB. 15 15 + 16 16 + properties: 17 17 + compatible: 18 18 + enum: 19 19 + - qcom,sc8280xp-qmp-usb43dp-phy 20 20 + 21 21 + reg: 22 22 + maxItems: 1 23 23 + 24 24 + clocks: 25 25 + maxItems: 4 26 26 + 27 27 + clock-names: 28 28 + items: 29 29 + - const: aux 30 30 + - const: ref 31 31 + - const: com_aux 32 32 + - const: usb3_pipe 33 33 + 34 34 + power-domains: 35 35 + maxItems: 1 36 36 + 37 37 + resets: 38 38 + maxItems: 2 39 39 + 40 40 + reset-names: 41 41 + items: 42 42 + - const: phy 43 43 + - const: common 44 44 + 45 45 + vdda-phy-supply: true 46 46 + 47 47 + vdda-pll-supply: true 48 48 + 49 49 + "#clock-cells": 50 50 + const: 1 51 51 + description: 52 52 + See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h 53 53 + 54 54 + "#phy-cells": 55 55 + const: 1 56 56 + description: 57 57 + See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h 58 58 + 59 59 + required: 60 60 + - compatible 61 61 + - reg 62 62 + - clocks 63 63 + - clock-names 64 64 + - power-domains 65 65 + - resets 66 66 + - reset-names 67 67 + - vdda-phy-supply 68 68 + - vdda-pll-supply 69 69 + - "#clock-cells" 70 70 + - "#phy-cells" 71 71 + 72 72 + additionalProperties: false 73 73 + 74 74 + examples: 75 75 + - | 76 76 + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 77 77 + 78 78 + phy@88eb000 { 79 79 + compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 80 80 + reg = <0x088eb000 0x4000>; 81 81 + 82 82 + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 83 83 + <&gcc GCC_USB4_EUD_CLKREF_CLK>, 84 84 + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 85 85 + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 86 86 + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 87 87 + 88 88 + power-domains = <&gcc USB30_PRIM_GDSC>; 89 89 + 90 90 + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 91 91 + <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 92 92 + reset-names = "phy", "common"; 93 93 + 94 94 + vdda-phy-supply = <&vreg_l9d>; 95 95 + vdda-pll-supply = <&vreg_l4d>; 96 96 + 97 97 + #clock-cells = <1>; 98 98 + #phy-cells = <1>; 99 99 + };

+54

Documentation/devicetree/bindings/phy/renesas,r8a779f0-ether-serdes.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/phy/renesas,r8a779f0-ether-serdes.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Renesas Ethernet SERDES 8 8 + 9 9 + maintainers: 10 10 + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 11 11 + 12 12 + properties: 13 13 + compatible: 14 14 + const: renesas,r8a779f0-ether-serdes 15 15 + 16 16 + reg: 17 17 + maxItems: 1 18 18 + 19 19 + clocks: 20 20 + maxItems: 1 21 21 + 22 22 + resets: 23 23 + maxItems: 1 24 24 + 25 25 + power-domains: 26 26 + maxItems: 1 27 27 + 28 28 + '#phy-cells': 29 29 + description: Port number of SERDES. 30 30 + const: 1 31 31 + 32 32 + required: 33 33 + - compatible 34 34 + - reg 35 35 + - clocks 36 36 + - resets 37 37 + - power-domains 38 38 + - '#phy-cells' 39 39 + 40 40 + additionalProperties: false 41 41 + 42 42 + examples: 43 43 + - | 44 44 + #include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 45 45 + #include <dt-bindings/power/r8a779f0-sysc.h> 46 46 + 47 47 + phy@e6444000 { 48 48 + compatible = "renesas,r8a779f0-ether-serdes"; 49 49 + reg = <0xe6444000 0xc00>; 50 50 + clocks = <&cpg CPG_MOD 1506>; 51 51 + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 52 52 + resets = <&cpg 1506>; 53 53 + #phy-cells = <1>; 54 54 + };

+42 -6

Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml

reviewed

··· 54 54 - ti,dm814-phy-gmii-sel 55 55 - ti,am654-phy-gmii-sel 56 56 - ti,j7200-cpsw5g-phy-gmii-sel 57 57 + - ti,j721e-cpsw9g-phy-gmii-sel 57 58 58 59 reg: 59 60 maxItems: 1 ··· 64 63 ti,qsgmii-main-ports: 65 64 $ref: /schemas/types.yaml#/definitions/uint32-array 66 65 description: | 67 67 - Required only for QSGMII mode. Array to select the port for 68 68 - QSGMII main mode. Rest of the ports are selected as QSGMII_SUB 69 69 - ports automatically. Any one of the 4 CPSW5G ports can act as the 70 70 - main port with the rest of them being the QSGMII_SUB ports. 71 71 - maxItems: 1 66 66 + Required only for QSGMII mode. Array to select the port/s for QSGMII 67 67 + main mode. The size of the array corresponds to the number of QSGMII 68 68 + interfaces and thus, the number of distinct QSGMII main ports, 69 69 + supported by the device. If the device supports two QSGMII interfaces 70 70 + but only one QSGMII interface is desired, repeat the QSGMII main port 71 71 + value corresponding to the QSGMII interface in the array. 72 72 + minItems: 1 73 73 + maxItems: 2 72 74 items: 73 75 minimum: 1 74 74 - maximum: 4 76 76 + maximum: 8 75 77 76 78 allOf: 77 79 - if: ··· 85 81 - ti,dra7xx-phy-gmii-sel 86 82 - ti,dm814-phy-gmii-sel 87 83 - ti,am654-phy-gmii-sel 84 84 + - ti,j7200-cpsw5g-phy-gmii-sel 85 85 + - ti,j721e-cpsw9g-phy-gmii-sel 88 86 then: 89 87 properties: 90 88 '#phy-cells': 91 89 const: 1 92 90 description: CPSW port number (starting from 1) 91 91 + 92 92 + - if: 93 93 + properties: 94 94 + compatible: 95 95 + contains: 96 96 + enum: 97 97 + - ti,j7200-cpsw5g-phy-gmii-sel 98 98 + then: 99 99 + properties: 100 100 + ti,qsgmii-main-ports: 101 101 + maxItems: 1 102 102 + items: 103 103 + minimum: 1 104 104 + maximum: 4 105 105 + 106 106 + - if: 107 107 + properties: 108 108 + compatible: 109 109 + contains: 110 110 + enum: 111 111 + - ti,j721e-cpsw9g-phy-gmii-sel 112 112 + then: 113 113 + properties: 114 114 + ti,qsgmii-main-ports: 115 115 + minItems: 2 116 116 + maxItems: 2 117 117 + items: 118 118 + minimum: 1 119 119 + maximum: 8 93 120 94 121 - if: 95 122 not: ··· 129 94 contains: 130 95 enum: 131 96 - ti,j7200-cpsw5g-phy-gmii-sel 97 97 + - ti,j721e-cpsw9g-phy-gmii-sel 132 98 then: 133 99 properties: 134 100 ti,qsgmii-main-ports: false

+2

Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml

reviewed

··· 15 15 enum: 16 16 - ti,j721e-wiz-16g 17 17 - ti,j721e-wiz-10g 18 18 + - ti,j721s2-wiz-10g 18 19 - ti,am64-wiz-10g 19 20 - ti,j7200-wiz-10g 21 21 + - ti,j784s4-wiz-10g 20 22 21 23 power-domains: 22 24 maxItems: 1

+24 -1

Documentation/driver-api/phy/phy.rst

reviewed

··· 94 94 can use phy_set_drvdata() after creating the PHY and use phy_get_drvdata() in 95 95 phy_ops to get back the private data. 96 96 97 97 - 4. Getting a reference to the PHY 97 97 + Getting a reference to the PHY 98 98 + ============================== 98 99 99 100 Before the controller can make use of the PHY, it has to get a reference to 100 101 it. This framework provides the following APIs to get a reference to the PHY. ··· 130 129 the phy_init() and phy_exit() calls, and phy_power_on() and 131 130 phy_power_off() calls are all NOP when applied to a NULL phy. The NULL 132 131 phy is useful in devices for handling optional phy devices. 132 132 + 133 133 + Order of API calls 134 134 + ================== 135 135 + 136 136 + The general order of calls should be:: 137 137 + 138 138 + [devm_][of_]phy_get() 139 139 + phy_init() 140 140 + phy_power_on() 141 141 + [phy_set_mode[_ext]()] 142 142 + ... 143 143 + phy_power_off() 144 144 + phy_exit() 145 145 + [[of_]phy_put()] 146 146 + 147 147 + Some PHY drivers may not implement :c:func:`phy_init` or :c:func:`phy_power_on`, 148 148 + but controllers should always call these functions to be compatible with other 149 149 + PHYs. Some PHYs may require :c:func:`phy_set_mode <phy_set_mode_ext>`, while 150 150 + others may use a default mode (typically configured via devicetree or other 151 151 + firmware). For compatibility, you should always call this function if you know 152 152 + what mode you will be using. Generally, this function should be called after 153 153 + :c:func:`phy_power_on`, although some PHY drivers may allow it at any time. 133 154 134 155 Releasing a reference to the PHY 135 156 ================================

+5

drivers/pci/controller/dwc/pcie-qcom-ep.c

reviewed

··· 14 14 #include <linux/delay.h> 15 15 #include <linux/gpio/consumer.h> 16 16 #include <linux/mfd/syscon.h> 17 17 + #include <linux/phy/pcie.h> 17 18 #include <linux/phy/phy.h> 18 19 #include <linux/platform_device.h> 19 20 #include <linux/pm_domain.h> ··· 268 267 ret = phy_init(pcie_ep->phy); 269 268 if (ret) 270 269 goto err_disable_clk; 270 270 + 271 271 + ret = phy_set_mode_ext(pcie_ep->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_EP); 272 272 + if (ret) 273 273 + goto err_phy_exit; 271 274 272 275 ret = phy_power_on(pcie_ep->phy); 273 276 if (ret)

+5

drivers/pci/controller/dwc/pcie-qcom.c

reviewed

··· 23 23 #include <linux/pci.h> 24 24 #include <linux/pm_runtime.h> 25 25 #include <linux/platform_device.h> 26 26 + #include <linux/phy/pcie.h> 26 27 #include <linux/phy/phy.h> 27 28 #include <linux/regulator/consumer.h> 28 29 #include <linux/reset.h> ··· 1499 1498 ret = pcie->cfg->ops->init(pcie); 1500 1499 if (ret) 1501 1500 return ret; 1501 1501 + 1502 1502 + ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); 1503 1503 + if (ret) 1504 1504 + goto err_deinit; 1502 1505 1503 1506 ret = phy_power_on(pcie->phy); 1504 1507 if (ret)

+71

drivers/phy/allwinner/phy-sun4i-usb.c

reviewed

··· 120 120 u8 phyctl_offset; 121 121 bool dedicated_clocks; 122 122 bool phy0_dual_route; 123 123 + bool needs_phy2_siddq; 123 124 int missing_phys; 124 125 }; 125 126 ··· 290 289 return ret; 291 290 } 292 291 292 292 + /* Some PHYs on some SoCs need the help of PHY2 to work. */ 293 293 + if (data->cfg->needs_phy2_siddq && phy->index != 2) { 294 294 + struct sun4i_usb_phy *phy2 = &data->phys[2]; 295 295 + 296 296 + ret = clk_prepare_enable(phy2->clk); 297 297 + if (ret) { 298 298 + reset_control_assert(phy->reset); 299 299 + clk_disable_unprepare(phy->clk2); 300 300 + clk_disable_unprepare(phy->clk); 301 301 + return ret; 302 302 + } 303 303 + 304 304 + ret = reset_control_deassert(phy2->reset); 305 305 + if (ret) { 306 306 + clk_disable_unprepare(phy2->clk); 307 307 + reset_control_assert(phy->reset); 308 308 + clk_disable_unprepare(phy->clk2); 309 309 + clk_disable_unprepare(phy->clk); 310 310 + return ret; 311 311 + } 312 312 + 313 313 + /* 314 314 + * This extra clock is just needed to access the 315 315 + * REG_HCI_PHY_CTL PMU register for PHY2. 316 316 + */ 317 317 + ret = clk_prepare_enable(phy2->clk2); 318 318 + if (ret) { 319 319 + reset_control_assert(phy2->reset); 320 320 + clk_disable_unprepare(phy2->clk); 321 321 + reset_control_assert(phy->reset); 322 322 + clk_disable_unprepare(phy->clk2); 323 323 + clk_disable_unprepare(phy->clk); 324 324 + return ret; 325 325 + } 326 326 + 327 327 + if (phy2->pmu && data->cfg->hci_phy_ctl_clear) { 328 328 + val = readl(phy2->pmu + REG_HCI_PHY_CTL); 329 329 + val &= ~data->cfg->hci_phy_ctl_clear; 330 330 + writel(val, phy2->pmu + REG_HCI_PHY_CTL); 331 331 + } 332 332 + 333 333 + clk_disable_unprepare(phy->clk2); 334 334 + } 335 335 + 293 336 if (phy->pmu && data->cfg->hci_phy_ctl_clear) { 294 337 val = readl(phy->pmu + REG_HCI_PHY_CTL); 295 338 val &= ~data->cfg->hci_phy_ctl_clear; ··· 397 352 sun4i_usb_phy0_update_iscr(_phy, ISCR_DPDM_PULLUP_EN, 0); 398 353 sun4i_usb_phy0_update_iscr(_phy, ISCR_ID_PULLUP_EN, 0); 399 354 data->phy0_init = false; 355 355 + } 356 356 + 357 357 + if (data->cfg->needs_phy2_siddq && phy->index != 2) { 358 358 + struct sun4i_usb_phy *phy2 = &data->phys[2]; 359 359 + 360 360 + clk_disable_unprepare(phy2->clk); 361 361 + reset_control_assert(phy2->reset); 400 362 } 401 363 402 364 sun4i_usb_phy_passby(phy, 0); ··· 837 785 dev_err(dev, "failed to get clock %s\n", name); 838 786 return PTR_ERR(phy->clk2); 839 787 } 788 788 + } else { 789 789 + snprintf(name, sizeof(name), "pmu%d_clk", i); 790 790 + phy->clk2 = devm_clk_get_optional(dev, name); 791 791 + if (IS_ERR(phy->clk2)) { 792 792 + dev_err(dev, "failed to get clock %s\n", name); 793 793 + return PTR_ERR(phy->clk2); 794 794 + } 840 795 } 841 796 842 797 snprintf(name, sizeof(name), "usb%d_reset", i); ··· 1032 973 .missing_phys = BIT(1) | BIT(2), 1033 974 }; 1034 975 976 976 + static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = { 977 977 + .num_phys = 4, 978 978 + .type = sun50i_h6_phy, 979 979 + .disc_thresh = 3, 980 980 + .phyctl_offset = REG_PHYCTL_A33, 981 981 + .dedicated_clocks = true, 982 982 + .phy0_dual_route = true, 983 983 + .hci_phy_ctl_clear = PHY_CTL_SIDDQ, 984 984 + .needs_phy2_siddq = true, 985 985 + }; 986 986 + 1035 987 static const struct of_device_id sun4i_usb_phy_of_match[] = { 1036 988 { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg }, 1037 989 { .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg }, ··· 1058 988 { .compatible = "allwinner,sun50i-a64-usb-phy", 1059 989 .data = &sun50i_a64_cfg}, 1060 990 { .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg }, 991 991 + { .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg }, 1061 992 { }, 1062 993 }; 1063 994 MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);

+205 -31

drivers/phy/allwinner/phy-sun6i-mipi-dphy.c

reviewed

··· 70 70 71 71 #define SUN6I_DPHY_ANA0_REG 0x4c 72 72 #define SUN6I_DPHY_ANA0_REG_PWS BIT(31) 73 73 + #define SUN6I_DPHY_ANA0_REG_PWEND BIT(30) 74 74 + #define SUN6I_DPHY_ANA0_REG_PWENC BIT(29) 73 75 #define SUN6I_DPHY_ANA0_REG_DMPC BIT(28) 74 76 #define SUN6I_DPHY_ANA0_REG_DMPD(n) (((n) & 0xf) << 24) 77 77 + #define SUN6I_DPHY_ANA0_REG_SRXDT(n) (((n) & 0xf) << 20) 78 78 + #define SUN6I_DPHY_ANA0_REG_SRXCK(n) (((n) & 0xf) << 16) 79 79 + #define SUN6I_DPHY_ANA0_REG_SDIV2 BIT(15) 75 80 #define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12) 76 81 #define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8) 82 82 + #define SUN6I_DPHY_ANA0_REG_PLR(n) (((n) & 0xf) << 4) 77 83 #define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2) 84 84 + #define SUN6I_DPHY_ANA0_REG_RSD BIT(1) 85 85 + #define SUN6I_DPHY_ANA0_REG_SELSCK BIT(0) 78 86 79 87 #define SUN6I_DPHY_ANA1_REG 0x50 80 88 #define SUN6I_DPHY_ANA1_REG_VTTMODE BIT(31) ··· 105 97 #define SUN6I_DPHY_ANA3_EN_LDOR BIT(18) 106 98 107 99 #define SUN6I_DPHY_ANA4_REG 0x5c 100 100 + #define SUN6I_DPHY_ANA4_REG_EN_MIPI BIT(31) 101 101 + #define SUN6I_DPHY_ANA4_REG_EN_COMTEST BIT(30) 102 102 + #define SUN6I_DPHY_ANA4_REG_COMTEST(n) (((n) & 3) << 28) 103 103 + #define SUN6I_DPHY_ANA4_REG_IB(n) (((n) & 3) << 25) 108 104 #define SUN6I_DPHY_ANA4_REG_DMPLVC BIT(24) 109 105 #define SUN6I_DPHY_ANA4_REG_DMPLVD(n) (((n) & 0xf) << 20) 106 106 + #define SUN6I_DPHY_ANA4_REG_VTT_SET(n) (((n) & 0x7) << 17) 110 107 #define SUN6I_DPHY_ANA4_REG_CKDV(n) (((n) & 0x1f) << 12) 111 108 #define SUN6I_DPHY_ANA4_REG_TMSC(n) (((n) & 3) << 10) 112 109 #define SUN6I_DPHY_ANA4_REG_TMSD(n) (((n) & 3) << 8) ··· 122 109 123 110 #define SUN6I_DPHY_DBG5_REG 0xf4 124 111 112 112 + #define SUN50I_DPHY_TX_SLEW_REG0 0xf8 113 113 + #define SUN50I_DPHY_TX_SLEW_REG1 0xfc 114 114 + #define SUN50I_DPHY_TX_SLEW_REG2 0x100 115 115 + 116 116 + #define SUN50I_DPHY_PLL_REG0 0x104 117 117 + #define SUN50I_DPHY_PLL_REG0_CP36_EN BIT(23) 118 118 + #define SUN50I_DPHY_PLL_REG0_LDO_EN BIT(22) 119 119 + #define SUN50I_DPHY_PLL_REG0_EN_LVS BIT(21) 120 120 + #define SUN50I_DPHY_PLL_REG0_PLL_EN BIT(20) 121 121 + #define SUN50I_DPHY_PLL_REG0_P(n) (((n) & 0xf) << 16) 122 122 + #define SUN50I_DPHY_PLL_REG0_N(n) (((n) & 0xff) << 8) 123 123 + #define SUN50I_DPHY_PLL_REG0_NDET BIT(7) 124 124 + #define SUN50I_DPHY_PLL_REG0_TDIV BIT(6) 125 125 + #define SUN50I_DPHY_PLL_REG0_M0(n) (((n) & 3) << 4) 126 126 + #define SUN50I_DPHY_PLL_REG0_M1(n) ((n) & 0xf) 127 127 + 128 128 + #define SUN50I_DPHY_PLL_REG1 0x108 129 129 + #define SUN50I_DPHY_PLL_REG1_UNLOCK_MDSEL(n) (((n) & 3) << 14) 130 130 + #define SUN50I_DPHY_PLL_REG1_LOCKMDSEL BIT(13) 131 131 + #define SUN50I_DPHY_PLL_REG1_LOCKDET_EN BIT(12) 132 132 + #define SUN50I_DPHY_PLL_REG1_VSETA(n) (((n) & 0x7) << 9) 133 133 + #define SUN50I_DPHY_PLL_REG1_VSETD(n) (((n) & 0x7) << 6) 134 134 + #define SUN50I_DPHY_PLL_REG1_LPF_SW BIT(5) 135 135 + #define SUN50I_DPHY_PLL_REG1_ICP_SEL(n) (((n) & 3) << 3) 136 136 + #define SUN50I_DPHY_PLL_REG1_ATEST_SEL(n) (((n) & 3) << 1) 137 137 + #define SUN50I_DPHY_PLL_REG1_TEST_EN BIT(0) 138 138 + 139 139 + #define SUN50I_DPHY_PLL_REG2 0x10c 140 140 + #define SUN50I_DPHY_PLL_REG2_SDM_EN BIT(31) 141 141 + #define SUN50I_DPHY_PLL_REG2_FF_EN BIT(30) 142 142 + #define SUN50I_DPHY_PLL_REG2_SS_EN BIT(29) 143 143 + #define SUN50I_DPHY_PLL_REG2_SS_FRAC(n) (((n) & 0x1ff) << 20) 144 144 + #define SUN50I_DPHY_PLL_REG2_SS_INT(n) (((n) & 0xff) << 12) 145 145 + #define SUN50I_DPHY_PLL_REG2_FRAC(n) ((n) & 0xfff) 146 146 + 147 147 + #define SUN50I_COMBO_PHY_REG0 0x110 148 148 + #define SUN50I_COMBO_PHY_REG0_EN_TEST_COMBOLDO BIT(5) 149 149 + #define SUN50I_COMBO_PHY_REG0_EN_TEST_0P8 BIT(4) 150 150 + #define SUN50I_COMBO_PHY_REG0_EN_MIPI BIT(3) 151 151 + #define SUN50I_COMBO_PHY_REG0_EN_LVDS BIT(2) 152 152 + #define SUN50I_COMBO_PHY_REG0_EN_COMBOLDO BIT(1) 153 153 + #define SUN50I_COMBO_PHY_REG0_EN_CP BIT(0) 154 154 + 155 155 + #define SUN50I_COMBO_PHY_REG1 0x114 156 156 + #define SUN50I_COMBO_PHY_REG2_REG_VREF1P6(n) (((n) & 0x7) << 4) 157 157 + #define SUN50I_COMBO_PHY_REG2_REG_VREF0P8(n) ((n) & 0x7) 158 158 + 159 159 + #define SUN50I_COMBO_PHY_REG2 0x118 160 160 + #define SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(n) ((n) & 0xff) 161 161 + 125 162 enum sun6i_dphy_direction { 126 163 SUN6I_DPHY_DIRECTION_TX, 127 164 SUN6I_DPHY_DIRECTION_RX, 165 165 + }; 166 166 + 167 167 + struct sun6i_dphy; 168 168 + 169 169 + struct sun6i_dphy_variant { 170 170 + void (*tx_power_on)(struct sun6i_dphy *dphy); 171 171 + bool rx_supported; 128 172 }; 129 173 130 174 struct sun6i_dphy { ··· 193 123 struct phy *phy; 194 124 struct phy_configure_opts_mipi_dphy config; 195 125 126 126 + const struct sun6i_dphy_variant *variant; 196 127 enum sun6i_dphy_direction direction; 197 128 }; 198 129 ··· 222 151 return 0; 223 152 } 224 153 225 225 - static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) 154 154 + static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy) 226 155 { 227 156 u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0); 228 228 - 229 229 - regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG, 230 230 - SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT); 231 231 - 232 232 - regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG, 233 233 - SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) | 234 234 - SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) | 235 235 - SUN6I_DPHY_TX_TIME0_HS_TRAIL(10)); 236 236 - 237 237 - regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG, 238 238 - SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) | 239 239 - SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) | 240 240 - SUN6I_DPHY_TX_TIME1_CLK_PRE(3) | 241 241 - SUN6I_DPHY_TX_TIME1_CLK_POST(10)); 242 242 - 243 243 - regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG, 244 244 - SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30)); 245 245 - 246 246 - regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0); 247 247 - 248 248 - regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG, 249 249 - SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) | 250 250 - SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3)); 251 251 - 252 252 - regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, 253 253 - SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) | 254 254 - SUN6I_DPHY_GCTL_EN); 255 157 256 158 regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, 257 159 SUN6I_DPHY_ANA0_REG_PWS | ··· 257 213 SUN6I_DPHY_ANA3_EN_LDOC | 258 214 SUN6I_DPHY_ANA3_EN_LDOD); 259 215 udelay(1); 216 216 + } 217 217 + 218 218 + static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy) 219 219 + { 220 220 + unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate; 221 221 + unsigned int div, n; 222 222 + 223 223 + regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG, 224 224 + SUN6I_DPHY_ANA4_REG_IB(2) | 225 225 + SUN6I_DPHY_ANA4_REG_DMPLVD(4) | 226 226 + SUN6I_DPHY_ANA4_REG_VTT_SET(3) | 227 227 + SUN6I_DPHY_ANA4_REG_CKDV(3) | 228 228 + SUN6I_DPHY_ANA4_REG_TMSD(1) | 229 229 + SUN6I_DPHY_ANA4_REG_TMSC(1) | 230 230 + SUN6I_DPHY_ANA4_REG_TXPUSD(2) | 231 231 + SUN6I_DPHY_ANA4_REG_TXPUSC(3) | 232 232 + SUN6I_DPHY_ANA4_REG_TXDNSD(2) | 233 233 + SUN6I_DPHY_ANA4_REG_TXDNSC(3)); 234 234 + 235 235 + regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG, 236 236 + SUN6I_DPHY_ANA2_EN_CK_CPU, 237 237 + SUN6I_DPHY_ANA2_EN_CK_CPU); 238 238 + 239 239 + regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG, 240 240 + SUN6I_DPHY_ANA2_REG_ENIB, 241 241 + SUN6I_DPHY_ANA2_REG_ENIB); 242 242 + 243 243 + regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG, 244 244 + SUN6I_DPHY_ANA3_EN_LDOR | 245 245 + SUN6I_DPHY_ANA3_EN_LDOC | 246 246 + SUN6I_DPHY_ANA3_EN_LDOD); 247 247 + 248 248 + regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, 249 249 + SUN6I_DPHY_ANA0_REG_PLR(4) | 250 250 + SUN6I_DPHY_ANA0_REG_SFB(1)); 251 251 + 252 252 + regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0, 253 253 + SUN50I_COMBO_PHY_REG0_EN_CP); 254 254 + 255 255 + /* Choose a divider to limit the VCO frequency to around 2 GHz. */ 256 256 + div = 16 >> order_base_2(DIV_ROUND_UP(mipi_symbol_rate, 264000000)); 257 257 + n = mipi_symbol_rate * div / 24000000; 258 258 + 259 259 + regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG0, 260 260 + SUN50I_DPHY_PLL_REG0_CP36_EN | 261 261 + SUN50I_DPHY_PLL_REG0_LDO_EN | 262 262 + SUN50I_DPHY_PLL_REG0_EN_LVS | 263 263 + SUN50I_DPHY_PLL_REG0_PLL_EN | 264 264 + SUN50I_DPHY_PLL_REG0_NDET | 265 265 + SUN50I_DPHY_PLL_REG0_P((div - 1) % 8) | 266 266 + SUN50I_DPHY_PLL_REG0_N(n) | 267 267 + SUN50I_DPHY_PLL_REG0_M0((div - 1) / 8) | 268 268 + SUN50I_DPHY_PLL_REG0_M1(2)); 269 269 + 270 270 + /* Disable sigma-delta modulation. */ 271 271 + regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0); 272 272 + 273 273 + regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG, 274 274 + SUN6I_DPHY_ANA4_REG_EN_MIPI, 275 275 + SUN6I_DPHY_ANA4_REG_EN_MIPI); 276 276 + 277 277 + regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0, 278 278 + SUN50I_COMBO_PHY_REG0_EN_MIPI | 279 279 + SUN50I_COMBO_PHY_REG0_EN_COMBOLDO, 280 280 + SUN50I_COMBO_PHY_REG0_EN_MIPI | 281 281 + SUN50I_COMBO_PHY_REG0_EN_COMBOLDO); 282 282 + 283 283 + regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG2, 284 284 + SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(20)); 285 285 + udelay(1); 286 286 + } 287 287 + 288 288 + static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) 289 289 + { 290 290 + u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0); 291 291 + 292 292 + regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG, 293 293 + SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT); 294 294 + 295 295 + regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG, 296 296 + SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) | 297 297 + SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) | 298 298 + SUN6I_DPHY_TX_TIME0_HS_TRAIL(10)); 299 299 + 300 300 + regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG, 301 301 + SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) | 302 302 + SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) | 303 303 + SUN6I_DPHY_TX_TIME1_CLK_PRE(3) | 304 304 + SUN6I_DPHY_TX_TIME1_CLK_POST(10)); 305 305 + 306 306 + regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG, 307 307 + SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30)); 308 308 + 309 309 + regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0); 310 310 + 311 311 + regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG, 312 312 + SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) | 313 313 + SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3)); 314 314 + 315 315 + dphy->variant->tx_power_on(dphy); 260 316 261 317 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG, 262 318 SUN6I_DPHY_ANA3_EN_VTTC | ··· 382 238 regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG, 383 239 SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK, 384 240 SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask)); 241 241 + 242 242 + regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, 243 243 + SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) | 244 244 + SUN6I_DPHY_GCTL_EN); 385 245 386 246 return 0; 387 247 } ··· 541 393 .reg_bits = 32, 542 394 .val_bits = 32, 543 395 .reg_stride = 4, 544 544 - .max_register = SUN6I_DPHY_DBG5_REG, 396 396 + .max_register = SUN50I_COMBO_PHY_REG2, 545 397 .name = "mipi-dphy", 546 398 }; 547 399 ··· 556 408 dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL); 557 409 if (!dphy) 558 410 return -ENOMEM; 411 411 + 412 412 + dphy->variant = device_get_match_data(&pdev->dev); 413 413 + if (!dphy->variant) 414 414 + return -EINVAL; 559 415 560 416 regs = devm_platform_ioremap_resource(pdev, 0); 561 417 if (IS_ERR(regs)) { ··· 597 445 ret = of_property_read_string(pdev->dev.of_node, "allwinner,direction", 598 446 &direction); 599 447 600 600 - if (!ret && !strncmp(direction, "rx", 2)) 448 448 + if (!ret && !strncmp(direction, "rx", 2)) { 449 449 + if (!dphy->variant->rx_supported) { 450 450 + dev_err(&pdev->dev, "RX not supported on this variant\n"); 451 451 + return -EOPNOTSUPP; 452 452 + } 453 453 + 601 454 dphy->direction = SUN6I_DPHY_DIRECTION_RX; 455 455 + } 602 456 603 457 phy_set_drvdata(dphy->phy, dphy); 604 458 phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate); ··· 612 454 return PTR_ERR_OR_ZERO(phy_provider); 613 455 } 614 456 457 457 + static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = { 458 458 + .tx_power_on = sun6i_a31_mipi_dphy_tx_power_on, 459 459 + .rx_supported = true, 460 460 + }; 461 461 + 462 462 + static const struct sun6i_dphy_variant sun50i_a100_mipi_dphy_variant = { 463 463 + .tx_power_on = sun50i_a100_mipi_dphy_tx_power_on, 464 464 + }; 465 465 + 615 466 static const struct of_device_id sun6i_dphy_of_table[] = { 616 616 - { .compatible = "allwinner,sun6i-a31-mipi-dphy" }, 467 467 + { 468 468 + .compatible = "allwinner,sun6i-a31-mipi-dphy", 469 469 + .data = &sun6i_a31_mipi_dphy_variant, 470 470 + }, 471 471 + { 472 472 + .compatible = "allwinner,sun50i-a100-mipi-dphy", 473 473 + .data = &sun50i_a100_mipi_dphy_variant, 474 474 + }, 617 475 { } 618 476 }; 619 477 MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);

+49 -46

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

reviewed

··· 18 18 #define PIARBCTL_CAM 0x00 19 19 #define PIARBCTL_SPLITTER 0x04 20 20 #define PIARBCTL_MISC 0x08 21 21 - #define PIARBCTL_MISC_SECURE_MASK 0x80000000 22 22 - #define PIARBCTL_MISC_USB_SELECT_MASK 0x40000000 23 23 - #define PIARBCTL_MISC_USB_4G_SDRAM_MASK 0x20000000 24 24 - #define PIARBCTL_MISC_USB_PRIORITY_MASK 0x000f0000 25 25 - #define PIARBCTL_MISC_USB_MEM_PAGE_MASK 0x0000f000 26 26 - #define PIARBCTL_MISC_CAM1_MEM_PAGE_MASK 0x00000f00 27 27 - #define PIARBCTL_MISC_CAM0_MEM_PAGE_MASK 0x000000f0 28 28 - #define PIARBCTL_MISC_SATA_PRIORITY_MASK 0x0000000f 21 21 + #define PIARBCTL_MISC_SATA_PRIORITY_MASK GENMASK(3, 0) 22 22 + #define PIARBCTL_MISC_CAM0_MEM_PAGE_MASK GENMASK(7, 4) 23 23 + #define PIARBCTL_MISC_CAM1_MEM_PAGE_MASK GENMASK(11, 8) 24 24 + #define PIARBCTL_MISC_USB_MEM_PAGE_MASK GENMASK(15, 12) 25 25 + #define PIARBCTL_MISC_USB_PRIORITY_MASK GENMASK(19, 16) 26 26 + #define PIARBCTL_MISC_USB_4G_SDRAM_MASK BIT(29) 27 27 + #define PIARBCTL_MISC_USB_SELECT_MASK BIT(30) 28 28 + #define PIARBCTL_MISC_SECURE_MASK BIT(31) 29 29 30 30 #define PIARBCTL_MISC_USB_ONLY_MASK \ 31 31 (PIARBCTL_MISC_USB_SELECT_MASK | \ ··· 35 35 36 36 /* Register definitions for the USB CTRL block */ 37 37 #define USB_CTRL_SETUP 0x00 38 38 - #define USB_CTRL_SETUP_STRAP_IPP_SEL_MASK 0x02000000 39 39 - #define USB_CTRL_SETUP_SCB2_EN_MASK 0x00008000 40 40 - #define USB_CTRL_SETUP_tca_drv_sel_MASK 0x01000000 41 41 - #define USB_CTRL_SETUP_SCB1_EN_MASK 0x00004000 42 42 - #define USB_CTRL_SETUP_SOFT_SHUTDOWN_MASK 0x00000200 43 43 - #define USB_CTRL_SETUP_IPP_MASK 0x00000020 44 44 - #define USB_CTRL_SETUP_IOC_MASK 0x00000010 38 38 + #define USB_CTRL_SETUP_IOC_MASK BIT(4) 39 39 + #define USB_CTRL_SETUP_IPP_MASK BIT(5) 40 40 + #define USB_CTRL_SETUP_SOFT_SHUTDOWN_MASK BIT(9) 41 41 + #define USB_CTRL_SETUP_SCB1_EN_MASK BIT(14) 42 42 + #define USB_CTRL_SETUP_SCB2_EN_MASK BIT(15) 43 43 + #define USB_CTRL_SETUP_tca_drv_sel_MASK BIT(24) 44 44 + #define USB_CTRL_SETUP_STRAP_IPP_SEL_MASK BIT(25) 45 45 #define USB_CTRL_USB_PM 0x04 46 46 - #define USB_CTRL_USB_PM_USB_PWRDN_MASK 0x80000000 47 47 - #define USB_CTRL_USB_PM_SOFT_RESET_MASK 0x40000000 48 48 - #define USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK 0x00800000 49 49 - #define USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK 0x00400000 50 50 - #define USB_CTRL_USB_PM_XHC_PME_EN_MASK 0x00000010 51 51 - #define USB_CTRL_USB_PM_XHC_S2_CLK_SWITCH_EN_MASK 0x00000008 46 46 + #define USB_CTRL_USB_PM_XHC_S2_CLK_SWITCH_EN_MASK BIT(3) 47 47 + #define USB_CTRL_USB_PM_XHC_PME_EN_MASK BIT(4) 48 48 + #define USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK BIT(22) 49 49 + #define USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK BIT(23) 50 50 + #define USB_CTRL_USB_PM_SOFT_RESET_MASK BIT(30) 51 51 + #define USB_CTRL_USB_PM_USB_PWRDN_MASK BIT(31) 52 52 #define USB_CTRL_USB_PM_STATUS 0x08 53 53 #define USB_CTRL_USB_DEVICE_CTL1 0x10 54 54 - #define USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK 0x00000003 54 54 + #define USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK GENMASK(1, 0) 55 55 #define USB_CTRL_TEST_PORT_CTL 0x30 56 56 - #define USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK 0x000000ff 56 56 + #define USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK GENMASK(7, 0) 57 57 #define USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_PME_GEN_MASK 0x0000002e 58 58 #define USB_CTRL_TP_DIAG1 0x34 59 59 - #define USB_CTLR_TP_DIAG1_wake_MASK 0x00000002 59 59 + #define USB_CTLR_TP_DIAG1_wake_MASK BIT(1) 60 60 #define USB_CTRL_CTLR_CSHCR 0x50 61 61 - #define USB_CTRL_CTLR_CSHCR_ctl_pme_en_MASK 0x00040000 61 61 + #define USB_CTRL_CTLR_CSHCR_ctl_pme_en_MASK BIT(18) 62 62 63 63 /* Register definitions for the USB_PHY block in 7211b0 */ 64 64 #define USB_PHY_PLL_CTL 0x00 65 65 - #define USB_PHY_PLL_CTL_PLL_RESETB_MASK 0x40000000 65 65 + #define USB_PHY_PLL_CTL_PLL_SUSPEND_MASK BIT(27) 66 66 + #define USB_PHY_PLL_CTL_PLL_RESETB_MASK BIT(30) 66 67 #define USB_PHY_PLL_LDO_CTL 0x08 67 67 - #define USB_PHY_PLL_LDO_CTL_AFE_CORERDY_MASK 0x00000004 68 68 - #define USB_PHY_PLL_LDO_CTL_AFE_LDO_PWRDWNB_MASK 0x00000002 69 69 - #define USB_PHY_PLL_LDO_CTL_AFE_BG_PWRDWNB_MASK 0x00000001 68 68 + #define USB_PHY_PLL_LDO_CTL_AFE_BG_PWRDWNB_MASK BIT(0) 69 69 + #define USB_PHY_PLL_LDO_CTL_AFE_LDO_PWRDWNB_MASK BIT(1) 70 70 + #define USB_PHY_PLL_LDO_CTL_AFE_CORERDY_MASK BIT(2) 70 71 #define USB_PHY_UTMI_CTL_1 0x04 71 71 - #define USB_PHY_UTMI_CTL_1_POWER_UP_FSM_EN_MASK 0x00000800 72 72 - #define USB_PHY_UTMI_CTL_1_PHY_MODE_MASK 0x0000000c 72 72 + #define USB_PHY_UTMI_CTL_1_PHY_MODE_MASK GENMASK(3, 2) 73 73 #define USB_PHY_UTMI_CTL_1_PHY_MODE_SHIFT 2 74 74 + #define USB_PHY_UTMI_CTL_1_POWER_UP_FSM_EN_MASK BIT(11) 74 75 #define USB_PHY_IDDQ 0x1c 75 75 - #define USB_PHY_IDDQ_phy_iddq_MASK 0x00000001 76 76 + #define USB_PHY_IDDQ_phy_iddq_MASK BIT(0) 76 77 #define USB_PHY_STATUS 0x20 77 77 - #define USB_PHY_STATUS_pll_lock_MASK 0x00000001 78 78 + #define USB_PHY_STATUS_pll_lock_MASK BIT(0) 78 79 79 80 /* Register definitions for the MDIO registers in the DWC2 block of 80 81 * the 7211b0. ··· 87 86 88 87 /* Register definitions for the BDC EC block in 7211b0 */ 89 88 #define BDC_EC_AXIRDA 0x0c 90 90 - #define BDC_EC_AXIRDA_RTS_MASK 0xf0000000 89 89 + #define BDC_EC_AXIRDA_RTS_MASK GENMASK(31, 28) 91 90 #define BDC_EC_AXIRDA_RTS_SHIFT 28 92 91 93 92 ··· 196 195 if (USB_CTRL_MASK(USB_DEVICE_CTL1, PORT_MODE)) { 197 196 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 198 197 reg &= ~USB_CTRL_MASK(USB_DEVICE_CTL1, PORT_MODE); 199 199 - reg |= params->mode; 198 198 + reg |= params->port_mode; 200 199 brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 201 200 } 202 202 - switch (params->mode) { 201 201 + switch (params->supported_port_modes) { 203 202 case USB_CTLR_MODE_HOST: 204 203 USB_CTRL_UNSET(ctrl, USB_PM, BDC_SOFT_RESETB); 205 204 break; ··· 260 259 brcm_usb_writel(reg, usb_phy + USB_PHY_UTMI_CTL_1); 261 260 } 262 261 262 262 + /* Disable PLL auto suspend */ 263 263 + reg = brcm_usb_readl(usb_phy + USB_PHY_PLL_CTL); 264 264 + reg |= USB_PHY_PLL_CTL_PLL_SUSPEND_MASK; 265 265 + brcm_usb_writel(reg, usb_phy + USB_PHY_PLL_CTL); 266 266 + 263 267 /* Init the PHY */ 264 268 reg = USB_PHY_PLL_LDO_CTL_AFE_CORERDY_MASK | 265 269 USB_PHY_PLL_LDO_CTL_AFE_LDO_PWRDWNB_MASK | ··· 282 276 /* Set the PHY_MODE */ 283 277 reg = brcm_usb_readl(usb_phy + USB_PHY_UTMI_CTL_1); 284 278 reg &= ~USB_PHY_UTMI_CTL_1_PHY_MODE_MASK; 285 285 - reg |= params->mode << USB_PHY_UTMI_CTL_1_PHY_MODE_SHIFT; 279 279 + reg |= params->supported_port_modes << USB_PHY_UTMI_CTL_1_PHY_MODE_SHIFT; 286 280 brcm_usb_writel(reg, usb_phy + USB_PHY_UTMI_CTL_1); 287 281 288 282 usb_init_common(params); ··· 292 286 * the default "Read Transaction Size" of 6 (1024 bytes). 293 287 * Set it to 4 (256 bytes). 294 288 */ 295 295 - if ((params->mode != USB_CTLR_MODE_HOST) && bdc_ec) { 289 289 + if ((params->supported_port_modes != USB_CTLR_MODE_HOST) && bdc_ec) { 296 290 reg = brcm_usb_readl(bdc_ec + BDC_EC_AXIRDA); 297 291 reg &= ~BDC_EC_AXIRDA_RTS_MASK; 298 292 reg |= (0x4 << BDC_EC_AXIRDA_RTS_SHIFT); ··· 337 331 338 332 pr_debug("%s\n", __func__); 339 333 340 340 - if (!params->wake_enabled) { 341 341 - USB_CTRL_SET(ctrl, USB_PM, USB_PWRDN); 342 342 - 334 334 + if (params->wake_enabled) { 343 335 /* Switch to using slower clock during suspend to save power */ 344 336 USB_CTRL_SET(ctrl, USB_PM, XHC_S2_CLK_SWITCH_EN); 345 345 - } else { 346 337 usb_wake_enable_7216(params, true); 338 338 + } else { 339 339 + USB_CTRL_SET(ctrl, USB_PM, USB_PWRDN); 347 340 } 348 341 } 349 342 ··· 390 385 return reg; 391 386 } 392 387 393 393 - static void usb_set_dual_select(struct brcm_usb_init_params *params, int mode) 388 388 + static void usb_set_dual_select(struct brcm_usb_init_params *params) 394 389 { 395 390 void __iomem *ctrl = params->regs[BRCM_REGS_CTRL]; 396 391 u32 reg; ··· 399 394 400 395 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 401 396 reg &= ~USB_CTRL_MASK(USB_DEVICE_CTL1, PORT_MODE); 402 402 - reg |= mode; 397 397 + reg |= params->port_mode; 403 398 brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 404 399 } 405 400 ··· 430 425 431 426 params->family_name = "7216"; 432 427 params->ops = &bcm7216_ops; 433 433 - params->suspend_with_clocks = true; 434 428 } 435 429 436 430 void brcm_usb_dvr_init_7211b0(struct brcm_usb_init_params *params) ··· 439 435 440 436 params->family_name = "7211"; 441 437 params->ops = &bcm7211b0_ops; 442 442 - params->suspend_with_clocks = true; 443 438 }

+45 -45

drivers/phy/broadcom/phy-brcm-usb-init.c

reviewed

··· 21 21 22 22 /* Register definitions for the USB CTRL block */ 23 23 #define USB_CTRL_SETUP 0x00 24 24 - #define USB_CTRL_SETUP_IOC_MASK 0x00000010 25 25 - #define USB_CTRL_SETUP_IPP_MASK 0x00000020 26 26 - #define USB_CTRL_SETUP_BABO_MASK 0x00000001 27 27 - #define USB_CTRL_SETUP_FNHW_MASK 0x00000002 28 28 - #define USB_CTRL_SETUP_FNBO_MASK 0x00000004 29 29 - #define USB_CTRL_SETUP_WABO_MASK 0x00000008 30 30 - #define USB_CTRL_SETUP_SCB_CLIENT_SWAP_MASK 0x00002000 /* option */ 31 31 - #define USB_CTRL_SETUP_SCB1_EN_MASK 0x00004000 /* option */ 32 32 - #define USB_CTRL_SETUP_SCB2_EN_MASK 0x00008000 /* option */ 33 33 - #define USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK 0X00020000 /* option */ 34 34 - #define USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK 0x00010000 /* option */ 35 35 - #define USB_CTRL_SETUP_STRAP_IPP_SEL_MASK 0x02000000 /* option */ 36 36 - #define USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK 0x04000000 /* option */ 37 37 - #define USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK 0x08000000 /* opt */ 38 38 - #define USB_CTRL_SETUP_OC3_DISABLE_MASK 0xc0000000 /* option */ 24 24 + #define USB_CTRL_SETUP_BABO_MASK BIT(0) 25 25 + #define USB_CTRL_SETUP_FNHW_MASK BIT(1) 26 26 + #define USB_CTRL_SETUP_FNBO_MASK BIT(2) 27 27 + #define USB_CTRL_SETUP_WABO_MASK BIT(3) 28 28 + #define USB_CTRL_SETUP_IOC_MASK BIT(4) 29 29 + #define USB_CTRL_SETUP_IPP_MASK BIT(5) 30 30 + #define USB_CTRL_SETUP_SCB_CLIENT_SWAP_MASK BIT(13) /* option */ 31 31 + #define USB_CTRL_SETUP_SCB1_EN_MASK BIT(14) /* option */ 32 32 + #define USB_CTRL_SETUP_SCB2_EN_MASK BIT(15) /* option */ 33 33 + #define USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK BIT(17) /* option */ 34 34 + #define USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK BIT(16) /* option */ 35 35 + #define USB_CTRL_SETUP_STRAP_IPP_SEL_MASK BIT(25) /* option */ 36 36 + #define USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK BIT(26) /* option */ 37 37 + #define USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK BIT(27) /* opt */ 38 38 + #define USB_CTRL_SETUP_OC3_DISABLE_MASK GENMASK(31, 30) /* option */ 39 39 #define USB_CTRL_PLL_CTL 0x04 40 40 - #define USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK 0x08000000 41 41 - #define USB_CTRL_PLL_CTL_PLL_RESETB_MASK 0x40000000 42 42 - #define USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK 0x80000000 /* option */ 40 40 + #define USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK BIT(27) 41 41 + #define USB_CTRL_PLL_CTL_PLL_RESETB_MASK BIT(30) 42 42 + #define USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK BIT(31) /* option */ 43 43 #define USB_CTRL_EBRIDGE 0x0c 44 44 - #define USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK 0x00020000 /* option */ 45 45 - #define USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK 0x00000f80 /* option */ 44 44 + #define USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK GENMASK(11, 7) /* option */ 45 45 + #define USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK BIT(17) /* option */ 46 46 #define USB_CTRL_OBRIDGE 0x10 47 47 - #define USB_CTRL_OBRIDGE_LS_KEEP_ALIVE_MASK 0x08000000 47 47 + #define USB_CTRL_OBRIDGE_LS_KEEP_ALIVE_MASK BIT(27) 48 48 #define USB_CTRL_MDIO 0x14 49 49 #define USB_CTRL_MDIO2 0x18 50 50 #define USB_CTRL_UTMI_CTL_1 0x2c 51 51 - #define USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK 0x00000800 52 52 - #define USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK 0x08000000 51 51 + #define USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK BIT(11) 52 52 + #define USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK BIT(27) 53 53 #define USB_CTRL_USB_PM 0x34 54 54 - #define USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK 0x00800000 /* option */ 55 55 - #define USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK 0x00400000 /* option */ 56 56 - #define USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK 0x40000000 /* option */ 57 57 - #define USB_CTRL_USB_PM_USB_PWRDN_MASK 0x80000000 /* option */ 58 58 - #define USB_CTRL_USB_PM_SOFT_RESET_MASK 0x40000000 /* option */ 59 59 - #define USB_CTRL_USB_PM_USB20_HC_RESETB_MASK 0x30000000 /* option */ 60 60 - #define USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK 0x00300000 /* option */ 61 61 - #define USB_CTRL_USB_PM_RMTWKUP_EN_MASK 0x00000001 54 54 + #define USB_CTRL_USB_PM_RMTWKUP_EN_MASK BIT(0) 55 55 + #define USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK GENMASK(21, 20) /* option */ 56 56 + #define USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK BIT(22) /* option */ 57 57 + #define USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK BIT(23) /* option */ 58 58 + #define USB_CTRL_USB_PM_USB20_HC_RESETB_MASK GENMASK(29, 28) /* option */ 59 59 + #define USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK BIT(30) /* option */ 60 60 + #define USB_CTRL_USB_PM_SOFT_RESET_MASK BIT(30) /* option */ 61 61 + #define USB_CTRL_USB_PM_USB_PWRDN_MASK BIT(31) /* option */ 62 62 #define USB_CTRL_USB_PM_STATUS 0x38 63 63 #define USB_CTRL_USB30_CTL1 0x60 64 64 - #define USB_CTRL_USB30_CTL1_PHY3_PLL_SEQ_START_MASK 0x00000010 65 65 - #define USB_CTRL_USB30_CTL1_PHY3_RESETB_MASK 0x00010000 66 66 - #define USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK 0x00020000 /* option */ 67 67 - #define USB_CTRL_USB30_CTL1_USB3_IOC_MASK 0x10000000 /* option */ 68 68 - #define USB_CTRL_USB30_CTL1_USB3_IPP_MASK 0x20000000 /* option */ 64 64 + #define USB_CTRL_USB30_CTL1_PHY3_PLL_SEQ_START_MASK BIT(4) 65 65 + #define USB_CTRL_USB30_CTL1_PHY3_RESETB_MASK BIT(16) 66 66 + #define USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK BIT(17) /* option */ 67 67 + #define USB_CTRL_USB30_CTL1_USB3_IOC_MASK BIT(28) /* option */ 68 68 + #define USB_CTRL_USB30_CTL1_USB3_IPP_MASK BIT(29) /* option */ 69 69 #define USB_CTRL_USB30_PCTL 0x70 70 70 - #define USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK 0x00000002 71 71 - #define USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK 0x00008000 72 72 - #define USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK 0x00020000 70 70 + #define USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK BIT(1) 71 71 + #define USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK BIT(15) 72 72 + #define USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK BIT(17) 73 73 #define USB_CTRL_USB_DEVICE_CTL1 0x90 74 74 - #define USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK 0x00000003 /* option */ 74 74 + #define USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK GENMASK(1, 0) /* option */ 75 75 76 76 /* Register definitions for the XHCI EC block */ 77 77 #define USB_XHCI_EC_IRAADR 0x658 ··· 876 876 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 877 877 reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, 878 878 PORT_MODE); 879 879 - reg |= params->mode; 879 879 + reg |= params->port_mode; 880 880 brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 881 881 } 882 882 if (USB_CTRL_MASK_FAMILY(params, USB_PM, BDC_SOFT_RESETB)) { 883 883 - switch (params->mode) { 883 883 + switch (params->supported_port_modes) { 884 884 case USB_CTLR_MODE_HOST: 885 885 USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB); 886 886 break; ··· 891 891 } 892 892 } 893 893 if (USB_CTRL_MASK_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE)) { 894 894 - if (params->mode == USB_CTLR_MODE_TYPEC_PD) 894 894 + if (params->supported_port_modes == USB_CTLR_MODE_TYPEC_PD) 895 895 USB_CTRL_SET_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE); 896 896 else 897 897 USB_CTRL_UNSET_FAMILY(params, SETUP, ··· 1000 1000 return reg; 1001 1001 } 1002 1002 1003 1003 - static void usb_set_dual_select(struct brcm_usb_init_params *params, int mode) 1003 1003 + static void usb_set_dual_select(struct brcm_usb_init_params *params) 1004 1004 { 1005 1005 void __iomem *ctrl = params->regs[BRCM_REGS_CTRL]; 1006 1006 u32 reg; ··· 1011 1011 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 1012 1012 reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, 1013 1013 PORT_MODE); 1014 1014 - reg |= mode; 1014 1014 + reg |= params->port_mode; 1015 1015 brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); 1016 1016 } 1017 1017 }

+5 -6

drivers/phy/broadcom/phy-brcm-usb-init.h

reviewed

··· 45 45 void (*uninit_eohci)(struct brcm_usb_init_params *params); 46 46 void (*uninit_xhci)(struct brcm_usb_init_params *params); 47 47 int (*get_dual_select)(struct brcm_usb_init_params *params); 48 48 - void (*set_dual_select)(struct brcm_usb_init_params *params, int mode); 48 48 + void (*set_dual_select)(struct brcm_usb_init_params *params); 49 49 }; 50 50 51 51 struct brcm_usb_init_params { 52 52 void __iomem *regs[BRCM_REGS_MAX]; 53 53 int ioc; 54 54 int ipp; 55 55 - int mode; 55 55 + int supported_port_modes; 56 56 + int port_mode; 56 57 u32 family_id; 57 58 u32 product_id; 58 59 int selected_family; ··· 62 61 const struct brcm_usb_init_ops *ops; 63 62 struct regmap *syscon_piarbctl; 64 63 bool wake_enabled; 65 65 - bool suspend_with_clocks; 66 64 }; 67 65 68 66 void brcm_usb_dvr_init_4908(struct brcm_usb_init_params *params); ··· 153 153 return 0; 154 154 } 155 155 156 156 - static inline void brcm_usb_set_dual_select(struct brcm_usb_init_params *ini, 157 157 - int mode) 156 156 + static inline void brcm_usb_set_dual_select(struct brcm_usb_init_params *ini) 158 157 { 159 158 if (ini->ops->set_dual_select) 160 160 - ini->ops->set_dual_select(ini, mode); 159 159 + ini->ops->set_dual_select(ini); 161 160 } 162 161 163 162 #endif /* _USB_BRCM_COMMON_INIT_H */

+19 -13

drivers/phy/broadcom/phy-brcm-usb.c

reviewed

··· 102 102 103 103 static irqreturn_t brcm_usb_phy_wake_isr(int irq, void *dev_id) 104 104 { 105 105 - struct phy *gphy = dev_id; 105 105 + struct device *dev = dev_id; 106 106 107 107 - pm_wakeup_event(&gphy->dev, 0); 107 107 + pm_wakeup_event(dev, 0); 108 108 109 109 return IRQ_HANDLED; 110 110 } ··· 233 233 return sprintf(buf, "%s\n", 234 234 value_to_name(&brcm_dr_mode_to_name[0], 235 235 ARRAY_SIZE(brcm_dr_mode_to_name), 236 236 - priv->ini.mode)); 236 236 + priv->ini.supported_port_modes)); 237 237 } 238 238 static DEVICE_ATTR_RO(dr_mode); 239 239 ··· 249 249 res = name_to_value(&brcm_dual_mode_to_name[0], 250 250 ARRAY_SIZE(brcm_dual_mode_to_name), buf, &value); 251 251 if (!res) { 252 252 - brcm_usb_set_dual_select(&priv->ini, value); 252 252 + priv->ini.port_mode = value; 253 253 + brcm_usb_set_dual_select(&priv->ini); 253 254 res = len; 254 255 } 255 256 mutex_unlock(&sysfs_lock); ··· 446 445 priv->suspend_clk = NULL; 447 446 } 448 447 449 449 - priv->wake_irq = platform_get_irq_byname(pdev, "wake"); 448 448 + priv->wake_irq = platform_get_irq_byname_optional(pdev, "wake"); 450 449 if (priv->wake_irq < 0) 451 451 - priv->wake_irq = platform_get_irq_byname(pdev, "wakeup"); 450 450 + priv->wake_irq = platform_get_irq_byname_optional(pdev, "wakeup"); 452 451 if (priv->wake_irq >= 0) { 453 452 err = devm_request_irq(dev, priv->wake_irq, 454 453 brcm_usb_phy_wake_isr, 0, 455 455 - dev_name(dev), gphy); 454 454 + dev_name(dev), dev); 456 455 if (err < 0) 457 456 return err; 458 457 device_set_wakeup_capable(dev, 1); ··· 496 495 of_property_read_u32(dn, "brcm,ipp", &priv->ini.ipp); 497 496 of_property_read_u32(dn, "brcm,ioc", &priv->ini.ioc); 498 497 499 499 - priv->ini.mode = USB_CTLR_MODE_HOST; 498 498 + priv->ini.supported_port_modes = USB_CTLR_MODE_HOST; 500 499 err = of_property_read_string(dn, "dr_mode", &mode); 501 500 if (err == 0) { 502 501 name_to_value(&brcm_dr_mode_to_name[0], 503 502 ARRAY_SIZE(brcm_dr_mode_to_name), 504 504 - mode, &priv->ini.mode); 503 503 + mode, &priv->ini.supported_port_modes); 505 504 } 505 505 + /* Default port_mode to supported port_modes */ 506 506 + priv->ini.port_mode = priv->ini.supported_port_modes; 507 507 + 506 508 if (of_property_read_bool(dn, "brcm,has-xhci")) 507 509 priv->has_xhci = true; 508 510 if (of_property_read_bool(dn, "brcm,has-eohci")) ··· 543 539 * Create sysfs entries for mode. 544 540 * Remove "dual_select" attribute if not in dual mode 545 541 */ 546 546 - if (priv->ini.mode != USB_CTLR_MODE_DRD) 542 542 + if (priv->ini.supported_port_modes != USB_CTLR_MODE_DRD) 547 543 brcm_usb_phy_attrs[1] = NULL; 548 544 err = sysfs_create_group(&dev->kobj, &brcm_usb_phy_group); 549 545 if (err) ··· 602 598 * and newer XHCI->2.0-clks/3.0-clks. 603 599 */ 604 600 605 605 - if (!priv->ini.suspend_with_clocks) { 601 601 + if (!priv->ini.wake_enabled) { 606 602 if (priv->phys[BRCM_USB_PHY_3_0].inited) 607 603 clk_disable_unprepare(priv->usb_30_clk); 608 604 if (priv->phys[BRCM_USB_PHY_2_0].inited || ··· 619 615 { 620 616 struct brcm_usb_phy_data *priv = dev_get_drvdata(dev); 621 617 622 622 - clk_prepare_enable(priv->usb_20_clk); 623 623 - clk_prepare_enable(priv->usb_30_clk); 618 618 + if (!priv->ini.wake_enabled) { 619 619 + clk_prepare_enable(priv->usb_20_clk); 620 620 + clk_prepare_enable(priv->usb_30_clk); 621 621 + } 624 622 brcm_usb_init_ipp(&priv->ini); 625 623 626 624 /*

+92 -48

drivers/phy/freescale/phy-fsl-imx8m-pcie.c

reviewed

··· 11 11 #include <linux/mfd/syscon.h> 12 12 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 13 13 #include <linux/module.h> 14 14 + #include <linux/of_device.h> 14 15 #include <linux/phy/phy.h> 15 16 #include <linux/platform_device.h> 16 17 #include <linux/regmap.h> ··· 32 31 #define IMX8MM_PCIE_PHY_CMN_REG065 0x194 33 32 #define ANA_AUX_RX_TERM (BIT(7) | BIT(4)) 34 33 #define ANA_AUX_TX_LVL GENMASK(3, 0) 35 35 - #define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4 36 36 - #define PCIE_PHY_CMN_REG75_PLL_DONE 0x3 34 34 + #define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4 35 35 + #define ANA_PLL_DONE 0x3 37 36 #define PCIE_PHY_TRSV_REG5 0x414 38 38 - #define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D 39 37 #define PCIE_PHY_TRSV_REG6 0x418 40 40 - #define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF 41 38 42 39 #define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24) 43 40 #define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3) ··· 46 47 #define IMX8MM_GPR_PCIE_SSC_EN BIT(16) 47 48 #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9) 48 49 50 50 + enum imx8_pcie_phy_type { 51 51 + IMX8MM, 52 52 + IMX8MP, 53 53 + }; 54 54 + 55 55 + struct imx8_pcie_phy_drvdata { 56 56 + const char *gpr; 57 57 + enum imx8_pcie_phy_type variant; 58 58 + }; 59 59 + 49 60 struct imx8_pcie_phy { 50 61 void __iomem *base; 51 62 struct clk *clk; 52 63 struct phy *phy; 53 64 struct regmap *iomuxc_gpr; 65 65 + struct reset_control *perst; 54 66 struct reset_control *reset; 55 67 u32 refclk_pad_mode; 56 68 u32 tx_deemph_gen1; 57 69 u32 tx_deemph_gen2; 58 70 bool clkreq_unused; 71 71 + const struct imx8_pcie_phy_drvdata *drvdata; 59 72 }; 60 73 61 74 static int imx8_pcie_phy_power_on(struct phy *phy) ··· 76 65 u32 val, pad_mode; 77 66 struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); 78 67 79 79 - reset_control_assert(imx8_phy->reset); 80 80 - 81 68 pad_mode = imx8_phy->refclk_pad_mode; 82 82 - /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */ 83 83 - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 84 84 - IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE, 85 85 - imx8_phy->clkreq_unused ? 86 86 - 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE); 87 87 - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 88 88 - IMX8MM_GPR_PCIE_AUX_EN, 89 89 - IMX8MM_GPR_PCIE_AUX_EN); 90 90 - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 91 91 - IMX8MM_GPR_PCIE_POWER_OFF, 0); 92 92 - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 93 93 - IMX8MM_GPR_PCIE_SSC_EN, 0); 69 69 + switch (imx8_phy->drvdata->variant) { 70 70 + case IMX8MM: 71 71 + reset_control_assert(imx8_phy->reset); 94 72 95 95 - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 96 96 - IMX8MM_GPR_PCIE_REF_CLK_SEL, 97 97 - pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ? 98 98 - IMX8MM_GPR_PCIE_REF_CLK_EXT : 99 99 - IMX8MM_GPR_PCIE_REF_CLK_PLL); 100 100 - usleep_range(100, 200); 101 101 - 102 102 - /* Do the PHY common block reset */ 103 103 - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 104 104 - IMX8MM_GPR_PCIE_CMN_RST, 105 105 - IMX8MM_GPR_PCIE_CMN_RST); 106 106 - usleep_range(200, 500); 73 73 + /* Tune PHY de-emphasis setting to pass PCIe compliance. */ 74 74 + if (imx8_phy->tx_deemph_gen1) 75 75 + writel(imx8_phy->tx_deemph_gen1, 76 76 + imx8_phy->base + PCIE_PHY_TRSV_REG5); 77 77 + if (imx8_phy->tx_deemph_gen2) 78 78 + writel(imx8_phy->tx_deemph_gen2, 79 79 + imx8_phy->base + PCIE_PHY_TRSV_REG6); 80 80 + break; 81 81 + case IMX8MP: /* Do nothing. */ 82 82 + break; 83 83 + } 107 84 108 85 if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT || 109 86 pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { ··· 119 120 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065); 120 121 } 121 122 122 122 - /* Tune PHY de-emphasis setting to pass PCIe compliance. */ 123 123 - if (imx8_phy->tx_deemph_gen1) 124 124 - writel(imx8_phy->tx_deemph_gen1, 125 125 - imx8_phy->base + PCIE_PHY_TRSV_REG5); 126 126 - if (imx8_phy->tx_deemph_gen2) 127 127 - writel(imx8_phy->tx_deemph_gen2, 128 128 - imx8_phy->base + PCIE_PHY_TRSV_REG6); 123 123 + /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */ 124 124 + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 125 125 + IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE, 126 126 + imx8_phy->clkreq_unused ? 127 127 + 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE); 128 128 + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 129 129 + IMX8MM_GPR_PCIE_AUX_EN, 130 130 + IMX8MM_GPR_PCIE_AUX_EN); 131 131 + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 132 132 + IMX8MM_GPR_PCIE_POWER_OFF, 0); 133 133 + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 134 134 + IMX8MM_GPR_PCIE_SSC_EN, 0); 129 135 130 130 - reset_control_deassert(imx8_phy->reset); 136 136 + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 137 137 + IMX8MM_GPR_PCIE_REF_CLK_SEL, 138 138 + pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ? 139 139 + IMX8MM_GPR_PCIE_REF_CLK_EXT : 140 140 + IMX8MM_GPR_PCIE_REF_CLK_PLL); 141 141 + usleep_range(100, 200); 142 142 + 143 143 + /* Do the PHY common block reset */ 144 144 + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 145 145 + IMX8MM_GPR_PCIE_CMN_RST, 146 146 + IMX8MM_GPR_PCIE_CMN_RST); 147 147 + 148 148 + switch (imx8_phy->drvdata->variant) { 149 149 + case IMX8MP: 150 150 + reset_control_deassert(imx8_phy->perst); 151 151 + fallthrough; 152 152 + case IMX8MM: 153 153 + reset_control_deassert(imx8_phy->reset); 154 154 + usleep_range(200, 500); 155 155 + break; 156 156 + } 131 157 132 158 /* Polling to check the phy is ready or not. */ 133 133 - ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75, 134 134 - val, val == PCIE_PHY_CMN_REG75_PLL_DONE, 135 135 - 10, 20000); 159 159 + ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075, 160 160 + val, val == ANA_PLL_DONE, 10, 20000); 136 161 return ret; 137 162 } 138 163 ··· 183 160 .owner = THIS_MODULE, 184 161 }; 185 162 163 163 + static const struct imx8_pcie_phy_drvdata imx8mm_drvdata = { 164 164 + .gpr = "fsl,imx8mm-iomuxc-gpr", 165 165 + .variant = IMX8MM, 166 166 + }; 167 167 + 168 168 + static const struct imx8_pcie_phy_drvdata imx8mp_drvdata = { 169 169 + .gpr = "fsl,imx8mp-iomuxc-gpr", 170 170 + .variant = IMX8MP, 171 171 + }; 172 172 + 173 173 + static const struct of_device_id imx8_pcie_phy_of_match[] = { 174 174 + {.compatible = "fsl,imx8mm-pcie-phy", .data = &imx8mm_drvdata, }, 175 175 + {.compatible = "fsl,imx8mp-pcie-phy", .data = &imx8mp_drvdata, }, 176 176 + { }, 177 177 + }; 178 178 + MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match); 179 179 + 186 180 static int imx8_pcie_phy_probe(struct platform_device *pdev) 187 181 { 188 182 struct phy_provider *phy_provider; ··· 211 171 imx8_phy = devm_kzalloc(dev, sizeof(*imx8_phy), GFP_KERNEL); 212 172 if (!imx8_phy) 213 173 return -ENOMEM; 174 174 + 175 175 + imx8_phy->drvdata = of_device_get_match_data(dev); 214 176 215 177 /* get PHY refclk pad mode */ 216 178 of_property_read_u32(np, "fsl,refclk-pad-mode", ··· 239 197 240 198 /* Grab GPR config register range */ 241 199 imx8_phy->iomuxc_gpr = 242 242 - syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 200 200 + syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr); 243 201 if (IS_ERR(imx8_phy->iomuxc_gpr)) { 244 202 dev_err(dev, "unable to find iomuxc registers\n"); 245 203 return PTR_ERR(imx8_phy->iomuxc_gpr); ··· 249 207 if (IS_ERR(imx8_phy->reset)) { 250 208 dev_err(dev, "Failed to get PCIEPHY reset control\n"); 251 209 return PTR_ERR(imx8_phy->reset); 210 210 + } 211 211 + 212 212 + if (imx8_phy->drvdata->variant == IMX8MP) { 213 213 + imx8_phy->perst = 214 214 + devm_reset_control_get_exclusive(dev, "perst"); 215 215 + if (IS_ERR(imx8_phy->perst)) 216 216 + dev_err_probe(dev, PTR_ERR(imx8_phy->perst), 217 217 + "Failed to get PCIE PHY PERST control\n"); 252 218 } 253 219 254 220 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ··· 274 224 275 225 return PTR_ERR_OR_ZERO(phy_provider); 276 226 } 277 277 - 278 278 - static const struct of_device_id imx8_pcie_phy_of_match[] = { 279 279 - {.compatible = "fsl,imx8mm-pcie-phy",}, 280 280 - { }, 281 281 - }; 282 282 - MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match); 283 227 284 228 static struct platform_driver imx8_pcie_phy_driver = { 285 229 .probe = imx8_pcie_phy_probe,

+1 -3

drivers/phy/marvell/phy-mmp3-hsic.c

reviewed

··· 41 41 { 42 42 struct device *dev = &pdev->dev; 43 43 struct phy_provider *provider; 44 44 - struct resource *resource; 45 44 void __iomem *base; 46 45 struct phy *phy; 47 46 48 48 - resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 49 49 - base = devm_ioremap_resource(dev, resource); 47 47 + base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 50 48 if (IS_ERR(base)) 51 49 return PTR_ERR(base); 52 50

+3

drivers/phy/marvell/phy-mvebu-a3700-comphy.c

reviewed

··· 826 826 if (ret) 827 827 return ret; 828 828 829 829 + /* COMPHY register reset (cleared automatically) */ 830 830 + comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST); 831 831 + 829 832 /* 830 833 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The 831 834 * register belong to UTMI module, so it is set in UTMI phy driver.

+1

drivers/phy/qualcomm/Kconfig

reviewed

··· 54 54 tristate "Qualcomm QMP PHY Driver" 55 55 depends on OF && COMMON_CLK && (ARCH_QCOM || COMPILE_TEST) 56 56 select GENERIC_PHY 57 57 + select MFD_SYSCON 57 58 help 58 59 Enable this to support the QMP PHY transceiver that is used 59 60 with controllers such as PCIe, UFS, and USB on Qualcomm chips.

+840 -955

drivers/phy/qualcomm/phy-qcom-qmp-combo.c

reviewed

··· 20 20 #include <linux/reset.h> 21 21 #include <linux/slab.h> 22 22 23 23 - #include <dt-bindings/phy/phy.h> 23 23 + #include <dt-bindings/phy/phy-qcom-qmp.h> 24 24 25 25 #include "phy-qcom-qmp.h" 26 26 ··· 63 63 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 64 64 65 65 #define PHY_INIT_COMPLETE_TIMEOUT 10000 66 66 - #define POWER_DOWN_DELAY_US_MIN 10 67 67 - #define POWER_DOWN_DELAY_US_MAX 11 68 66 69 67 struct qmp_phy_init_tbl { 70 68 unsigned int offset; 71 69 unsigned int val; 72 72 - /* 73 73 - * register part of layout ? 74 74 - * if yes, then offset gives index in the reg-layout 75 75 - */ 76 76 - bool in_layout; 77 70 /* 78 71 * mask of lanes for which this register is written 79 72 * for cases when second lane needs different values ··· 78 85 { \ 79 86 .offset = o, \ 80 87 .val = v, \ 81 81 - .lane_mask = 0xff, \ 82 82 - } 83 83 - 84 84 - #define QMP_PHY_INIT_CFG_L(o, v) \ 85 85 - { \ 86 86 - .offset = o, \ 87 87 - .val = v, \ 88 88 - .in_layout = true, \ 89 88 .lane_mask = 0xff, \ 90 89 } 91 90 ··· 106 121 [QPHY_SW_RESET] = 0x00, 107 122 [QPHY_START_CTRL] = 0x08, 108 123 [QPHY_PCS_STATUS] = 0x174, 124 124 + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 109 125 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, 110 126 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, 111 127 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, ··· 796 810 { 0x3f, 0xff, 0xff, 0xff } 797 811 }; 798 812 799 799 - struct qmp_phy; 813 813 + struct qmp_combo; 800 814 801 801 - /* struct qmp_phy_cfg - per-PHY initialization config */ 815 815 + struct qmp_combo_offsets { 816 816 + u16 com; 817 817 + u16 txa; 818 818 + u16 rxa; 819 819 + u16 txb; 820 820 + u16 rxb; 821 821 + u16 usb3_serdes; 822 822 + u16 usb3_pcs_misc; 823 823 + u16 usb3_pcs; 824 824 + u16 usb3_pcs_usb; 825 825 + u16 dp_serdes; 826 826 + u16 dp_dp_phy; 827 827 + }; 828 828 + 802 829 struct qmp_phy_cfg { 803 803 - /* phy-type - PCIE/UFS/USB */ 804 804 - unsigned int type; 805 805 - int lanes; 830 830 + const struct qmp_combo_offsets *offsets; 806 831 807 832 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 808 833 const struct qmp_phy_init_tbl *serdes_tbl; ··· 826 829 int pcs_tbl_num; 827 830 const struct qmp_phy_init_tbl *pcs_usb_tbl; 828 831 int pcs_usb_tbl_num; 832 832 + 833 833 + const struct qmp_phy_init_tbl *dp_serdes_tbl; 834 834 + int dp_serdes_tbl_num; 835 835 + const struct qmp_phy_init_tbl *dp_tx_tbl; 836 836 + int dp_tx_tbl_num; 829 837 830 838 /* Init sequence for DP PHY block link rates */ 831 839 const struct qmp_phy_init_tbl *serdes_tbl_rbr; ··· 849 847 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 850 848 851 849 /* DP PHY callbacks */ 852 852 - int (*configure_dp_phy)(struct qmp_phy *qphy); 853 853 - void (*configure_dp_tx)(struct qmp_phy *qphy); 854 854 - int (*calibrate_dp_phy)(struct qmp_phy *qphy); 855 855 - void (*dp_aux_init)(struct qmp_phy *qphy); 850 850 + int (*configure_dp_phy)(struct qmp_combo *qmp); 851 851 + void (*configure_dp_tx)(struct qmp_combo *qmp); 852 852 + int (*calibrate_dp_phy)(struct qmp_combo *qmp); 853 853 + void (*dp_aux_init)(struct qmp_combo *qmp); 856 854 857 855 /* clock ids to be requested */ 858 856 const char * const *clk_list; ··· 867 865 /* array of registers with different offsets */ 868 866 const unsigned int *regs; 869 867 870 870 - unsigned int start_ctrl; 871 871 - unsigned int pwrdn_ctrl; 872 872 - /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 873 873 - unsigned int phy_status; 874 874 - 875 868 /* true, if PHY needs delay after POWER_DOWN */ 876 869 bool has_pwrdn_delay; 877 877 - /* power_down delay in usec */ 878 878 - int pwrdn_delay_min; 879 879 - int pwrdn_delay_max; 880 870 881 871 /* Offset from PCS to PCS_USB region */ 882 872 unsigned int pcs_usb_offset; 883 873 884 874 }; 885 875 886 886 - struct qmp_phy_combo_cfg { 887 887 - const struct qmp_phy_cfg *usb_cfg; 888 888 - const struct qmp_phy_cfg *dp_cfg; 889 889 - }; 876 876 + struct qmp_combo { 877 877 + struct device *dev; 890 878 891 891 - /** 892 892 - * struct qmp_phy - per-lane phy descriptor 893 893 - * 894 894 - * @phy: generic phy 895 895 - * @cfg: phy specific configuration 896 896 - * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 897 897 - * @tx: iomapped memory space for lane's tx 898 898 - * @rx: iomapped memory space for lane's rx 899 899 - * @pcs: iomapped memory space for lane's pcs 900 900 - * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 901 901 - * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 902 902 - * @pcs_misc: iomapped memory space for lane's pcs_misc 903 903 - * @pcs_usb: iomapped memory space for lane's pcs_usb 904 904 - * @pipe_clk: pipe clock 905 905 - * @qmp: QMP phy to which this lane belongs 906 906 - * @mode: current PHY mode 907 907 - * @dp_aux_cfg: Display port aux config 908 908 - * @dp_opts: Display port optional config 909 909 - * @dp_clks: Display port clocks 910 910 - */ 911 911 - struct qmp_phy { 912 912 - struct phy *phy; 913 879 const struct qmp_phy_cfg *cfg; 880 880 + 881 881 + void __iomem *com; 882 882 + 914 883 void __iomem *serdes; 915 884 void __iomem *tx; 916 885 void __iomem *rx; ··· 890 917 void __iomem *rx2; 891 918 void __iomem *pcs_misc; 892 919 void __iomem *pcs_usb; 920 920 + 921 921 + void __iomem *dp_serdes; 922 922 + void __iomem *dp_tx; 923 923 + void __iomem *dp_tx2; 924 924 + void __iomem *dp_dp_phy; 925 925 + 893 926 struct clk *pipe_clk; 894 894 - struct qcom_qmp *qmp; 895 895 - enum phy_mode mode; 896 896 - unsigned int dp_aux_cfg; 897 897 - struct phy_configure_opts_dp dp_opts; 898 898 - struct qmp_phy_dp_clks *dp_clks; 899 899 - }; 900 900 - 901 901 - struct qmp_phy_dp_clks { 902 902 - struct qmp_phy *qphy; 903 903 - struct clk_hw dp_link_hw; 904 904 - struct clk_hw dp_pixel_hw; 905 905 - }; 906 906 - 907 907 - /** 908 908 - * struct qcom_qmp - structure holding QMP phy block attributes 909 909 - * 910 910 - * @dev: device 911 911 - * @dp_com: iomapped memory space for phy's dp_com control block 912 912 - * 913 913 - * @clks: array of clocks required by phy 914 914 - * @resets: array of resets required by phy 915 915 - * @vregs: regulator supplies bulk data 916 916 - * 917 917 - * @phys: array of per-lane phy descriptors 918 918 - * @phy_mutex: mutex lock for PHY common block initialization 919 919 - * @init_count: phy common block initialization count 920 920 - * @ufs_reset: optional UFS PHY reset handle 921 921 - */ 922 922 - struct qcom_qmp { 923 923 - struct device *dev; 924 924 - void __iomem *dp_com; 925 925 - 926 927 struct clk_bulk_data *clks; 927 928 struct reset_control_bulk_data *resets; 928 929 struct regulator_bulk_data *vregs; 929 930 930 930 - struct qmp_phy **phys; 931 931 - 932 931 struct mutex phy_mutex; 933 932 int init_count; 934 933 935 935 - struct reset_control *ufs_reset; 934 934 + struct phy *usb_phy; 935 935 + enum phy_mode mode; 936 936 + 937 937 + struct phy *dp_phy; 938 938 + unsigned int dp_aux_cfg; 939 939 + struct phy_configure_opts_dp dp_opts; 940 940 + 941 941 + struct clk_fixed_rate pipe_clk_fixed; 942 942 + struct clk_hw dp_link_hw; 943 943 + struct clk_hw dp_pixel_hw; 936 944 }; 937 945 938 938 - static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy); 939 939 - static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy); 940 940 - static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy); 941 941 - static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy); 946 946 + static void qmp_v3_dp_aux_init(struct qmp_combo *qmp); 947 947 + static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp); 948 948 + static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp); 949 949 + static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp); 942 950 943 943 - static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy); 944 944 - static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); 945 945 - static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy); 946 946 - static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy); 951 951 + static void qmp_v4_dp_aux_init(struct qmp_combo *qmp); 952 952 + static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp); 953 953 + static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp); 954 954 + static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); 947 955 948 948 - static int qcom_qmp_v5_phy_configure_dp_phy(struct qmp_phy *qphy); 956 956 + static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp); 949 957 950 958 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 951 959 { ··· 958 1004 }; 959 1005 960 1006 static const char * const qmp_v4_phy_clk_l[] = { 961 961 - "aux", "ref_clk_src", "ref", "com_aux", 1007 1007 + "aux", "ref", "com_aux", 962 1008 }; 963 1009 964 1010 /* the primary usb3 phy on sm8250 doesn't have a ref clock */ ··· 975 1021 "phy", 976 1022 }; 977 1023 978 978 - static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { 979 979 - .type = PHY_TYPE_USB3, 980 980 - .lanes = 2, 1024 1024 + static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { 1025 1025 + .com = 0x0000, 1026 1026 + .txa = 0x0400, 1027 1027 + .rxa = 0x0600, 1028 1028 + .txb = 0x0a00, 1029 1029 + .rxb = 0x0c00, 1030 1030 + .usb3_serdes = 0x1000, 1031 1031 + .usb3_pcs_misc = 0x1200, 1032 1032 + .usb3_pcs = 0x1400, 1033 1033 + .usb3_pcs_usb = 0x1700, 1034 1034 + .dp_serdes = 0x2000, 1035 1035 + .dp_dp_phy = 0x2200, 1036 1036 + }; 981 1037 1038 1038 + static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { 982 1039 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 983 1040 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 984 1041 .tx_tbl = qmp_v3_usb3_tx_tbl, ··· 998 1033 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 999 1034 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1000 1035 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1001 1001 - .clk_list = qmp_v3_phy_clk_l, 1002 1002 - .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1003 1003 - .reset_list = sc7180_usb3phy_reset_l, 1004 1004 - .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1005 1005 - .vreg_list = qmp_phy_vreg_l, 1006 1006 - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1007 1007 - .regs = qmp_v3_usb3phy_regs_layout, 1008 1036 1009 1009 - .start_ctrl = SERDES_START | PCS_START, 1010 1010 - .pwrdn_ctrl = SW_PWRDN, 1011 1011 - .phy_status = PHYSTATUS, 1012 1012 - 1013 1013 - .has_pwrdn_delay = true, 1014 1014 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1015 1015 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1016 1016 - }; 1017 1017 - 1018 1018 - static const struct qmp_phy_cfg sc7180_dpphy_cfg = { 1019 1019 - .type = PHY_TYPE_DP, 1020 1020 - .lanes = 2, 1021 1021 - 1022 1022 - .serdes_tbl = qmp_v3_dp_serdes_tbl, 1023 1023 - .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1024 1024 - .tx_tbl = qmp_v3_dp_tx_tbl, 1025 1025 - .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1037 1037 + .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1038 1038 + .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1039 1039 + .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1040 1040 + .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1026 1041 1027 1042 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1028 1043 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), ··· 1018 1073 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1019 1074 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1020 1075 1076 1076 + .dp_aux_init = qmp_v3_dp_aux_init, 1077 1077 + .configure_dp_tx = qmp_v3_configure_dp_tx, 1078 1078 + .configure_dp_phy = qmp_v3_configure_dp_phy, 1079 1079 + .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1080 1080 + 1021 1081 .clk_list = qmp_v3_phy_clk_l, 1022 1082 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1023 1083 .reset_list = sc7180_usb3phy_reset_l, ··· 1031 1081 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1032 1082 .regs = qmp_v3_usb3phy_regs_layout, 1033 1083 1034 1034 - .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, 1035 1035 - .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, 1036 1036 - .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, 1037 1037 - .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate, 1084 1084 + .has_pwrdn_delay = true, 1038 1085 }; 1039 1086 1040 1040 - static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { 1041 1041 - .usb_cfg = &sc7180_usb3phy_cfg, 1042 1042 - .dp_cfg = &sc7180_dpphy_cfg, 1043 1043 - }; 1044 1044 - 1045 1045 - static const struct qmp_phy_cfg sdm845_usb3phy_cfg = { 1046 1046 - .type = PHY_TYPE_USB3, 1047 1047 - .lanes = 2, 1048 1048 - 1087 1087 + static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = { 1049 1088 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1050 1089 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1051 1090 .tx_tbl = qmp_v3_usb3_tx_tbl, ··· 1043 1104 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1044 1105 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1045 1106 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1107 1107 + 1108 1108 + .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1109 1109 + .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1110 1110 + .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1111 1111 + .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1112 1112 + 1113 1113 + .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1114 1114 + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1115 1115 + .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1116 1116 + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1117 1117 + .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1118 1118 + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1119 1119 + .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1120 1120 + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1121 1121 + 1122 1122 + .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1123 1123 + .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1124 1124 + .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1125 1125 + .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1126 1126 + 1127 1127 + .dp_aux_init = qmp_v3_dp_aux_init, 1128 1128 + .configure_dp_tx = qmp_v3_configure_dp_tx, 1129 1129 + .configure_dp_phy = qmp_v3_configure_dp_phy, 1130 1130 + .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1131 1131 + 1046 1132 .clk_list = qmp_v3_phy_clk_l, 1047 1133 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1048 1134 .reset_list = msm8996_usb3phy_reset_l, ··· 1076 1112 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1077 1113 .regs = qmp_v3_usb3phy_regs_layout, 1078 1114 1079 1079 - .start_ctrl = SERDES_START | PCS_START, 1080 1080 - .pwrdn_ctrl = SW_PWRDN, 1081 1081 - .phy_status = PHYSTATUS, 1082 1082 - 1083 1115 .has_pwrdn_delay = true, 1084 1084 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1085 1085 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1086 1116 }; 1087 1117 1088 1088 - static const struct qmp_phy_combo_cfg sdm845_usb3dpphy_cfg = { 1089 1089 - .usb_cfg = &sdm845_usb3phy_cfg, 1090 1090 - .dp_cfg = &sc7180_dpphy_cfg, 1091 1091 - }; 1092 1092 - 1093 1093 - static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { 1094 1094 - .type = PHY_TYPE_USB3, 1095 1095 - .lanes = 2, 1096 1096 - 1118 1118 + static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = { 1097 1119 .serdes_tbl = sm8150_usb3_serdes_tbl, 1098 1120 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1099 1121 .tx_tbl = sm8150_usb3_tx_tbl, ··· 1090 1140 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1091 1141 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1092 1142 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1093 1093 - .clk_list = qmp_v4_phy_clk_l, 1094 1094 - .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1095 1095 - .reset_list = msm8996_usb3phy_reset_l, 1096 1096 - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1097 1097 - .vreg_list = qmp_phy_vreg_l, 1098 1098 - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1099 1099 - .regs = qmp_v4_usb3phy_regs_layout, 1100 1100 - .pcs_usb_offset = 0x300, 1101 1143 1102 1102 - .start_ctrl = SERDES_START | PCS_START, 1103 1103 - .pwrdn_ctrl = SW_PWRDN, 1104 1104 - .phy_status = PHYSTATUS, 1105 1105 - 1106 1106 - 1107 1107 - .has_pwrdn_delay = true, 1108 1108 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1109 1109 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1110 1110 - }; 1111 1111 - 1112 1112 - static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { 1113 1113 - .type = PHY_TYPE_DP, 1114 1114 - .lanes = 2, 1115 1115 - 1116 1116 - .serdes_tbl = qmp_v4_dp_serdes_tbl, 1117 1117 - .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1118 1118 - .tx_tbl = qmp_v4_dp_tx_tbl, 1119 1119 - .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1144 1144 + .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1145 1145 + .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1146 1146 + .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1147 1147 + .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1120 1148 1121 1149 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1122 1150 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), ··· 1110 1182 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1111 1183 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1112 1184 1113 1113 - .clk_list = qmp_v3_phy_clk_l, 1114 1114 - .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1115 1115 - .reset_list = sc7180_usb3phy_reset_l, 1116 1116 - .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1117 1117 - .vreg_list = qmp_phy_vreg_l, 1118 1118 - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1119 1119 - .regs = qmp_v3_usb3phy_regs_layout, 1185 1185 + .dp_aux_init = qmp_v4_dp_aux_init, 1186 1186 + .configure_dp_tx = qmp_v4_configure_dp_tx, 1187 1187 + .configure_dp_phy = qmp_v4_configure_dp_phy, 1188 1188 + .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1120 1189 1121 1121 - .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, 1122 1122 - .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, 1123 1123 - .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, 1124 1124 - .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, 1125 1125 - }; 1126 1126 - 1127 1127 - static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { 1128 1128 - .usb_cfg = &sm8150_usb3phy_cfg, 1129 1129 - .dp_cfg = &sc8180x_dpphy_cfg, 1130 1130 - }; 1131 1131 - 1132 1132 - static const struct qmp_phy_cfg sc8280xp_usb43dp_usb_cfg = { 1133 1133 - .type = PHY_TYPE_USB3, 1134 1134 - .lanes = 2, 1135 1135 - 1136 1136 - .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 1137 1137 - .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 1138 1138 - .tx_tbl = sc8280xp_usb43dp_tx_tbl, 1139 1139 - .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 1140 1140 - .rx_tbl = sc8280xp_usb43dp_rx_tbl, 1141 1141 - .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 1142 1142 - .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 1143 1143 - .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 1144 1190 .clk_list = qmp_v4_phy_clk_l, 1145 1191 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1146 1192 .reset_list = msm8996_usb3phy_reset_l, ··· 1124 1222 .regs = qmp_v4_usb3phy_regs_layout, 1125 1223 .pcs_usb_offset = 0x300, 1126 1224 1127 1127 - .start_ctrl = SERDES_START | PCS_START, 1128 1128 - .pwrdn_ctrl = SW_PWRDN, 1129 1129 - .phy_status = PHYSTATUS, 1130 1130 - 1131 1225 .has_pwrdn_delay = true, 1132 1132 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1133 1133 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1134 1226 }; 1135 1227 1136 1136 - static const struct qmp_phy_cfg sc8280xp_usb43dp_dp_cfg = { 1137 1137 - .type = PHY_TYPE_DP, 1138 1138 - .lanes = 2, 1228 1228 + static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { 1229 1229 + .offsets = &qmp_combo_offsets_v5, 1139 1230 1140 1140 - .serdes_tbl = qmp_v5_dp_serdes_tbl, 1141 1141 - .serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 1142 1142 - .tx_tbl = qmp_v5_5nm_dp_tx_tbl, 1143 1143 - .tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 1231 1231 + .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 1232 1232 + .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 1233 1233 + .tx_tbl = sc8280xp_usb43dp_tx_tbl, 1234 1234 + .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 1235 1235 + .rx_tbl = sc8280xp_usb43dp_rx_tbl, 1236 1236 + .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 1237 1237 + .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 1238 1238 + .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 1239 1239 + 1240 1240 + .dp_serdes_tbl = qmp_v5_dp_serdes_tbl, 1241 1241 + .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 1242 1242 + .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl, 1243 1243 + .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 1144 1244 1145 1245 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1146 1246 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), ··· 1158 1254 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1159 1255 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1160 1256 1257 1257 + .dp_aux_init = qmp_v4_dp_aux_init, 1258 1258 + .configure_dp_tx = qmp_v4_configure_dp_tx, 1259 1259 + .configure_dp_phy = qmp_v5_configure_dp_phy, 1260 1260 + .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1261 1261 + 1161 1262 .clk_list = qmp_v4_phy_clk_l, 1162 1263 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1163 1264 .reset_list = msm8996_usb3phy_reset_l, ··· 1170 1261 .vreg_list = qmp_phy_vreg_l, 1171 1262 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1172 1263 .regs = qmp_v4_usb3phy_regs_layout, 1173 1173 - 1174 1174 - .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, 1175 1175 - .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, 1176 1176 - .configure_dp_phy = qcom_qmp_v5_phy_configure_dp_phy, 1177 1177 - .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, 1178 1264 }; 1179 1265 1180 1180 - static const struct qmp_phy_combo_cfg sc8280xp_usb43dpphy_combo_cfg = { 1181 1181 - .usb_cfg = &sc8280xp_usb43dp_usb_cfg, 1182 1182 - .dp_cfg = &sc8280xp_usb43dp_dp_cfg, 1183 1183 - }; 1184 1184 - 1185 1185 - static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { 1186 1186 - .type = PHY_TYPE_USB3, 1187 1187 - .lanes = 2, 1188 1188 - 1266 1266 + static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { 1189 1267 .serdes_tbl = sm8150_usb3_serdes_tbl, 1190 1268 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1191 1269 .tx_tbl = sm8250_usb3_tx_tbl, ··· 1183 1287 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 1184 1288 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 1185 1289 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 1186 1186 - .clk_list = qmp_v4_sm8250_usbphy_clk_l, 1187 1187 - .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 1188 1188 - .reset_list = msm8996_usb3phy_reset_l, 1189 1189 - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1190 1190 - .vreg_list = qmp_phy_vreg_l, 1191 1191 - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1192 1192 - .regs = qmp_v4_usb3phy_regs_layout, 1193 1193 - .pcs_usb_offset = 0x300, 1194 1290 1195 1195 - .start_ctrl = SERDES_START | PCS_START, 1196 1196 - .pwrdn_ctrl = SW_PWRDN, 1197 1197 - .phy_status = PHYSTATUS, 1198 1198 - 1199 1199 - .has_pwrdn_delay = true, 1200 1200 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1201 1201 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1202 1202 - }; 1203 1203 - 1204 1204 - static const struct qmp_phy_cfg sm8250_dpphy_cfg = { 1205 1205 - .type = PHY_TYPE_DP, 1206 1206 - .lanes = 2, 1207 1207 - 1208 1208 - .serdes_tbl = qmp_v4_dp_serdes_tbl, 1209 1209 - .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1210 1210 - .tx_tbl = qmp_v4_dp_tx_tbl, 1211 1211 - .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1291 1291 + .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1292 1292 + .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1293 1293 + .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1294 1294 + .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1212 1295 1213 1296 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1214 1297 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), ··· 1203 1328 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1204 1329 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1205 1330 1206 1206 - .clk_list = qmp_v4_phy_clk_l, 1207 1207 - .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1331 1331 + .dp_aux_init = qmp_v4_dp_aux_init, 1332 1332 + .configure_dp_tx = qmp_v4_configure_dp_tx, 1333 1333 + .configure_dp_phy = qmp_v4_configure_dp_phy, 1334 1334 + .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1335 1335 + 1336 1336 + .clk_list = qmp_v4_sm8250_usbphy_clk_l, 1337 1337 + .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 1208 1338 .reset_list = msm8996_usb3phy_reset_l, 1209 1339 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1210 1340 .vreg_list = qmp_phy_vreg_l, 1211 1341 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1212 1342 .regs = qmp_v4_usb3phy_regs_layout, 1343 1343 + .pcs_usb_offset = 0x300, 1213 1344 1214 1214 - .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, 1215 1215 - .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, 1216 1216 - .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, 1217 1217 - .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, 1218 1218 - }; 1219 1219 - 1220 1220 - static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = { 1221 1221 - .usb_cfg = &sm8250_usb3phy_cfg, 1222 1222 - .dp_cfg = &sm8250_dpphy_cfg, 1345 1345 + .has_pwrdn_delay = true, 1223 1346 }; 1224 1347 1225 1348 static void qmp_combo_configure_lane(void __iomem *base, 1226 1226 - const unsigned int *regs, 1227 1349 const struct qmp_phy_init_tbl tbl[], 1228 1350 int num, 1229 1351 u8 lane_mask) ··· 1235 1363 if (!(t->lane_mask & lane_mask)) 1236 1364 continue; 1237 1365 1238 1238 - if (t->in_layout) 1239 1239 - writel(t->val, base + regs[t->offset]); 1240 1240 - else 1241 1241 - writel(t->val, base + t->offset); 1366 1366 + writel(t->val, base + t->offset); 1242 1367 } 1243 1368 } 1244 1369 1245 1370 static void qmp_combo_configure(void __iomem *base, 1246 1246 - const unsigned int *regs, 1247 1371 const struct qmp_phy_init_tbl tbl[], 1248 1372 int num) 1249 1373 { 1250 1250 - qmp_combo_configure_lane(base, regs, tbl, num, 0xff); 1374 1374 + qmp_combo_configure_lane(base, tbl, num, 0xff); 1251 1375 } 1252 1376 1253 1253 - static int qmp_combo_serdes_init(struct qmp_phy *qphy) 1377 1377 + static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) 1254 1378 { 1255 1255 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1256 1256 - void __iomem *serdes = qphy->serdes; 1257 1257 - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1258 1258 - const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 1259 1259 - int serdes_tbl_num = cfg->serdes_tbl_num; 1379 1379 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1380 1380 + void __iomem *serdes = qmp->dp_serdes; 1381 1381 + const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1260 1382 1261 1261 - qmp_combo_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 1383 1383 + qmp_combo_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num); 1262 1384 1263 1263 - if (cfg->type == PHY_TYPE_DP) { 1264 1264 - switch (dp_opts->link_rate) { 1265 1265 - case 1620: 1266 1266 - qmp_combo_configure(serdes, cfg->regs, 1267 1267 - cfg->serdes_tbl_rbr, 1268 1268 - cfg->serdes_tbl_rbr_num); 1269 1269 - break; 1270 1270 - case 2700: 1271 1271 - qmp_combo_configure(serdes, cfg->regs, 1272 1272 - cfg->serdes_tbl_hbr, 1273 1273 - cfg->serdes_tbl_hbr_num); 1274 1274 - break; 1275 1275 - case 5400: 1276 1276 - qmp_combo_configure(serdes, cfg->regs, 1277 1277 - cfg->serdes_tbl_hbr2, 1278 1278 - cfg->serdes_tbl_hbr2_num); 1279 1279 - break; 1280 1280 - case 8100: 1281 1281 - qmp_combo_configure(serdes, cfg->regs, 1282 1282 - cfg->serdes_tbl_hbr3, 1283 1283 - cfg->serdes_tbl_hbr3_num); 1284 1284 - break; 1285 1285 - default: 1286 1286 - /* Other link rates aren't supported */ 1287 1287 - return -EINVAL; 1288 1288 - } 1385 1385 + switch (dp_opts->link_rate) { 1386 1386 + case 1620: 1387 1387 + qmp_combo_configure(serdes, cfg->serdes_tbl_rbr, 1388 1388 + cfg->serdes_tbl_rbr_num); 1389 1389 + break; 1390 1390 + case 2700: 1391 1391 + qmp_combo_configure(serdes, cfg->serdes_tbl_hbr, 1392 1392 + cfg->serdes_tbl_hbr_num); 1393 1393 + break; 1394 1394 + case 5400: 1395 1395 + qmp_combo_configure(serdes, cfg->serdes_tbl_hbr2, 1396 1396 + cfg->serdes_tbl_hbr2_num); 1397 1397 + break; 1398 1398 + case 8100: 1399 1399 + qmp_combo_configure(serdes, cfg->serdes_tbl_hbr3, 1400 1400 + cfg->serdes_tbl_hbr3_num); 1401 1401 + break; 1402 1402 + default: 1403 1403 + /* Other link rates aren't supported */ 1404 1404 + return -EINVAL; 1289 1405 } 1290 1406 1291 1407 return 0; 1292 1408 } 1293 1409 1294 1294 - static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) 1410 1410 + static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) 1295 1411 { 1296 1412 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1297 1413 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 1298 1298 - qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1414 1414 + qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1299 1415 1300 1416 /* Turn on BIAS current for PHY/PLL */ 1301 1417 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 1302 1418 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 1303 1303 - qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 1419 1419 + qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 1304 1420 1305 1305 - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1421 1421 + writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1306 1422 1307 1423 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1308 1424 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 1309 1425 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 1310 1426 DP_PHY_PD_CTL_DP_CLAMP_EN, 1311 1311 - qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1427 1427 + qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1312 1428 1313 1429 writel(QSERDES_V3_COM_BIAS_EN | 1314 1430 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 1315 1431 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 1316 1432 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 1317 1317 - qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 1433 1433 + qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 1318 1434 1319 1319 - writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); 1320 1320 - writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1321 1321 - writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1322 1322 - writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); 1323 1323 - writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); 1324 1324 - writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); 1325 1325 - writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); 1326 1326 - writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); 1327 1327 - writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); 1328 1328 - writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); 1329 1329 - qphy->dp_aux_cfg = 0; 1435 1435 + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 1436 1436 + writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1437 1437 + writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 1438 1438 + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 1439 1439 + writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 1440 1440 + writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 1441 1441 + writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 1442 1442 + writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 1443 1443 + writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 1444 1444 + writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 1445 1445 + qmp->dp_aux_cfg = 0; 1330 1446 1331 1447 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 1332 1448 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 1333 1449 PHY_AUX_REQ_ERR_MASK, 1334 1334 - qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 1450 1450 + qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 1335 1451 } 1336 1452 1337 1337 - static int qmp_combo_configure_dp_swing(struct qmp_phy *qphy, 1453 1453 + static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp, 1338 1454 unsigned int drv_lvl_reg, unsigned int emp_post_reg) 1339 1455 { 1340 1340 - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1341 1341 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1456 1456 + const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1457 1457 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1342 1458 unsigned int v_level = 0, p_level = 0; 1343 1459 u8 voltage_swing_cfg, pre_emphasis_cfg; 1344 1460 int i; ··· 1352 1492 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 1353 1493 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 1354 1494 1355 1355 - writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); 1356 1356 - writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); 1357 1357 - writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); 1358 1358 - writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); 1495 1495 + writel(voltage_swing_cfg, qmp->dp_tx + drv_lvl_reg); 1496 1496 + writel(pre_emphasis_cfg, qmp->dp_tx + emp_post_reg); 1497 1497 + writel(voltage_swing_cfg, qmp->dp_tx2 + drv_lvl_reg); 1498 1498 + writel(pre_emphasis_cfg, qmp->dp_tx2 + emp_post_reg); 1359 1499 1360 1500 return 0; 1361 1501 } 1362 1502 1363 1363 - static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) 1503 1503 + static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) 1364 1504 { 1365 1365 - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1505 1505 + const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1366 1506 u32 bias_en, drvr_en; 1367 1507 1368 1368 - if (qmp_combo_configure_dp_swing(qphy, QSERDES_V3_TX_TX_DRV_LVL, 1508 1508 + if (qmp_combo_configure_dp_swing(qmp, QSERDES_V3_TX_TX_DRV_LVL, 1369 1509 QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) 1370 1510 return; 1371 1511 ··· 1377 1517 drvr_en = 0x10; 1378 1518 } 1379 1519 1380 1380 - writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1381 1381 - writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1382 1382 - writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1383 1383 - writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1520 1520 + writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1521 1521 + writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1522 1522 + writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1523 1523 + writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1384 1524 } 1385 1525 1386 1386 - static bool qmp_combo_configure_dp_mode(struct qmp_phy *qphy) 1526 1526 + static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 1387 1527 { 1388 1528 u32 val; 1389 1529 bool reverse = false; ··· 1403 1543 * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) 1404 1544 * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 1405 1545 * if (orientation == ORIENTATION_CC2) 1406 1406 - * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); 1546 1546 + * writel(0x4c, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_MODE); 1407 1547 */ 1408 1548 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 1409 1409 - writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1549 1549 + writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1410 1550 1411 1411 - writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); 1551 1551 + writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 1412 1552 1413 1553 return reverse; 1414 1554 } 1415 1555 1416 1416 - static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) 1556 1556 + static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 1417 1557 { 1418 1418 - const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; 1419 1419 - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1558 1558 + const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1420 1559 u32 phy_vco_div, status; 1421 1560 unsigned long pixel_freq; 1422 1561 1423 1423 - qmp_combo_configure_dp_mode(qphy); 1562 1562 + qmp_combo_configure_dp_mode(qmp); 1424 1563 1425 1425 - writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 1426 1426 - writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 1564 1564 + writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 1565 1565 + writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 1427 1566 1428 1567 switch (dp_opts->link_rate) { 1429 1568 case 1620: ··· 1445 1586 /* Other link rates aren't supported */ 1446 1587 return -EINVAL; 1447 1588 } 1448 1448 - writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); 1589 1589 + writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_VCO_DIV); 1449 1590 1450 1450 - clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); 1451 1451 - clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); 1591 1591 + clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 1592 1592 + clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 1452 1593 1453 1453 - writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1454 1454 - writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1455 1455 - writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); 1456 1456 - writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1457 1457 - writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); 1594 1594 + writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 1595 1595 + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1596 1596 + writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1597 1597 + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1598 1598 + writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1458 1599 1459 1459 - writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); 1600 1600 + writel(0x20, qmp->dp_serdes + QSERDES_V3_COM_RESETSM_CNTRL); 1460 1601 1461 1461 - if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, 1602 1602 + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V3_COM_C_READY_STATUS, 1462 1603 status, 1463 1604 ((status & BIT(0)) > 0), 1464 1605 500, 1465 1606 10000)) 1466 1607 return -ETIMEDOUT; 1467 1608 1468 1468 - writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1609 1609 + writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1469 1610 1470 1470 - if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, 1611 1611 + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS, 1471 1612 status, 1472 1613 ((status & BIT(1)) > 0), 1473 1614 500, 1474 1615 10000)) 1475 1616 return -ETIMEDOUT; 1476 1617 1477 1477 - writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); 1618 1618 + writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1478 1619 udelay(2000); 1479 1479 - writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1620 1620 + writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1480 1621 1481 1481 - return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, 1622 1622 + return readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS, 1482 1623 status, 1483 1624 ((status & BIT(1)) > 0), 1484 1625 500, ··· 1489 1630 * We need to calibrate the aux setting here as many times 1490 1631 * as the caller tries 1491 1632 */ 1492 1492 - static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) 1633 1633 + static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) 1493 1634 { 1494 1635 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 1495 1636 u8 val; 1496 1637 1497 1497 - qphy->dp_aux_cfg++; 1498 1498 - qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 1499 1499 - val = cfg1_settings[qphy->dp_aux_cfg]; 1638 1638 + qmp->dp_aux_cfg++; 1639 1639 + qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 1640 1640 + val = cfg1_settings[qmp->dp_aux_cfg]; 1500 1641 1501 1501 - writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1642 1642 + writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1502 1643 1503 1644 return 0; 1504 1645 } 1505 1646 1506 1506 - static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) 1647 1647 + static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) 1507 1648 { 1508 1649 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1509 1650 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 1510 1510 - qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1651 1651 + qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1511 1652 1512 1653 /* Turn on BIAS current for PHY/PLL */ 1513 1513 - writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); 1654 1654 + writel(0x17, qmp->dp_serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); 1514 1655 1515 1515 - writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); 1516 1516 - writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1517 1517 - writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1518 1518 - writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); 1519 1519 - writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); 1520 1520 - writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); 1521 1521 - writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); 1522 1522 - writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); 1523 1523 - writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); 1524 1524 - writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); 1525 1525 - qphy->dp_aux_cfg = 0; 1656 1656 + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 1657 1657 + writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1658 1658 + writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 1659 1659 + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 1660 1660 + writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 1661 1661 + writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 1662 1662 + writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 1663 1663 + writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 1664 1664 + writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 1665 1665 + writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 1666 1666 + qmp->dp_aux_cfg = 0; 1526 1667 1527 1668 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 1528 1669 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 1529 1670 PHY_AUX_REQ_ERR_MASK, 1530 1530 - qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 1671 1671 + qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 1531 1672 } 1532 1673 1533 1533 - static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) 1674 1674 + static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) 1534 1675 { 1535 1676 /* Program default values before writing proper values */ 1536 1536 - writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); 1537 1537 - writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); 1677 1677 + writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL); 1678 1678 + writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL); 1538 1679 1539 1539 - writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1540 1540 - writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1680 1680 + writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1681 1681 + writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1541 1682 1542 1542 - qmp_combo_configure_dp_swing(qphy, QSERDES_V4_TX_TX_DRV_LVL, 1683 1683 + qmp_combo_configure_dp_swing(qmp, QSERDES_V4_TX_TX_DRV_LVL, 1543 1684 QSERDES_V4_TX_TX_EMP_POST1_LVL); 1544 1685 } 1545 1686 1546 1546 - static int qcom_qmp_v45_phy_configure_dp_phy(struct qmp_phy *qphy) 1687 1687 + static int qmp_v45_configure_dp_phy(struct qmp_combo *qmp) 1547 1688 { 1548 1548 - const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; 1549 1549 - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1689 1689 + const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1550 1690 u32 phy_vco_div, status; 1551 1691 unsigned long pixel_freq; 1552 1692 1553 1553 - writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); 1693 1693 + writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1); 1554 1694 1555 1555 - qmp_combo_configure_dp_mode(qphy); 1695 1695 + qmp_combo_configure_dp_mode(qmp); 1556 1696 1557 1557 - writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1558 1558 - writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1697 1697 + writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1698 1698 + writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 1559 1699 1560 1560 - writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 1561 1561 - writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 1700 1700 + writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 1701 1701 + writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 1562 1702 1563 1703 switch (dp_opts->link_rate) { 1564 1704 case 1620: ··· 1580 1722 /* Other link rates aren't supported */ 1581 1723 return -EINVAL; 1582 1724 } 1583 1583 - writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); 1725 1725 + writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV); 1584 1726 1585 1585 - clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); 1586 1586 - clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); 1727 1727 + clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 1728 1728 + clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 1587 1729 1588 1588 - writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1589 1589 - writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); 1590 1590 - writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1591 1591 - writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); 1730 1730 + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1731 1731 + writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1732 1732 + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1733 1733 + writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1592 1734 1593 1593 - writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); 1735 1735 + writel(0x20, qmp->dp_serdes + QSERDES_V4_COM_RESETSM_CNTRL); 1594 1736 1595 1595 - if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, 1737 1737 + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V4_COM_C_READY_STATUS, 1596 1738 status, 1597 1739 ((status & BIT(0)) > 0), 1598 1740 500, 1599 1741 10000)) 1600 1742 return -ETIMEDOUT; 1601 1743 1602 1602 - if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, 1744 1744 + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V4_COM_CMN_STATUS, 1603 1745 status, 1604 1746 ((status & BIT(0)) > 0), 1605 1747 500, 1606 1748 10000)) 1607 1749 return -ETIMEDOUT; 1608 1750 1609 1609 - if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, 1751 1751 + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V4_COM_CMN_STATUS, 1610 1752 status, 1611 1753 ((status & BIT(1)) > 0), 1612 1754 500, 1613 1755 10000)) 1614 1756 return -ETIMEDOUT; 1615 1757 1616 1616 - writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1758 1758 + writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1617 1759 1618 1618 - if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, 1760 1760 + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS, 1619 1761 status, 1620 1762 ((status & BIT(0)) > 0), 1621 1763 500, 1622 1764 10000)) 1623 1765 return -ETIMEDOUT; 1624 1766 1625 1625 - if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, 1767 1767 + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS, 1626 1768 status, 1627 1769 ((status & BIT(1)) > 0), 1628 1770 500, ··· 1632 1774 return 0; 1633 1775 } 1634 1776 1635 1635 - static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) 1777 1777 + static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 1636 1778 { 1637 1637 - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1779 1779 + const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1638 1780 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 1639 1781 bool reverse = false; 1640 1782 u32 status; 1641 1783 int ret; 1642 1784 1643 1643 - ret = qcom_qmp_v45_phy_configure_dp_phy(qphy); 1785 1785 + ret = qmp_v45_configure_dp_phy(qmp); 1644 1786 if (ret < 0) 1645 1787 return ret; 1646 1788 ··· 1666 1808 drvr1_en = 0x10; 1667 1809 } 1668 1810 1669 1669 - writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); 1670 1670 - writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 1671 1671 - writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); 1672 1672 - writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 1811 1811 + writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); 1812 1812 + writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 1813 1813 + writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); 1814 1814 + writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 1673 1815 1674 1674 - writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); 1816 1816 + writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1675 1817 udelay(2000); 1676 1676 - writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1818 1818 + writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1677 1819 1678 1678 - if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, 1820 1820 + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS, 1679 1821 status, 1680 1822 ((status & BIT(1)) > 0), 1681 1823 500, 1682 1824 10000)) 1683 1825 return -ETIMEDOUT; 1684 1826 1685 1685 - writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); 1686 1686 - writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); 1827 1827 + writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV); 1828 1828 + writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV); 1687 1829 1688 1688 - writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); 1689 1689 - writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); 1830 1830 + writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL); 1831 1831 + writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL); 1690 1832 1691 1691 - writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1692 1692 - writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1833 1833 + writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1834 1834 + writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1693 1835 1694 1836 return 0; 1695 1837 } 1696 1838 1697 1697 - static int qcom_qmp_v5_phy_configure_dp_phy(struct qmp_phy *qphy) 1839 1839 + static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp) 1698 1840 { 1699 1699 - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1841 1841 + const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1700 1842 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 1701 1843 bool reverse = false; 1702 1844 u32 status; 1703 1845 int ret; 1704 1846 1705 1705 - ret = qcom_qmp_v45_phy_configure_dp_phy(qphy); 1847 1847 + ret = qmp_v45_configure_dp_phy(qmp); 1706 1848 if (ret < 0) 1707 1849 return ret; 1708 1850 ··· 1723 1865 drvr1_en = 0x10; 1724 1866 } 1725 1867 1726 1726 - writel(drvr0_en, qphy->tx + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); 1727 1727 - writel(bias0_en, qphy->tx + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); 1728 1728 - writel(drvr1_en, qphy->tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); 1729 1729 - writel(bias1_en, qphy->tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); 1868 1868 + writel(drvr0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); 1869 1869 + writel(bias0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); 1870 1870 + writel(drvr1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); 1871 1871 + writel(bias1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); 1730 1872 1731 1731 - writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); 1873 1873 + writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1732 1874 udelay(2000); 1733 1733 - writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1875 1875 + writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 1734 1876 1735 1735 - if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, 1877 1877 + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS, 1736 1878 status, 1737 1879 ((status & BIT(1)) > 0), 1738 1880 500, 1739 1881 10000)) 1740 1882 return -ETIMEDOUT; 1741 1883 1742 1742 - writel(0x0a, qphy->tx + QSERDES_V5_5NM_TX_TX_POL_INV); 1743 1743 - writel(0x0a, qphy->tx2 + QSERDES_V5_5NM_TX_TX_POL_INV); 1884 1884 + writel(0x0a, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_POL_INV); 1885 1885 + writel(0x0a, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_POL_INV); 1744 1886 1745 1745 - writel(0x27, qphy->tx + QSERDES_V5_5NM_TX_TX_DRV_LVL); 1746 1746 - writel(0x27, qphy->tx2 + QSERDES_V5_5NM_TX_TX_DRV_LVL); 1887 1887 + writel(0x27, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_DRV_LVL); 1888 1888 + writel(0x27, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_DRV_LVL); 1747 1889 1748 1748 - writel(0x20, qphy->tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); 1749 1749 - writel(0x20, qphy->tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); 1890 1890 + writel(0x20, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); 1891 1891 + writel(0x20, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); 1750 1892 1751 1893 return 0; 1752 1894 } ··· 1755 1897 * We need to calibrate the aux setting here as many times 1756 1898 * as the caller tries 1757 1899 */ 1758 1758 - static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy) 1900 1900 + static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp) 1759 1901 { 1760 1902 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 1761 1903 u8 val; 1762 1904 1763 1763 - qphy->dp_aux_cfg++; 1764 1764 - qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 1765 1765 - val = cfg1_settings[qphy->dp_aux_cfg]; 1905 1905 + qmp->dp_aux_cfg++; 1906 1906 + qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 1907 1907 + val = cfg1_settings[qmp->dp_aux_cfg]; 1766 1908 1767 1767 - writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1909 1909 + writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1768 1910 1769 1911 return 0; 1770 1912 } 1771 1913 1772 1772 - static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) 1914 1914 + static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts) 1773 1915 { 1774 1916 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 1775 1775 - struct qmp_phy *qphy = phy_get_drvdata(phy); 1776 1776 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1917 1917 + struct qmp_combo *qmp = phy_get_drvdata(phy); 1918 1918 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1777 1919 1778 1778 - memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); 1779 1779 - if (qphy->dp_opts.set_voltages) { 1780 1780 - cfg->configure_dp_tx(qphy); 1781 1781 - qphy->dp_opts.set_voltages = 0; 1920 1920 + memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 1921 1921 + if (qmp->dp_opts.set_voltages) { 1922 1922 + cfg->configure_dp_tx(qmp); 1923 1923 + qmp->dp_opts.set_voltages = 0; 1782 1924 } 1783 1925 1784 1926 return 0; 1785 1927 } 1786 1928 1787 1787 - static int qcom_qmp_dp_phy_calibrate(struct phy *phy) 1929 1929 + static int qmp_combo_dp_calibrate(struct phy *phy) 1788 1930 { 1789 1789 - struct qmp_phy *qphy = phy_get_drvdata(phy); 1790 1790 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1931 1931 + struct qmp_combo *qmp = phy_get_drvdata(phy); 1932 1932 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1791 1933 1792 1934 if (cfg->calibrate_dp_phy) 1793 1793 - return cfg->calibrate_dp_phy(qphy); 1935 1935 + return cfg->calibrate_dp_phy(qmp); 1794 1936 1795 1937 return 0; 1796 1938 } 1797 1939 1798 1798 - static int qmp_combo_com_init(struct qmp_phy *qphy) 1940 1940 + static int qmp_combo_com_init(struct qmp_combo *qmp) 1799 1941 { 1800 1800 - struct qcom_qmp *qmp = qphy->qmp; 1801 1801 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1802 1802 - void __iomem *pcs = qphy->pcs; 1803 1803 - void __iomem *dp_com = qmp->dp_com; 1942 1942 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1943 1943 + void __iomem *com = qmp->com; 1804 1944 int ret; 1805 1945 1806 1946 mutex_lock(&qmp->phy_mutex); ··· 1807 1951 return 0; 1808 1952 } 1809 1953 1810 1810 - /* turn on regulator supplies */ 1811 1954 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1812 1955 if (ret) { 1813 1956 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); ··· 1829 1974 if (ret) 1830 1975 goto err_assert_reset; 1831 1976 1832 1832 - qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 1977 1977 + qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 1833 1978 1834 1979 /* override hardware control for reset of qmp phy */ 1835 1835 - qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1980 1980 + qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1836 1981 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 1837 1982 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 1838 1983 1839 1984 /* Default type-c orientation, i.e CC1 */ 1840 1840 - qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); 1985 1985 + qphy_setbits(com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); 1841 1986 1842 1842 - qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, USB3_MODE | DP_MODE); 1987 1987 + qphy_setbits(com, QPHY_V3_DP_COM_PHY_MODE_CTRL, USB3_MODE | DP_MODE); 1843 1988 1844 1989 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 1845 1845 - qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1990 1990 + qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1846 1991 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 1847 1992 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 1848 1993 1849 1849 - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 1850 1850 - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 1994 1994 + qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 1995 1995 + qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 1851 1996 1852 1852 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 1853 1853 - qphy_setbits(pcs, 1854 1854 - cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1855 1855 - cfg->pwrdn_ctrl); 1856 1856 - else 1857 1857 - qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 1858 1858 - cfg->pwrdn_ctrl); 1997 1997 + qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1998 1998 + SW_PWRDN); 1859 1999 1860 2000 mutex_unlock(&qmp->phy_mutex); 1861 2001 ··· 1866 2016 return ret; 1867 2017 } 1868 2018 1869 1869 - static int qmp_combo_com_exit(struct qmp_phy *qphy) 2019 2019 + static int qmp_combo_com_exit(struct qmp_combo *qmp) 1870 2020 { 1871 1871 - struct qcom_qmp *qmp = qphy->qmp; 1872 1872 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2021 2021 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1873 2022 1874 2023 mutex_lock(&qmp->phy_mutex); 1875 2024 if (--qmp->init_count) { 1876 2025 mutex_unlock(&qmp->phy_mutex); 1877 2026 return 0; 1878 2027 } 1879 1879 - 1880 1880 - reset_control_assert(qmp->ufs_reset); 1881 2028 1882 2029 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1883 2030 ··· 1887 2040 return 0; 1888 2041 } 1889 2042 1890 1890 - static int qmp_combo_init(struct phy *phy) 2043 2043 + static int qmp_combo_dp_init(struct phy *phy) 1891 2044 { 1892 1892 - struct qmp_phy *qphy = phy_get_drvdata(phy); 1893 1893 - struct qcom_qmp *qmp = qphy->qmp; 1894 1894 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2045 2045 + struct qmp_combo *qmp = phy_get_drvdata(phy); 2046 2046 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1895 2047 int ret; 1896 1896 - dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 1897 2048 1898 1898 - ret = qmp_combo_com_init(qphy); 2049 2049 + ret = qmp_combo_com_init(qmp); 1899 2050 if (ret) 1900 2051 return ret; 1901 2052 1902 1902 - if (cfg->type == PHY_TYPE_DP) 1903 1903 - cfg->dp_aux_init(qphy); 2053 2053 + cfg->dp_aux_init(qmp); 1904 2054 1905 2055 return 0; 1906 2056 } 1907 2057 1908 1908 - static int qmp_combo_power_on(struct phy *phy) 2058 2058 + static int qmp_combo_dp_exit(struct phy *phy) 1909 2059 { 1910 1910 - struct qmp_phy *qphy = phy_get_drvdata(phy); 1911 1911 - struct qcom_qmp *qmp = qphy->qmp; 1912 1912 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1913 1913 - void __iomem *tx = qphy->tx; 1914 1914 - void __iomem *rx = qphy->rx; 1915 1915 - void __iomem *pcs = qphy->pcs; 2060 2060 + struct qmp_combo *qmp = phy_get_drvdata(phy); 2061 2061 + 2062 2062 + qmp_combo_com_exit(qmp); 2063 2063 + 2064 2064 + return 0; 2065 2065 + } 2066 2066 + 2067 2067 + static int qmp_combo_dp_power_on(struct phy *phy) 2068 2068 + { 2069 2069 + struct qmp_combo *qmp = phy_get_drvdata(phy); 2070 2070 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2071 2071 + void __iomem *tx = qmp->dp_tx; 2072 2072 + void __iomem *tx2 = qmp->dp_tx2; 2073 2073 + 2074 2074 + qmp_combo_dp_serdes_init(qmp); 2075 2075 + 2076 2076 + qmp_combo_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 2077 2077 + qmp_combo_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 2078 2078 + 2079 2079 + /* Configure special DP tx tunings */ 2080 2080 + cfg->configure_dp_tx(qmp); 2081 2081 + 2082 2082 + /* Configure link rate, swing, etc. */ 2083 2083 + cfg->configure_dp_phy(qmp); 2084 2084 + 2085 2085 + return 0; 2086 2086 + } 2087 2087 + 2088 2088 + static int qmp_combo_dp_power_off(struct phy *phy) 2089 2089 + { 2090 2090 + struct qmp_combo *qmp = phy_get_drvdata(phy); 2091 2091 + 2092 2092 + /* Assert DP PHY power down */ 2093 2093 + writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2094 2094 + 2095 2095 + return 0; 2096 2096 + } 2097 2097 + 2098 2098 + static int qmp_combo_usb_power_on(struct phy *phy) 2099 2099 + { 2100 2100 + struct qmp_combo *qmp = phy_get_drvdata(phy); 2101 2101 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2102 2102 + void __iomem *serdes = qmp->serdes; 2103 2103 + void __iomem *tx = qmp->tx; 2104 2104 + void __iomem *rx = qmp->rx; 2105 2105 + void __iomem *tx2 = qmp->tx2; 2106 2106 + void __iomem *rx2 = qmp->rx2; 2107 2107 + void __iomem *pcs = qmp->pcs; 1916 2108 void __iomem *status; 1917 1917 - unsigned int mask, val, ready; 2109 2109 + unsigned int val; 1918 2110 int ret; 1919 2111 1920 1920 - qmp_combo_serdes_init(qphy); 2112 2112 + qmp_combo_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); 1921 2113 1922 1922 - ret = clk_prepare_enable(qphy->pipe_clk); 2114 2114 + ret = clk_prepare_enable(qmp->pipe_clk); 1923 2115 if (ret) { 1924 2116 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1925 2117 return ret; 1926 2118 } 1927 2119 1928 2120 /* Tx, Rx, and PCS configurations */ 1929 1929 - qmp_combo_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2121 2121 + qmp_combo_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2122 2122 + qmp_combo_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 1930 2123 1931 1931 - if (cfg->lanes >= 2) { 1932 1932 - qmp_combo_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, 1933 1933 - cfg->tx_tbl_num, 2); 1934 1934 - } 2124 2124 + qmp_combo_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2125 2125 + qmp_combo_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 1935 2126 1936 1936 - /* Configure special DP tx tunings */ 1937 1937 - if (cfg->type == PHY_TYPE_DP) 1938 1938 - cfg->configure_dp_tx(qphy); 1939 1939 - 1940 1940 - qmp_combo_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); 1941 1941 - 1942 1942 - if (cfg->lanes >= 2) { 1943 1943 - qmp_combo_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, 1944 1944 - cfg->rx_tbl_num, 2); 1945 1945 - } 1946 1946 - 1947 1947 - /* Configure link rate, swing, etc. */ 1948 1948 - if (cfg->type == PHY_TYPE_DP) 1949 1949 - cfg->configure_dp_phy(qphy); 1950 1950 - else 1951 1951 - qmp_combo_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1952 1952 - 1953 1953 - ret = reset_control_deassert(qmp->ufs_reset); 1954 1954 - if (ret) 1955 1955 - goto err_disable_pipe_clk; 2127 2127 + qmp_combo_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1956 2128 1957 2129 if (cfg->has_pwrdn_delay) 1958 1958 - usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 2130 2130 + usleep_range(10, 20); 1959 2131 1960 1960 - if (cfg->type != PHY_TYPE_DP) { 1961 1961 - /* Pull PHY out of reset state */ 1962 1962 - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1963 1963 - /* start SerDes and Phy-Coding-Sublayer */ 1964 1964 - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2132 2132 + /* Pull PHY out of reset state */ 2133 2133 + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1965 2134 1966 1966 - status = pcs + cfg->regs[QPHY_PCS_STATUS]; 1967 1967 - mask = cfg->phy_status; 1968 1968 - ready = 0; 2135 2135 + /* start SerDes and Phy-Coding-Sublayer */ 2136 2136 + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 1969 2137 1970 1970 - ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 1971 1971 - PHY_INIT_COMPLETE_TIMEOUT); 1972 1972 - if (ret) { 1973 1973 - dev_err(qmp->dev, "phy initialization timed-out\n"); 1974 1974 - goto err_disable_pipe_clk; 1975 1975 - } 2138 2138 + status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2139 2139 + ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 2140 2140 + PHY_INIT_COMPLETE_TIMEOUT); 2141 2141 + if (ret) { 2142 2142 + dev_err(qmp->dev, "phy initialization timed-out\n"); 2143 2143 + goto err_disable_pipe_clk; 1976 2144 } 2145 2145 + 1977 2146 return 0; 1978 2147 1979 2148 err_disable_pipe_clk: 1980 1980 - clk_disable_unprepare(qphy->pipe_clk); 2149 2149 + clk_disable_unprepare(qmp->pipe_clk); 1981 2150 1982 2151 return ret; 1983 2152 } 1984 2153 1985 1985 - static int qmp_combo_power_off(struct phy *phy) 2154 2154 + static int qmp_combo_usb_power_off(struct phy *phy) 1986 2155 { 1987 1987 - struct qmp_phy *qphy = phy_get_drvdata(phy); 1988 1988 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2156 2156 + struct qmp_combo *qmp = phy_get_drvdata(phy); 2157 2157 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1989 2158 1990 1990 - clk_disable_unprepare(qphy->pipe_clk); 2159 2159 + clk_disable_unprepare(qmp->pipe_clk); 1991 2160 1992 1992 - if (cfg->type == PHY_TYPE_DP) { 1993 1993 - /* Assert DP PHY power down */ 1994 1994 - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1995 1995 - } else { 1996 1996 - /* PHY reset */ 1997 1997 - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2161 2161 + /* PHY reset */ 2162 2162 + qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1998 2163 1999 1999 - /* stop SerDes and Phy-Coding-Sublayer */ 2000 2000 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2164 2164 + /* stop SerDes and Phy-Coding-Sublayer */ 2165 2165 + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2166 2166 + SERDES_START | PCS_START); 2001 2167 2002 2002 - /* Put PHY into POWER DOWN state: active low */ 2003 2003 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 2004 2004 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2005 2005 - cfg->pwrdn_ctrl); 2006 2006 - } else { 2007 2007 - qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 2008 2008 - cfg->pwrdn_ctrl); 2009 2009 - } 2010 2010 - } 2168 2168 + /* Put PHY into POWER DOWN state: active low */ 2169 2169 + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2170 2170 + SW_PWRDN); 2011 2171 2012 2172 return 0; 2013 2173 } 2014 2174 2015 2015 - static int qmp_combo_exit(struct phy *phy) 2175 2175 + static int qmp_combo_usb_init(struct phy *phy) 2016 2176 { 2017 2017 - struct qmp_phy *qphy = phy_get_drvdata(phy); 2018 2018 - 2019 2019 - qmp_combo_com_exit(qphy); 2020 2020 - 2021 2021 - return 0; 2022 2022 - } 2023 2023 - 2024 2024 - static int qmp_combo_enable(struct phy *phy) 2025 2025 - { 2177 2177 + struct qmp_combo *qmp = phy_get_drvdata(phy); 2026 2178 int ret; 2027 2179 2028 2028 - ret = qmp_combo_init(phy); 2180 2180 + ret = qmp_combo_com_init(qmp); 2029 2181 if (ret) 2030 2182 return ret; 2031 2183 2032 2032 - ret = qmp_combo_power_on(phy); 2184 2184 + ret = qmp_combo_usb_power_on(phy); 2033 2185 if (ret) 2034 2034 - qmp_combo_exit(phy); 2186 2186 + qmp_combo_com_exit(qmp); 2035 2187 2036 2188 return ret; 2037 2189 } 2038 2190 2039 2039 - static int qmp_combo_disable(struct phy *phy) 2191 2191 + static int qmp_combo_usb_exit(struct phy *phy) 2040 2192 { 2193 2193 + struct qmp_combo *qmp = phy_get_drvdata(phy); 2041 2194 int ret; 2042 2195 2043 2043 - ret = qmp_combo_power_off(phy); 2196 2196 + ret = qmp_combo_usb_power_off(phy); 2044 2197 if (ret) 2045 2198 return ret; 2046 2046 - return qmp_combo_exit(phy); 2199 2199 + 2200 2200 + return qmp_combo_com_exit(qmp); 2047 2201 } 2048 2202 2049 2049 - static int qmp_combo_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2203 2203 + static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2050 2204 { 2051 2051 - struct qmp_phy *qphy = phy_get_drvdata(phy); 2205 2205 + struct qmp_combo *qmp = phy_get_drvdata(phy); 2052 2206 2053 2053 - qphy->mode = mode; 2207 2207 + qmp->mode = mode; 2054 2208 2055 2209 return 0; 2056 2210 } 2057 2211 2058 2058 - static void qmp_combo_enable_autonomous_mode(struct qmp_phy *qphy) 2212 2212 + static const struct phy_ops qmp_combo_usb_phy_ops = { 2213 2213 + .init = qmp_combo_usb_init, 2214 2214 + .exit = qmp_combo_usb_exit, 2215 2215 + .set_mode = qmp_combo_usb_set_mode, 2216 2216 + .owner = THIS_MODULE, 2217 2217 + }; 2218 2218 + 2219 2219 + static const struct phy_ops qmp_combo_dp_phy_ops = { 2220 2220 + .init = qmp_combo_dp_init, 2221 2221 + .configure = qmp_combo_dp_configure, 2222 2222 + .power_on = qmp_combo_dp_power_on, 2223 2223 + .calibrate = qmp_combo_dp_calibrate, 2224 2224 + .power_off = qmp_combo_dp_power_off, 2225 2225 + .exit = qmp_combo_dp_exit, 2226 2226 + .owner = THIS_MODULE, 2227 2227 + }; 2228 2228 + 2229 2229 + static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp) 2059 2230 { 2060 2060 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2061 2061 - void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; 2062 2062 - void __iomem *pcs_misc = qphy->pcs_misc; 2231 2231 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2232 2232 + void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2233 2233 + void __iomem *pcs_misc = qmp->pcs_misc; 2063 2234 u32 intr_mask; 2064 2235 2065 2065 - if (qphy->mode == PHY_MODE_USB_HOST_SS || 2066 2066 - qphy->mode == PHY_MODE_USB_DEVICE_SS) 2236 2236 + if (qmp->mode == PHY_MODE_USB_HOST_SS || 2237 2237 + qmp->mode == PHY_MODE_USB_DEVICE_SS) 2067 2238 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2068 2239 else 2069 2240 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; ··· 2102 2237 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2103 2238 } 2104 2239 2105 2105 - static void qmp_combo_disable_autonomous_mode(struct qmp_phy *qphy) 2240 2240 + static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp) 2106 2241 { 2107 2107 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2108 2108 - void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; 2109 2109 - void __iomem *pcs_misc = qphy->pcs_misc; 2242 2242 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2243 2243 + void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2244 2244 + void __iomem *pcs_misc = qmp->pcs_misc; 2110 2245 2111 2246 /* Disable i/o clamp_n on resume for normal mode */ 2112 2247 if (pcs_misc) ··· 2122 2257 2123 2258 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 2124 2259 { 2125 2125 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2126 2126 - struct qmp_phy *qphy = qmp->phys[0]; 2127 2127 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2260 2260 + struct qmp_combo *qmp = dev_get_drvdata(dev); 2261 2261 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2128 2262 2129 2129 - dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); 2130 2130 - 2131 2131 - /* Supported only for USB3 PHY and luckily USB3 is the first phy */ 2132 2132 - if (cfg->type != PHY_TYPE_USB3) 2133 2133 - return 0; 2263 2263 + dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 2134 2264 2135 2265 if (!qmp->init_count) { 2136 2266 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2137 2267 return 0; 2138 2268 } 2139 2269 2140 2140 - qmp_combo_enable_autonomous_mode(qphy); 2270 2270 + qmp_combo_enable_autonomous_mode(qmp); 2141 2271 2142 2142 - clk_disable_unprepare(qphy->pipe_clk); 2272 2272 + clk_disable_unprepare(qmp->pipe_clk); 2143 2273 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2144 2274 2145 2275 return 0; ··· 2142 2282 2143 2283 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 2144 2284 { 2145 2145 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2146 2146 - struct qmp_phy *qphy = qmp->phys[0]; 2147 2147 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2285 2285 + struct qmp_combo *qmp = dev_get_drvdata(dev); 2286 2286 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2148 2287 int ret = 0; 2149 2288 2150 2150 - dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); 2151 2151 - 2152 2152 - /* Supported only for USB3 PHY and luckily USB3 is the first phy */ 2153 2153 - if (cfg->type != PHY_TYPE_USB3) 2154 2154 - return 0; 2289 2289 + dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 2155 2290 2156 2291 if (!qmp->init_count) { 2157 2292 dev_vdbg(dev, "PHY not initialized, bailing out\n"); ··· 2157 2302 if (ret) 2158 2303 return ret; 2159 2304 2160 2160 - ret = clk_prepare_enable(qphy->pipe_clk); 2305 2305 + ret = clk_prepare_enable(qmp->pipe_clk); 2161 2306 if (ret) { 2162 2307 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2163 2308 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2164 2309 return ret; 2165 2310 } 2166 2311 2167 2167 - qmp_combo_disable_autonomous_mode(qphy); 2312 2312 + qmp_combo_disable_autonomous_mode(qmp); 2168 2313 2169 2314 return 0; 2170 2315 } 2171 2316 2172 2172 - static int qmp_combo_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2317 2317 + static const struct dev_pm_ops qmp_combo_pm_ops = { 2318 2318 + SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 2319 2319 + qmp_combo_runtime_resume, NULL) 2320 2320 + }; 2321 2321 + 2322 2322 + static int qmp_combo_vreg_init(struct qmp_combo *qmp) 2173 2323 { 2174 2174 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2324 2324 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2325 2325 + struct device *dev = qmp->dev; 2175 2326 int num = cfg->num_vregs; 2176 2327 int ret, i; 2177 2328 ··· 2207 2346 return 0; 2208 2347 } 2209 2348 2210 2210 - static int qmp_combo_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2349 2349 + static int qmp_combo_reset_init(struct qmp_combo *qmp) 2211 2350 { 2212 2212 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2351 2351 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2352 2352 + struct device *dev = qmp->dev; 2213 2353 int i; 2214 2354 int ret; 2215 2355 ··· 2229 2367 return 0; 2230 2368 } 2231 2369 2232 2232 - static int qmp_combo_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2370 2370 + static int qmp_combo_clk_init(struct qmp_combo *qmp) 2233 2371 { 2234 2234 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2372 2372 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2373 2373 + struct device *dev = qmp->dev; 2235 2374 int num = cfg->num_clks; 2236 2375 int i; 2237 2376 ··· 2269 2406 * clk | +-------+ | +-----+ 2270 2407 * +---------------+ 2271 2408 */ 2272 2272 - static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 2409 2409 + static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np) 2273 2410 { 2274 2274 - struct clk_fixed_rate *fixed; 2411 2411 + struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2275 2412 struct clk_init_data init = { }; 2276 2276 - int ret; 2413 2413 + char name[64]; 2277 2414 2278 2278 - ret = of_property_read_string(np, "clock-output-names", &init.name); 2279 2279 - if (ret) { 2280 2280 - dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2281 2281 - return ret; 2282 2282 - } 2283 2283 - 2284 2284 - fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2285 2285 - if (!fixed) 2286 2286 - return -ENOMEM; 2287 2287 - 2415 2415 + snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 2416 2416 + init.name = name; 2288 2417 init.ops = &clk_fixed_rate_ops; 2289 2418 2290 2419 /* controllers using QMP phys use 125MHz pipe clock interface */ 2291 2420 fixed->fixed_rate = 125000000; 2292 2421 fixed->hw.init = &init; 2293 2422 2294 2294 - ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2295 2295 - if (ret) 2296 2296 - return ret; 2297 2297 - 2298 2298 - ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2299 2299 - if (ret) 2300 2300 - return ret; 2301 2301 - 2302 2302 - /* 2303 2303 - * Roll a devm action because the clock provider is the child node, but 2304 2304 - * the child node is not actually a device. 2305 2305 - */ 2306 2306 - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2423 2423 + return devm_clk_hw_register(qmp->dev, &fixed->hw); 2307 2424 } 2308 2425 2309 2426 /* ··· 2335 2492 * for DP pixel clock 2336 2493 * 2337 2494 */ 2338 2338 - static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, 2339 2339 - struct clk_rate_request *req) 2495 2495 + static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 2340 2496 { 2341 2497 switch (req->rate) { 2342 2498 case 1620000000UL / 2: ··· 2347 2505 } 2348 2506 } 2349 2507 2350 2350 - static unsigned long 2351 2351 - qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2508 2508 + static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2352 2509 { 2353 2353 - const struct qmp_phy_dp_clks *dp_clks; 2354 2354 - const struct qmp_phy *qphy; 2510 2510 + const struct qmp_combo *qmp; 2355 2511 const struct phy_configure_opts_dp *dp_opts; 2356 2512 2357 2357 - dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); 2358 2358 - qphy = dp_clks->qphy; 2359 2359 - dp_opts = &qphy->dp_opts; 2513 2513 + qmp = container_of(hw, struct qmp_combo, dp_pixel_hw); 2514 2514 + dp_opts = &qmp->dp_opts; 2360 2515 2361 2516 switch (dp_opts->link_rate) { 2362 2517 case 1620: ··· 2369 2530 } 2370 2531 } 2371 2532 2372 2372 - static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { 2373 2373 - .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, 2374 2374 - .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, 2533 2533 + static const struct clk_ops qmp_dp_pixel_clk_ops = { 2534 2534 + .determine_rate = qmp_dp_pixel_clk_determine_rate, 2535 2535 + .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 2375 2536 }; 2376 2537 2377 2377 - static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, 2378 2378 - struct clk_rate_request *req) 2538 2538 + static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 2379 2539 { 2380 2540 switch (req->rate) { 2381 2541 case 162000000: ··· 2387 2549 } 2388 2550 } 2389 2551 2390 2390 - static unsigned long 2391 2391 - qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2552 2552 + static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2392 2553 { 2393 2393 - const struct qmp_phy_dp_clks *dp_clks; 2394 2394 - const struct qmp_phy *qphy; 2554 2554 + const struct qmp_combo *qmp; 2395 2555 const struct phy_configure_opts_dp *dp_opts; 2396 2556 2397 2397 - dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); 2398 2398 - qphy = dp_clks->qphy; 2399 2399 - dp_opts = &qphy->dp_opts; 2557 2557 + qmp = container_of(hw, struct qmp_combo, dp_link_hw); 2558 2558 + dp_opts = &qmp->dp_opts; 2400 2559 2401 2560 switch (dp_opts->link_rate) { 2402 2561 case 1620: ··· 2406 2571 } 2407 2572 } 2408 2573 2409 2409 - static const struct clk_ops qcom_qmp_dp_link_clk_ops = { 2410 2410 - .determine_rate = qcom_qmp_dp_link_clk_determine_rate, 2411 2411 - .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, 2574 2574 + static const struct clk_ops qmp_dp_link_clk_ops = { 2575 2575 + .determine_rate = qmp_dp_link_clk_determine_rate, 2576 2576 + .recalc_rate = qmp_dp_link_clk_recalc_rate, 2412 2577 }; 2413 2578 2414 2414 - static struct clk_hw * 2415 2415 - qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 2579 2579 + static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 2416 2580 { 2417 2417 - struct qmp_phy_dp_clks *dp_clks = data; 2581 2581 + struct qmp_combo *qmp = data; 2418 2582 unsigned int idx = clkspec->args[0]; 2419 2583 2420 2584 if (idx >= 2) { ··· 2422 2588 } 2423 2589 2424 2590 if (idx == 0) 2425 2425 - return &dp_clks->dp_link_hw; 2591 2591 + return &qmp->dp_link_hw; 2426 2592 2427 2427 - return &dp_clks->dp_pixel_hw; 2593 2593 + return &qmp->dp_pixel_hw; 2428 2594 } 2429 2595 2430 2430 - static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, 2431 2431 - struct device_node *np) 2596 2596 + static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np) 2432 2597 { 2433 2598 struct clk_init_data init = { }; 2434 2434 - struct qmp_phy_dp_clks *dp_clks; 2435 2599 char name[64]; 2436 2600 int ret; 2437 2601 2438 2438 - dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); 2439 2439 - if (!dp_clks) 2440 2440 - return -ENOMEM; 2441 2441 - 2442 2442 - dp_clks->qphy = qphy; 2443 2443 - qphy->dp_clks = dp_clks; 2444 2444 - 2445 2602 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 2446 2446 - init.ops = &qcom_qmp_dp_link_clk_ops; 2603 2603 + init.ops = &qmp_dp_link_clk_ops; 2447 2604 init.name = name; 2448 2448 - dp_clks->dp_link_hw.init = &init; 2449 2449 - ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); 2605 2605 + qmp->dp_link_hw.init = &init; 2606 2606 + ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 2450 2607 if (ret) 2451 2608 return ret; 2452 2609 2453 2610 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 2454 2454 - init.ops = &qcom_qmp_dp_pixel_clk_ops; 2611 2611 + init.ops = &qmp_dp_pixel_clk_ops; 2455 2612 init.name = name; 2456 2456 - dp_clks->dp_pixel_hw.init = &init; 2457 2457 - ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); 2613 2613 + qmp->dp_pixel_hw.init = &init; 2614 2614 + ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 2458 2615 if (ret) 2459 2616 return ret; 2460 2617 2461 2461 - ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); 2618 2618 + return 0; 2619 2619 + } 2620 2620 + 2621 2621 + static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data) 2622 2622 + { 2623 2623 + struct qmp_combo *qmp = data; 2624 2624 + 2625 2625 + switch (clkspec->args[0]) { 2626 2626 + case QMP_USB43DP_USB3_PIPE_CLK: 2627 2627 + return &qmp->pipe_clk_fixed.hw; 2628 2628 + case QMP_USB43DP_DP_LINK_CLK: 2629 2629 + return &qmp->dp_link_hw; 2630 2630 + case QMP_USB43DP_DP_VCO_DIV_CLK: 2631 2631 + return &qmp->dp_pixel_hw; 2632 2632 + } 2633 2633 + 2634 2634 + return ERR_PTR(-EINVAL); 2635 2635 + } 2636 2636 + 2637 2637 + static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np, 2638 2638 + struct device_node *dp_np) 2639 2639 + { 2640 2640 + int ret; 2641 2641 + 2642 2642 + ret = phy_pipe_clk_register(qmp, usb_np); 2643 2643 + if (ret) 2644 2644 + return ret; 2645 2645 + 2646 2646 + ret = phy_dp_clks_register(qmp, dp_np); 2647 2647 + if (ret) 2648 2648 + return ret; 2649 2649 + 2650 2650 + /* 2651 2651 + * Register a single provider for bindings without child nodes. 2652 2652 + */ 2653 2653 + if (usb_np == qmp->dev->of_node) 2654 2654 + return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); 2655 2655 + 2656 2656 + /* 2657 2657 + * Register multiple providers for legacy bindings with child nodes. 2658 2658 + */ 2659 2659 + ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get, 2660 2660 + &qmp->pipe_clk_fixed.hw); 2462 2661 if (ret) 2463 2662 return ret; 2464 2663 ··· 2499 2632 * Roll a devm action because the clock provider is the child node, but 2500 2633 * the child node is not actually a device. 2501 2634 */ 2502 2502 - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2635 2635 + ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); 2636 2636 + if (ret) 2637 2637 + return ret; 2638 2638 + 2639 2639 + ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp); 2640 2640 + if (ret) 2641 2641 + return ret; 2642 2642 + 2643 2643 + return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); 2503 2644 } 2504 2645 2505 2505 - static const struct phy_ops qmp_combo_usb_ops = { 2506 2506 - .init = qmp_combo_enable, 2507 2507 - .exit = qmp_combo_disable, 2508 2508 - .set_mode = qmp_combo_set_mode, 2509 2509 - .owner = THIS_MODULE, 2510 2510 - }; 2511 2511 - 2512 2512 - static const struct phy_ops qmp_combo_dp_ops = { 2513 2513 - .init = qmp_combo_init, 2514 2514 - .configure = qcom_qmp_dp_phy_configure, 2515 2515 - .power_on = qmp_combo_power_on, 2516 2516 - .calibrate = qcom_qmp_dp_phy_calibrate, 2517 2517 - .power_off = qmp_combo_power_off, 2518 2518 - .exit = qmp_combo_exit, 2519 2519 - .set_mode = qmp_combo_set_mode, 2520 2520 - .owner = THIS_MODULE, 2521 2521 - }; 2522 2522 - 2523 2523 - static int qmp_combo_create(struct device *dev, struct device_node *np, int id, 2524 2524 - void __iomem *serdes, const struct qmp_phy_cfg *cfg) 2646 2646 + static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_node *np) 2525 2647 { 2526 2526 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2527 2527 - struct phy *generic_phy; 2528 2528 - struct qmp_phy *qphy; 2529 2529 - const struct phy_ops *ops; 2530 2530 - int ret; 2531 2531 - 2532 2532 - qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 2533 2533 - if (!qphy) 2534 2534 - return -ENOMEM; 2535 2535 - 2536 2536 - qphy->cfg = cfg; 2537 2537 - qphy->serdes = serdes; 2538 2538 - /* 2539 2539 - * Get memory resources for each phy lane: 2540 2540 - * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2541 2541 - * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2542 2542 - * For single lane PHYs: pcs_misc (optional) -> 3. 2543 2543 - */ 2544 2544 - qphy->tx = devm_of_iomap(dev, np, 0, NULL); 2545 2545 - if (IS_ERR(qphy->tx)) 2546 2546 - return PTR_ERR(qphy->tx); 2547 2547 - 2548 2548 - qphy->rx = devm_of_iomap(dev, np, 1, NULL); 2549 2549 - if (IS_ERR(qphy->rx)) 2550 2550 - return PTR_ERR(qphy->rx); 2551 2551 - 2552 2552 - qphy->pcs = devm_of_iomap(dev, np, 2, NULL); 2553 2553 - if (IS_ERR(qphy->pcs)) 2554 2554 - return PTR_ERR(qphy->pcs); 2555 2555 - 2556 2556 - if (cfg->pcs_usb_offset) 2557 2557 - qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset; 2558 2558 - 2559 2559 - if (cfg->lanes >= 2) { 2560 2560 - qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); 2561 2561 - if (IS_ERR(qphy->tx2)) 2562 2562 - return PTR_ERR(qphy->tx2); 2563 2563 - 2564 2564 - qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); 2565 2565 - if (IS_ERR(qphy->rx2)) 2566 2566 - return PTR_ERR(qphy->rx2); 2567 2567 - 2568 2568 - qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2569 2569 - } else { 2570 2570 - qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2571 2571 - } 2572 2572 - 2573 2573 - if (IS_ERR(qphy->pcs_misc)) { 2574 2574 - dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2575 2575 - qphy->pcs_misc = NULL; 2576 2576 - } 2648 2648 + struct device *dev = qmp->dev; 2577 2649 2578 2650 /* 2579 2579 - * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 2580 2580 - * based phys, so they essentially have pipe clock. So, 2581 2581 - * we return error in case phy is USB3 or PIPE type. 2582 2582 - * Otherwise, we initialize pipe clock to NULL for 2583 2583 - * all phys that don't need this. 2651 2651 + * Get memory resources from the DP child node: 2652 2652 + * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 2653 2653 + * tx2 -> 3; rx2 -> 4 2654 2654 + * 2655 2655 + * Note that only tx/tx2 and pcs (dp_phy) are used by the DP 2656 2656 + * implementation. 2584 2657 */ 2585 2585 - qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2586 2586 - if (IS_ERR(qphy->pipe_clk)) { 2587 2587 - if (cfg->type == PHY_TYPE_USB3) 2588 2588 - return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), 2589 2589 - "failed to get lane%d pipe_clk\n", 2590 2590 - id); 2591 2591 - qphy->pipe_clk = NULL; 2592 2592 - } 2658 2658 + qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); 2659 2659 + if (IS_ERR(qmp->dp_tx)) 2660 2660 + return PTR_ERR(qmp->dp_tx); 2593 2661 2594 2594 - if (cfg->type == PHY_TYPE_DP) 2595 2595 - ops = &qmp_combo_dp_ops; 2596 2596 - else 2597 2597 - ops = &qmp_combo_usb_ops; 2662 2662 + qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); 2663 2663 + if (IS_ERR(qmp->dp_dp_phy)) 2664 2664 + return PTR_ERR(qmp->dp_dp_phy); 2598 2665 2599 2599 - generic_phy = devm_phy_create(dev, np, ops); 2600 2600 - if (IS_ERR(generic_phy)) { 2601 2601 - ret = PTR_ERR(generic_phy); 2602 2602 - dev_err(dev, "failed to create qphy %d\n", ret); 2603 2603 - return ret; 2604 2604 - } 2605 2605 - 2606 2606 - qphy->phy = generic_phy; 2607 2607 - qphy->qmp = qmp; 2608 2608 - qmp->phys[id] = qphy; 2609 2609 - phy_set_drvdata(generic_phy, qphy); 2666 2666 + qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); 2667 2667 + if (IS_ERR(qmp->dp_tx2)) 2668 2668 + return PTR_ERR(qmp->dp_tx2); 2610 2669 2611 2670 return 0; 2671 2671 + } 2672 2672 + 2673 2673 + static int qmp_combo_parse_dt_lecacy_usb(struct qmp_combo *qmp, struct device_node *np) 2674 2674 + { 2675 2675 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2676 2676 + struct device *dev = qmp->dev; 2677 2677 + 2678 2678 + /* 2679 2679 + * Get memory resources from the USB child node: 2680 2680 + * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 2681 2681 + * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 2682 2682 + */ 2683 2683 + qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2684 2684 + if (IS_ERR(qmp->tx)) 2685 2685 + return PTR_ERR(qmp->tx); 2686 2686 + 2687 2687 + qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2688 2688 + if (IS_ERR(qmp->rx)) 2689 2689 + return PTR_ERR(qmp->rx); 2690 2690 + 2691 2691 + qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 2692 2692 + if (IS_ERR(qmp->pcs)) 2693 2693 + return PTR_ERR(qmp->pcs); 2694 2694 + 2695 2695 + if (cfg->pcs_usb_offset) 2696 2696 + qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 2697 2697 + 2698 2698 + qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2699 2699 + if (IS_ERR(qmp->tx2)) 2700 2700 + return PTR_ERR(qmp->tx2); 2701 2701 + 2702 2702 + qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2703 2703 + if (IS_ERR(qmp->rx2)) 2704 2704 + return PTR_ERR(qmp->rx2); 2705 2705 + 2706 2706 + qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2707 2707 + if (IS_ERR(qmp->pcs_misc)) { 2708 2708 + dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2709 2709 + qmp->pcs_misc = NULL; 2710 2710 + } 2711 2711 + 2712 2712 + qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2713 2713 + if (IS_ERR(qmp->pipe_clk)) { 2714 2714 + return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2715 2715 + "failed to get pipe clock\n"); 2716 2716 + } 2717 2717 + 2718 2718 + return 0; 2719 2719 + } 2720 2720 + 2721 2721 + static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np, 2722 2722 + struct device_node *dp_np) 2723 2723 + { 2724 2724 + struct platform_device *pdev = to_platform_device(qmp->dev); 2725 2725 + int ret; 2726 2726 + 2727 2727 + qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2728 2728 + if (IS_ERR(qmp->serdes)) 2729 2729 + return PTR_ERR(qmp->serdes); 2730 2730 + 2731 2731 + qmp->com = devm_platform_ioremap_resource(pdev, 1); 2732 2732 + if (IS_ERR(qmp->com)) 2733 2733 + return PTR_ERR(qmp->com); 2734 2734 + 2735 2735 + qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); 2736 2736 + if (IS_ERR(qmp->dp_serdes)) 2737 2737 + return PTR_ERR(qmp->dp_serdes); 2738 2738 + 2739 2739 + ret = qmp_combo_parse_dt_lecacy_usb(qmp, usb_np); 2740 2740 + if (ret) 2741 2741 + return ret; 2742 2742 + 2743 2743 + ret = qmp_combo_parse_dt_lecacy_dp(qmp, dp_np); 2744 2744 + if (ret) 2745 2745 + return ret; 2746 2746 + 2747 2747 + return 0; 2748 2748 + } 2749 2749 + 2750 2750 + static int qmp_combo_parse_dt(struct qmp_combo *qmp) 2751 2751 + { 2752 2752 + struct platform_device *pdev = to_platform_device(qmp->dev); 2753 2753 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2754 2754 + const struct qmp_combo_offsets *offs = cfg->offsets; 2755 2755 + struct device *dev = qmp->dev; 2756 2756 + void __iomem *base; 2757 2757 + 2758 2758 + if (!offs) 2759 2759 + return -EINVAL; 2760 2760 + 2761 2761 + base = devm_platform_ioremap_resource(pdev, 0); 2762 2762 + if (IS_ERR(base)) 2763 2763 + return PTR_ERR(base); 2764 2764 + 2765 2765 + qmp->com = base + offs->com; 2766 2766 + qmp->tx = base + offs->txa; 2767 2767 + qmp->rx = base + offs->rxa; 2768 2768 + qmp->tx2 = base + offs->txb; 2769 2769 + qmp->rx2 = base + offs->rxb; 2770 2770 + 2771 2771 + qmp->serdes = base + offs->usb3_serdes; 2772 2772 + qmp->pcs_misc = base + offs->usb3_pcs_misc; 2773 2773 + qmp->pcs = base + offs->usb3_pcs; 2774 2774 + qmp->pcs_usb = base + offs->usb3_pcs_usb; 2775 2775 + 2776 2776 + qmp->dp_serdes = base + offs->dp_serdes; 2777 2777 + qmp->dp_tx = base + offs->txa; 2778 2778 + qmp->dp_tx2 = base + offs->txb; 2779 2779 + qmp->dp_dp_phy = base + offs->dp_dp_phy; 2780 2780 + 2781 2781 + qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); 2782 2782 + if (IS_ERR(qmp->pipe_clk)) { 2783 2783 + return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2784 2784 + "failed to get usb3_pipe clock\n"); 2785 2785 + } 2786 2786 + 2787 2787 + return 0; 2788 2788 + } 2789 2789 + 2790 2790 + static struct phy *qmp_combo_phy_xlate(struct device *dev, struct of_phandle_args *args) 2791 2791 + { 2792 2792 + struct qmp_combo *qmp = dev_get_drvdata(dev); 2793 2793 + 2794 2794 + if (args->args_count == 0) 2795 2795 + return ERR_PTR(-EINVAL); 2796 2796 + 2797 2797 + switch (args->args[0]) { 2798 2798 + case QMP_USB43DP_USB3_PHY: 2799 2799 + return qmp->usb_phy; 2800 2800 + case QMP_USB43DP_DP_PHY: 2801 2801 + return qmp->dp_phy; 2802 2802 + } 2803 2803 + 2804 2804 + return ERR_PTR(-EINVAL); 2805 2805 + } 2806 2806 + 2807 2807 + static int qmp_combo_probe(struct platform_device *pdev) 2808 2808 + { 2809 2809 + struct qmp_combo *qmp; 2810 2810 + struct device *dev = &pdev->dev; 2811 2811 + struct device_node *dp_np, *usb_np; 2812 2812 + struct phy_provider *phy_provider; 2813 2813 + int ret; 2814 2814 + 2815 2815 + qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2816 2816 + if (!qmp) 2817 2817 + return -ENOMEM; 2818 2818 + 2819 2819 + qmp->dev = dev; 2820 2820 + 2821 2821 + qmp->cfg = of_device_get_match_data(dev); 2822 2822 + if (!qmp->cfg) 2823 2823 + return -EINVAL; 2824 2824 + 2825 2825 + mutex_init(&qmp->phy_mutex); 2826 2826 + 2827 2827 + ret = qmp_combo_clk_init(qmp); 2828 2828 + if (ret) 2829 2829 + return ret; 2830 2830 + 2831 2831 + ret = qmp_combo_reset_init(qmp); 2832 2832 + if (ret) 2833 2833 + return ret; 2834 2834 + 2835 2835 + ret = qmp_combo_vreg_init(qmp); 2836 2836 + if (ret) 2837 2837 + return ret; 2838 2838 + 2839 2839 + /* Check for legacy binding with child nodes. */ 2840 2840 + usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); 2841 2841 + if (usb_np) { 2842 2842 + dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); 2843 2843 + if (!dp_np) { 2844 2844 + of_node_put(usb_np); 2845 2845 + return -EINVAL; 2846 2846 + } 2847 2847 + 2848 2848 + ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np); 2849 2849 + } else { 2850 2850 + usb_np = of_node_get(dev->of_node); 2851 2851 + dp_np = of_node_get(dev->of_node); 2852 2852 + 2853 2853 + ret = qmp_combo_parse_dt(qmp); 2854 2854 + } 2855 2855 + if (ret) 2856 2856 + goto err_node_put; 2857 2857 + 2858 2858 + pm_runtime_set_active(dev); 2859 2859 + ret = devm_pm_runtime_enable(dev); 2860 2860 + if (ret) 2861 2861 + goto err_node_put; 2862 2862 + /* 2863 2863 + * Prevent runtime pm from being ON by default. Users can enable 2864 2864 + * it using power/control in sysfs. 2865 2865 + */ 2866 2866 + pm_runtime_forbid(dev); 2867 2867 + 2868 2868 + ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); 2869 2869 + if (ret) 2870 2870 + goto err_node_put; 2871 2871 + 2872 2872 + qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); 2873 2873 + if (IS_ERR(qmp->usb_phy)) { 2874 2874 + ret = PTR_ERR(qmp->usb_phy); 2875 2875 + dev_err(dev, "failed to create USB PHY: %d\n", ret); 2876 2876 + goto err_node_put; 2877 2877 + } 2878 2878 + 2879 2879 + phy_set_drvdata(qmp->usb_phy, qmp); 2880 2880 + 2881 2881 + qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); 2882 2882 + if (IS_ERR(qmp->dp_phy)) { 2883 2883 + ret = PTR_ERR(qmp->dp_phy); 2884 2884 + dev_err(dev, "failed to create DP PHY: %d\n", ret); 2885 2885 + goto err_node_put; 2886 2886 + } 2887 2887 + 2888 2888 + phy_set_drvdata(qmp->dp_phy, qmp); 2889 2889 + 2890 2890 + dev_set_drvdata(dev, qmp); 2891 2891 + 2892 2892 + if (usb_np == dev->of_node) 2893 2893 + phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate); 2894 2894 + else 2895 2895 + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2896 2896 + 2897 2897 + of_node_put(usb_np); 2898 2898 + of_node_put(dp_np); 2899 2899 + 2900 2900 + return PTR_ERR_OR_ZERO(phy_provider); 2901 2901 + 2902 2902 + err_node_put: 2903 2903 + of_node_put(usb_np); 2904 2904 + of_node_put(dp_np); 2905 2905 + return ret; 2612 2906 } 2613 2907 2614 2908 static const struct of_device_id qmp_combo_of_match_table[] = { 2615 2909 { 2616 2910 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 2617 2911 .data = &sc7180_usb3dpphy_cfg, 2912 2912 + }, 2913 2913 + { 2914 2914 + .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 2915 2915 + .data = &sc8180x_usb3dpphy_cfg, 2916 2916 + }, 2917 2917 + { 2918 2918 + .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 2919 2919 + .data = &sc8280xp_usb43dpphy_cfg, 2618 2920 }, 2619 2921 { 2620 2922 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", ··· 2793 2757 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 2794 2758 .data = &sm8250_usb3dpphy_cfg, 2795 2759 }, 2796 2796 - { 2797 2797 - .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 2798 2798 - .data = &sc8180x_usb3dpphy_cfg, 2799 2799 - }, 2800 2800 - { 2801 2801 - .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 2802 2802 - .data = &sc8280xp_usb43dpphy_combo_cfg, 2803 2803 - }, 2804 2760 { } 2805 2761 }; 2806 2762 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 2807 2807 - 2808 2808 - static const struct dev_pm_ops qmp_combo_pm_ops = { 2809 2809 - SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 2810 2810 - qmp_combo_runtime_resume, NULL) 2811 2811 - }; 2812 2812 - 2813 2813 - static int qmp_combo_probe(struct platform_device *pdev) 2814 2814 - { 2815 2815 - struct qcom_qmp *qmp; 2816 2816 - struct device *dev = &pdev->dev; 2817 2817 - struct device_node *child; 2818 2818 - struct phy_provider *phy_provider; 2819 2819 - void __iomem *serdes; 2820 2820 - void __iomem *usb_serdes; 2821 2821 - void __iomem *dp_serdes = NULL; 2822 2822 - const struct qmp_phy_combo_cfg *combo_cfg = NULL; 2823 2823 - const struct qmp_phy_cfg *cfg = NULL; 2824 2824 - const struct qmp_phy_cfg *usb_cfg = NULL; 2825 2825 - const struct qmp_phy_cfg *dp_cfg = NULL; 2826 2826 - int num, id, expected_phys; 2827 2827 - int ret; 2828 2828 - 2829 2829 - qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2830 2830 - if (!qmp) 2831 2831 - return -ENOMEM; 2832 2832 - 2833 2833 - qmp->dev = dev; 2834 2834 - dev_set_drvdata(dev, qmp); 2835 2835 - 2836 2836 - /* Get the specific init parameters of QMP phy */ 2837 2837 - combo_cfg = of_device_get_match_data(dev); 2838 2838 - if (!combo_cfg) 2839 2839 - return -EINVAL; 2840 2840 - 2841 2841 - usb_cfg = combo_cfg->usb_cfg; 2842 2842 - cfg = usb_cfg; /* Setup clks and regulators */ 2843 2843 - 2844 2844 - /* per PHY serdes; usually located at base address */ 2845 2845 - usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); 2846 2846 - if (IS_ERR(serdes)) 2847 2847 - return PTR_ERR(serdes); 2848 2848 - 2849 2849 - qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 2850 2850 - if (IS_ERR(qmp->dp_com)) 2851 2851 - return PTR_ERR(qmp->dp_com); 2852 2852 - 2853 2853 - /* Only two serdes for combo PHY */ 2854 2854 - dp_serdes = devm_platform_ioremap_resource(pdev, 2); 2855 2855 - if (IS_ERR(dp_serdes)) 2856 2856 - return PTR_ERR(dp_serdes); 2857 2857 - 2858 2858 - dp_cfg = combo_cfg->dp_cfg; 2859 2859 - expected_phys = 2; 2860 2860 - 2861 2861 - mutex_init(&qmp->phy_mutex); 2862 2862 - 2863 2863 - ret = qmp_combo_clk_init(dev, cfg); 2864 2864 - if (ret) 2865 2865 - return ret; 2866 2866 - 2867 2867 - ret = qmp_combo_reset_init(dev, cfg); 2868 2868 - if (ret) 2869 2869 - return ret; 2870 2870 - 2871 2871 - ret = qmp_combo_vreg_init(dev, cfg); 2872 2872 - if (ret) 2873 2873 - return dev_err_probe(dev, ret, 2874 2874 - "failed to get regulator supplies\n"); 2875 2875 - 2876 2876 - num = of_get_available_child_count(dev->of_node); 2877 2877 - /* do we have a rogue child node ? */ 2878 2878 - if (num > expected_phys) 2879 2879 - return -EINVAL; 2880 2880 - 2881 2881 - qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 2882 2882 - if (!qmp->phys) 2883 2883 - return -ENOMEM; 2884 2884 - 2885 2885 - pm_runtime_set_active(dev); 2886 2886 - ret = devm_pm_runtime_enable(dev); 2887 2887 - if (ret) 2888 2888 - return ret; 2889 2889 - /* 2890 2890 - * Prevent runtime pm from being ON by default. Users can enable 2891 2891 - * it using power/control in sysfs. 2892 2892 - */ 2893 2893 - pm_runtime_forbid(dev); 2894 2894 - 2895 2895 - id = 0; 2896 2896 - for_each_available_child_of_node(dev->of_node, child) { 2897 2897 - if (of_node_name_eq(child, "dp-phy")) { 2898 2898 - cfg = dp_cfg; 2899 2899 - serdes = dp_serdes; 2900 2900 - 2901 2901 - /* Create per-lane phy */ 2902 2902 - ret = qmp_combo_create(dev, child, id, serdes, cfg); 2903 2903 - if (ret) { 2904 2904 - dev_err(dev, "failed to create lane%d phy, %d\n", 2905 2905 - id, ret); 2906 2906 - goto err_node_put; 2907 2907 - } 2908 2908 - 2909 2909 - ret = phy_dp_clks_register(qmp, qmp->phys[id], child); 2910 2910 - if (ret) { 2911 2911 - dev_err(qmp->dev, 2912 2912 - "failed to register DP clock source\n"); 2913 2913 - goto err_node_put; 2914 2914 - } 2915 2915 - } else if (of_node_name_eq(child, "usb3-phy")) { 2916 2916 - cfg = usb_cfg; 2917 2917 - serdes = usb_serdes; 2918 2918 - 2919 2919 - /* Create per-lane phy */ 2920 2920 - ret = qmp_combo_create(dev, child, id, serdes, cfg); 2921 2921 - if (ret) { 2922 2922 - dev_err(dev, "failed to create lane%d phy, %d\n", 2923 2923 - id, ret); 2924 2924 - goto err_node_put; 2925 2925 - } 2926 2926 - 2927 2927 - /* 2928 2928 - * Register the pipe clock provided by phy. 2929 2929 - * See function description to see details of this pipe clock. 2930 2930 - */ 2931 2931 - ret = phy_pipe_clk_register(qmp, child); 2932 2932 - if (ret) { 2933 2933 - dev_err(qmp->dev, 2934 2934 - "failed to register pipe clock source\n"); 2935 2935 - goto err_node_put; 2936 2936 - } 2937 2937 - } 2938 2938 - 2939 2939 - id++; 2940 2940 - } 2941 2941 - 2942 2942 - phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2943 2943 - 2944 2944 - return PTR_ERR_OR_ZERO(phy_provider); 2945 2945 - 2946 2946 - err_node_put: 2947 2947 - of_node_put(child); 2948 2948 - return ret; 2949 2949 - } 2950 2763 2951 2764 static struct platform_driver qmp_combo_driver = { 2952 2765 .probe = qmp_combo_probe,

+22 -81

drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c

reviewed

··· 20 20 #include <linux/reset.h> 21 21 #include <linux/slab.h> 22 22 23 23 - #include <dt-bindings/phy/phy.h> 24 24 - 25 23 #include "phy-qcom-qmp.h" 26 24 27 25 /* QPHY_SW_RESET bit */ ··· 33 35 #define PLL_READY_GATE_EN BIT(3) 34 36 /* QPHY_PCS_STATUS bit */ 35 37 #define PHYSTATUS BIT(6) 36 36 - #define PHYSTATUS_4_20 BIT(7) 37 38 /* QPHY_COM_PCS_READY_STATUS bit */ 38 39 #define PCS_READY BIT(0) 39 40 40 41 #define PHY_INIT_COMPLETE_TIMEOUT 10000 41 42 #define POWER_DOWN_DELAY_US_MIN 10 42 42 - #define POWER_DOWN_DELAY_US_MAX 11 43 43 + #define POWER_DOWN_DELAY_US_MAX 20 43 44 44 45 struct qmp_phy_init_tbl { 45 46 unsigned int offset; 46 47 unsigned int val; 47 47 - /* 48 48 - * register part of layout ? 49 49 - * if yes, then offset gives index in the reg-layout 50 50 - */ 51 51 - bool in_layout; 52 48 /* 53 49 * mask of lanes for which this register is written 54 50 * for cases when second lane needs different values ··· 54 62 { \ 55 63 .offset = o, \ 56 64 .val = v, \ 57 57 - .lane_mask = 0xff, \ 58 58 - } 59 59 - 60 60 - #define QMP_PHY_INIT_CFG_L(o, v) \ 61 61 - { \ 62 62 - .offset = o, \ 63 63 - .val = v, \ 64 64 - .in_layout = true, \ 65 65 .lane_mask = 0xff, \ 66 66 } 67 67 ··· 75 91 QPHY_SW_RESET, 76 92 QPHY_START_CTRL, 77 93 QPHY_PCS_STATUS, 78 78 - QPHY_PCS_POWER_DOWN_CONTROL, 79 94 /* Keep last to ensure regs_layout arrays are properly initialized */ 80 95 QPHY_LAYOUT_SIZE 81 96 }; ··· 194 211 195 212 /* array of registers with different offsets */ 196 213 const unsigned int *regs; 197 197 - 198 198 - unsigned int start_ctrl; 199 199 - unsigned int pwrdn_ctrl; 200 200 - unsigned int mask_com_pcs_ready; 201 201 - /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 202 202 - unsigned int phy_status; 203 203 - 204 204 - /* true, if PHY needs delay after POWER_DOWN */ 205 205 - bool has_pwrdn_delay; 206 206 - /* power_down delay in usec */ 207 207 - int pwrdn_delay_min; 208 208 - int pwrdn_delay_max; 209 214 }; 210 215 211 216 /** ··· 306 335 .vreg_list = qmp_phy_vreg_l, 307 336 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 308 337 .regs = pciephy_regs_layout, 309 309 - 310 310 - .start_ctrl = PCS_START | PLL_READY_GATE_EN, 311 311 - .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 312 312 - .mask_com_pcs_ready = PCS_READY, 313 313 - .phy_status = PHYSTATUS, 314 314 - 315 315 - .has_pwrdn_delay = true, 316 316 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 317 317 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 318 338 }; 319 339 320 340 static void qmp_pcie_msm8996_configure_lane(void __iomem *base, 321 321 - const unsigned int *regs, 322 341 const struct qmp_phy_init_tbl tbl[], 323 342 int num, 324 343 u8 lane_mask) ··· 323 362 if (!(t->lane_mask & lane_mask)) 324 363 continue; 325 364 326 326 - if (t->in_layout) 327 327 - writel(t->val, base + regs[t->offset]); 328 328 - else 329 329 - writel(t->val, base + t->offset); 365 365 + writel(t->val, base + t->offset); 330 366 } 331 367 } 332 368 333 369 static void qmp_pcie_msm8996_configure(void __iomem *base, 334 334 - const unsigned int *regs, 335 370 const struct qmp_phy_init_tbl tbl[], 336 371 int num) 337 372 { 338 338 - qmp_pcie_msm8996_configure_lane(base, regs, tbl, num, 0xff); 373 373 + qmp_pcie_msm8996_configure_lane(base, tbl, num, 0xff); 339 374 } 340 375 341 376 static int qmp_pcie_msm8996_serdes_init(struct qmp_phy *qphy) ··· 342 385 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 343 386 int serdes_tbl_num = cfg->serdes_tbl_num; 344 387 void __iomem *status; 345 345 - unsigned int mask, val; 388 388 + unsigned int val; 346 389 int ret; 347 390 348 348 - qmp_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 391 391 + qmp_pcie_msm8996_configure(serdes, serdes_tbl, serdes_tbl_num); 349 392 350 393 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); 351 394 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 352 395 SERDES_START | PCS_START); 353 396 354 397 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; 355 355 - mask = cfg->mask_com_pcs_ready; 356 356 - 357 357 - ret = readl_poll_timeout(status, val, (val & mask), 10, 398 398 + ret = readl_poll_timeout(status, val, (val & PCS_READY), 200, 358 399 PHY_INIT_COMPLETE_TIMEOUT); 359 400 if (ret) { 360 401 dev_err(qmp->dev, ··· 376 421 return 0; 377 422 } 378 423 379 379 - /* turn on regulator supplies */ 380 424 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 381 425 if (ret) { 382 426 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); ··· 468 514 void __iomem *rx = qphy->rx; 469 515 void __iomem *pcs = qphy->pcs; 470 516 void __iomem *status; 471 471 - unsigned int mask, val, ready; 517 517 + unsigned int val; 472 518 int ret; 473 519 474 520 qmp_pcie_msm8996_serdes_init(qphy); ··· 487 533 } 488 534 489 535 /* Tx, Rx, and PCS configurations */ 490 490 - qmp_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl, 491 491 - cfg->tx_tbl_num, 1); 492 492 - 493 493 - qmp_pcie_msm8996_configure_lane(rx, cfg->regs, cfg->rx_tbl, 494 494 - cfg->rx_tbl_num, 1); 495 495 - 496 496 - qmp_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 536 536 + qmp_pcie_msm8996_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 537 537 + qmp_pcie_msm8996_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 538 538 + qmp_pcie_msm8996_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 497 539 498 540 /* 499 541 * Pull out PHY from POWER DOWN state. 500 542 * This is active low enable signal to power-down PHY. 501 543 */ 502 502 - qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 544 544 + qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 545 545 + SW_PWRDN | REFCLK_DRV_DSBL); 503 546 504 504 - if (cfg->has_pwrdn_delay) 505 505 - usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 547 547 + usleep_range(POWER_DOWN_DELAY_US_MIN, POWER_DOWN_DELAY_US_MAX); 506 548 507 549 /* Pull PHY out of reset state */ 508 550 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 509 551 510 552 /* start SerDes and Phy-Coding-Sublayer */ 511 511 - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 553 553 + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], 554 554 + PCS_START | PLL_READY_GATE_EN); 512 555 513 556 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 514 514 - mask = cfg->phy_status; 515 515 - ready = 0; 516 516 - 517 517 - ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 557 557 + ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 518 558 PHY_INIT_COMPLETE_TIMEOUT); 519 559 if (ret) { 520 560 dev_err(qmp->dev, "phy initialization timed-out\n"); ··· 536 588 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 537 589 538 590 /* stop SerDes and Phy-Coding-Sublayer */ 539 539 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 591 591 + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], 592 592 + SERDES_START | PCS_START); 540 593 541 594 /* Put PHY into POWER DOWN state: active low */ 542 542 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 543 543 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 544 544 - cfg->pwrdn_ctrl); 545 545 - } else { 546 546 - qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 547 547 - cfg->pwrdn_ctrl); 548 548 - } 595 595 + qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 596 596 + SW_PWRDN | REFCLK_DRV_DSBL); 549 597 550 598 return 0; 551 599 } ··· 721 777 qphy->cfg = cfg; 722 778 qphy->serdes = serdes; 723 779 /* 724 724 - * Get memory resources for each phy lane: 780 780 + * Get memory resources for each PHY: 725 781 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 726 782 */ 727 783 qphy->tx = devm_of_iomap(dev, np, 0, NULL); ··· 795 851 qmp->dev = dev; 796 852 dev_set_drvdata(dev, qmp); 797 853 798 798 - /* Get the specific init parameters of QMP phy */ 799 854 cfg = of_device_get_match_data(dev); 800 855 if (!cfg) 801 856 return -EINVAL; 802 857 803 803 - /* per PHY serdes; usually located at base address */ 804 858 serdes = devm_platform_ioremap_resource(pdev, 0); 805 859 if (IS_ERR(serdes)) 806 860 return PTR_ERR(serdes); ··· 817 875 818 876 ret = qmp_pcie_msm8996_vreg_init(dev, cfg); 819 877 if (ret) 820 820 - return dev_err_probe(dev, ret, 821 821 - "failed to get regulator supplies\n"); 878 878 + return ret; 822 879 823 880 num = of_get_available_child_count(dev->of_node); 824 881 /* do we have a rogue child node ? */

+902 -565

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

reviewed

··· 10 10 #include <linux/io.h> 11 11 #include <linux/iopoll.h> 12 12 #include <linux/kernel.h> 13 13 + #include <linux/mfd/syscon.h> 13 14 #include <linux/module.h> 14 15 #include <linux/of.h> 15 16 #include <linux/of_device.h> 16 17 #include <linux/of_address.h> 18 18 + #include <linux/phy/pcie.h> 17 19 #include <linux/phy/phy.h> 18 20 #include <linux/platform_device.h> 21 21 + #include <linux/regmap.h> 19 22 #include <linux/regulator/consumer.h> 20 23 #include <linux/reset.h> 21 24 #include <linux/slab.h> 22 22 - 23 23 - #include <dt-bindings/phy/phy.h> 24 25 25 26 #include "phy-qcom-qmp.h" 26 27 ··· 43 42 unsigned int offset; 44 43 unsigned int val; 45 44 /* 46 46 - * register part of layout ? 47 47 - * if yes, then offset gives index in the reg-layout 48 48 - */ 49 49 - bool in_layout; 50 50 - /* 51 45 * mask of lanes for which this register is written 52 46 * for cases when second lane needs different values 53 47 */ ··· 56 60 .lane_mask = 0xff, \ 57 61 } 58 62 59 59 - #define QMP_PHY_INIT_CFG_L(o, v) \ 60 60 - { \ 61 61 - .offset = o, \ 62 62 - .val = v, \ 63 63 - .in_layout = true, \ 64 64 - .lane_mask = 0xff, \ 65 65 - } 66 66 - 67 63 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 68 64 { \ 69 65 .offset = o, \ ··· 65 77 66 78 /* set of registers with offsets different per-PHY */ 67 79 enum qphy_reg_layout { 68 68 - /* Common block control registers */ 69 69 - QPHY_COM_SW_RESET, 70 70 - QPHY_COM_POWER_DOWN_CONTROL, 71 71 - QPHY_COM_START_CONTROL, 72 72 - QPHY_COM_PCS_READY_STATUS, 73 80 /* PCS registers */ 74 81 QPHY_SW_RESET, 75 82 QPHY_START_CTRL, ··· 82 99 }; 83 100 84 101 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 85 85 - [QPHY_COM_SW_RESET] = 0x400, 86 86 - [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, 87 87 - [QPHY_COM_START_CONTROL] = 0x408, 88 88 - [QPHY_COM_PCS_READY_STATUS] = 0x448, 89 102 [QPHY_SW_RESET] = 0x00, 90 103 [QPHY_START_CTRL] = 0x08, 91 104 [QPHY_PCS_STATUS] = 0x174, 105 105 + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 92 106 }; 93 107 94 108 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 95 109 [QPHY_SW_RESET] = 0x00, 96 110 [QPHY_START_CTRL] = 0x08, 97 111 [QPHY_PCS_STATUS] = 0x174, 112 112 + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 98 113 }; 99 114 100 115 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 101 116 [QPHY_SW_RESET] = 0x00, 102 117 [QPHY_START_CTRL] = 0x08, 103 118 [QPHY_PCS_STATUS] = 0x2ac, 119 119 + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 104 120 }; 105 121 106 122 static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { ··· 375 393 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 376 394 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 377 395 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 378 378 - QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), 379 379 - QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), 380 396 }; 381 397 382 398 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { ··· 485 505 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 486 506 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 487 507 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 508 508 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 509 509 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 510 510 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 511 511 + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 512 512 + }; 513 513 + 514 514 + static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { 488 515 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 489 516 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 490 517 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), ··· 504 517 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 505 518 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 506 519 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 507 507 - QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 508 520 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 509 509 - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 510 510 - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 511 511 - QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 512 521 }; 513 522 514 523 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { ··· 837 854 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 838 855 }; 839 856 857 857 + static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = { 858 858 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 859 859 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 860 860 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 861 861 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 862 862 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 863 863 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 864 864 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 865 865 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 866 866 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 867 867 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 868 868 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 869 869 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 870 870 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 871 871 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 872 872 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 873 873 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 874 874 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 875 875 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 876 876 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 877 877 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 878 878 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 879 879 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 880 880 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 881 881 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 882 882 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 883 883 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 884 884 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 885 885 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 886 886 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 887 887 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 888 888 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 889 889 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 890 890 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 891 891 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 892 892 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 893 893 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 894 894 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9), 895 895 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 896 896 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94), 897 897 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 898 898 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 899 899 + }; 900 900 + 901 901 + static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 902 902 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 903 903 + }; 904 904 + 905 905 + static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = { 906 906 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 907 907 + }; 908 908 + 909 909 + static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = { 910 910 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 911 911 + }; 912 912 + 913 913 + static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = { 914 914 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 915 915 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 916 916 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 917 917 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 918 918 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 919 919 + }; 920 920 + 921 921 + static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = { 922 922 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 923 923 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 924 924 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 925 925 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 926 926 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 927 927 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 928 928 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 929 929 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 930 930 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 931 931 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 932 932 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 933 933 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 934 934 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 935 935 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 936 936 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 937 937 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 938 938 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 939 939 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 940 940 + }; 941 941 + 942 942 + static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = { 943 943 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 944 944 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 945 945 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 946 946 + }; 947 947 + 948 948 + static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 949 949 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 950 950 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 951 951 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 952 952 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 953 953 + }; 954 954 + 955 955 + static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = { 956 956 + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 957 957 + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 958 958 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 959 959 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 960 960 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 961 961 + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 962 962 + }; 963 963 + 964 964 + static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = { 965 965 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 966 966 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 967 967 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 968 968 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 969 969 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 970 970 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 971 971 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 972 972 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 973 973 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 974 974 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 975 975 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 976 976 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 977 977 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 978 978 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 979 979 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 980 980 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 981 981 + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 982 982 + }; 983 983 + 984 984 + static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = { 985 985 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 986 986 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88), 987 987 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 988 988 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f), 989 989 + }; 990 990 + 991 991 + static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 992 992 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 993 993 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 994 994 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 995 995 + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 996 996 + }; 997 997 + 840 998 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 841 999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 842 1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), ··· 1308 1184 }; 1309 1185 1310 1186 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 1187 1187 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1188 1188 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1189 1189 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1190 1190 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1191 1191 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1192 1192 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1193 1193 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1194 1194 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1195 1195 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1196 1196 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1197 1197 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1198 1198 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1199 1199 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1200 1200 + }; 1201 1201 + 1202 1202 + static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = { 1311 1203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1312 1204 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1313 1205 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1314 1206 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1315 1207 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1316 1208 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1317 1317 - QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1318 1209 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1319 1319 - QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1320 1210 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1321 1211 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1322 1212 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), ··· 1338 1200 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1339 1201 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1340 1202 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1341 1341 - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1342 1342 - QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1343 1203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1344 1204 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1345 1205 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), ··· 1350 1214 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1351 1215 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 1352 1216 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1353 1353 - QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1354 1217 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1355 1355 - QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1356 1356 - QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1357 1357 - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1358 1358 - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1359 1359 - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1360 1218 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 1361 1361 - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1362 1362 - QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1363 1363 - QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1364 1219 }; 1365 1220 1366 1221 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { ··· 1412 1285 }; 1413 1286 1414 1287 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 1415 1415 - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), 1416 1416 - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), 1417 1417 - QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), 1418 1418 - QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), 1288 1288 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 1289 1289 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 1290 1290 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 1291 1291 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99), 1419 1292 }; 1420 1293 1421 1294 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1422 1422 - QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1423 1423 - QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1424 1295 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1425 1296 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1426 1297 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1427 1298 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1428 1299 }; 1429 1300 1301 1301 + static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { 1302 1302 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1303 1303 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1304 1304 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00), 1305 1305 + }; 1306 1306 + 1307 1307 + static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = { 1308 1308 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1309 1309 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1310 1310 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1311 1311 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1312 1312 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1313 1313 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1314 1314 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1315 1315 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1316 1316 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1317 1317 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1318 1318 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1319 1319 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1320 1320 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1321 1321 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1322 1322 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1323 1323 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1324 1324 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1325 1325 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1326 1326 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1327 1327 + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1328 1328 + }; 1329 1329 + 1330 1330 + static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = { 1331 1331 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1332 1332 + }; 1333 1333 + 1334 1334 + struct qmp_pcie_offsets { 1335 1335 + u16 serdes; 1336 1336 + u16 pcs; 1337 1337 + u16 pcs_misc; 1338 1338 + u16 tx; 1339 1339 + u16 rx; 1340 1340 + u16 tx2; 1341 1341 + u16 rx2; 1342 1342 + }; 1343 1343 + 1344 1344 + struct qmp_phy_cfg_tbls { 1345 1345 + const struct qmp_phy_init_tbl *serdes; 1346 1346 + int serdes_num; 1347 1347 + const struct qmp_phy_init_tbl *tx; 1348 1348 + int tx_num; 1349 1349 + const struct qmp_phy_init_tbl *rx; 1350 1350 + int rx_num; 1351 1351 + const struct qmp_phy_init_tbl *pcs; 1352 1352 + int pcs_num; 1353 1353 + const struct qmp_phy_init_tbl *pcs_misc; 1354 1354 + int pcs_misc_num; 1355 1355 + }; 1356 1356 + 1430 1357 /* struct qmp_phy_cfg - per-PHY initialization config */ 1431 1358 struct qmp_phy_cfg { 1432 1359 int lanes; 1433 1360 1434 1434 - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1435 1435 - const struct qmp_phy_init_tbl *serdes_tbl; 1436 1436 - int serdes_tbl_num; 1437 1437 - const struct qmp_phy_init_tbl *serdes_tbl_sec; 1438 1438 - int serdes_tbl_num_sec; 1439 1439 - const struct qmp_phy_init_tbl *tx_tbl; 1440 1440 - int tx_tbl_num; 1441 1441 - const struct qmp_phy_init_tbl *tx_tbl_sec; 1442 1442 - int tx_tbl_num_sec; 1443 1443 - const struct qmp_phy_init_tbl *rx_tbl; 1444 1444 - int rx_tbl_num; 1445 1445 - const struct qmp_phy_init_tbl *rx_tbl_sec; 1446 1446 - int rx_tbl_num_sec; 1447 1447 - const struct qmp_phy_init_tbl *pcs_tbl; 1448 1448 - int pcs_tbl_num; 1449 1449 - const struct qmp_phy_init_tbl *pcs_tbl_sec; 1450 1450 - int pcs_tbl_num_sec; 1451 1451 - const struct qmp_phy_init_tbl *pcs_misc_tbl; 1452 1452 - int pcs_misc_tbl_num; 1453 1453 - const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; 1454 1454 - int pcs_misc_tbl_num_sec; 1361 1361 + const struct qmp_pcie_offsets *offsets; 1362 1362 + 1363 1363 + /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 1364 1364 + const struct qmp_phy_cfg_tbls tbls; 1365 1365 + /* 1366 1366 + * Additional init sequences for PHY blocks, providing additional 1367 1367 + * register programming. They are used for providing separate sequences 1368 1368 + * for the Root Complex and End Point use cases. 1369 1369 + * 1370 1370 + * If EP mode is not supported, both tables can be left unset. 1371 1371 + */ 1372 1372 + const struct qmp_phy_cfg_tbls *tbls_rc; 1373 1373 + const struct qmp_phy_cfg_tbls *tbls_ep; 1374 1374 + 1375 1375 + const struct qmp_phy_init_tbl *serdes_4ln_tbl; 1376 1376 + int serdes_4ln_num; 1455 1377 1456 1378 /* clock ids to be requested */ 1457 1379 const char * const *clk_list; ··· 1515 1339 /* array of registers with different offsets */ 1516 1340 const unsigned int *regs; 1517 1341 1518 1518 - unsigned int start_ctrl; 1519 1342 unsigned int pwrdn_ctrl; 1520 1343 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1521 1344 unsigned int phy_status; 1522 1345 1523 1523 - /* true, if PHY needs delay after POWER_DOWN */ 1524 1524 - bool has_pwrdn_delay; 1525 1525 - /* power_down delay in usec */ 1526 1526 - int pwrdn_delay_min; 1527 1527 - int pwrdn_delay_max; 1346 1346 + bool skip_start_delay; 1528 1347 1529 1348 /* QMP PHY pipe clock interface rate */ 1530 1349 unsigned long pipe_clock_rate; 1531 1350 }; 1532 1351 1533 1533 - /** 1534 1534 - * struct qmp_phy - per-lane phy descriptor 1535 1535 - * 1536 1536 - * @phy: generic phy 1537 1537 - * @cfg: phy specific configuration 1538 1538 - * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 1539 1539 - * @tx: iomapped memory space for lane's tx 1540 1540 - * @rx: iomapped memory space for lane's rx 1541 1541 - * @pcs: iomapped memory space for lane's pcs 1542 1542 - * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 1543 1543 - * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 1544 1544 - * @pcs_misc: iomapped memory space for lane's pcs_misc 1545 1545 - * @pipe_clk: pipe clock 1546 1546 - * @qmp: QMP phy to which this lane belongs 1547 1547 - */ 1548 1548 - struct qmp_phy { 1549 1549 - struct phy *phy; 1550 1550 - const struct qmp_phy_cfg *cfg; 1551 1551 - void __iomem *serdes; 1552 1552 - void __iomem *tx; 1553 1553 - void __iomem *rx; 1554 1554 - void __iomem *pcs; 1555 1555 - void __iomem *tx2; 1556 1556 - void __iomem *rx2; 1557 1557 - void __iomem *pcs_misc; 1558 1558 - struct clk *pipe_clk; 1559 1559 - struct qcom_qmp *qmp; 1560 1560 - }; 1561 1561 - 1562 1562 - /** 1563 1563 - * struct qcom_qmp - structure holding QMP phy block attributes 1564 1564 - * 1565 1565 - * @dev: device 1566 1566 - * 1567 1567 - * @clks: array of clocks required by phy 1568 1568 - * @resets: array of resets required by phy 1569 1569 - * @vregs: regulator supplies bulk data 1570 1570 - * 1571 1571 - * @phys: array of per-lane phy descriptors 1572 1572 - */ 1573 1573 - struct qcom_qmp { 1352 1352 + struct qmp_pcie { 1574 1353 struct device *dev; 1575 1354 1355 1355 + const struct qmp_phy_cfg *cfg; 1356 1356 + bool tcsr_4ln_config; 1357 1357 + 1358 1358 + void __iomem *serdes; 1359 1359 + void __iomem *pcs; 1360 1360 + void __iomem *pcs_misc; 1361 1361 + void __iomem *tx; 1362 1362 + void __iomem *rx; 1363 1363 + void __iomem *tx2; 1364 1364 + void __iomem *rx2; 1365 1365 + 1366 1366 + void __iomem *port_b; 1367 1367 + 1576 1368 struct clk_bulk_data *clks; 1369 1369 + struct clk_bulk_data pipe_clks[2]; 1370 1370 + int num_pipe_clks; 1371 1371 + 1577 1372 struct reset_control_bulk_data *resets; 1578 1373 struct regulator_bulk_data *vregs; 1579 1374 1580 1580 - struct qmp_phy **phys; 1375 1375 + struct phy *phy; 1376 1376 + int mode; 1377 1377 + 1378 1378 + struct clk_fixed_rate pipe_clk_fixed; 1581 1379 }; 1582 1380 1583 1381 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) ··· 1579 1429 } 1580 1430 1581 1431 /* list of clocks required by phy */ 1432 1432 + static const char * const ipq8074_pciephy_clk_l[] = { 1433 1433 + "aux", "cfg_ahb", 1434 1434 + }; 1435 1435 + 1582 1436 static const char * const msm8996_phy_clk_l[] = { 1583 1437 "aux", "cfg_ahb", "ref", 1584 1438 }; 1585 1439 1440 1440 + static const char * const sc8280xp_pciephy_clk_l[] = { 1441 1441 + "aux", "cfg_ahb", "ref", "rchng", 1442 1442 + }; 1586 1443 1587 1444 static const char * const sdm845_pciephy_clk_l[] = { 1588 1445 "aux", "cfg_ahb", "ref", "refgen", ··· 1598 1441 /* list of regulators */ 1599 1442 static const char * const qmp_phy_vreg_l[] = { 1600 1443 "vdda-phy", "vdda-pll", 1601 1601 - }; 1602 1602 - 1603 1603 - static const char * const ipq8074_pciephy_clk_l[] = { 1604 1604 - "aux", "cfg_ahb", 1605 1444 }; 1606 1445 1607 1446 /* list of resets */ ··· 1609 1456 "phy", 1610 1457 }; 1611 1458 1459 1459 + static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { 1460 1460 + .serdes = 0, 1461 1461 + .pcs = 0x0200, 1462 1462 + .pcs_misc = 0x0600, 1463 1463 + .tx = 0x0e00, 1464 1464 + .rx = 0x1000, 1465 1465 + .tx2 = 0x1600, 1466 1466 + .rx2 = 0x1800, 1467 1467 + }; 1468 1468 + 1612 1469 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 1613 1470 .lanes = 1, 1614 1471 1615 1615 - .serdes_tbl = ipq8074_pcie_serdes_tbl, 1616 1616 - .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 1617 1617 - .tx_tbl = ipq8074_pcie_tx_tbl, 1618 1618 - .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 1619 1619 - .rx_tbl = ipq8074_pcie_rx_tbl, 1620 1620 - .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 1621 1621 - .pcs_tbl = ipq8074_pcie_pcs_tbl, 1622 1622 - .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 1472 1472 + .tbls = { 1473 1473 + .serdes = ipq8074_pcie_serdes_tbl, 1474 1474 + .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 1475 1475 + .tx = ipq8074_pcie_tx_tbl, 1476 1476 + .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 1477 1477 + .rx = ipq8074_pcie_rx_tbl, 1478 1478 + .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 1479 1479 + .pcs = ipq8074_pcie_pcs_tbl, 1480 1480 + .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 1481 1481 + }, 1623 1482 .clk_list = ipq8074_pciephy_clk_l, 1624 1483 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1625 1484 .reset_list = ipq8074_pciephy_reset_l, ··· 1640 1475 .num_vregs = 0, 1641 1476 .regs = pciephy_regs_layout, 1642 1477 1643 1643 - .start_ctrl = SERDES_START | PCS_START, 1644 1478 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1645 1479 .phy_status = PHYSTATUS, 1646 1646 - 1647 1647 - .has_pwrdn_delay = true, 1648 1648 - .pwrdn_delay_min = 995, /* us */ 1649 1649 - .pwrdn_delay_max = 1005, /* us */ 1650 1480 }; 1651 1481 1652 1482 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 1653 1483 .lanes = 1, 1654 1484 1655 1655 - .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl, 1656 1656 - .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 1657 1657 - .tx_tbl = ipq8074_pcie_gen3_tx_tbl, 1658 1658 - .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 1659 1659 - .rx_tbl = ipq8074_pcie_gen3_rx_tbl, 1660 1660 - .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 1661 1661 - .pcs_tbl = ipq8074_pcie_gen3_pcs_tbl, 1662 1662 - .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 1485 1485 + .tbls = { 1486 1486 + .serdes = ipq8074_pcie_gen3_serdes_tbl, 1487 1487 + .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 1488 1488 + .tx = ipq8074_pcie_gen3_tx_tbl, 1489 1489 + .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 1490 1490 + .rx = ipq8074_pcie_gen3_rx_tbl, 1491 1491 + .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 1492 1492 + .pcs = ipq8074_pcie_gen3_pcs_tbl, 1493 1493 + .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 1494 1494 + .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl, 1495 1495 + .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl), 1496 1496 + }, 1663 1497 .clk_list = ipq8074_pciephy_clk_l, 1664 1498 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1665 1499 .reset_list = ipq8074_pciephy_reset_l, ··· 1667 1503 .num_vregs = 0, 1668 1504 .regs = ipq_pciephy_gen3_regs_layout, 1669 1505 1670 1670 - .start_ctrl = SERDES_START | PCS_START, 1671 1506 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1672 1672 - 1673 1673 - .has_pwrdn_delay = true, 1674 1674 - .pwrdn_delay_min = 995, /* us */ 1675 1675 - .pwrdn_delay_max = 1005, /* us */ 1507 1507 + .phy_status = PHYSTATUS, 1676 1508 1677 1509 .pipe_clock_rate = 250000000, 1678 1510 }; ··· 1676 1516 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 1677 1517 .lanes = 1, 1678 1518 1679 1679 - .serdes_tbl = ipq6018_pcie_serdes_tbl, 1680 1680 - .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 1681 1681 - .tx_tbl = ipq6018_pcie_tx_tbl, 1682 1682 - .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 1683 1683 - .rx_tbl = ipq6018_pcie_rx_tbl, 1684 1684 - .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 1685 1685 - .pcs_tbl = ipq6018_pcie_pcs_tbl, 1686 1686 - .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 1687 1687 - .pcs_misc_tbl = ipq6018_pcie_pcs_misc_tbl, 1688 1688 - .pcs_misc_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 1519 1519 + .tbls = { 1520 1520 + .serdes = ipq6018_pcie_serdes_tbl, 1521 1521 + .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 1522 1522 + .tx = ipq6018_pcie_tx_tbl, 1523 1523 + .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 1524 1524 + .rx = ipq6018_pcie_rx_tbl, 1525 1525 + .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 1526 1526 + .pcs = ipq6018_pcie_pcs_tbl, 1527 1527 + .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 1528 1528 + .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 1529 1529 + .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 1530 1530 + }, 1689 1531 .clk_list = ipq8074_pciephy_clk_l, 1690 1532 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1691 1533 .reset_list = ipq8074_pciephy_reset_l, ··· 1696 1534 .num_vregs = 0, 1697 1535 .regs = ipq_pciephy_gen3_regs_layout, 1698 1536 1699 1699 - .start_ctrl = SERDES_START | PCS_START, 1700 1537 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1701 1701 - 1702 1702 - .has_pwrdn_delay = true, 1703 1703 - .pwrdn_delay_min = 995, /* us */ 1704 1704 - .pwrdn_delay_max = 1005, /* us */ 1538 1538 + .phy_status = PHYSTATUS, 1705 1539 }; 1706 1540 1707 1541 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 1708 1542 .lanes = 1, 1709 1543 1710 1710 - .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, 1711 1711 - .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 1712 1712 - .tx_tbl = sdm845_qmp_pcie_tx_tbl, 1713 1713 - .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 1714 1714 - .rx_tbl = sdm845_qmp_pcie_rx_tbl, 1715 1715 - .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 1716 1716 - .pcs_tbl = sdm845_qmp_pcie_pcs_tbl, 1717 1717 - .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 1718 1718 - .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, 1719 1719 - .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 1544 1544 + .tbls = { 1545 1545 + .serdes = sdm845_qmp_pcie_serdes_tbl, 1546 1546 + .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 1547 1547 + .tx = sdm845_qmp_pcie_tx_tbl, 1548 1548 + .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 1549 1549 + .rx = sdm845_qmp_pcie_rx_tbl, 1550 1550 + .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 1551 1551 + .pcs = sdm845_qmp_pcie_pcs_tbl, 1552 1552 + .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 1553 1553 + .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 1554 1554 + .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 1555 1555 + }, 1720 1556 .clk_list = sdm845_pciephy_clk_l, 1721 1557 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1722 1558 .reset_list = sdm845_pciephy_reset_l, ··· 1723 1563 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1724 1564 .regs = sdm845_qmp_pciephy_regs_layout, 1725 1565 1726 1726 - .start_ctrl = PCS_START | SERDES_START, 1727 1566 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1728 1567 .phy_status = PHYSTATUS, 1729 1729 - 1730 1730 - .has_pwrdn_delay = true, 1731 1731 - .pwrdn_delay_min = 995, /* us */ 1732 1732 - .pwrdn_delay_max = 1005, /* us */ 1733 1568 }; 1734 1569 1735 1570 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 1736 1571 .lanes = 1, 1737 1572 1738 1738 - .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, 1739 1739 - .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 1740 1740 - .tx_tbl = sdm845_qhp_pcie_tx_tbl, 1741 1741 - .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 1742 1742 - .rx_tbl = sdm845_qhp_pcie_rx_tbl, 1743 1743 - .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), 1744 1744 - .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, 1745 1745 - .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 1573 1573 + .tbls = { 1574 1574 + .serdes = sdm845_qhp_pcie_serdes_tbl, 1575 1575 + .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 1576 1576 + .tx = sdm845_qhp_pcie_tx_tbl, 1577 1577 + .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 1578 1578 + .rx = sdm845_qhp_pcie_rx_tbl, 1579 1579 + .rx_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), 1580 1580 + .pcs = sdm845_qhp_pcie_pcs_tbl, 1581 1581 + .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 1582 1582 + }, 1746 1583 .clk_list = sdm845_pciephy_clk_l, 1747 1584 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1748 1585 .reset_list = sdm845_pciephy_reset_l, ··· 1748 1591 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1749 1592 .regs = sdm845_qhp_pciephy_regs_layout, 1750 1593 1751 1751 - .start_ctrl = PCS_START | SERDES_START, 1752 1594 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1753 1595 .phy_status = PHYSTATUS, 1754 1754 - 1755 1755 - .has_pwrdn_delay = true, 1756 1756 - .pwrdn_delay_min = 995, /* us */ 1757 1757 - .pwrdn_delay_max = 1005, /* us */ 1758 1596 }; 1759 1597 1760 1598 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 1761 1599 .lanes = 1, 1762 1600 1763 1763 - .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, 1764 1764 - .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1765 1765 - .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, 1766 1766 - .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 1767 1767 - .tx_tbl = sm8250_qmp_pcie_tx_tbl, 1768 1768 - .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1769 1769 - .rx_tbl = sm8250_qmp_pcie_rx_tbl, 1770 1770 - .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1771 1771 - .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, 1772 1772 - .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 1773 1773 - .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, 1774 1774 - .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1775 1775 - .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, 1776 1776 - .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 1777 1777 - .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, 1778 1778 - .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1779 1779 - .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 1780 1780 - .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 1601 1601 + .tbls = { 1602 1602 + .serdes = sm8250_qmp_pcie_serdes_tbl, 1603 1603 + .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1604 1604 + .tx = sm8250_qmp_pcie_tx_tbl, 1605 1605 + .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1606 1606 + .rx = sm8250_qmp_pcie_rx_tbl, 1607 1607 + .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1608 1608 + .pcs = sm8250_qmp_pcie_pcs_tbl, 1609 1609 + .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1610 1610 + .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1611 1611 + .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1612 1612 + }, 1613 1613 + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1614 1614 + .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 1615 1615 + .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 1616 1616 + .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 1617 1617 + .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 1618 1618 + .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 1619 1619 + .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 1620 1620 + .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 1621 1621 + .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 1622 1622 + }, 1781 1623 .clk_list = sdm845_pciephy_clk_l, 1782 1624 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1783 1625 .reset_list = sdm845_pciephy_reset_l, ··· 1785 1629 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1786 1630 .regs = sm8250_pcie_regs_layout, 1787 1631 1788 1788 - .start_ctrl = PCS_START | SERDES_START, 1789 1632 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1790 1633 .phy_status = PHYSTATUS, 1791 1791 - 1792 1792 - .has_pwrdn_delay = true, 1793 1793 - .pwrdn_delay_min = 995, /* us */ 1794 1794 - .pwrdn_delay_max = 1005, /* us */ 1795 1634 }; 1796 1635 1797 1636 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 1798 1637 .lanes = 2, 1799 1638 1800 1800 - .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, 1801 1801 - .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1802 1802 - .tx_tbl = sm8250_qmp_pcie_tx_tbl, 1803 1803 - .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1804 1804 - .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, 1805 1805 - .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 1806 1806 - .rx_tbl = sm8250_qmp_pcie_rx_tbl, 1807 1807 - .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1808 1808 - .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, 1809 1809 - .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 1810 1810 - .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, 1811 1811 - .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1812 1812 - .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, 1813 1813 - .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 1814 1814 - .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, 1815 1815 - .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1816 1816 - .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 1817 1817 - .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 1639 1639 + .tbls = { 1640 1640 + .serdes = sm8250_qmp_pcie_serdes_tbl, 1641 1641 + .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1642 1642 + .tx = sm8250_qmp_pcie_tx_tbl, 1643 1643 + .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1644 1644 + .rx = sm8250_qmp_pcie_rx_tbl, 1645 1645 + .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1646 1646 + .pcs = sm8250_qmp_pcie_pcs_tbl, 1647 1647 + .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1648 1648 + .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1649 1649 + .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1650 1650 + }, 1651 1651 + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1652 1652 + .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 1653 1653 + .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 1654 1654 + .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 1655 1655 + .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 1656 1656 + .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 1657 1657 + .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 1658 1658 + .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 1659 1659 + .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 1660 1660 + }, 1818 1661 .clk_list = sdm845_pciephy_clk_l, 1819 1662 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1820 1663 .reset_list = sdm845_pciephy_reset_l, ··· 1822 1667 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1823 1668 .regs = sm8250_pcie_regs_layout, 1824 1669 1825 1825 - .start_ctrl = PCS_START | SERDES_START, 1826 1670 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1827 1671 .phy_status = PHYSTATUS, 1828 1828 - 1829 1829 - .has_pwrdn_delay = true, 1830 1830 - .pwrdn_delay_min = 995, /* us */ 1831 1831 - .pwrdn_delay_max = 1005, /* us */ 1832 1672 }; 1833 1673 1834 1674 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 1835 1675 .lanes = 1, 1836 1676 1837 1837 - .serdes_tbl = msm8998_pcie_serdes_tbl, 1838 1838 - .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 1839 1839 - .tx_tbl = msm8998_pcie_tx_tbl, 1840 1840 - .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 1841 1841 - .rx_tbl = msm8998_pcie_rx_tbl, 1842 1842 - .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 1843 1843 - .pcs_tbl = msm8998_pcie_pcs_tbl, 1844 1844 - .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 1677 1677 + .tbls = { 1678 1678 + .serdes = msm8998_pcie_serdes_tbl, 1679 1679 + .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 1680 1680 + .tx = msm8998_pcie_tx_tbl, 1681 1681 + .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 1682 1682 + .rx = msm8998_pcie_rx_tbl, 1683 1683 + .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 1684 1684 + .pcs = msm8998_pcie_pcs_tbl, 1685 1685 + .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 1686 1686 + }, 1845 1687 .clk_list = msm8996_phy_clk_l, 1846 1688 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1847 1689 .reset_list = ipq8074_pciephy_reset_l, ··· 1847 1695 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1848 1696 .regs = pciephy_regs_layout, 1849 1697 1850 1850 - .start_ctrl = SERDES_START | PCS_START, 1851 1698 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1852 1699 .phy_status = PHYSTATUS, 1700 1700 + 1701 1701 + .skip_start_delay = true, 1853 1702 }; 1854 1703 1855 1704 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 1856 1705 .lanes = 1, 1857 1706 1858 1858 - .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, 1859 1859 - .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 1860 1860 - .tx_tbl = sc8180x_qmp_pcie_tx_tbl, 1861 1861 - .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 1862 1862 - .rx_tbl = sc8180x_qmp_pcie_rx_tbl, 1863 1863 - .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 1864 1864 - .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl, 1865 1865 - .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 1866 1866 - .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl, 1867 1867 - .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 1707 1707 + .tbls = { 1708 1708 + .serdes = sc8180x_qmp_pcie_serdes_tbl, 1709 1709 + .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 1710 1710 + .tx = sc8180x_qmp_pcie_tx_tbl, 1711 1711 + .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 1712 1712 + .rx = sc8180x_qmp_pcie_rx_tbl, 1713 1713 + .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 1714 1714 + .pcs = sc8180x_qmp_pcie_pcs_tbl, 1715 1715 + .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 1716 1716 + .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 1717 1717 + .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 1718 1718 + }, 1868 1719 .clk_list = sdm845_pciephy_clk_l, 1869 1720 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1870 1721 .reset_list = sdm845_pciephy_reset_l, ··· 1876 1721 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1877 1722 .regs = sm8250_pcie_regs_layout, 1878 1723 1879 1879 - .start_ctrl = PCS_START | SERDES_START, 1880 1724 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1725 1725 + .phy_status = PHYSTATUS, 1726 1726 + }; 1881 1727 1882 1882 - .has_pwrdn_delay = true, 1883 1883 - .pwrdn_delay_min = 995, /* us */ 1884 1884 - .pwrdn_delay_max = 1005, /* us */ 1728 1728 + static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { 1729 1729 + .lanes = 1, 1730 1730 + 1731 1731 + .offsets = &qmp_pcie_offsets_v5, 1732 1732 + 1733 1733 + .tbls = { 1734 1734 + .serdes = sc8280xp_qmp_pcie_serdes_tbl, 1735 1735 + .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 1736 1736 + .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl, 1737 1737 + .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl), 1738 1738 + .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl, 1739 1739 + .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl), 1740 1740 + .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl, 1741 1741 + .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl), 1742 1742 + .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl, 1743 1743 + .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl), 1744 1744 + }, 1745 1745 + 1746 1746 + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1747 1747 + .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl, 1748 1748 + .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl), 1749 1749 + }, 1750 1750 + 1751 1751 + .clk_list = sc8280xp_pciephy_clk_l, 1752 1752 + .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 1753 1753 + .reset_list = sdm845_pciephy_reset_l, 1754 1754 + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1755 1755 + .vreg_list = qmp_phy_vreg_l, 1756 1756 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1757 1757 + .regs = sm8250_pcie_regs_layout, 1758 1758 + 1759 1759 + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1760 1760 + .phy_status = PHYSTATUS, 1761 1761 + }; 1762 1762 + 1763 1763 + static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { 1764 1764 + .lanes = 2, 1765 1765 + 1766 1766 + .offsets = &qmp_pcie_offsets_v5, 1767 1767 + 1768 1768 + .tbls = { 1769 1769 + .serdes = sc8280xp_qmp_pcie_serdes_tbl, 1770 1770 + .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 1771 1771 + .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 1772 1772 + .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 1773 1773 + .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 1774 1774 + .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 1775 1775 + .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 1776 1776 + .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 1777 1777 + .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 1778 1778 + .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 1779 1779 + }, 1780 1780 + 1781 1781 + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1782 1782 + .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 1783 1783 + .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 1784 1784 + }, 1785 1785 + 1786 1786 + .clk_list = sc8280xp_pciephy_clk_l, 1787 1787 + .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 1788 1788 + .reset_list = sdm845_pciephy_reset_l, 1789 1789 + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1790 1790 + .vreg_list = qmp_phy_vreg_l, 1791 1791 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1792 1792 + .regs = sm8250_pcie_regs_layout, 1793 1793 + 1794 1794 + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1795 1795 + .phy_status = PHYSTATUS, 1796 1796 + }; 1797 1797 + 1798 1798 + static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { 1799 1799 + .lanes = 4, 1800 1800 + 1801 1801 + .offsets = &qmp_pcie_offsets_v5, 1802 1802 + 1803 1803 + .tbls = { 1804 1804 + .serdes = sc8280xp_qmp_pcie_serdes_tbl, 1805 1805 + .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 1806 1806 + .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 1807 1807 + .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 1808 1808 + .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 1809 1809 + .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 1810 1810 + .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 1811 1811 + .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 1812 1812 + .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 1813 1813 + .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 1814 1814 + }, 1815 1815 + 1816 1816 + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1817 1817 + .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 1818 1818 + .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 1819 1819 + }, 1820 1820 + 1821 1821 + .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl, 1822 1822 + .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl), 1823 1823 + 1824 1824 + .clk_list = sc8280xp_pciephy_clk_l, 1825 1825 + .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 1826 1826 + .reset_list = sdm845_pciephy_reset_l, 1827 1827 + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1828 1828 + .vreg_list = qmp_phy_vreg_l, 1829 1829 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1830 1830 + .regs = sm8250_pcie_regs_layout, 1831 1831 + 1832 1832 + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1833 1833 + .phy_status = PHYSTATUS, 1885 1834 }; 1886 1835 1887 1836 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 1888 1837 .lanes = 2, 1889 1838 1890 1890 - .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, 1891 1891 - .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 1892 1892 - .tx_tbl = sdx55_qmp_pcie_tx_tbl, 1893 1893 - .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 1894 1894 - .rx_tbl = sdx55_qmp_pcie_rx_tbl, 1895 1895 - .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 1896 1896 - .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, 1897 1897 - .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 1898 1898 - .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, 1899 1899 - .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 1839 1839 + .tbls = { 1840 1840 + .serdes = sdx55_qmp_pcie_serdes_tbl, 1841 1841 + .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 1842 1842 + .tx = sdx55_qmp_pcie_tx_tbl, 1843 1843 + .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 1844 1844 + .rx = sdx55_qmp_pcie_rx_tbl, 1845 1845 + .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 1846 1846 + .pcs = sdx55_qmp_pcie_pcs_tbl, 1847 1847 + .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 1848 1848 + .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 1849 1849 + .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 1850 1850 + }, 1900 1851 .clk_list = sdm845_pciephy_clk_l, 1901 1852 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1902 1853 .reset_list = sdm845_pciephy_reset_l, ··· 2011 1750 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2012 1751 .regs = sm8250_pcie_regs_layout, 2013 1752 2014 2014 - .start_ctrl = PCS_START | SERDES_START, 2015 1753 .pwrdn_ctrl = SW_PWRDN, 2016 1754 .phy_status = PHYSTATUS_4_20, 2017 2017 - 2018 2018 - .has_pwrdn_delay = true, 2019 2019 - .pwrdn_delay_min = 995, /* us */ 2020 2020 - .pwrdn_delay_max = 1005, /* us */ 2021 1755 }; 2022 1756 2023 1757 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 2024 1758 .lanes = 1, 2025 1759 2026 2026 - .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, 2027 2027 - .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), 2028 2028 - .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, 2029 2029 - .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 2030 2030 - .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl, 2031 2031 - .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), 2032 2032 - .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl, 2033 2033 - .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), 2034 2034 - .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 2035 2035 - .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 1760 1760 + .tbls = { 1761 1761 + .serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl, 1762 1762 + .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), 1763 1763 + .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 1764 1764 + .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 1765 1765 + .rx = sm8450_qmp_gen3x1_pcie_rx_tbl, 1766 1766 + .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), 1767 1767 + .pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl, 1768 1768 + .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), 1769 1769 + .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 1770 1770 + .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 1771 1771 + }, 2036 1772 .clk_list = sdm845_pciephy_clk_l, 2037 1773 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2038 1774 .reset_list = sdm845_pciephy_reset_l, ··· 2038 1780 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2039 1781 .regs = sm8250_pcie_regs_layout, 2040 1782 2041 2041 - .start_ctrl = SERDES_START | PCS_START, 2042 1783 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2043 1784 .phy_status = PHYSTATUS, 2044 2044 - 2045 2045 - .has_pwrdn_delay = true, 2046 2046 - .pwrdn_delay_min = 995, /* us */ 2047 2047 - .pwrdn_delay_max = 1005, /* us */ 2048 1785 }; 2049 1786 2050 1787 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 2051 1788 .lanes = 2, 2052 1789 2053 2053 - .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, 2054 2054 - .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 2055 2055 - .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl, 2056 2056 - .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 2057 2057 - .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl, 2058 2058 - .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 2059 2059 - .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl, 2060 2060 - .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 2061 2061 - .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 2062 2062 - .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 1790 1790 + .tbls = { 1791 1791 + .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 1792 1792 + .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 1793 1793 + .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 1794 1794 + .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 1795 1795 + .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 1796 1796 + .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 1797 1797 + .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 1798 1798 + .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 1799 1799 + .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 1800 1800 + .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 1801 1801 + }, 1802 1802 + 1803 1803 + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1804 1804 + .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, 1805 1805 + .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), 1806 1806 + .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, 1807 1807 + .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), 1808 1808 + }, 1809 1809 + 1810 1810 + .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 1811 1811 + .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, 1812 1812 + .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), 1813 1813 + .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 1814 1814 + .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 1815 1815 + }, 1816 1816 + 2063 1817 .clk_list = sdm845_pciephy_clk_l, 2064 1818 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2065 1819 .reset_list = sdm845_pciephy_reset_l, ··· 2080 1810 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2081 1811 .regs = sm8250_pcie_regs_layout, 2082 1812 2083 2083 - .start_ctrl = SERDES_START | PCS_START, 2084 1813 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2085 1814 .phy_status = PHYSTATUS_4_20, 2086 2086 - 2087 2087 - .has_pwrdn_delay = true, 2088 2088 - .pwrdn_delay_min = 995, /* us */ 2089 2089 - .pwrdn_delay_max = 1005, /* us */ 2090 1815 }; 2091 1816 2092 1817 static void qmp_pcie_configure_lane(void __iomem *base, 2093 2093 - const unsigned int *regs, 2094 1818 const struct qmp_phy_init_tbl tbl[], 2095 1819 int num, 2096 1820 u8 lane_mask) ··· 2099 1835 if (!(t->lane_mask & lane_mask)) 2100 1836 continue; 2101 1837 2102 2102 - if (t->in_layout) 2103 2103 - writel(t->val, base + regs[t->offset]); 2104 2104 - else 2105 2105 - writel(t->val, base + t->offset); 1838 1838 + writel(t->val, base + t->offset); 2106 1839 } 2107 1840 } 2108 1841 2109 1842 static void qmp_pcie_configure(void __iomem *base, 2110 2110 - const unsigned int *regs, 2111 1843 const struct qmp_phy_init_tbl tbl[], 2112 1844 int num) 2113 1845 { 2114 2114 - qmp_pcie_configure_lane(base, regs, tbl, num, 0xff); 1846 1846 + qmp_pcie_configure_lane(base, tbl, num, 0xff); 2115 1847 } 2116 1848 2117 2117 - static int qmp_pcie_serdes_init(struct qmp_phy *qphy) 1849 1849 + static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 2118 1850 { 2119 2119 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2120 2120 - void __iomem *serdes = qphy->serdes; 2121 2121 - const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 2122 2122 - int serdes_tbl_num = cfg->serdes_tbl_num; 1851 1851 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1852 1852 + const struct qmp_pcie_offsets *offs = cfg->offsets; 1853 1853 + void __iomem *tx3, *rx3, *tx4, *rx4; 2123 1854 2124 2124 - qmp_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 2125 2125 - qmp_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, cfg->serdes_tbl_num_sec); 1855 1855 + tx3 = qmp->port_b + offs->tx; 1856 1856 + rx3 = qmp->port_b + offs->rx; 1857 1857 + tx4 = qmp->port_b + offs->tx2; 1858 1858 + rx4 = qmp->port_b + offs->rx2; 2126 1859 2127 2127 - return 0; 1860 1860 + qmp_pcie_configure_lane(tx3, tbls->tx, tbls->tx_num, 1); 1861 1861 + qmp_pcie_configure_lane(rx3, tbls->rx, tbls->rx_num, 1); 1862 1862 + 1863 1863 + qmp_pcie_configure_lane(tx4, tbls->tx, tbls->tx_num, 2); 1864 1864 + qmp_pcie_configure_lane(rx4, tbls->rx, tbls->rx_num, 2); 1865 1865 + } 1866 1866 + 1867 1867 + static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 1868 1868 + { 1869 1869 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1870 1870 + void __iomem *serdes = qmp->serdes; 1871 1871 + void __iomem *tx = qmp->tx; 1872 1872 + void __iomem *rx = qmp->rx; 1873 1873 + void __iomem *tx2 = qmp->tx2; 1874 1874 + void __iomem *rx2 = qmp->rx2; 1875 1875 + void __iomem *pcs = qmp->pcs; 1876 1876 + void __iomem *pcs_misc = qmp->pcs_misc; 1877 1877 + 1878 1878 + if (!tbls) 1879 1879 + return; 1880 1880 + 1881 1881 + qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num); 1882 1882 + 1883 1883 + qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1); 1884 1884 + qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1); 1885 1885 + 1886 1886 + if (cfg->lanes >= 2) { 1887 1887 + qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2); 1888 1888 + qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2); 1889 1889 + } 1890 1890 + 1891 1891 + qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); 1892 1892 + qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 1893 1893 + 1894 1894 + if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 1895 1895 + qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); 1896 1896 + qmp_pcie_init_port_b(qmp, tbls); 1897 1897 + } 2128 1898 } 2129 1899 2130 1900 static int qmp_pcie_init(struct phy *phy) 2131 1901 { 2132 2132 - struct qmp_phy *qphy = phy_get_drvdata(phy); 2133 2133 - struct qcom_qmp *qmp = qphy->qmp; 2134 2134 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2135 2135 - void __iomem *pcs = qphy->pcs; 1902 1902 + struct qmp_pcie *qmp = phy_get_drvdata(phy); 1903 1903 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2136 1904 int ret; 2137 1905 2138 2138 - /* turn on regulator supplies */ 2139 1906 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2140 1907 if (ret) { 2141 1908 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); ··· 2179 1884 goto err_disable_regulators; 2180 1885 } 2181 1886 1887 1887 + usleep_range(200, 300); 1888 1888 + 2182 1889 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2183 1890 if (ret) { 2184 1891 dev_err(qmp->dev, "reset deassert failed\n"); ··· 2190 1893 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2191 1894 if (ret) 2192 1895 goto err_assert_reset; 2193 2193 - 2194 2194 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 2195 2195 - qphy_setbits(pcs, 2196 2196 - cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2197 2197 - cfg->pwrdn_ctrl); 2198 2198 - else 2199 2199 - qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 2200 2200 - cfg->pwrdn_ctrl); 2201 1896 2202 1897 return 0; 2203 1898 ··· 2203 1914 2204 1915 static int qmp_pcie_exit(struct phy *phy) 2205 1916 { 2206 2206 - struct qmp_phy *qphy = phy_get_drvdata(phy); 2207 2207 - struct qcom_qmp *qmp = qphy->qmp; 2208 2208 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1917 1917 + struct qmp_pcie *qmp = phy_get_drvdata(phy); 1918 1918 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2209 1919 2210 1920 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2211 1921 ··· 2217 1929 2218 1930 static int qmp_pcie_power_on(struct phy *phy) 2219 1931 { 2220 2220 - struct qmp_phy *qphy = phy_get_drvdata(phy); 2221 2221 - struct qcom_qmp *qmp = qphy->qmp; 2222 2222 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2223 2223 - void __iomem *tx = qphy->tx; 2224 2224 - void __iomem *rx = qphy->rx; 2225 2225 - void __iomem *pcs = qphy->pcs; 2226 2226 - void __iomem *pcs_misc = qphy->pcs_misc; 1932 1932 + struct qmp_pcie *qmp = phy_get_drvdata(phy); 1933 1933 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1934 1934 + const struct qmp_phy_cfg_tbls *mode_tbls; 1935 1935 + void __iomem *pcs = qmp->pcs; 2227 1936 void __iomem *status; 2228 2228 - unsigned int mask, val, ready; 1937 1937 + unsigned int mask, val; 2229 1938 int ret; 2230 1939 2231 2231 - qmp_pcie_serdes_init(qphy); 1940 1940 + qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1941 1941 + cfg->pwrdn_ctrl); 2232 1942 2233 2233 - ret = clk_prepare_enable(qphy->pipe_clk); 2234 2234 - if (ret) { 2235 2235 - dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1943 1943 + if (qmp->mode == PHY_MODE_PCIE_RC) 1944 1944 + mode_tbls = cfg->tbls_rc; 1945 1945 + else 1946 1946 + mode_tbls = cfg->tbls_ep; 1947 1947 + 1948 1948 + qmp_pcie_init_registers(qmp, &cfg->tbls); 1949 1949 + qmp_pcie_init_registers(qmp, mode_tbls); 1950 1950 + 1951 1951 + ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); 1952 1952 + if (ret) 2236 1953 return ret; 2237 2237 - } 2238 2238 - 2239 2239 - /* Tx, Rx, and PCS configurations */ 2240 2240 - qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2241 2241 - qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, cfg->tx_tbl_num_sec, 1); 2242 2242 - 2243 2243 - if (cfg->lanes >= 2) { 2244 2244 - qmp_pcie_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl, 2245 2245 - cfg->tx_tbl_num, 2); 2246 2246 - qmp_pcie_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl_sec, 2247 2247 - cfg->tx_tbl_num_sec, 2); 2248 2248 - } 2249 2249 - 2250 2250 - qmp_pcie_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2251 2251 - qmp_pcie_configure_lane(rx, cfg->regs, cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); 2252 2252 - 2253 2253 - if (cfg->lanes >= 2) { 2254 2254 - qmp_pcie_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl, 2255 2255 - cfg->rx_tbl_num, 2); 2256 2256 - qmp_pcie_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl_sec, 2257 2257 - cfg->rx_tbl_num_sec, 2); 2258 2258 - } 2259 2259 - 2260 2260 - qmp_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2261 2261 - qmp_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, cfg->pcs_tbl_num_sec); 2262 2262 - 2263 2263 - qmp_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num); 2264 2264 - qmp_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, cfg->pcs_misc_tbl_num_sec); 2265 2265 - 2266 2266 - /* 2267 2267 - * Pull out PHY from POWER DOWN state. 2268 2268 - * This is active low enable signal to power-down PHY. 2269 2269 - */ 2270 2270 - qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 2271 2271 - 2272 2272 - if (cfg->has_pwrdn_delay) 2273 2273 - usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 2274 1954 2275 1955 /* Pull PHY out of reset state */ 2276 1956 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2277 1957 2278 1958 /* start SerDes and Phy-Coding-Sublayer */ 2279 2279 - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1959 1959 + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 1960 1960 + 1961 1961 + if (!cfg->skip_start_delay) 1962 1962 + usleep_range(1000, 1200); 2280 1963 2281 1964 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2282 1965 mask = cfg->phy_status; 2283 2283 - ready = 0; 2284 2284 - 2285 2285 - ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 1966 1966 + ret = readl_poll_timeout(status, val, !(val & mask), 200, 2286 1967 PHY_INIT_COMPLETE_TIMEOUT); 2287 1968 if (ret) { 2288 1969 dev_err(qmp->dev, "phy initialization timed-out\n"); ··· 2261 2004 return 0; 2262 2005 2263 2006 err_disable_pipe_clk: 2264 2264 - clk_disable_unprepare(qphy->pipe_clk); 2007 2007 + clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 2265 2008 2266 2009 return ret; 2267 2010 } 2268 2011 2269 2012 static int qmp_pcie_power_off(struct phy *phy) 2270 2013 { 2271 2271 - struct qmp_phy *qphy = phy_get_drvdata(phy); 2272 2272 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2014 2014 + struct qmp_pcie *qmp = phy_get_drvdata(phy); 2015 2015 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2273 2016 2274 2274 - clk_disable_unprepare(qphy->pipe_clk); 2017 2017 + clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 2275 2018 2276 2019 /* PHY reset */ 2277 2277 - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2020 2020 + qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2278 2021 2279 2022 /* stop SerDes and Phy-Coding-Sublayer */ 2280 2280 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2023 2023 + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2024 2024 + SERDES_START | PCS_START); 2281 2025 2282 2026 /* Put PHY into POWER DOWN state: active low */ 2283 2283 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 2284 2284 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2285 2285 - cfg->pwrdn_ctrl); 2286 2286 - } else { 2287 2287 - qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 2288 2288 - cfg->pwrdn_ctrl); 2289 2289 - } 2027 2027 + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2028 2028 + cfg->pwrdn_ctrl); 2290 2029 2291 2030 return 0; 2292 2031 } ··· 2313 2060 return qmp_pcie_exit(phy); 2314 2061 } 2315 2062 2316 2316 - static int qmp_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2063 2063 + static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2317 2064 { 2318 2318 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2065 2065 + struct qmp_pcie *qmp = phy_get_drvdata(phy); 2066 2066 + 2067 2067 + switch (submode) { 2068 2068 + case PHY_MODE_PCIE_RC: 2069 2069 + case PHY_MODE_PCIE_EP: 2070 2070 + qmp->mode = submode; 2071 2071 + break; 2072 2072 + default: 2073 2073 + dev_err(&phy->dev, "Unsupported submode %d\n", submode); 2074 2074 + return -EINVAL; 2075 2075 + } 2076 2076 + 2077 2077 + return 0; 2078 2078 + } 2079 2079 + 2080 2080 + static const struct phy_ops qmp_pcie_phy_ops = { 2081 2081 + .power_on = qmp_pcie_enable, 2082 2082 + .power_off = qmp_pcie_disable, 2083 2083 + .set_mode = qmp_pcie_set_mode, 2084 2084 + .owner = THIS_MODULE, 2085 2085 + }; 2086 2086 + 2087 2087 + static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) 2088 2088 + { 2089 2089 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2090 2090 + struct device *dev = qmp->dev; 2319 2091 int num = cfg->num_vregs; 2320 2092 int i; 2321 2093 ··· 2354 2076 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2355 2077 } 2356 2078 2357 2357 - static int qmp_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2079 2079 + static int qmp_pcie_reset_init(struct qmp_pcie *qmp) 2358 2080 { 2359 2359 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2081 2081 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2082 2082 + struct device *dev = qmp->dev; 2360 2083 int i; 2361 2084 int ret; 2362 2085 ··· 2376 2097 return 0; 2377 2098 } 2378 2099 2379 2379 - static int qmp_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2100 2100 + static int qmp_pcie_clk_init(struct qmp_pcie *qmp) 2380 2101 { 2381 2381 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2102 2102 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2103 2103 + struct device *dev = qmp->dev; 2382 2104 int num = cfg->num_clks; 2383 2105 int i; 2384 2106 ··· 2416 2136 * clk | +-------+ | +-----+ 2417 2137 * +---------------+ 2418 2138 */ 2419 2419 - static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 2139 2139 + static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) 2420 2140 { 2421 2421 - struct clk_fixed_rate *fixed; 2141 2141 + struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2422 2142 struct clk_init_data init = { }; 2423 2143 int ret; 2424 2144 ··· 2428 2148 return ret; 2429 2149 } 2430 2150 2431 2431 - fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2432 2432 - if (!fixed) 2433 2433 - return -ENOMEM; 2434 2434 - 2435 2151 init.ops = &clk_fixed_rate_ops; 2436 2152 2437 2153 /* 2438 2154 * Controllers using QMP PHY-s use 125MHz pipe clock interface 2439 2155 * unless other frequency is specified in the PHY config. 2440 2156 */ 2441 2441 - if (qmp->phys[0]->cfg->pipe_clock_rate) 2442 2442 - fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; 2157 2157 + if (qmp->cfg->pipe_clock_rate) 2158 2158 + fixed->fixed_rate = qmp->cfg->pipe_clock_rate; 2443 2159 else 2444 2160 fixed->fixed_rate = 125000000; 2445 2161 ··· 2456 2180 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2457 2181 } 2458 2182 2459 2459 - static const struct phy_ops qmp_pcie_ops = { 2460 2460 - .power_on = qmp_pcie_enable, 2461 2461 - .power_off = qmp_pcie_disable, 2462 2462 - .owner = THIS_MODULE, 2463 2463 - }; 2464 2464 - 2465 2465 - static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, 2466 2466 - void __iomem *serdes, const struct qmp_phy_cfg *cfg) 2183 2183 + static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np) 2467 2184 { 2468 2468 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2469 2469 - struct phy *generic_phy; 2470 2470 - struct qmp_phy *qphy; 2471 2471 - int ret; 2185 2185 + struct platform_device *pdev = to_platform_device(qmp->dev); 2186 2186 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2187 2187 + struct device *dev = qmp->dev; 2188 2188 + struct clk *clk; 2472 2189 2473 2473 - qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 2474 2474 - if (!qphy) 2475 2475 - return -ENOMEM; 2190 2190 + qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2191 2191 + if (IS_ERR(qmp->serdes)) 2192 2192 + return PTR_ERR(qmp->serdes); 2476 2193 2477 2477 - qphy->cfg = cfg; 2478 2478 - qphy->serdes = serdes; 2479 2194 /* 2480 2480 - * Get memory resources for each phy lane: 2195 2195 + * Get memory resources for the PHY: 2481 2196 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2482 2197 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2483 2198 * For single lane PHYs: pcs_misc (optional) -> 3. 2484 2199 */ 2485 2485 - qphy->tx = devm_of_iomap(dev, np, 0, NULL); 2486 2486 - if (IS_ERR(qphy->tx)) 2487 2487 - return PTR_ERR(qphy->tx); 2200 2200 + qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2201 2201 + if (IS_ERR(qmp->tx)) 2202 2202 + return PTR_ERR(qmp->tx); 2488 2203 2489 2204 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 2490 2490 - qphy->rx = qphy->tx; 2205 2205 + qmp->rx = qmp->tx; 2491 2206 else 2492 2492 - qphy->rx = devm_of_iomap(dev, np, 1, NULL); 2493 2493 - if (IS_ERR(qphy->rx)) 2494 2494 - return PTR_ERR(qphy->rx); 2207 2207 + qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2208 2208 + if (IS_ERR(qmp->rx)) 2209 2209 + return PTR_ERR(qmp->rx); 2495 2210 2496 2496 - qphy->pcs = devm_of_iomap(dev, np, 2, NULL); 2497 2497 - if (IS_ERR(qphy->pcs)) 2498 2498 - return PTR_ERR(qphy->pcs); 2211 2211 + qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 2212 2212 + if (IS_ERR(qmp->pcs)) 2213 2213 + return PTR_ERR(qmp->pcs); 2499 2214 2500 2215 if (cfg->lanes >= 2) { 2501 2501 - qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); 2502 2502 - if (IS_ERR(qphy->tx2)) 2503 2503 - return PTR_ERR(qphy->tx2); 2216 2216 + qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2217 2217 + if (IS_ERR(qmp->tx2)) 2218 2218 + return PTR_ERR(qmp->tx2); 2504 2219 2505 2505 - qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); 2506 2506 - if (IS_ERR(qphy->rx2)) 2507 2507 - return PTR_ERR(qphy->rx2); 2220 2220 + qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2221 2221 + if (IS_ERR(qmp->rx2)) 2222 2222 + return PTR_ERR(qmp->rx2); 2508 2223 2509 2509 - qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2224 2224 + qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2510 2225 } else { 2511 2511 - qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2226 2226 + qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2512 2227 } 2513 2228 2514 2514 - if (IS_ERR(qphy->pcs_misc) && 2229 2229 + if (IS_ERR(qmp->pcs_misc) && 2515 2230 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 2516 2516 - qphy->pcs_misc = qphy->pcs + 0x400; 2231 2231 + qmp->pcs_misc = qmp->pcs + 0x400; 2517 2232 2518 2518 - if (IS_ERR(qphy->pcs_misc)) { 2519 2519 - if (cfg->pcs_misc_tbl || cfg->pcs_misc_tbl_sec) 2520 2520 - return PTR_ERR(qphy->pcs_misc); 2233 2233 + if (IS_ERR(qmp->pcs_misc)) { 2234 2234 + if (cfg->tbls.pcs_misc || 2235 2235 + (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || 2236 2236 + (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { 2237 2237 + return PTR_ERR(qmp->pcs_misc); 2238 2238 + } 2521 2239 } 2522 2240 2523 2523 - qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2524 2524 - if (IS_ERR(qphy->pipe_clk)) { 2525 2525 - return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), 2526 2526 - "failed to get lane%d pipe clock\n", id); 2241 2241 + clk = devm_get_clk_from_child(dev, np, NULL); 2242 2242 + if (IS_ERR(clk)) { 2243 2243 + return dev_err_probe(dev, PTR_ERR(clk), 2244 2244 + "failed to get pipe clock\n"); 2527 2245 } 2528 2246 2529 2529 - generic_phy = devm_phy_create(dev, np, &qmp_pcie_ops); 2530 2530 - if (IS_ERR(generic_phy)) { 2531 2531 - ret = PTR_ERR(generic_phy); 2532 2532 - dev_err(dev, "failed to create qphy %d\n", ret); 2533 2533 - return ret; 2534 2534 - } 2535 2535 - 2536 2536 - qphy->phy = generic_phy; 2537 2537 - qphy->qmp = qmp; 2538 2538 - qmp->phys[id] = qphy; 2539 2539 - phy_set_drvdata(generic_phy, qphy); 2247 2247 + qmp->num_pipe_clks = 1; 2248 2248 + qmp->pipe_clks[0].id = "pipe"; 2249 2249 + qmp->pipe_clks[0].clk = clk; 2540 2250 2541 2251 return 0; 2542 2252 } 2543 2253 2254 2254 + static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp) 2255 2255 + { 2256 2256 + struct regmap *tcsr; 2257 2257 + unsigned int args[2]; 2258 2258 + int ret; 2259 2259 + 2260 2260 + tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, 2261 2261 + "qcom,4ln-config-sel", 2262 2262 + ARRAY_SIZE(args), args); 2263 2263 + if (IS_ERR(tcsr)) { 2264 2264 + ret = PTR_ERR(tcsr); 2265 2265 + if (ret == -ENOENT) 2266 2266 + return 0; 2267 2267 + 2268 2268 + dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); 2269 2269 + return ret; 2270 2270 + } 2271 2271 + 2272 2272 + ret = regmap_test_bits(tcsr, args[0], BIT(args[1])); 2273 2273 + if (ret < 0) { 2274 2274 + dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); 2275 2275 + return ret; 2276 2276 + } 2277 2277 + 2278 2278 + qmp->tcsr_4ln_config = ret; 2279 2279 + 2280 2280 + dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); 2281 2281 + 2282 2282 + return 0; 2283 2283 + } 2284 2284 + 2285 2285 + static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) 2286 2286 + { 2287 2287 + struct platform_device *pdev = to_platform_device(qmp->dev); 2288 2288 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2289 2289 + const struct qmp_pcie_offsets *offs = cfg->offsets; 2290 2290 + struct device *dev = qmp->dev; 2291 2291 + void __iomem *base; 2292 2292 + int ret; 2293 2293 + 2294 2294 + if (!offs) 2295 2295 + return -EINVAL; 2296 2296 + 2297 2297 + ret = qmp_pcie_get_4ln_config(qmp); 2298 2298 + if (ret) 2299 2299 + return ret; 2300 2300 + 2301 2301 + base = devm_platform_ioremap_resource(pdev, 0); 2302 2302 + if (IS_ERR(base)) 2303 2303 + return PTR_ERR(base); 2304 2304 + 2305 2305 + qmp->serdes = base + offs->serdes; 2306 2306 + qmp->pcs = base + offs->pcs; 2307 2307 + qmp->pcs_misc = base + offs->pcs_misc; 2308 2308 + qmp->tx = base + offs->tx; 2309 2309 + qmp->rx = base + offs->rx; 2310 2310 + 2311 2311 + if (cfg->lanes >= 2) { 2312 2312 + qmp->tx2 = base + offs->tx2; 2313 2313 + qmp->rx2 = base + offs->rx2; 2314 2314 + } 2315 2315 + 2316 2316 + if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 2317 2317 + qmp->port_b = devm_platform_ioremap_resource(pdev, 1); 2318 2318 + if (IS_ERR(qmp->port_b)) 2319 2319 + return PTR_ERR(qmp->port_b); 2320 2320 + } 2321 2321 + 2322 2322 + qmp->num_pipe_clks = 2; 2323 2323 + qmp->pipe_clks[0].id = "pipe"; 2324 2324 + qmp->pipe_clks[1].id = "pipediv2"; 2325 2325 + 2326 2326 + ret = devm_clk_bulk_get(dev, qmp->num_pipe_clks, qmp->pipe_clks); 2327 2327 + if (ret) 2328 2328 + return ret; 2329 2329 + 2330 2330 + return 0; 2331 2331 + } 2332 2332 + 2333 2333 + static int qmp_pcie_probe(struct platform_device *pdev) 2334 2334 + { 2335 2335 + struct device *dev = &pdev->dev; 2336 2336 + struct phy_provider *phy_provider; 2337 2337 + struct device_node *np; 2338 2338 + struct qmp_pcie *qmp; 2339 2339 + int ret; 2340 2340 + 2341 2341 + qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2342 2342 + if (!qmp) 2343 2343 + return -ENOMEM; 2344 2344 + 2345 2345 + qmp->dev = dev; 2346 2346 + 2347 2347 + qmp->cfg = of_device_get_match_data(dev); 2348 2348 + if (!qmp->cfg) 2349 2349 + return -EINVAL; 2350 2350 + 2351 2351 + WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); 2352 2352 + WARN_ON_ONCE(!qmp->cfg->phy_status); 2353 2353 + 2354 2354 + ret = qmp_pcie_clk_init(qmp); 2355 2355 + if (ret) 2356 2356 + return ret; 2357 2357 + 2358 2358 + ret = qmp_pcie_reset_init(qmp); 2359 2359 + if (ret) 2360 2360 + return ret; 2361 2361 + 2362 2362 + ret = qmp_pcie_vreg_init(qmp); 2363 2363 + if (ret) 2364 2364 + return ret; 2365 2365 + 2366 2366 + /* Check for legacy binding with child node. */ 2367 2367 + np = of_get_next_available_child(dev->of_node, NULL); 2368 2368 + if (np) { 2369 2369 + ret = qmp_pcie_parse_dt_legacy(qmp, np); 2370 2370 + } else { 2371 2371 + np = of_node_get(dev->of_node); 2372 2372 + ret = qmp_pcie_parse_dt(qmp); 2373 2373 + } 2374 2374 + if (ret) 2375 2375 + goto err_node_put; 2376 2376 + 2377 2377 + ret = phy_pipe_clk_register(qmp, np); 2378 2378 + if (ret) 2379 2379 + goto err_node_put; 2380 2380 + 2381 2381 + qmp->mode = PHY_MODE_PCIE_RC; 2382 2382 + 2383 2383 + qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); 2384 2384 + if (IS_ERR(qmp->phy)) { 2385 2385 + ret = PTR_ERR(qmp->phy); 2386 2386 + dev_err(dev, "failed to create PHY: %d\n", ret); 2387 2387 + goto err_node_put; 2388 2388 + } 2389 2389 + 2390 2390 + phy_set_drvdata(qmp->phy, qmp); 2391 2391 + 2392 2392 + of_node_put(np); 2393 2393 + 2394 2394 + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2395 2395 + 2396 2396 + return PTR_ERR_OR_ZERO(phy_provider); 2397 2397 + 2398 2398 + err_node_put: 2399 2399 + of_node_put(np); 2400 2400 + return ret; 2401 2401 + } 2402 2402 + 2544 2403 static const struct of_device_id qmp_pcie_of_match_table[] = { 2545 2404 { 2546 2546 - .compatible = "qcom,msm8998-qmp-pcie-phy", 2547 2547 - .data = &msm8998_pciephy_cfg, 2548 2548 - }, { 2549 2549 - .compatible = "qcom,ipq8074-qmp-pcie-phy", 2550 2550 - .data = &ipq8074_pciephy_cfg, 2405 2405 + .compatible = "qcom,ipq6018-qmp-pcie-phy", 2406 2406 + .data = &ipq6018_pciephy_cfg, 2551 2407 }, { 2552 2408 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 2553 2409 .data = &ipq8074_pciephy_gen3_cfg, 2554 2410 }, { 2555 2555 - .compatible = "qcom,ipq6018-qmp-pcie-phy", 2556 2556 - .data = &ipq6018_pciephy_cfg, 2411 2411 + .compatible = "qcom,ipq8074-qmp-pcie-phy", 2412 2412 + .data = &ipq8074_pciephy_cfg, 2413 2413 + }, { 2414 2414 + .compatible = "qcom,msm8998-qmp-pcie-phy", 2415 2415 + .data = &msm8998_pciephy_cfg, 2557 2416 }, { 2558 2417 .compatible = "qcom,sc8180x-qmp-pcie-phy", 2559 2418 .data = &sc8180x_pciephy_cfg, 2419 2419 + }, { 2420 2420 + .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy", 2421 2421 + .data = &sc8280xp_qmp_gen3x1_pciephy_cfg, 2422 2422 + }, { 2423 2423 + .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy", 2424 2424 + .data = &sc8280xp_qmp_gen3x2_pciephy_cfg, 2425 2425 + }, { 2426 2426 + .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy", 2427 2427 + .data = &sc8280xp_qmp_gen3x4_pciephy_cfg, 2560 2428 }, { 2561 2429 .compatible = "qcom,sdm845-qhp-pcie-phy", 2562 2430 .data = &sdm845_qhp_pciephy_cfg, 2563 2431 }, { 2564 2432 .compatible = "qcom,sdm845-qmp-pcie-phy", 2565 2433 .data = &sdm845_qmp_pciephy_cfg, 2434 2434 + }, { 2435 2435 + .compatible = "qcom,sdx55-qmp-pcie-phy", 2436 2436 + .data = &sdx55_qmp_pciephy_cfg, 2566 2437 }, { 2567 2438 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 2568 2439 .data = &sm8250_qmp_gen3x1_pciephy_cfg, ··· 2720 2297 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 2721 2298 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2722 2299 }, { 2723 2723 - .compatible = "qcom,sdx55-qmp-pcie-phy", 2724 2724 - .data = &sdx55_qmp_pciephy_cfg, 2725 2725 - }, { 2726 2300 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 2727 2301 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 2728 2302 }, { ··· 2729 2309 { }, 2730 2310 }; 2731 2311 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 2732 2732 - 2733 2733 - static int qmp_pcie_probe(struct platform_device *pdev) 2734 2734 - { 2735 2735 - struct qcom_qmp *qmp; 2736 2736 - struct device *dev = &pdev->dev; 2737 2737 - struct device_node *child; 2738 2738 - struct phy_provider *phy_provider; 2739 2739 - void __iomem *serdes; 2740 2740 - const struct qmp_phy_cfg *cfg = NULL; 2741 2741 - int num, id; 2742 2742 - int ret; 2743 2743 - 2744 2744 - qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2745 2745 - if (!qmp) 2746 2746 - return -ENOMEM; 2747 2747 - 2748 2748 - qmp->dev = dev; 2749 2749 - dev_set_drvdata(dev, qmp); 2750 2750 - 2751 2751 - /* Get the specific init parameters of QMP phy */ 2752 2752 - cfg = of_device_get_match_data(dev); 2753 2753 - if (!cfg) 2754 2754 - return -EINVAL; 2755 2755 - 2756 2756 - /* per PHY serdes; usually located at base address */ 2757 2757 - serdes = devm_platform_ioremap_resource(pdev, 0); 2758 2758 - if (IS_ERR(serdes)) 2759 2759 - return PTR_ERR(serdes); 2760 2760 - 2761 2761 - ret = qmp_pcie_clk_init(dev, cfg); 2762 2762 - if (ret) 2763 2763 - return ret; 2764 2764 - 2765 2765 - ret = qmp_pcie_reset_init(dev, cfg); 2766 2766 - if (ret) 2767 2767 - return ret; 2768 2768 - 2769 2769 - ret = qmp_pcie_vreg_init(dev, cfg); 2770 2770 - if (ret) 2771 2771 - return dev_err_probe(dev, ret, 2772 2772 - "failed to get regulator supplies\n"); 2773 2773 - 2774 2774 - num = of_get_available_child_count(dev->of_node); 2775 2775 - /* do we have a rogue child node ? */ 2776 2776 - if (num > 1) 2777 2777 - return -EINVAL; 2778 2778 - 2779 2779 - qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 2780 2780 - if (!qmp->phys) 2781 2781 - return -ENOMEM; 2782 2782 - 2783 2783 - id = 0; 2784 2784 - for_each_available_child_of_node(dev->of_node, child) { 2785 2785 - /* Create per-lane phy */ 2786 2786 - ret = qmp_pcie_create(dev, child, id, serdes, cfg); 2787 2787 - if (ret) { 2788 2788 - dev_err(dev, "failed to create lane%d phy, %d\n", 2789 2789 - id, ret); 2790 2790 - goto err_node_put; 2791 2791 - } 2792 2792 - 2793 2793 - /* 2794 2794 - * Register the pipe clock provided by phy. 2795 2795 - * See function description to see details of this pipe clock. 2796 2796 - */ 2797 2797 - ret = phy_pipe_clk_register(qmp, child); 2798 2798 - if (ret) { 2799 2799 - dev_err(qmp->dev, 2800 2800 - "failed to register pipe clock source\n"); 2801 2801 - goto err_node_put; 2802 2802 - } 2803 2803 - 2804 2804 - id++; 2805 2805 - } 2806 2806 - 2807 2807 - phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2808 2808 - 2809 2809 - return PTR_ERR_OR_ZERO(phy_provider); 2810 2810 - 2811 2811 - err_node_put: 2812 2812 - of_node_put(child); 2813 2813 - return ret; 2814 2814 - } 2815 2312 2816 2313 static struct platform_driver qmp_pcie_driver = { 2817 2314 .probe = qmp_pcie_probe,

+2

drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h

reviewed

··· 8 8 #define QCOM_PHY_QMP_PCS_PCIE_V5_H_ 9 9 10 10 /* Only for QMP V5 PHY - PCS_PCIE registers */ 11 11 + #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 12 12 + #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 11 13 #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 12 14 #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 13 15 #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94

+2

drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h

reviewed

··· 8 8 9 9 /* Only for QMP V5_20 PHY - PCIe PCS registers */ 10 10 #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c 11 11 + #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084 11 12 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 12 13 #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 14 14 + #define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0 13 15 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 14 16 #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c 15 17 #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184

+14

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 2 + /* 3 3 + * Copyright (c) 2022, Linaro Ltd. 4 4 + */ 5 5 + 6 6 + #ifndef QCOM_PHY_QMP_PCS_V5_20_H_ 7 7 + #define QCOM_PHY_QMP_PCS_V5_20_H_ 8 8 + 9 9 + #define QPHY_V5_20_PCS_G3S2_PRE_GAIN 0x170 10 10 + #define QPHY_V5_20_PCS_RX_SIGDET_LVL 0x188 11 11 + #define QPHY_V5_20_PCS_EQ_CONFIG4 0x1e0 12 12 + #define QPHY_V5_20_PCS_EQ_CONFIG5 0x1e4 13 13 + 14 14 + #endif

+213 -271

drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

reviewed

··· 20 20 #include <linux/reset.h> 21 21 #include <linux/slab.h> 22 22 23 23 - #include <dt-bindings/phy/phy.h> 24 24 - 25 23 #include "phy-qcom-qmp.h" 26 24 27 25 /* QPHY_SW_RESET bit */ ··· 29 31 /* QPHY_START_CONTROL bits */ 30 32 #define SERDES_START BIT(0) 31 33 #define PCS_START BIT(1) 32 32 - /* QPHY_PCS_STATUS bit */ 33 33 - #define PHYSTATUS BIT(6) 34 34 /* QPHY_PCS_READY_STATUS bit */ 35 35 #define PCS_READY BIT(0) 36 36 ··· 37 41 struct qmp_phy_init_tbl { 38 42 unsigned int offset; 39 43 unsigned int val; 40 40 - /* 41 41 - * register part of layout ? 42 42 - * if yes, then offset gives index in the reg-layout 43 43 - */ 44 44 - bool in_layout; 45 44 /* 46 45 * mask of lanes for which this register is written 47 46 * for cases when second lane needs different values ··· 48 57 { \ 49 58 .offset = o, \ 50 59 .val = v, \ 51 51 - .lane_mask = 0xff, \ 52 52 - } 53 53 - 54 54 - #define QMP_PHY_INIT_CFG_L(o, v) \ 55 55 - { \ 56 56 - .offset = o, \ 57 57 - .val = v, \ 58 58 - .in_layout = true, \ 59 60 .lane_mask = 0xff, \ 60 61 } 61 62 ··· 72 89 static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { 73 90 [QPHY_START_CTRL] = 0x00, 74 91 [QPHY_PCS_READY_STATUS] = 0x168, 92 92 + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 75 93 }; 76 94 77 95 static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { 78 96 [QPHY_START_CTRL] = 0x00, 79 97 [QPHY_PCS_READY_STATUS] = 0x160, 98 98 + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 80 99 }; 81 100 82 101 static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { 83 102 [QPHY_START_CTRL] = 0x00, 84 103 [QPHY_PCS_READY_STATUS] = 0x168, 104 104 + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 85 105 }; 86 106 87 107 static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { 88 108 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, 89 109 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, 90 110 [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, 111 111 + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, 91 112 }; 92 113 93 114 static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { ··· 518 531 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 519 532 }; 520 533 534 534 + struct qmp_ufs_offsets { 535 535 + u16 serdes; 536 536 + u16 pcs; 537 537 + u16 tx; 538 538 + u16 rx; 539 539 + u16 tx2; 540 540 + u16 rx2; 541 541 + }; 542 542 + 521 543 /* struct qmp_phy_cfg - per-PHY initialization config */ 522 544 struct qmp_phy_cfg { 523 545 int lanes; 546 546 + 547 547 + const struct qmp_ufs_offsets *offsets; 524 548 525 549 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 526 550 const struct qmp_phy_init_tbl *serdes_tbl; ··· 553 555 /* array of registers with different offsets */ 554 556 const unsigned int *regs; 555 557 556 556 - unsigned int start_ctrl; 557 557 - unsigned int pwrdn_ctrl; 558 558 - /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 559 559 - unsigned int phy_status; 560 560 - 561 558 /* true, if PCS block has no separate SW_RESET register */ 562 559 bool no_pcs_sw_reset; 563 560 }; 564 561 565 565 - /** 566 566 - * struct qmp_phy - per-lane phy descriptor 567 567 - * 568 568 - * @phy: generic phy 569 569 - * @cfg: phy specific configuration 570 570 - * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 571 571 - * @tx: iomapped memory space for lane's tx 572 572 - * @rx: iomapped memory space for lane's rx 573 573 - * @pcs: iomapped memory space for lane's pcs 574 574 - * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 575 575 - * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 576 576 - * @pcs_misc: iomapped memory space for lane's pcs_misc 577 577 - * @qmp: QMP phy to which this lane belongs 578 578 - */ 579 579 - struct qmp_phy { 580 580 - struct phy *phy; 562 562 + struct qmp_ufs { 563 563 + struct device *dev; 564 564 + 581 565 const struct qmp_phy_cfg *cfg; 566 566 + 582 567 void __iomem *serdes; 568 568 + void __iomem *pcs; 569 569 + void __iomem *pcs_misc; 583 570 void __iomem *tx; 584 571 void __iomem *rx; 585 585 - void __iomem *pcs; 586 572 void __iomem *tx2; 587 573 void __iomem *rx2; 588 588 - void __iomem *pcs_misc; 589 589 - struct qcom_qmp *qmp; 590 590 - }; 591 591 - 592 592 - /** 593 593 - * struct qcom_qmp - structure holding QMP phy block attributes 594 594 - * 595 595 - * @dev: device 596 596 - * 597 597 - * @clks: array of clocks required by phy 598 598 - * @resets: array of resets required by phy 599 599 - * @vregs: regulator supplies bulk data 600 600 - * 601 601 - * @phys: array of per-lane phy descriptors 602 602 - * @ufs_reset: optional UFS PHY reset handle 603 603 - */ 604 604 - struct qcom_qmp { 605 605 - struct device *dev; 606 574 607 575 struct clk_bulk_data *clks; 608 576 struct regulator_bulk_data *vregs; 609 609 - 610 610 - struct qmp_phy **phys; 611 611 - 612 577 struct reset_control *ufs_reset; 578 578 + 579 579 + struct phy *phy; 613 580 }; 614 581 615 582 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) ··· 620 657 "vdda-phy", "vdda-pll", 621 658 }; 622 659 660 660 + static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = { 661 661 + .serdes = 0, 662 662 + .pcs = 0xc00, 663 663 + .tx = 0x400, 664 664 + .rx = 0x600, 665 665 + .tx2 = 0x800, 666 666 + .rx2 = 0xa00, 667 667 + }; 668 668 + 623 669 static const struct qmp_phy_cfg msm8996_ufs_cfg = { 624 670 .lanes = 1, 625 671 ··· 647 675 648 676 .regs = msm8996_ufsphy_regs_layout, 649 677 650 650 - .start_ctrl = SERDES_START, 651 651 - .pwrdn_ctrl = SW_PWRDN, 652 652 - .phy_status = PHYSTATUS, 653 653 - 654 678 .no_pcs_sw_reset = true, 679 679 + }; 680 680 + 681 681 + static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { 682 682 + .lanes = 2, 683 683 + 684 684 + .offsets = &qmp_ufs_offsets_v5, 685 685 + 686 686 + .serdes_tbl = sm8350_ufsphy_serdes_tbl, 687 687 + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), 688 688 + .tx_tbl = sm8350_ufsphy_tx_tbl, 689 689 + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), 690 690 + .rx_tbl = sm8350_ufsphy_rx_tbl, 691 691 + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), 692 692 + .pcs_tbl = sm8350_ufsphy_pcs_tbl, 693 693 + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), 694 694 + .clk_list = sdm845_ufs_phy_clk_l, 695 695 + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 696 696 + .vreg_list = qmp_phy_vreg_l, 697 697 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 698 698 + .regs = sm8150_ufsphy_regs_layout, 655 699 }; 656 700 657 701 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { ··· 686 698 .vreg_list = qmp_phy_vreg_l, 687 699 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 688 700 .regs = sdm845_ufsphy_regs_layout, 689 689 - 690 690 - .start_ctrl = SERDES_START, 691 691 - .pwrdn_ctrl = SW_PWRDN, 692 692 - .phy_status = PHYSTATUS, 693 701 694 702 .no_pcs_sw_reset = true, 695 703 }; ··· 707 723 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 708 724 .regs = sm6115_ufsphy_regs_layout, 709 725 710 710 - .start_ctrl = SERDES_START, 711 711 - .pwrdn_ctrl = SW_PWRDN, 712 712 - 713 726 .no_pcs_sw_reset = true, 714 727 }; 715 728 ··· 726 745 .vreg_list = qmp_phy_vreg_l, 727 746 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 728 747 .regs = sm8150_ufsphy_regs_layout, 729 729 - 730 730 - .start_ctrl = SERDES_START, 731 731 - .pwrdn_ctrl = SW_PWRDN, 732 732 - .phy_status = PHYSTATUS, 733 748 }; 734 749 735 750 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { ··· 744 767 .vreg_list = qmp_phy_vreg_l, 745 768 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 746 769 .regs = sm8150_ufsphy_regs_layout, 747 747 - 748 748 - .start_ctrl = SERDES_START, 749 749 - .pwrdn_ctrl = SW_PWRDN, 750 750 - .phy_status = PHYSTATUS, 751 770 }; 752 771 753 772 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { ··· 762 789 .vreg_list = qmp_phy_vreg_l, 763 790 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 764 791 .regs = sm8150_ufsphy_regs_layout, 765 765 - 766 766 - .start_ctrl = SERDES_START, 767 767 - .pwrdn_ctrl = SW_PWRDN, 768 768 - .phy_status = PHYSTATUS, 769 792 }; 770 793 771 794 static void qmp_ufs_configure_lane(void __iomem *base, 772 772 - const unsigned int *regs, 773 795 const struct qmp_phy_init_tbl tbl[], 774 796 int num, 775 797 u8 lane_mask) ··· 779 811 if (!(t->lane_mask & lane_mask)) 780 812 continue; 781 813 782 782 - if (t->in_layout) 783 783 - writel(t->val, base + regs[t->offset]); 784 784 - else 785 785 - writel(t->val, base + t->offset); 814 814 + writel(t->val, base + t->offset); 786 815 } 787 816 } 788 817 789 818 static void qmp_ufs_configure(void __iomem *base, 790 790 - const unsigned int *regs, 791 819 const struct qmp_phy_init_tbl tbl[], 792 820 int num) 793 821 { 794 794 - qmp_ufs_configure_lane(base, regs, tbl, num, 0xff); 822 822 + qmp_ufs_configure_lane(base, tbl, num, 0xff); 795 823 } 796 824 797 797 - static int qmp_ufs_serdes_init(struct qmp_phy *qphy) 825 825 + static int qmp_ufs_serdes_init(struct qmp_ufs *qmp) 798 826 { 799 799 - const struct qmp_phy_cfg *cfg = qphy->cfg; 800 800 - void __iomem *serdes = qphy->serdes; 827 827 + const struct qmp_phy_cfg *cfg = qmp->cfg; 828 828 + void __iomem *serdes = qmp->serdes; 801 829 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 802 830 int serdes_tbl_num = cfg->serdes_tbl_num; 803 831 804 804 - qmp_ufs_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 832 832 + qmp_ufs_configure(serdes, serdes_tbl, serdes_tbl_num); 805 833 806 834 return 0; 807 835 } 808 836 809 809 - static int qmp_ufs_com_init(struct qmp_phy *qphy) 837 837 + static int qmp_ufs_com_init(struct qmp_ufs *qmp) 810 838 { 811 811 - struct qcom_qmp *qmp = qphy->qmp; 812 812 - const struct qmp_phy_cfg *cfg = qphy->cfg; 813 813 - void __iomem *pcs = qphy->pcs; 839 839 + const struct qmp_phy_cfg *cfg = qmp->cfg; 840 840 + void __iomem *pcs = qmp->pcs; 814 841 int ret; 815 842 816 816 - /* turn on regulator supplies */ 817 843 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 818 844 if (ret) { 819 845 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); ··· 818 856 if (ret) 819 857 goto err_disable_regulators; 820 858 821 821 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 822 822 - qphy_setbits(pcs, 823 823 - cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 824 824 - cfg->pwrdn_ctrl); 825 825 - else 826 826 - qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 827 827 - cfg->pwrdn_ctrl); 859 859 + qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 828 860 829 861 return 0; 830 862 ··· 828 872 return ret; 829 873 } 830 874 831 831 - static int qmp_ufs_com_exit(struct qmp_phy *qphy) 875 875 + static int qmp_ufs_com_exit(struct qmp_ufs *qmp) 832 876 { 833 833 - struct qcom_qmp *qmp = qphy->qmp; 834 834 - const struct qmp_phy_cfg *cfg = qphy->cfg; 877 877 + const struct qmp_phy_cfg *cfg = qmp->cfg; 835 878 836 879 reset_control_assert(qmp->ufs_reset); 837 880 ··· 843 888 844 889 static int qmp_ufs_init(struct phy *phy) 845 890 { 846 846 - struct qmp_phy *qphy = phy_get_drvdata(phy); 847 847 - struct qcom_qmp *qmp = qphy->qmp; 848 848 - const struct qmp_phy_cfg *cfg = qphy->cfg; 891 891 + struct qmp_ufs *qmp = phy_get_drvdata(phy); 892 892 + const struct qmp_phy_cfg *cfg = qmp->cfg; 849 893 int ret; 850 894 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 851 895 ··· 875 921 return ret; 876 922 } 877 923 878 878 - ret = qmp_ufs_com_init(qphy); 924 924 + ret = qmp_ufs_com_init(qmp); 879 925 if (ret) 880 926 return ret; 881 927 ··· 884 930 885 931 static int qmp_ufs_power_on(struct phy *phy) 886 932 { 887 887 - struct qmp_phy *qphy = phy_get_drvdata(phy); 888 888 - struct qcom_qmp *qmp = qphy->qmp; 889 889 - const struct qmp_phy_cfg *cfg = qphy->cfg; 890 890 - void __iomem *tx = qphy->tx; 891 891 - void __iomem *rx = qphy->rx; 892 892 - void __iomem *pcs = qphy->pcs; 933 933 + struct qmp_ufs *qmp = phy_get_drvdata(phy); 934 934 + const struct qmp_phy_cfg *cfg = qmp->cfg; 935 935 + void __iomem *tx = qmp->tx; 936 936 + void __iomem *rx = qmp->rx; 937 937 + void __iomem *pcs = qmp->pcs; 893 938 void __iomem *status; 894 894 - unsigned int mask, val, ready; 939 939 + unsigned int val; 895 940 int ret; 896 941 897 897 - qmp_ufs_serdes_init(qphy); 942 942 + qmp_ufs_serdes_init(qmp); 898 943 899 944 /* Tx, Rx, and PCS configurations */ 900 900 - qmp_ufs_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); 945 945 + qmp_ufs_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 946 946 + qmp_ufs_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 901 947 902 948 if (cfg->lanes >= 2) { 903 903 - qmp_ufs_configure_lane(qphy->tx2, cfg->regs, 904 904 - cfg->tx_tbl, cfg->tx_tbl_num, 2); 949 949 + qmp_ufs_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 950 950 + qmp_ufs_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 905 951 } 906 952 907 907 - qmp_ufs_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); 908 908 - 909 909 - if (cfg->lanes >= 2) { 910 910 - qmp_ufs_configure_lane(qphy->rx2, cfg->regs, 911 911 - cfg->rx_tbl, cfg->rx_tbl_num, 2); 912 912 - } 913 913 - 914 914 - qmp_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 953 953 + qmp_ufs_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 915 954 916 955 ret = reset_control_deassert(qmp->ufs_reset); 917 956 if (ret) ··· 913 966 /* Pull PHY out of reset state */ 914 967 if (!cfg->no_pcs_sw_reset) 915 968 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 916 916 - /* start SerDes and Phy-Coding-Sublayer */ 917 917 - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 969 969 + 970 970 + /* start SerDes */ 971 971 + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START); 918 972 919 973 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; 920 920 - mask = PCS_READY; 921 921 - ready = PCS_READY; 922 922 - 923 923 - ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 974 974 + ret = readl_poll_timeout(status, val, (val & PCS_READY), 200, 924 975 PHY_INIT_COMPLETE_TIMEOUT); 925 976 if (ret) { 926 977 dev_err(qmp->dev, "phy initialization timed-out\n"); ··· 930 985 931 986 static int qmp_ufs_power_off(struct phy *phy) 932 987 { 933 933 - struct qmp_phy *qphy = phy_get_drvdata(phy); 934 934 - const struct qmp_phy_cfg *cfg = qphy->cfg; 988 988 + struct qmp_ufs *qmp = phy_get_drvdata(phy); 989 989 + const struct qmp_phy_cfg *cfg = qmp->cfg; 935 990 936 991 /* PHY reset */ 937 992 if (!cfg->no_pcs_sw_reset) 938 938 - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 993 993 + qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 939 994 940 940 - /* stop SerDes and Phy-Coding-Sublayer */ 941 941 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 995 995 + /* stop SerDes */ 996 996 + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START); 942 997 943 998 /* Put PHY into POWER DOWN state: active low */ 944 944 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 945 945 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 946 946 - cfg->pwrdn_ctrl); 947 947 - } else { 948 948 - qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 949 949 - cfg->pwrdn_ctrl); 950 950 - } 999 999 + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1000 1000 + SW_PWRDN); 951 1001 952 1002 return 0; 953 1003 } 954 1004 955 1005 static int qmp_ufs_exit(struct phy *phy) 956 1006 { 957 957 - struct qmp_phy *qphy = phy_get_drvdata(phy); 1007 1007 + struct qmp_ufs *qmp = phy_get_drvdata(phy); 958 1008 959 959 - qmp_ufs_com_exit(qphy); 1009 1009 + qmp_ufs_com_exit(qmp); 960 1010 961 1011 return 0; 962 1012 } ··· 981 1041 return qmp_ufs_exit(phy); 982 1042 } 983 1043 984 984 - static int qmp_ufs_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 1044 1044 + static const struct phy_ops qcom_qmp_ufs_phy_ops = { 1045 1045 + .power_on = qmp_ufs_enable, 1046 1046 + .power_off = qmp_ufs_disable, 1047 1047 + .owner = THIS_MODULE, 1048 1048 + }; 1049 1049 + 1050 1050 + static int qmp_ufs_vreg_init(struct qmp_ufs *qmp) 985 1051 { 986 986 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 1052 1052 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1053 1053 + struct device *dev = qmp->dev; 987 1054 int num = cfg->num_vregs; 988 1055 int i; 989 1056 ··· 1004 1057 return devm_regulator_bulk_get(dev, num, qmp->vregs); 1005 1058 } 1006 1059 1007 1007 - static int qmp_ufs_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 1060 1060 + static int qmp_ufs_clk_init(struct qmp_ufs *qmp) 1008 1061 { 1009 1009 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 1062 1062 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1063 1063 + struct device *dev = qmp->dev; 1010 1064 int num = cfg->num_clks; 1011 1065 int i; 1012 1066 ··· 1021 1073 return devm_clk_bulk_get(dev, num, qmp->clks); 1022 1074 } 1023 1075 1024 1024 - static const struct phy_ops qcom_qmp_ufs_ops = { 1025 1025 - .power_on = qmp_ufs_enable, 1026 1026 - .power_off = qmp_ufs_disable, 1027 1027 - .owner = THIS_MODULE, 1028 1028 - }; 1029 1029 - 1030 1030 - static int qmp_ufs_create(struct device *dev, struct device_node *np, int id, 1031 1031 - void __iomem *serdes, const struct qmp_phy_cfg *cfg) 1076 1076 + static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np) 1032 1077 { 1033 1033 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 1034 1034 - struct phy *generic_phy; 1035 1035 - struct qmp_phy *qphy; 1036 1036 - int ret; 1078 1078 + struct platform_device *pdev = to_platform_device(qmp->dev); 1079 1079 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1080 1080 + struct device *dev = qmp->dev; 1037 1081 1038 1038 - qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 1039 1039 - if (!qphy) 1040 1040 - return -ENOMEM; 1082 1082 + qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 1083 1083 + if (IS_ERR(qmp->serdes)) 1084 1084 + return PTR_ERR(qmp->serdes); 1041 1085 1042 1042 - qphy->cfg = cfg; 1043 1043 - qphy->serdes = serdes; 1044 1086 /* 1045 1045 - * Get memory resources for each phy lane: 1087 1087 + * Get memory resources for the PHY: 1046 1088 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 1047 1089 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 1048 1090 * For single lane PHYs: pcs_misc (optional) -> 3. 1049 1091 */ 1050 1050 - qphy->tx = devm_of_iomap(dev, np, 0, NULL); 1051 1051 - if (IS_ERR(qphy->tx)) 1052 1052 - return PTR_ERR(qphy->tx); 1092 1092 + qmp->tx = devm_of_iomap(dev, np, 0, NULL); 1093 1093 + if (IS_ERR(qmp->tx)) 1094 1094 + return PTR_ERR(qmp->tx); 1053 1095 1054 1054 - qphy->rx = devm_of_iomap(dev, np, 1, NULL); 1055 1055 - if (IS_ERR(qphy->rx)) 1056 1056 - return PTR_ERR(qphy->rx); 1096 1096 + qmp->rx = devm_of_iomap(dev, np, 1, NULL); 1097 1097 + if (IS_ERR(qmp->rx)) 1098 1098 + return PTR_ERR(qmp->rx); 1057 1099 1058 1058 - qphy->pcs = devm_of_iomap(dev, np, 2, NULL); 1059 1059 - if (IS_ERR(qphy->pcs)) 1060 1060 - return PTR_ERR(qphy->pcs); 1100 1100 + qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 1101 1101 + if (IS_ERR(qmp->pcs)) 1102 1102 + return PTR_ERR(qmp->pcs); 1061 1103 1062 1104 if (cfg->lanes >= 2) { 1063 1063 - qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); 1064 1064 - if (IS_ERR(qphy->tx2)) 1065 1065 - return PTR_ERR(qphy->tx2); 1105 1105 + qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 1106 1106 + if (IS_ERR(qmp->tx2)) 1107 1107 + return PTR_ERR(qmp->tx2); 1066 1108 1067 1067 - qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); 1068 1068 - if (IS_ERR(qphy->rx2)) 1069 1069 - return PTR_ERR(qphy->rx2); 1109 1109 + qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 1110 1110 + if (IS_ERR(qmp->rx2)) 1111 1111 + return PTR_ERR(qmp->rx2); 1070 1112 1071 1071 - qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 1113 1113 + qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 1072 1114 } else { 1073 1073 - qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 1115 1115 + qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 1074 1116 } 1075 1117 1076 1076 - if (IS_ERR(qphy->pcs_misc)) 1118 1118 + if (IS_ERR(qmp->pcs_misc)) 1077 1119 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 1078 1120 1079 1079 - generic_phy = devm_phy_create(dev, np, &qcom_qmp_ufs_ops); 1080 1080 - if (IS_ERR(generic_phy)) { 1081 1081 - ret = PTR_ERR(generic_phy); 1082 1082 - dev_err(dev, "failed to create qphy %d\n", ret); 1083 1083 - return ret; 1121 1121 + return 0; 1122 1122 + } 1123 1123 + 1124 1124 + static int qmp_ufs_parse_dt(struct qmp_ufs *qmp) 1125 1125 + { 1126 1126 + struct platform_device *pdev = to_platform_device(qmp->dev); 1127 1127 + const struct qmp_phy_cfg *cfg = qmp->cfg; 1128 1128 + const struct qmp_ufs_offsets *offs = cfg->offsets; 1129 1129 + void __iomem *base; 1130 1130 + 1131 1131 + if (!offs) 1132 1132 + return -EINVAL; 1133 1133 + 1134 1134 + base = devm_platform_ioremap_resource(pdev, 0); 1135 1135 + if (IS_ERR(base)) 1136 1136 + return PTR_ERR(base); 1137 1137 + 1138 1138 + qmp->serdes = base + offs->serdes; 1139 1139 + qmp->pcs = base + offs->pcs; 1140 1140 + qmp->tx = base + offs->tx; 1141 1141 + qmp->rx = base + offs->rx; 1142 1142 + 1143 1143 + if (cfg->lanes >= 2) { 1144 1144 + qmp->tx2 = base + offs->tx2; 1145 1145 + qmp->rx2 = base + offs->rx2; 1084 1146 } 1085 1147 1086 1086 - qphy->phy = generic_phy; 1087 1087 - qphy->qmp = qmp; 1088 1088 - qmp->phys[id] = qphy; 1089 1089 - phy_set_drvdata(generic_phy, qphy); 1090 1090 - 1091 1148 return 0; 1149 1149 + } 1150 1150 + 1151 1151 + static int qmp_ufs_probe(struct platform_device *pdev) 1152 1152 + { 1153 1153 + struct device *dev = &pdev->dev; 1154 1154 + struct phy_provider *phy_provider; 1155 1155 + struct device_node *np; 1156 1156 + struct qmp_ufs *qmp; 1157 1157 + int ret; 1158 1158 + 1159 1159 + qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 1160 1160 + if (!qmp) 1161 1161 + return -ENOMEM; 1162 1162 + 1163 1163 + qmp->dev = dev; 1164 1164 + 1165 1165 + qmp->cfg = of_device_get_match_data(dev); 1166 1166 + if (!qmp->cfg) 1167 1167 + return -EINVAL; 1168 1168 + 1169 1169 + ret = qmp_ufs_clk_init(qmp); 1170 1170 + if (ret) 1171 1171 + return ret; 1172 1172 + 1173 1173 + ret = qmp_ufs_vreg_init(qmp); 1174 1174 + if (ret) 1175 1175 + return ret; 1176 1176 + 1177 1177 + /* Check for legacy binding with child node. */ 1178 1178 + np = of_get_next_available_child(dev->of_node, NULL); 1179 1179 + if (np) { 1180 1180 + ret = qmp_ufs_parse_dt_legacy(qmp, np); 1181 1181 + } else { 1182 1182 + np = of_node_get(dev->of_node); 1183 1183 + ret = qmp_ufs_parse_dt(qmp); 1184 1184 + } 1185 1185 + if (ret) 1186 1186 + goto err_node_put; 1187 1187 + 1188 1188 + qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops); 1189 1189 + if (IS_ERR(qmp->phy)) { 1190 1190 + ret = PTR_ERR(qmp->phy); 1191 1191 + dev_err(dev, "failed to create PHY: %d\n", ret); 1192 1192 + goto err_node_put; 1193 1193 + } 1194 1194 + 1195 1195 + phy_set_drvdata(qmp->phy, qmp); 1196 1196 + 1197 1197 + of_node_put(np); 1198 1198 + 1199 1199 + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1200 1200 + 1201 1201 + return PTR_ERR_OR_ZERO(phy_provider); 1202 1202 + 1203 1203 + err_node_put: 1204 1204 + of_node_put(np); 1205 1205 + return ret; 1092 1206 } 1093 1207 1094 1208 static const struct of_device_id qmp_ufs_of_match_table[] = { ··· 1165 1155 .data = &sm8150_ufsphy_cfg, 1166 1156 }, { 1167 1157 .compatible = "qcom,sc8280xp-qmp-ufs-phy", 1168 1168 - .data = &sm8350_ufsphy_cfg, 1158 1158 + .data = &sc8280xp_ufsphy_cfg, 1169 1159 }, { 1170 1160 .compatible = "qcom,sdm845-qmp-ufs-phy", 1171 1161 .data = &sdm845_ufsphy_cfg, ··· 1191 1181 { }, 1192 1182 }; 1193 1183 MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table); 1194 1194 - 1195 1195 - static int qmp_ufs_probe(struct platform_device *pdev) 1196 1196 - { 1197 1197 - struct qcom_qmp *qmp; 1198 1198 - struct device *dev = &pdev->dev; 1199 1199 - struct device_node *child; 1200 1200 - struct phy_provider *phy_provider; 1201 1201 - void __iomem *serdes; 1202 1202 - const struct qmp_phy_cfg *cfg = NULL; 1203 1203 - int num, id; 1204 1204 - int ret; 1205 1205 - 1206 1206 - qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 1207 1207 - if (!qmp) 1208 1208 - return -ENOMEM; 1209 1209 - 1210 1210 - qmp->dev = dev; 1211 1211 - dev_set_drvdata(dev, qmp); 1212 1212 - 1213 1213 - /* Get the specific init parameters of QMP phy */ 1214 1214 - cfg = of_device_get_match_data(dev); 1215 1215 - if (!cfg) 1216 1216 - return -EINVAL; 1217 1217 - 1218 1218 - /* per PHY serdes; usually located at base address */ 1219 1219 - serdes = devm_platform_ioremap_resource(pdev, 0); 1220 1220 - if (IS_ERR(serdes)) 1221 1221 - return PTR_ERR(serdes); 1222 1222 - 1223 1223 - ret = qmp_ufs_clk_init(dev, cfg); 1224 1224 - if (ret) 1225 1225 - return ret; 1226 1226 - 1227 1227 - ret = qmp_ufs_vreg_init(dev, cfg); 1228 1228 - if (ret) 1229 1229 - return dev_err_probe(dev, ret, 1230 1230 - "failed to get regulator supplies\n"); 1231 1231 - 1232 1232 - num = of_get_available_child_count(dev->of_node); 1233 1233 - /* do we have a rogue child node ? */ 1234 1234 - if (num > 1) 1235 1235 - return -EINVAL; 1236 1236 - 1237 1237 - qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 1238 1238 - if (!qmp->phys) 1239 1239 - return -ENOMEM; 1240 1240 - 1241 1241 - id = 0; 1242 1242 - for_each_available_child_of_node(dev->of_node, child) { 1243 1243 - /* Create per-lane phy */ 1244 1244 - ret = qmp_ufs_create(dev, child, id, serdes, cfg); 1245 1245 - if (ret) { 1246 1246 - dev_err(dev, "failed to create lane%d phy, %d\n", 1247 1247 - id, ret); 1248 1248 - goto err_node_put; 1249 1249 - } 1250 1250 - 1251 1251 - id++; 1252 1252 - } 1253 1253 - 1254 1254 - phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1255 1255 - 1256 1256 - return PTR_ERR_OR_ZERO(phy_provider); 1257 1257 - 1258 1258 - err_node_put: 1259 1259 - of_node_put(child); 1260 1260 - return ret; 1261 1261 - } 1262 1184 1263 1185 static struct platform_driver qmp_ufs_driver = { 1264 1186 .probe = qmp_ufs_probe,

+292 -453

drivers/phy/qualcomm/phy-qcom-qmp-usb.c

reviewed

··· 20 20 #include <linux/reset.h> 21 21 #include <linux/slab.h> 22 22 23 23 - #include <dt-bindings/phy/phy.h> 24 24 - 25 23 #include "phy-qcom-qmp.h" 26 24 27 25 /* QPHY_SW_RESET bit */ ··· 61 63 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 62 64 63 65 #define PHY_INIT_COMPLETE_TIMEOUT 10000 64 64 - #define POWER_DOWN_DELAY_US_MIN 10 65 65 - #define POWER_DOWN_DELAY_US_MAX 11 66 66 67 67 struct qmp_phy_init_tbl { 68 68 unsigned int offset; 69 69 unsigned int val; 70 70 - /* 71 71 - * register part of layout ? 72 72 - * if yes, then offset gives index in the reg-layout 73 73 - */ 74 74 - bool in_layout; 75 70 /* 76 71 * mask of lanes for which this register is written 77 72 * for cases when second lane needs different values ··· 76 85 { \ 77 86 .offset = o, \ 78 87 .val = v, \ 79 79 - .lane_mask = 0xff, \ 80 80 - } 81 81 - 82 82 - #define QMP_PHY_INIT_CFG_L(o, v) \ 83 83 - { \ 84 84 - .offset = o, \ 85 85 - .val = v, \ 86 86 - .in_layout = true, \ 87 88 .lane_mask = 0xff, \ 88 89 } 89 90 ··· 109 126 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, 110 127 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, 111 128 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178, 129 129 + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 112 130 }; 113 131 114 132 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ··· 119 135 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, 120 136 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, 121 137 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, 138 138 + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 122 139 }; 123 140 124 141 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ··· 1412 1427 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1413 1428 }; 1414 1429 1430 1430 + struct qmp_usb_offsets { 1431 1431 + u16 serdes; 1432 1432 + u16 pcs; 1433 1433 + u16 pcs_usb; 1434 1434 + u16 tx; 1435 1435 + u16 rx; 1436 1436 + }; 1437 1437 + 1415 1438 /* struct qmp_phy_cfg - per-PHY initialization config */ 1416 1439 struct qmp_phy_cfg { 1417 1440 int lanes; 1441 1441 + 1442 1442 + const struct qmp_usb_offsets *offsets; 1418 1443 1419 1444 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1420 1445 const struct qmp_phy_init_tbl *serdes_tbl; ··· 1451 1456 /* array of registers with different offsets */ 1452 1457 const unsigned int *regs; 1453 1458 1454 1454 - unsigned int start_ctrl; 1455 1455 - unsigned int pwrdn_ctrl; 1456 1456 - /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1457 1457 - unsigned int phy_status; 1458 1458 - 1459 1459 /* true, if PHY needs delay after POWER_DOWN */ 1460 1460 bool has_pwrdn_delay; 1461 1461 - /* power_down delay in usec */ 1462 1462 - int pwrdn_delay_min; 1463 1463 - int pwrdn_delay_max; 1464 1461 1465 1462 /* true, if PHY has a separate DP_COM control block */ 1466 1463 bool has_phy_dp_com_ctrl; ··· 1461 1474 unsigned int pcs_usb_offset; 1462 1475 }; 1463 1476 1464 1464 - /** 1465 1465 - * struct qmp_phy - per-lane phy descriptor 1466 1466 - * 1467 1467 - * @phy: generic phy 1468 1468 - * @cfg: phy specific configuration 1469 1469 - * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 1470 1470 - * @tx: iomapped memory space for lane's tx 1471 1471 - * @rx: iomapped memory space for lane's rx 1472 1472 - * @pcs: iomapped memory space for lane's pcs 1473 1473 - * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 1474 1474 - * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 1475 1475 - * @pcs_misc: iomapped memory space for lane's pcs_misc 1476 1476 - * @pcs_usb: iomapped memory space for lane's pcs_usb 1477 1477 - * @pipe_clk: pipe clock 1478 1478 - * @qmp: QMP phy to which this lane belongs 1479 1479 - * @mode: current PHY mode 1480 1480 - */ 1481 1481 - struct qmp_phy { 1482 1482 - struct phy *phy; 1477 1477 + struct qmp_usb { 1478 1478 + struct device *dev; 1479 1479 + 1483 1480 const struct qmp_phy_cfg *cfg; 1481 1481 + 1484 1482 void __iomem *serdes; 1485 1485 - void __iomem *tx; 1486 1486 - void __iomem *rx; 1487 1483 void __iomem *pcs; 1488 1488 - void __iomem *tx2; 1489 1489 - void __iomem *rx2; 1490 1484 void __iomem *pcs_misc; 1491 1485 void __iomem *pcs_usb; 1492 1492 - struct clk *pipe_clk; 1493 1493 - struct qcom_qmp *qmp; 1494 1494 - enum phy_mode mode; 1495 1495 - }; 1486 1486 + void __iomem *tx; 1487 1487 + void __iomem *rx; 1488 1488 + void __iomem *tx2; 1489 1489 + void __iomem *rx2; 1496 1490 1497 1497 - /** 1498 1498 - * struct qcom_qmp - structure holding QMP phy block attributes 1499 1499 - * 1500 1500 - * @dev: device 1501 1501 - * @dp_com: iomapped memory space for phy's dp_com control block 1502 1502 - * 1503 1503 - * @clks: array of clocks required by phy 1504 1504 - * @resets: array of resets required by phy 1505 1505 - * @vregs: regulator supplies bulk data 1506 1506 - * 1507 1507 - * @phys: array of per-lane phy descriptors 1508 1508 - */ 1509 1509 - struct qcom_qmp { 1510 1510 - struct device *dev; 1511 1491 void __iomem *dp_com; 1512 1492 1493 1493 + struct clk *pipe_clk; 1513 1494 struct clk_bulk_data *clks; 1514 1495 struct reset_control_bulk_data *resets; 1515 1496 struct regulator_bulk_data *vregs; 1516 1497 1517 1517 - struct qmp_phy **phys; 1498 1498 + enum phy_mode mode; 1499 1499 + 1500 1500 + struct phy *phy; 1501 1501 + 1502 1502 + struct clk_fixed_rate pipe_clk_fixed; 1518 1503 }; 1519 1504 1520 1505 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) ··· 1523 1564 }; 1524 1565 1525 1566 static const char * const qmp_v4_phy_clk_l[] = { 1567 1567 + "aux", "ref", "com_aux", 1568 1568 + }; 1569 1569 + 1570 1570 + static const char * const qmp_v4_ref_phy_clk_l[] = { 1526 1571 "aux", "ref_clk_src", "ref", "com_aux", 1527 1572 }; 1528 1573 ··· 1562 1599 "vdda-phy", "vdda-pll", 1563 1600 }; 1564 1601 1602 1602 + static const struct qmp_usb_offsets qmp_usb_offsets_v5 = { 1603 1603 + .serdes = 0, 1604 1604 + .pcs = 0x0200, 1605 1605 + .pcs_usb = 0x1200, 1606 1606 + .tx = 0x0e00, 1607 1607 + .rx = 0x1000, 1608 1608 + }; 1609 1609 + 1565 1610 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { 1566 1611 .lanes = 1, 1567 1612 ··· 1587 1616 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1588 1617 .vreg_list = qmp_phy_vreg_l, 1589 1618 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1590 1590 - .regs = usb3phy_regs_layout, 1591 1591 - 1592 1592 - .start_ctrl = SERDES_START | PCS_START, 1593 1593 - .pwrdn_ctrl = SW_PWRDN, 1594 1594 - .phy_status = PHYSTATUS, 1619 1619 + .regs = qmp_v3_usb3phy_regs_layout, 1595 1620 }; 1596 1621 1597 1622 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { ··· 1608 1641 .vreg_list = qmp_phy_vreg_l, 1609 1642 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1610 1643 .regs = usb3phy_regs_layout, 1611 1611 - 1612 1612 - .start_ctrl = SERDES_START | PCS_START, 1613 1613 - .pwrdn_ctrl = SW_PWRDN, 1614 1614 - .phy_status = PHYSTATUS, 1615 1644 }; 1616 1645 1617 1646 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { ··· 1629 1666 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1630 1667 .regs = qmp_v3_usb3phy_regs_layout, 1631 1668 1632 1632 - .start_ctrl = SERDES_START | PCS_START, 1633 1633 - .pwrdn_ctrl = SW_PWRDN, 1634 1634 - .phy_status = PHYSTATUS, 1635 1635 - 1636 1669 .has_pwrdn_delay = true, 1637 1637 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1638 1638 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1639 1639 - 1640 1670 .has_phy_dp_com_ctrl = true, 1641 1671 }; 1642 1672 ··· 1652 1696 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1653 1697 .regs = qmp_v3_usb3phy_regs_layout, 1654 1698 1655 1655 - .start_ctrl = SERDES_START | PCS_START, 1656 1656 - .pwrdn_ctrl = SW_PWRDN, 1657 1657 - .phy_status = PHYSTATUS, 1658 1658 - 1659 1699 .has_pwrdn_delay = true, 1660 1660 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1661 1661 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1662 1662 - 1663 1700 .has_phy_dp_com_ctrl = true, 1664 1701 }; 1665 1702 1666 1703 static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { 1667 1704 .lanes = 1, 1705 1705 + 1706 1706 + .offsets = &qmp_usb_offsets_v5, 1668 1707 1669 1708 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, 1670 1709 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl), ··· 1671 1720 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl), 1672 1721 .clk_list = qmp_v4_phy_clk_l, 1673 1722 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1674 1674 - .reset_list = msm8996_usb3phy_reset_l, 1675 1675 - .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1723 1723 + .reset_list = qcm2290_usb3phy_reset_l, 1724 1724 + .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), 1676 1725 .vreg_list = qmp_phy_vreg_l, 1677 1726 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1678 1727 .regs = qmp_v4_usb3phy_regs_layout, 1679 1679 - 1680 1680 - .start_ctrl = SERDES_START | PCS_START, 1681 1681 - .pwrdn_ctrl = SW_PWRDN, 1682 1682 - .phy_status = PHYSTATUS, 1683 1683 - 1684 1684 - .has_pwrdn_delay = true, 1685 1685 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1686 1686 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1687 1728 }; 1688 1729 1689 1730 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { ··· 1697 1754 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1698 1755 .regs = qmp_v3_usb3phy_regs_layout, 1699 1756 1700 1700 - .start_ctrl = SERDES_START | PCS_START, 1701 1701 - .pwrdn_ctrl = SW_PWRDN, 1702 1702 - .phy_status = PHYSTATUS, 1703 1703 - 1704 1757 .has_pwrdn_delay = true, 1705 1705 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1706 1706 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1707 1758 }; 1708 1759 1709 1760 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { ··· 1718 1781 .vreg_list = qmp_phy_vreg_l, 1719 1782 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1720 1783 .regs = qmp_v3_usb3phy_regs_layout, 1721 1721 - 1722 1722 - .start_ctrl = SERDES_START | PCS_START, 1723 1723 - .pwrdn_ctrl = SW_PWRDN, 1724 1724 - .phy_status = PHYSTATUS, 1725 1784 }; 1726 1785 1727 1786 static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { ··· 1733 1800 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1734 1801 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1735 1802 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1736 1736 - .clk_list = qmp_v4_phy_clk_l, 1737 1737 - .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1803 1803 + .clk_list = qmp_v4_ref_phy_clk_l, 1804 1804 + .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1738 1805 .reset_list = msm8996_usb3phy_reset_l, 1739 1806 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1740 1807 .vreg_list = qmp_phy_vreg_l, ··· 1742 1809 .regs = qmp_v4_usb3phy_regs_layout, 1743 1810 .pcs_usb_offset = 0x300, 1744 1811 1745 1745 - .start_ctrl = SERDES_START | PCS_START, 1746 1746 - .pwrdn_ctrl = SW_PWRDN, 1747 1747 - .phy_status = PHYSTATUS, 1748 1748 - 1749 1749 - 1750 1812 .has_pwrdn_delay = true, 1751 1751 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1752 1752 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1753 1753 - 1754 1813 .has_phy_dp_com_ctrl = true, 1755 1814 }; 1756 1815 ··· 1759 1834 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), 1760 1835 .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl, 1761 1836 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl), 1762 1762 - .clk_list = qmp_v4_phy_clk_l, 1763 1763 - .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1837 1837 + .clk_list = qmp_v4_ref_phy_clk_l, 1838 1838 + .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1764 1839 .reset_list = msm8996_usb3phy_reset_l, 1765 1840 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1766 1841 .vreg_list = qmp_phy_vreg_l, ··· 1768 1843 .regs = qmp_v4_usb3phy_regs_layout, 1769 1844 .pcs_usb_offset = 0x600, 1770 1845 1771 1771 - .start_ctrl = SERDES_START | PCS_START, 1772 1772 - .pwrdn_ctrl = SW_PWRDN, 1773 1773 - .phy_status = PHYSTATUS, 1774 1774 - 1775 1846 .has_pwrdn_delay = true, 1776 1776 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1777 1777 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1778 1847 }; 1779 1848 1780 1849 static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { ··· 1793 1874 .regs = qmp_v4_usb3phy_regs_layout, 1794 1875 .pcs_usb_offset = 0x300, 1795 1876 1796 1796 - .start_ctrl = SERDES_START | PCS_START, 1797 1797 - .pwrdn_ctrl = SW_PWRDN, 1798 1798 - .phy_status = PHYSTATUS, 1799 1799 - 1800 1877 .has_pwrdn_delay = true, 1801 1801 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1802 1802 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1803 1803 - 1804 1878 .has_phy_dp_com_ctrl = true, 1805 1879 }; 1806 1880 ··· 1810 1898 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 1811 1899 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl, 1812 1900 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl), 1813 1813 - .clk_list = qmp_v4_phy_clk_l, 1814 1814 - .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1901 1901 + .clk_list = qmp_v4_ref_phy_clk_l, 1902 1902 + .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1815 1903 .reset_list = msm8996_usb3phy_reset_l, 1816 1904 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1817 1905 .vreg_list = qmp_phy_vreg_l, ··· 1819 1907 .regs = qmp_v4_usb3phy_regs_layout, 1820 1908 .pcs_usb_offset = 0x600, 1821 1909 1822 1822 - .start_ctrl = SERDES_START | PCS_START, 1823 1823 - .pwrdn_ctrl = SW_PWRDN, 1824 1824 - .phy_status = PHYSTATUS, 1825 1825 - 1826 1910 .has_pwrdn_delay = true, 1827 1827 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1828 1828 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1829 1911 }; 1830 1912 1831 1913 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { ··· 1844 1938 .regs = qmp_v4_usb3phy_regs_layout, 1845 1939 .pcs_usb_offset = 0x600, 1846 1940 1847 1847 - .start_ctrl = SERDES_START | PCS_START, 1848 1848 - .pwrdn_ctrl = SW_PWRDN, 1849 1849 - .phy_status = PHYSTATUS, 1850 1850 - 1851 1941 .has_pwrdn_delay = true, 1852 1852 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1853 1853 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1854 1942 }; 1855 1943 1856 1944 static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { ··· 1869 1969 .regs = qmp_v4_usb3phy_regs_layout, 1870 1970 .pcs_usb_offset = 0x1000, 1871 1971 1872 1872 - .start_ctrl = SERDES_START | PCS_START, 1873 1873 - .pwrdn_ctrl = SW_PWRDN, 1874 1874 - .phy_status = PHYSTATUS, 1875 1875 - 1876 1972 .has_pwrdn_delay = true, 1877 1877 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1878 1878 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1879 1973 }; 1880 1974 1881 1975 static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { ··· 1894 2000 .regs = qmp_v4_usb3phy_regs_layout, 1895 2001 .pcs_usb_offset = 0x300, 1896 2002 1897 1897 - .start_ctrl = SERDES_START | PCS_START, 1898 1898 - .pwrdn_ctrl = SW_PWRDN, 1899 1899 - .phy_status = PHYSTATUS, 1900 1900 - 1901 2003 .has_pwrdn_delay = true, 1902 1902 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1903 1903 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1904 1904 - 1905 2004 .has_phy_dp_com_ctrl = true, 1906 2005 }; 1907 2006 ··· 1911 2024 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 1912 2025 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl, 1913 2026 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl), 1914 1914 - .clk_list = qmp_v4_phy_clk_l, 1915 1915 - .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 2027 2027 + .clk_list = qmp_v4_ref_phy_clk_l, 2028 2028 + .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1916 2029 .reset_list = msm8996_usb3phy_reset_l, 1917 2030 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1918 2031 .vreg_list = qmp_phy_vreg_l, ··· 1920 2033 .regs = qmp_v4_usb3phy_regs_layout, 1921 2034 .pcs_usb_offset = 0x1000, 1922 2035 1923 1923 - .start_ctrl = SERDES_START | PCS_START, 1924 1924 - .pwrdn_ctrl = SW_PWRDN, 1925 1925 - .phy_status = PHYSTATUS, 1926 1926 - 1927 2036 .has_pwrdn_delay = true, 1928 1928 - .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 1929 1929 - .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 1930 2037 }; 1931 2038 1932 2039 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { ··· 1941 2060 .vreg_list = qmp_phy_vreg_l, 1942 2061 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1943 2062 .regs = qcm2290_usb3phy_regs_layout, 1944 1944 - 1945 1945 - .start_ctrl = SERDES_START | PCS_START, 1946 1946 - .pwrdn_ctrl = SW_PWRDN, 1947 1947 - .phy_status = PHYSTATUS, 1948 2063 }; 1949 2064 1950 2065 static void qmp_usb_configure_lane(void __iomem *base, 1951 1951 - const unsigned int *regs, 1952 2066 const struct qmp_phy_init_tbl tbl[], 1953 2067 int num, 1954 2068 u8 lane_mask) ··· 1958 2082 if (!(t->lane_mask & lane_mask)) 1959 2083 continue; 1960 2084 1961 1961 - if (t->in_layout) 1962 1962 - writel(t->val, base + regs[t->offset]); 1963 1963 - else 1964 1964 - writel(t->val, base + t->offset); 2085 2085 + writel(t->val, base + t->offset); 1965 2086 } 1966 2087 } 1967 2088 1968 2089 static void qmp_usb_configure(void __iomem *base, 1969 1969 - const unsigned int *regs, 1970 2090 const struct qmp_phy_init_tbl tbl[], 1971 2091 int num) 1972 2092 { 1973 1973 - qmp_usb_configure_lane(base, regs, tbl, num, 0xff); 2093 2093 + qmp_usb_configure_lane(base, tbl, num, 0xff); 1974 2094 } 1975 2095 1976 1976 - static int qmp_usb_serdes_init(struct qmp_phy *qphy) 2096 2096 + static int qmp_usb_serdes_init(struct qmp_usb *qmp) 1977 2097 { 1978 1978 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1979 1979 - void __iomem *serdes = qphy->serdes; 2098 2098 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2099 2099 + void __iomem *serdes = qmp->serdes; 1980 2100 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 1981 2101 int serdes_tbl_num = cfg->serdes_tbl_num; 1982 2102 1983 1983 - qmp_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 2103 2103 + qmp_usb_configure(serdes, serdes_tbl, serdes_tbl_num); 1984 2104 1985 2105 return 0; 1986 2106 } 1987 2107 1988 2108 static int qmp_usb_init(struct phy *phy) 1989 2109 { 1990 1990 - struct qmp_phy *qphy = phy_get_drvdata(phy); 1991 1991 - struct qcom_qmp *qmp = qphy->qmp; 1992 1992 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1993 1993 - void __iomem *pcs = qphy->pcs; 2110 2110 + struct qmp_usb *qmp = phy_get_drvdata(phy); 2111 2111 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2112 2112 + void __iomem *pcs = qmp->pcs; 1994 2113 void __iomem *dp_com = qmp->dp_com; 1995 2114 int ret; 1996 2115 1997 1997 - /* turn on regulator supplies */ 1998 2116 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1999 2117 if (ret) { 2000 2118 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); ··· 2034 2164 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 2035 2165 } 2036 2166 2037 2037 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 2038 2038 - qphy_setbits(pcs, 2039 2039 - cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2040 2040 - cfg->pwrdn_ctrl); 2041 2041 - else 2042 2042 - qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 2043 2043 - cfg->pwrdn_ctrl); 2167 2167 + qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 2044 2168 2045 2169 return 0; 2046 2170 ··· 2048 2184 2049 2185 static int qmp_usb_exit(struct phy *phy) 2050 2186 { 2051 2051 - struct qmp_phy *qphy = phy_get_drvdata(phy); 2052 2052 - struct qcom_qmp *qmp = qphy->qmp; 2053 2053 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2187 2187 + struct qmp_usb *qmp = phy_get_drvdata(phy); 2188 2188 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2054 2189 2055 2190 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2056 2191 ··· 2062 2199 2063 2200 static int qmp_usb_power_on(struct phy *phy) 2064 2201 { 2065 2065 - struct qmp_phy *qphy = phy_get_drvdata(phy); 2066 2066 - struct qcom_qmp *qmp = qphy->qmp; 2067 2067 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2068 2068 - void __iomem *tx = qphy->tx; 2069 2069 - void __iomem *rx = qphy->rx; 2070 2070 - void __iomem *pcs = qphy->pcs; 2202 2202 + struct qmp_usb *qmp = phy_get_drvdata(phy); 2203 2203 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2204 2204 + void __iomem *tx = qmp->tx; 2205 2205 + void __iomem *rx = qmp->rx; 2206 2206 + void __iomem *pcs = qmp->pcs; 2071 2207 void __iomem *status; 2072 2072 - unsigned int mask, val, ready; 2208 2208 + unsigned int val; 2073 2209 int ret; 2074 2210 2075 2075 - qmp_usb_serdes_init(qphy); 2211 2211 + qmp_usb_serdes_init(qmp); 2076 2212 2077 2077 - ret = clk_prepare_enable(qphy->pipe_clk); 2213 2213 + ret = clk_prepare_enable(qmp->pipe_clk); 2078 2214 if (ret) { 2079 2215 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2080 2216 return ret; 2081 2217 } 2082 2218 2083 2219 /* Tx, Rx, and PCS configurations */ 2084 2084 - qmp_usb_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2220 2220 + qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2221 2221 + qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2085 2222 2086 2223 if (cfg->lanes >= 2) { 2087 2087 - qmp_usb_configure_lane(qphy->tx2, cfg->regs, 2088 2088 - cfg->tx_tbl, cfg->tx_tbl_num, 2); 2224 2224 + qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 2225 2225 + qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 2089 2226 } 2090 2227 2091 2091 - qmp_usb_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2092 2092 - 2093 2093 - if (cfg->lanes >= 2) { 2094 2094 - qmp_usb_configure_lane(qphy->rx2, cfg->regs, 2095 2095 - cfg->rx_tbl, cfg->rx_tbl_num, 2); 2096 2096 - } 2097 2097 - 2098 2098 - /* Configure link rate, swing, etc. */ 2099 2099 - qmp_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2228 2228 + qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2100 2229 2101 2230 if (cfg->has_pwrdn_delay) 2102 2102 - usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 2231 2231 + usleep_range(10, 20); 2103 2232 2104 2233 /* Pull PHY out of reset state */ 2105 2234 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2106 2235 2107 2236 /* start SerDes and Phy-Coding-Sublayer */ 2108 2108 - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2237 2237 + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2109 2238 2110 2239 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2111 2111 - mask = cfg->phy_status; 2112 2112 - ready = 0; 2113 2113 - 2114 2114 - ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 2240 2240 + ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 2115 2241 PHY_INIT_COMPLETE_TIMEOUT); 2116 2242 if (ret) { 2117 2243 dev_err(qmp->dev, "phy initialization timed-out\n"); ··· 2110 2258 return 0; 2111 2259 2112 2260 err_disable_pipe_clk: 2113 2113 - clk_disable_unprepare(qphy->pipe_clk); 2261 2261 + clk_disable_unprepare(qmp->pipe_clk); 2114 2262 2115 2263 return ret; 2116 2264 } 2117 2265 2118 2266 static int qmp_usb_power_off(struct phy *phy) 2119 2267 { 2120 2120 - struct qmp_phy *qphy = phy_get_drvdata(phy); 2121 2121 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2268 2268 + struct qmp_usb *qmp = phy_get_drvdata(phy); 2269 2269 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2122 2270 2123 2123 - clk_disable_unprepare(qphy->pipe_clk); 2271 2271 + clk_disable_unprepare(qmp->pipe_clk); 2124 2272 2125 2273 /* PHY reset */ 2126 2126 - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2274 2274 + qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2127 2275 2128 2276 /* stop SerDes and Phy-Coding-Sublayer */ 2129 2129 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2277 2277 + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2278 2278 + SERDES_START | PCS_START); 2130 2279 2131 2280 /* Put PHY into POWER DOWN state: active low */ 2132 2132 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 2133 2133 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2134 2134 - cfg->pwrdn_ctrl); 2135 2135 - } else { 2136 2136 - qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 2137 2137 - cfg->pwrdn_ctrl); 2138 2138 - } 2281 2281 + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2282 2282 + SW_PWRDN); 2139 2283 2140 2284 return 0; 2141 2285 } ··· 2163 2315 2164 2316 static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2165 2317 { 2166 2166 - struct qmp_phy *qphy = phy_get_drvdata(phy); 2318 2318 + struct qmp_usb *qmp = phy_get_drvdata(phy); 2167 2319 2168 2168 - qphy->mode = mode; 2320 2320 + qmp->mode = mode; 2169 2321 2170 2322 return 0; 2171 2323 } 2172 2324 2173 2173 - static void qmp_usb_enable_autonomous_mode(struct qmp_phy *qphy) 2325 2325 + static const struct phy_ops qmp_usb_phy_ops = { 2326 2326 + .init = qmp_usb_enable, 2327 2327 + .exit = qmp_usb_disable, 2328 2328 + .set_mode = qmp_usb_set_mode, 2329 2329 + .owner = THIS_MODULE, 2330 2330 + }; 2331 2331 + 2332 2332 + static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp) 2174 2333 { 2175 2175 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2176 2176 - void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; 2177 2177 - void __iomem *pcs_misc = qphy->pcs_misc; 2334 2334 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2335 2335 + void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2336 2336 + void __iomem *pcs_misc = qmp->pcs_misc; 2178 2337 u32 intr_mask; 2179 2338 2180 2180 - if (qphy->mode == PHY_MODE_USB_HOST_SS || 2181 2181 - qphy->mode == PHY_MODE_USB_DEVICE_SS) 2339 2339 + if (qmp->mode == PHY_MODE_USB_HOST_SS || 2340 2340 + qmp->mode == PHY_MODE_USB_DEVICE_SS) 2182 2341 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2183 2342 else 2184 2343 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; ··· 2206 2351 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2207 2352 } 2208 2353 2209 2209 - static void qmp_usb_disable_autonomous_mode(struct qmp_phy *qphy) 2354 2354 + static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp) 2210 2355 { 2211 2211 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2212 2212 - void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; 2213 2213 - void __iomem *pcs_misc = qphy->pcs_misc; 2356 2356 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2357 2357 + void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2358 2358 + void __iomem *pcs_misc = qmp->pcs_misc; 2214 2359 2215 2360 /* Disable i/o clamp_n on resume for normal mode */ 2216 2361 if (pcs_misc) ··· 2226 2371 2227 2372 static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev) 2228 2373 { 2229 2229 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2230 2230 - struct qmp_phy *qphy = qmp->phys[0]; 2231 2231 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2374 2374 + struct qmp_usb *qmp = dev_get_drvdata(dev); 2375 2375 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2232 2376 2233 2233 - dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); 2377 2377 + dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 2234 2378 2235 2235 - if (!qphy->phy->init_count) { 2379 2379 + if (!qmp->phy->init_count) { 2236 2380 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2237 2381 return 0; 2238 2382 } 2239 2383 2240 2240 - qmp_usb_enable_autonomous_mode(qphy); 2384 2384 + qmp_usb_enable_autonomous_mode(qmp); 2241 2385 2242 2242 - clk_disable_unprepare(qphy->pipe_clk); 2386 2386 + clk_disable_unprepare(qmp->pipe_clk); 2243 2387 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2244 2388 2245 2389 return 0; ··· 2246 2392 2247 2393 static int __maybe_unused qmp_usb_runtime_resume(struct device *dev) 2248 2394 { 2249 2249 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2250 2250 - struct qmp_phy *qphy = qmp->phys[0]; 2251 2251 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2395 2395 + struct qmp_usb *qmp = dev_get_drvdata(dev); 2396 2396 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2252 2397 int ret = 0; 2253 2398 2254 2254 - dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); 2399 2399 + dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 2255 2400 2256 2256 - if (!qphy->phy->init_count) { 2401 2401 + if (!qmp->phy->init_count) { 2257 2402 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2258 2403 return 0; 2259 2404 } ··· 2261 2408 if (ret) 2262 2409 return ret; 2263 2410 2264 2264 - ret = clk_prepare_enable(qphy->pipe_clk); 2411 2411 + ret = clk_prepare_enable(qmp->pipe_clk); 2265 2412 if (ret) { 2266 2413 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2267 2414 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2268 2415 return ret; 2269 2416 } 2270 2417 2271 2271 - qmp_usb_disable_autonomous_mode(qphy); 2418 2418 + qmp_usb_disable_autonomous_mode(qmp); 2272 2419 2273 2420 return 0; 2274 2421 } 2275 2422 2276 2276 - static int qmp_usb_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2423 2423 + static const struct dev_pm_ops qmp_usb_pm_ops = { 2424 2424 + SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend, 2425 2425 + qmp_usb_runtime_resume, NULL) 2426 2426 + }; 2427 2427 + 2428 2428 + static int qmp_usb_vreg_init(struct qmp_usb *qmp) 2277 2429 { 2278 2278 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2430 2430 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2431 2431 + struct device *dev = qmp->dev; 2279 2432 int num = cfg->num_vregs; 2280 2433 int i; 2281 2434 ··· 2295 2436 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2296 2437 } 2297 2438 2298 2298 - static int qmp_usb_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2439 2439 + static int qmp_usb_reset_init(struct qmp_usb *qmp) 2299 2440 { 2300 2300 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2441 2441 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2442 2442 + struct device *dev = qmp->dev; 2301 2443 int i; 2302 2444 int ret; 2303 2445 ··· 2317 2457 return 0; 2318 2458 } 2319 2459 2320 2320 - static int qmp_usb_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2460 2460 + static int qmp_usb_clk_init(struct qmp_usb *qmp) 2321 2461 { 2322 2322 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2462 2462 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2463 2463 + struct device *dev = qmp->dev; 2323 2464 int num = cfg->num_clks; 2324 2465 int i; 2325 2466 ··· 2357 2496 * clk | +-------+ | +-----+ 2358 2497 * +---------------+ 2359 2498 */ 2360 2360 - static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 2499 2499 + static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np) 2361 2500 { 2362 2362 - struct clk_fixed_rate *fixed; 2501 2501 + struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2363 2502 struct clk_init_data init = { }; 2364 2503 int ret; 2365 2504 ··· 2368 2507 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2369 2508 return ret; 2370 2509 } 2371 2371 - 2372 2372 - fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2373 2373 - if (!fixed) 2374 2374 - return -ENOMEM; 2375 2510 2376 2511 init.ops = &clk_fixed_rate_ops; 2377 2512 ··· 2390 2533 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2391 2534 } 2392 2535 2393 2393 - static const struct phy_ops qmp_usb_ops = { 2394 2394 - .init = qmp_usb_enable, 2395 2395 - .exit = qmp_usb_disable, 2396 2396 - .set_mode = qmp_usb_set_mode, 2397 2397 - .owner = THIS_MODULE, 2398 2398 - }; 2399 2399 - 2400 2536 static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np, 2401 2537 int index, bool exclusive) 2402 2538 { ··· 2405 2555 return devm_of_iomap(dev, np, index, NULL); 2406 2556 } 2407 2557 2408 2408 - static 2409 2409 - int qmp_usb_create(struct device *dev, struct device_node *np, int id, 2410 2410 - void __iomem *serdes, const struct qmp_phy_cfg *cfg) 2558 2558 + static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np) 2411 2559 { 2412 2412 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 2413 2413 - struct phy *generic_phy; 2414 2414 - struct qmp_phy *qphy; 2560 2560 + struct platform_device *pdev = to_platform_device(qmp->dev); 2561 2561 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2562 2562 + struct device *dev = qmp->dev; 2415 2563 bool exclusive = true; 2416 2416 - int ret; 2564 2564 + 2565 2565 + qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2566 2566 + if (IS_ERR(qmp->serdes)) 2567 2567 + return PTR_ERR(qmp->serdes); 2568 2568 + 2569 2569 + if (cfg->has_phy_dp_com_ctrl) { 2570 2570 + qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 2571 2571 + if (IS_ERR(qmp->dp_com)) 2572 2572 + return PTR_ERR(qmp->dp_com); 2573 2573 + } 2417 2574 2418 2575 /* 2419 2576 * FIXME: These bindings should be fixed to not rely on overlapping ··· 2431 2574 if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy")) 2432 2575 exclusive = false; 2433 2576 2434 2434 - qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 2435 2435 - if (!qphy) 2436 2436 - return -ENOMEM; 2437 2437 - 2438 2438 - qphy->cfg = cfg; 2439 2439 - qphy->serdes = serdes; 2440 2577 /* 2441 2441 - * Get memory resources for each phy lane: 2578 2578 + * Get memory resources for the PHY: 2442 2579 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2443 2580 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2444 2581 * For single lane PHYs: pcs_misc (optional) -> 3. 2445 2582 */ 2446 2446 - qphy->tx = devm_of_iomap(dev, np, 0, NULL); 2447 2447 - if (IS_ERR(qphy->tx)) 2448 2448 - return PTR_ERR(qphy->tx); 2583 2583 + qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2584 2584 + if (IS_ERR(qmp->tx)) 2585 2585 + return PTR_ERR(qmp->tx); 2449 2586 2450 2450 - qphy->rx = devm_of_iomap(dev, np, 1, NULL); 2451 2451 - if (IS_ERR(qphy->rx)) 2452 2452 - return PTR_ERR(qphy->rx); 2587 2587 + qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2588 2588 + if (IS_ERR(qmp->rx)) 2589 2589 + return PTR_ERR(qmp->rx); 2453 2590 2454 2454 - qphy->pcs = qmp_usb_iomap(dev, np, 2, exclusive); 2455 2455 - if (IS_ERR(qphy->pcs)) 2456 2456 - return PTR_ERR(qphy->pcs); 2591 2591 + qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive); 2592 2592 + if (IS_ERR(qmp->pcs)) 2593 2593 + return PTR_ERR(qmp->pcs); 2457 2594 2458 2595 if (cfg->pcs_usb_offset) 2459 2459 - qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset; 2596 2596 + qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 2460 2597 2461 2598 if (cfg->lanes >= 2) { 2462 2462 - qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); 2463 2463 - if (IS_ERR(qphy->tx2)) 2464 2464 - return PTR_ERR(qphy->tx2); 2599 2599 + qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2600 2600 + if (IS_ERR(qmp->tx2)) 2601 2601 + return PTR_ERR(qmp->tx2); 2465 2602 2466 2466 - qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); 2467 2467 - if (IS_ERR(qphy->rx2)) 2468 2468 - return PTR_ERR(qphy->rx2); 2603 2603 + qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2604 2604 + if (IS_ERR(qmp->rx2)) 2605 2605 + return PTR_ERR(qmp->rx2); 2469 2606 2470 2470 - qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2607 2607 + qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2471 2608 } else { 2472 2472 - qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2609 2609 + qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2473 2610 } 2474 2611 2475 2475 - if (IS_ERR(qphy->pcs_misc)) { 2612 2612 + if (IS_ERR(qmp->pcs_misc)) { 2476 2613 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2477 2477 - qphy->pcs_misc = NULL; 2614 2614 + qmp->pcs_misc = NULL; 2478 2615 } 2479 2616 2480 2480 - qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2481 2481 - if (IS_ERR(qphy->pipe_clk)) { 2482 2482 - return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), 2483 2483 - "failed to get lane%d pipe clock\n", id); 2617 2617 + qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2618 2618 + if (IS_ERR(qmp->pipe_clk)) { 2619 2619 + return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2620 2620 + "failed to get pipe clock\n"); 2484 2621 } 2485 2485 - 2486 2486 - generic_phy = devm_phy_create(dev, np, &qmp_usb_ops); 2487 2487 - if (IS_ERR(generic_phy)) { 2488 2488 - ret = PTR_ERR(generic_phy); 2489 2489 - dev_err(dev, "failed to create qphy %d\n", ret); 2490 2490 - return ret; 2491 2491 - } 2492 2492 - 2493 2493 - qphy->phy = generic_phy; 2494 2494 - qphy->qmp = qmp; 2495 2495 - qmp->phys[id] = qphy; 2496 2496 - phy_set_drvdata(generic_phy, qphy); 2497 2622 2498 2623 return 0; 2499 2624 } 2500 2625 2626 2626 + static int qmp_usb_parse_dt(struct qmp_usb *qmp) 2627 2627 + { 2628 2628 + struct platform_device *pdev = to_platform_device(qmp->dev); 2629 2629 + const struct qmp_phy_cfg *cfg = qmp->cfg; 2630 2630 + const struct qmp_usb_offsets *offs = cfg->offsets; 2631 2631 + struct device *dev = qmp->dev; 2632 2632 + void __iomem *base; 2633 2633 + 2634 2634 + if (!offs) 2635 2635 + return -EINVAL; 2636 2636 + 2637 2637 + base = devm_platform_ioremap_resource(pdev, 0); 2638 2638 + if (IS_ERR(base)) 2639 2639 + return PTR_ERR(base); 2640 2640 + 2641 2641 + qmp->serdes = base + offs->serdes; 2642 2642 + qmp->pcs = base + offs->pcs; 2643 2643 + qmp->pcs_usb = base + offs->pcs_usb; 2644 2644 + qmp->tx = base + offs->tx; 2645 2645 + qmp->rx = base + offs->rx; 2646 2646 + 2647 2647 + qmp->pipe_clk = devm_clk_get(dev, "pipe"); 2648 2648 + if (IS_ERR(qmp->pipe_clk)) { 2649 2649 + return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2650 2650 + "failed to get pipe clock\n"); 2651 2651 + } 2652 2652 + 2653 2653 + return 0; 2654 2654 + } 2655 2655 + 2656 2656 + static int qmp_usb_probe(struct platform_device *pdev) 2657 2657 + { 2658 2658 + struct device *dev = &pdev->dev; 2659 2659 + struct phy_provider *phy_provider; 2660 2660 + struct device_node *np; 2661 2661 + struct qmp_usb *qmp; 2662 2662 + int ret; 2663 2663 + 2664 2664 + qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2665 2665 + if (!qmp) 2666 2666 + return -ENOMEM; 2667 2667 + 2668 2668 + qmp->dev = dev; 2669 2669 + 2670 2670 + qmp->cfg = of_device_get_match_data(dev); 2671 2671 + if (!qmp->cfg) 2672 2672 + return -EINVAL; 2673 2673 + 2674 2674 + ret = qmp_usb_clk_init(qmp); 2675 2675 + if (ret) 2676 2676 + return ret; 2677 2677 + 2678 2678 + ret = qmp_usb_reset_init(qmp); 2679 2679 + if (ret) 2680 2680 + return ret; 2681 2681 + 2682 2682 + ret = qmp_usb_vreg_init(qmp); 2683 2683 + if (ret) 2684 2684 + return ret; 2685 2685 + 2686 2686 + /* Check for legacy binding with child node. */ 2687 2687 + np = of_get_next_available_child(dev->of_node, NULL); 2688 2688 + if (np) { 2689 2689 + ret = qmp_usb_parse_dt_legacy(qmp, np); 2690 2690 + } else { 2691 2691 + np = of_node_get(dev->of_node); 2692 2692 + ret = qmp_usb_parse_dt(qmp); 2693 2693 + } 2694 2694 + if (ret) 2695 2695 + goto err_node_put; 2696 2696 + 2697 2697 + pm_runtime_set_active(dev); 2698 2698 + ret = devm_pm_runtime_enable(dev); 2699 2699 + if (ret) 2700 2700 + goto err_node_put; 2701 2701 + /* 2702 2702 + * Prevent runtime pm from being ON by default. Users can enable 2703 2703 + * it using power/control in sysfs. 2704 2704 + */ 2705 2705 + pm_runtime_forbid(dev); 2706 2706 + 2707 2707 + ret = phy_pipe_clk_register(qmp, np); 2708 2708 + if (ret) 2709 2709 + goto err_node_put; 2710 2710 + 2711 2711 + qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops); 2712 2712 + if (IS_ERR(qmp->phy)) { 2713 2713 + ret = PTR_ERR(qmp->phy); 2714 2714 + dev_err(dev, "failed to create PHY: %d\n", ret); 2715 2715 + goto err_node_put; 2716 2716 + } 2717 2717 + 2718 2718 + phy_set_drvdata(qmp->phy, qmp); 2719 2719 + 2720 2720 + of_node_put(np); 2721 2721 + 2722 2722 + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2723 2723 + 2724 2724 + return PTR_ERR_OR_ZERO(phy_provider); 2725 2725 + 2726 2726 + err_node_put: 2727 2727 + of_node_put(np); 2728 2728 + return ret; 2729 2729 + } 2730 2730 + 2501 2731 static const struct of_device_id qmp_usb_of_match_table[] = { 2502 2732 { 2733 2733 + .compatible = "qcom,ipq6018-qmp-usb3-phy", 2734 2734 + .data = &ipq8074_usb3phy_cfg, 2735 2735 + }, { 2503 2736 .compatible = "qcom,ipq8074-qmp-usb3-phy", 2504 2737 .data = &ipq8074_usb3phy_cfg, 2505 2738 }, { 2506 2739 .compatible = "qcom,msm8996-qmp-usb3-phy", 2507 2740 .data = &msm8996_usb3phy_cfg, 2508 2741 }, { 2509 2509 - .compatible = "qcom,ipq6018-qmp-usb3-phy", 2510 2510 - .data = &ipq8074_usb3phy_cfg, 2742 2742 + .compatible = "qcom,msm8998-qmp-usb3-phy", 2743 2743 + .data = &msm8998_usb3phy_cfg, 2744 2744 + }, { 2745 2745 + .compatible = "qcom,qcm2290-qmp-usb3-phy", 2746 2746 + .data = &qcm2290_usb3phy_cfg, 2511 2747 }, { 2512 2748 .compatible = "qcom,sc7180-qmp-usb3-phy", 2513 2749 .data = &sc7180_usb3phy_cfg, ··· 2617 2667 .compatible = "qcom,sdm845-qmp-usb3-uni-phy", 2618 2668 .data = &qmp_v3_usb3_uniphy_cfg, 2619 2669 }, { 2620 2620 - .compatible = "qcom,msm8998-qmp-usb3-phy", 2621 2621 - .data = &msm8998_usb3phy_cfg, 2670 2670 + .compatible = "qcom,sdx55-qmp-usb3-uni-phy", 2671 2671 + .data = &sdx55_usb3_uniphy_cfg, 2672 2672 + }, { 2673 2673 + .compatible = "qcom,sdx65-qmp-usb3-uni-phy", 2674 2674 + .data = &sdx65_usb3_uniphy_cfg, 2622 2675 }, { 2623 2676 .compatible = "qcom,sm8150-qmp-usb3-phy", 2624 2677 .data = &sm8150_usb3phy_cfg, ··· 2635 2682 .compatible = "qcom,sm8250-qmp-usb3-uni-phy", 2636 2683 .data = &sm8250_usb3_uniphy_cfg, 2637 2684 }, { 2638 2638 - .compatible = "qcom,sdx55-qmp-usb3-uni-phy", 2639 2639 - .data = &sdx55_usb3_uniphy_cfg, 2640 2640 - }, { 2641 2641 - .compatible = "qcom,sdx65-qmp-usb3-uni-phy", 2642 2642 - .data = &sdx65_usb3_uniphy_cfg, 2643 2643 - }, { 2644 2685 .compatible = "qcom,sm8350-qmp-usb3-phy", 2645 2686 .data = &sm8350_usb3phy_cfg, 2646 2687 }, { ··· 2643 2696 }, { 2644 2697 .compatible = "qcom,sm8450-qmp-usb3-phy", 2645 2698 .data = &sm8350_usb3phy_cfg, 2646 2646 - }, { 2647 2647 - .compatible = "qcom,qcm2290-qmp-usb3-phy", 2648 2648 - .data = &qcm2290_usb3phy_cfg, 2649 2699 }, 2650 2700 { }, 2651 2701 }; 2652 2702 MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table); 2653 2653 - 2654 2654 - static const struct dev_pm_ops qmp_usb_pm_ops = { 2655 2655 - SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend, 2656 2656 - qmp_usb_runtime_resume, NULL) 2657 2657 - }; 2658 2658 - 2659 2659 - static int qmp_usb_probe(struct platform_device *pdev) 2660 2660 - { 2661 2661 - struct qcom_qmp *qmp; 2662 2662 - struct device *dev = &pdev->dev; 2663 2663 - struct device_node *child; 2664 2664 - struct phy_provider *phy_provider; 2665 2665 - void __iomem *serdes; 2666 2666 - const struct qmp_phy_cfg *cfg = NULL; 2667 2667 - int num, id; 2668 2668 - int ret; 2669 2669 - 2670 2670 - qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2671 2671 - if (!qmp) 2672 2672 - return -ENOMEM; 2673 2673 - 2674 2674 - qmp->dev = dev; 2675 2675 - dev_set_drvdata(dev, qmp); 2676 2676 - 2677 2677 - /* Get the specific init parameters of QMP phy */ 2678 2678 - cfg = of_device_get_match_data(dev); 2679 2679 - if (!cfg) 2680 2680 - return -EINVAL; 2681 2681 - 2682 2682 - /* per PHY serdes; usually located at base address */ 2683 2683 - serdes = devm_platform_ioremap_resource(pdev, 0); 2684 2684 - if (IS_ERR(serdes)) 2685 2685 - return PTR_ERR(serdes); 2686 2686 - 2687 2687 - /* per PHY dp_com; if PHY has dp_com control block */ 2688 2688 - if (cfg->has_phy_dp_com_ctrl) { 2689 2689 - qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 2690 2690 - if (IS_ERR(qmp->dp_com)) 2691 2691 - return PTR_ERR(qmp->dp_com); 2692 2692 - } 2693 2693 - 2694 2694 - ret = qmp_usb_clk_init(dev, cfg); 2695 2695 - if (ret) 2696 2696 - return ret; 2697 2697 - 2698 2698 - ret = qmp_usb_reset_init(dev, cfg); 2699 2699 - if (ret) 2700 2700 - return ret; 2701 2701 - 2702 2702 - ret = qmp_usb_vreg_init(dev, cfg); 2703 2703 - if (ret) 2704 2704 - return dev_err_probe(dev, ret, 2705 2705 - "failed to get regulator supplies\n"); 2706 2706 - 2707 2707 - num = of_get_available_child_count(dev->of_node); 2708 2708 - /* do we have a rogue child node ? */ 2709 2709 - if (num > 1) 2710 2710 - return -EINVAL; 2711 2711 - 2712 2712 - qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 2713 2713 - if (!qmp->phys) 2714 2714 - return -ENOMEM; 2715 2715 - 2716 2716 - pm_runtime_set_active(dev); 2717 2717 - ret = devm_pm_runtime_enable(dev); 2718 2718 - if (ret) 2719 2719 - return ret; 2720 2720 - /* 2721 2721 - * Prevent runtime pm from being ON by default. Users can enable 2722 2722 - * it using power/control in sysfs. 2723 2723 - */ 2724 2724 - pm_runtime_forbid(dev); 2725 2725 - 2726 2726 - id = 0; 2727 2727 - for_each_available_child_of_node(dev->of_node, child) { 2728 2728 - /* Create per-lane phy */ 2729 2729 - ret = qmp_usb_create(dev, child, id, serdes, cfg); 2730 2730 - if (ret) { 2731 2731 - dev_err(dev, "failed to create lane%d phy, %d\n", 2732 2732 - id, ret); 2733 2733 - goto err_node_put; 2734 2734 - } 2735 2735 - 2736 2736 - /* 2737 2737 - * Register the pipe clock provided by phy. 2738 2738 - * See function description to see details of this pipe clock. 2739 2739 - */ 2740 2740 - ret = phy_pipe_clk_register(qmp, child); 2741 2741 - if (ret) { 2742 2742 - dev_err(qmp->dev, 2743 2743 - "failed to register pipe clock source\n"); 2744 2744 - goto err_node_put; 2745 2745 - } 2746 2746 - 2747 2747 - id++; 2748 2748 - } 2749 2749 - 2750 2750 - phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2751 2751 - 2752 2752 - return PTR_ERR_OR_ZERO(phy_provider); 2753 2753 - 2754 2754 - err_node_put: 2755 2755 - of_node_put(child); 2756 2756 - return ret; 2757 2757 - } 2758 2703 2759 2704 static struct platform_driver qmp_usb_driver = { 2760 2705 .probe = qmp_usb_probe,

+1

drivers/phy/qualcomm/phy-qcom-qmp.h

reviewed

··· 38 38 #include "phy-qcom-qmp-pcs-pcie-v4_20.h" 39 39 40 40 #include "phy-qcom-qmp-pcs-v5.h" 41 41 + #include "phy-qcom-qmp-pcs-v5_20.h" 41 42 #include "phy-qcom-qmp-pcs-pcie-v5.h" 42 43 #include "phy-qcom-qmp-pcs-usb-v5.h" 43 44 #include "phy-qcom-qmp-pcs-ufs-v5.h"

+8

drivers/phy/renesas/Kconfig

reviewed

··· 2 2 # 3 3 # Phy drivers for Renesas platforms 4 4 # 5 5 + # NOTE: Please sorted config names alphabetically. 6 6 + config PHY_R8A779F0_ETHERNET_SERDES 7 7 + tristate "Renesas R-Car S4-8 Ethernet SERDES driver" 8 8 + depends on ARCH_RENESAS || COMPILE_TEST 9 9 + select GENERIC_PHY 10 10 + help 11 11 + Support for Ethernet SERDES found on Renesas R-Car S4-8 SoCs. 12 12 + 5 13 config PHY_RCAR_GEN2 6 14 tristate "Renesas R-Car generation 2 USB PHY driver" 7 15 depends on ARCH_RENESAS

+1

drivers/phy/renesas/Makefile

reviewed

··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 + obj-$(CONFIG_PHY_R8A779F0_ETHERNET_SERDES) += r8a779f0-ether-serdes.o 2 3 obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o 3 4 obj-$(CONFIG_PHY_RCAR_GEN3_PCIE) += phy-rcar-gen3-pcie.o 4 5 obj-$(CONFIG_PHY_RCAR_GEN3_USB2) += phy-rcar-gen3-usb2.o

+417

drivers/phy/renesas/r8a779f0-ether-serdes.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* Renesas Ethernet SERDES device driver 3 3 + * 4 4 + * Copyright (C) 2022 Renesas Electronics Corporation 5 5 + */ 6 6 + 7 7 + #include <linux/delay.h> 8 8 + #include <linux/err.h> 9 9 + #include <linux/iopoll.h> 10 10 + #include <linux/kernel.h> 11 11 + #include <linux/phy.h> 12 12 + #include <linux/phy/phy.h> 13 13 + #include <linux/platform_device.h> 14 14 + #include <linux/reset.h> 15 15 + 16 16 + #define R8A779F0_ETH_SERDES_NUM 3 17 17 + #define R8A779F0_ETH_SERDES_OFFSET 0x0400 18 18 + #define R8A779F0_ETH_SERDES_BANK_SELECT 0x03fc 19 19 + #define R8A779F0_ETH_SERDES_TIMEOUT_US 100000 20 20 + #define R8A779F0_ETH_SERDES_NUM_RETRY_LINKUP 3 21 21 + #define R8A779F0_ETH_SERDES_NUM_RETRY_INIT 3 22 22 + 23 23 + struct r8a779f0_eth_serdes_drv_data; 24 24 + struct r8a779f0_eth_serdes_channel { 25 25 + struct r8a779f0_eth_serdes_drv_data *dd; 26 26 + struct phy *phy; 27 27 + void __iomem *addr; 28 28 + phy_interface_t phy_interface; 29 29 + int speed; 30 30 + int index; 31 31 + }; 32 32 + 33 33 + struct r8a779f0_eth_serdes_drv_data { 34 34 + void __iomem *addr; 35 35 + struct platform_device *pdev; 36 36 + struct reset_control *reset; 37 37 + struct r8a779f0_eth_serdes_channel channel[R8A779F0_ETH_SERDES_NUM]; 38 38 + bool initialized; 39 39 + }; 40 40 + 41 41 + /* 42 42 + * The datasheet describes initialization procedure without any information 43 43 + * about registers' name/bits. So, this is all black magic to initialize 44 44 + * the hardware. 45 45 + */ 46 46 + static void r8a779f0_eth_serdes_write32(void __iomem *addr, u32 offs, u32 bank, u32 data) 47 47 + { 48 48 + iowrite32(bank, addr + R8A779F0_ETH_SERDES_BANK_SELECT); 49 49 + iowrite32(data, addr + offs); 50 50 + } 51 51 + 52 52 + static int 53 53 + r8a779f0_eth_serdes_reg_wait(struct r8a779f0_eth_serdes_channel *channel, 54 54 + u32 offs, u32 bank, u32 mask, u32 expected) 55 55 + { 56 56 + int ret; 57 57 + u32 val; 58 58 + 59 59 + iowrite32(bank, channel->addr + R8A779F0_ETH_SERDES_BANK_SELECT); 60 60 + 61 61 + ret = readl_poll_timeout_atomic(channel->addr + offs, val, 62 62 + (val & mask) == expected, 63 63 + 1, R8A779F0_ETH_SERDES_TIMEOUT_US); 64 64 + if (ret) 65 65 + dev_dbg(&channel->phy->dev, 66 66 + "%s: index %d, offs %x, bank %x, mask %x, expected %x\n", 67 67 + __func__, channel->index, offs, bank, mask, expected); 68 68 + 69 69 + return ret; 70 70 + } 71 71 + 72 72 + static int 73 73 + r8a779f0_eth_serdes_common_init_ram(struct r8a779f0_eth_serdes_drv_data *dd) 74 74 + { 75 75 + struct r8a779f0_eth_serdes_channel *channel; 76 76 + int i, ret; 77 77 + 78 78 + for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) { 79 79 + channel = &dd->channel[i]; 80 80 + ret = r8a779f0_eth_serdes_reg_wait(channel, 0x026c, 0x180, BIT(0), 0x01); 81 81 + if (ret) 82 82 + return ret; 83 83 + } 84 84 + 85 85 + r8a779f0_eth_serdes_write32(dd->addr, 0x026c, 0x180, 0x03); 86 86 + 87 87 + return ret; 88 88 + } 89 89 + 90 90 + static int 91 91 + r8a779f0_eth_serdes_common_setting(struct r8a779f0_eth_serdes_channel *channel) 92 92 + { 93 93 + struct r8a779f0_eth_serdes_drv_data *dd = channel->dd; 94 94 + 95 95 + switch (channel->phy_interface) { 96 96 + case PHY_INTERFACE_MODE_SGMII: 97 97 + r8a779f0_eth_serdes_write32(dd->addr, 0x0244, 0x180, 0x0097); 98 98 + r8a779f0_eth_serdes_write32(dd->addr, 0x01d0, 0x180, 0x0060); 99 99 + r8a779f0_eth_serdes_write32(dd->addr, 0x01d8, 0x180, 0x2200); 100 100 + r8a779f0_eth_serdes_write32(dd->addr, 0x01d4, 0x180, 0x0000); 101 101 + r8a779f0_eth_serdes_write32(dd->addr, 0x01e0, 0x180, 0x003d); 102 102 + return 0; 103 103 + default: 104 104 + return -EOPNOTSUPP; 105 105 + } 106 106 + } 107 107 + 108 108 + static int 109 109 + r8a779f0_eth_serdes_chan_setting(struct r8a779f0_eth_serdes_channel *channel) 110 110 + { 111 111 + int ret; 112 112 + 113 113 + switch (channel->phy_interface) { 114 114 + case PHY_INTERFACE_MODE_SGMII: 115 115 + r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2000); 116 116 + r8a779f0_eth_serdes_write32(channel->addr, 0x01c0, 0x180, 0x0011); 117 117 + r8a779f0_eth_serdes_write32(channel->addr, 0x0248, 0x180, 0x0540); 118 118 + r8a779f0_eth_serdes_write32(channel->addr, 0x0258, 0x180, 0x0015); 119 119 + r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x0100); 120 120 + r8a779f0_eth_serdes_write32(channel->addr, 0x01a0, 0x180, 0x0000); 121 121 + r8a779f0_eth_serdes_write32(channel->addr, 0x00d0, 0x180, 0x0002); 122 122 + r8a779f0_eth_serdes_write32(channel->addr, 0x0150, 0x180, 0x0003); 123 123 + r8a779f0_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x0100); 124 124 + r8a779f0_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0100); 125 125 + r8a779f0_eth_serdes_write32(channel->addr, 0x0174, 0x180, 0x0000); 126 126 + r8a779f0_eth_serdes_write32(channel->addr, 0x0160, 0x180, 0x0007); 127 127 + r8a779f0_eth_serdes_write32(channel->addr, 0x01ac, 0x180, 0x0000); 128 128 + r8a779f0_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x0310); 129 129 + r8a779f0_eth_serdes_write32(channel->addr, 0x00c8, 0x380, 0x0101); 130 130 + ret = r8a779f0_eth_serdes_reg_wait(channel, 0x00c8, 0x0180, BIT(0), 0); 131 131 + if (ret) 132 132 + return ret; 133 133 + 134 134 + r8a779f0_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0101); 135 135 + ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0148, 0x0180, BIT(0), 0); 136 136 + if (ret) 137 137 + return ret; 138 138 + 139 139 + r8a779f0_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x1310); 140 140 + r8a779f0_eth_serdes_write32(channel->addr, 0x00d8, 0x180, 0x1800); 141 141 + r8a779f0_eth_serdes_write32(channel->addr, 0x00dc, 0x180, 0x0000); 142 142 + r8a779f0_eth_serdes_write32(channel->addr, 0x001c, 0x300, 0x0001); 143 143 + r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2100); 144 144 + ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0000, 0x0380, BIT(8), 0); 145 145 + if (ret) 146 146 + return ret; 147 147 + 148 148 + if (channel->speed == 1000) 149 149 + r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x0140); 150 150 + else if (channel->speed == 100) 151 151 + r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x2100); 152 152 + 153 153 + /* For AN_ON */ 154 154 + r8a779f0_eth_serdes_write32(channel->addr, 0x0004, 0x1f80, 0x0005); 155 155 + r8a779f0_eth_serdes_write32(channel->addr, 0x0028, 0x1f80, 0x07a1); 156 156 + r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f80, 0x0208); 157 157 + break; 158 158 + default: 159 159 + return -EOPNOTSUPP; 160 160 + } 161 161 + 162 162 + return 0; 163 163 + } 164 164 + 165 165 + static int 166 166 + r8a779f0_eth_serdes_chan_speed(struct r8a779f0_eth_serdes_channel *channel) 167 167 + { 168 168 + int ret; 169 169 + 170 170 + switch (channel->phy_interface) { 171 171 + case PHY_INTERFACE_MODE_SGMII: 172 172 + /* For AN_ON */ 173 173 + if (channel->speed == 1000) 174 174 + r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x1140); 175 175 + else if (channel->speed == 100) 176 176 + r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x3100); 177 177 + ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0008, 0x1f80, BIT(0), 1); 178 178 + if (ret) 179 179 + return ret; 180 180 + r8a779f0_eth_serdes_write32(channel->addr, 0x0008, 0x1f80, 0x0000); 181 181 + break; 182 182 + default: 183 183 + return -EOPNOTSUPP; 184 184 + } 185 185 + 186 186 + return 0; 187 187 + } 188 188 + 189 189 + 190 190 + static int r8a779f0_eth_serdes_monitor_linkup(struct r8a779f0_eth_serdes_channel *channel) 191 191 + { 192 192 + int i, ret; 193 193 + 194 194 + for (i = 0; i < R8A779F0_ETH_SERDES_NUM_RETRY_LINKUP; i++) { 195 195 + ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0004, 0x300, 196 196 + BIT(2), BIT(2)); 197 197 + if (!ret) 198 198 + break; 199 199 + 200 200 + /* restart */ 201 201 + r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x0100); 202 202 + udelay(1); 203 203 + r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x0000); 204 204 + } 205 205 + 206 206 + return ret; 207 207 + } 208 208 + 209 209 + static int r8a779f0_eth_serdes_hw_init(struct r8a779f0_eth_serdes_channel *channel) 210 210 + { 211 211 + struct r8a779f0_eth_serdes_drv_data *dd = channel->dd; 212 212 + int i, ret; 213 213 + 214 214 + if (dd->initialized) 215 215 + return 0; 216 216 + 217 217 + ret = r8a779f0_eth_serdes_common_init_ram(dd); 218 218 + if (ret) 219 219 + return ret; 220 220 + 221 221 + for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) { 222 222 + ret = r8a779f0_eth_serdes_reg_wait(&dd->channel[i], 0x0000, 223 223 + 0x300, BIT(15), 0); 224 224 + if (ret) 225 225 + return ret; 226 226 + } 227 227 + 228 228 + for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) 229 229 + r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03d4, 0x380, 0x0443); 230 230 + 231 231 + ret = r8a779f0_eth_serdes_common_setting(channel); 232 232 + if (ret) 233 233 + return ret; 234 234 + 235 235 + for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) 236 236 + r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03d0, 0x380, 0x0001); 237 237 + 238 238 + 239 239 + r8a779f0_eth_serdes_write32(dd->addr, 0x0000, 0x380, 0x8000); 240 240 + 241 241 + ret = r8a779f0_eth_serdes_common_init_ram(dd); 242 242 + if (ret) 243 243 + return ret; 244 244 + 245 245 + ret = r8a779f0_eth_serdes_reg_wait(&dd->channel[0], 0x0000, 0x380, BIT(15), 0); 246 246 + if (ret) 247 247 + return ret; 248 248 + 249 249 + for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) { 250 250 + ret = r8a779f0_eth_serdes_chan_setting(&dd->channel[i]); 251 251 + if (ret) 252 252 + return ret; 253 253 + } 254 254 + 255 255 + for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) { 256 256 + ret = r8a779f0_eth_serdes_chan_speed(&dd->channel[i]); 257 257 + if (ret) 258 258 + return ret; 259 259 + } 260 260 + 261 261 + for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) 262 262 + r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03c0, 0x380, 0x0000); 263 263 + for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) 264 264 + r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03d0, 0x380, 0x0000); 265 265 + 266 266 + for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) { 267 267 + ret = r8a779f0_eth_serdes_monitor_linkup(&dd->channel[i]); 268 268 + if (ret) 269 269 + return ret; 270 270 + } 271 271 + 272 272 + return 0; 273 273 + } 274 274 + 275 275 + static int r8a779f0_eth_serdes_init(struct phy *p) 276 276 + { 277 277 + struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p); 278 278 + int i, ret; 279 279 + 280 280 + for (i = 0; i < R8A779F0_ETH_SERDES_NUM_RETRY_INIT; i++) { 281 281 + ret = r8a779f0_eth_serdes_hw_init(channel); 282 282 + if (!ret) { 283 283 + channel->dd->initialized = true; 284 284 + break; 285 285 + } 286 286 + usleep_range(1000, 2000); 287 287 + } 288 288 + 289 289 + return ret; 290 290 + } 291 291 + 292 292 + static int r8a779f0_eth_serdes_set_mode(struct phy *p, enum phy_mode mode, 293 293 + int submode) 294 294 + { 295 295 + struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p); 296 296 + 297 297 + if (mode != PHY_MODE_ETHERNET) 298 298 + return -EOPNOTSUPP; 299 299 + 300 300 + switch (submode) { 301 301 + case PHY_INTERFACE_MODE_GMII: 302 302 + case PHY_INTERFACE_MODE_SGMII: 303 303 + case PHY_INTERFACE_MODE_USXGMII: 304 304 + channel->phy_interface = submode; 305 305 + return 0; 306 306 + default: 307 307 + return -EOPNOTSUPP; 308 308 + } 309 309 + } 310 310 + 311 311 + static int r8a779f0_eth_serdes_set_speed(struct phy *p, int speed) 312 312 + { 313 313 + struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p); 314 314 + 315 315 + channel->speed = speed; 316 316 + 317 317 + return 0; 318 318 + } 319 319 + 320 320 + static const struct phy_ops r8a779f0_eth_serdes_ops = { 321 321 + .init = r8a779f0_eth_serdes_init, 322 322 + .set_mode = r8a779f0_eth_serdes_set_mode, 323 323 + .set_speed = r8a779f0_eth_serdes_set_speed, 324 324 + }; 325 325 + 326 326 + static struct phy *r8a779f0_eth_serdes_xlate(struct device *dev, 327 327 + struct of_phandle_args *args) 328 328 + { 329 329 + struct r8a779f0_eth_serdes_drv_data *dd = dev_get_drvdata(dev); 330 330 + 331 331 + if (args->args[0] >= R8A779F0_ETH_SERDES_NUM) 332 332 + return ERR_PTR(-ENODEV); 333 333 + 334 334 + return dd->channel[args->args[0]].phy; 335 335 + } 336 336 + 337 337 + static const struct of_device_id r8a779f0_eth_serdes_of_table[] = { 338 338 + { .compatible = "renesas,r8a779f0-ether-serdes", }, 339 339 + { } 340 340 + }; 341 341 + MODULE_DEVICE_TABLE(of, r8a779f0_eth_serdes_of_table); 342 342 + 343 343 + static int r8a779f0_eth_serdes_probe(struct platform_device *pdev) 344 344 + { 345 345 + struct r8a779f0_eth_serdes_drv_data *dd; 346 346 + struct phy_provider *provider; 347 347 + struct resource *res; 348 348 + int i; 349 349 + 350 350 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 351 351 + if (!res) { 352 352 + dev_err(&pdev->dev, "invalid resource\n"); 353 353 + return -EINVAL; 354 354 + } 355 355 + 356 356 + dd = devm_kzalloc(&pdev->dev, sizeof(*dd), GFP_KERNEL); 357 357 + if (!dd) 358 358 + return -ENOMEM; 359 359 + 360 360 + platform_set_drvdata(pdev, dd); 361 361 + dd->pdev = pdev; 362 362 + dd->addr = devm_ioremap_resource(&pdev->dev, res); 363 363 + if (IS_ERR(dd->addr)) 364 364 + return PTR_ERR(dd->addr); 365 365 + 366 366 + dd->reset = devm_reset_control_get(&pdev->dev, NULL); 367 367 + if (IS_ERR(dd->reset)) 368 368 + return PTR_ERR(dd->reset); 369 369 + 370 370 + reset_control_reset(dd->reset); 371 371 + 372 372 + for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) { 373 373 + struct r8a779f0_eth_serdes_channel *channel = &dd->channel[i]; 374 374 + 375 375 + channel->phy = devm_phy_create(&pdev->dev, NULL, 376 376 + &r8a779f0_eth_serdes_ops); 377 377 + if (IS_ERR(channel->phy)) 378 378 + return PTR_ERR(channel->phy); 379 379 + channel->addr = dd->addr + R8A779F0_ETH_SERDES_OFFSET * i; 380 380 + channel->dd = dd; 381 381 + channel->index = i; 382 382 + phy_set_drvdata(channel->phy, channel); 383 383 + } 384 384 + 385 385 + provider = devm_of_phy_provider_register(&pdev->dev, 386 386 + r8a779f0_eth_serdes_xlate); 387 387 + if (IS_ERR(provider)) 388 388 + return PTR_ERR(provider); 389 389 + 390 390 + pm_runtime_enable(&pdev->dev); 391 391 + pm_runtime_get_sync(&pdev->dev); 392 392 + 393 393 + return 0; 394 394 + } 395 395 + 396 396 + static int r8a779f0_eth_serdes_remove(struct platform_device *pdev) 397 397 + { 398 398 + pm_runtime_put(&pdev->dev); 399 399 + pm_runtime_disable(&pdev->dev); 400 400 + 401 401 + platform_set_drvdata(pdev, NULL); 402 402 + 403 403 + return 0; 404 404 + } 405 405 + 406 406 + static struct platform_driver r8a779f0_eth_serdes_driver_platform = { 407 407 + .probe = r8a779f0_eth_serdes_probe, 408 408 + .remove = r8a779f0_eth_serdes_remove, 409 409 + .driver = { 410 410 + .name = "r8a779f0_eth_serdes", 411 411 + .of_match_table = r8a779f0_eth_serdes_of_table, 412 412 + } 413 413 + }; 414 414 + module_platform_driver(r8a779f0_eth_serdes_driver_platform); 415 415 + MODULE_AUTHOR("Yoshihiro Shimoda"); 416 416 + MODULE_DESCRIPTION("Renesas Ethernet SERDES device driver"); 417 417 + MODULE_LICENSE("GPL");

+14

drivers/phy/tegra/phy-tegra194-p2u.c

reviewed

··· 15 15 #include <linux/phy/phy.h> 16 16 17 17 #define P2U_CONTROL_CMN 0x74 18 18 + #define P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE BIT(13) 18 19 #define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN BIT(20) 19 20 20 21 #define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0 ··· 86 85 return 0; 87 86 } 88 87 88 88 + static int tegra_p2u_calibrate(struct phy *x) 89 89 + { 90 90 + struct tegra_p2u *phy = phy_get_drvdata(x); 91 91 + u32 val; 92 92 + 93 93 + val = p2u_readl(phy, P2U_CONTROL_CMN); 94 94 + val |= P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE; 95 95 + p2u_writel(phy, val, P2U_CONTROL_CMN); 96 96 + 97 97 + return 0; 98 98 + } 99 99 + 89 100 static const struct phy_ops ops = { 90 101 .power_on = tegra_p2u_power_on, 102 102 + .calibrate = tegra_p2u_calibrate, 91 103 .owner = THIS_MODULE, 92 104 }; 93 105

-1

drivers/phy/tegra/xusb-tegra124.c

reviewed

··· 1652 1652 1653 1653 static const struct tegra_xusb_port_ops tegra124_usb3_port_ops = { 1654 1654 .release = tegra_xusb_usb3_port_release, 1655 1655 - .remove = tegra_xusb_usb3_port_remove, 1656 1655 .enable = tegra124_usb3_port_enable, 1657 1656 .disable = tegra124_usb3_port_disable, 1658 1657 .map = tegra124_usb3_port_map,

-1

drivers/phy/tegra/xusb-tegra186.c

reviewed

··· 1185 1185 1186 1186 static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = { 1187 1187 .release = tegra_xusb_usb3_port_release, 1188 1188 - .remove = tegra_xusb_usb3_port_remove, 1189 1188 .enable = tegra186_usb3_port_enable, 1190 1189 .disable = tegra186_usb3_port_disable, 1191 1190 .map = tegra186_usb3_port_map,

-1

drivers/phy/tegra/xusb-tegra210.c

reviewed

··· 3078 3078 3079 3079 static const struct tegra_xusb_port_ops tegra210_usb3_port_ops = { 3080 3080 .release = tegra_xusb_usb3_port_release, 3081 3081 - .remove = tegra_xusb_usb3_port_remove, 3082 3081 .enable = tegra210_usb3_port_enable, 3083 3082 .disable = tegra210_usb3_port_disable, 3084 3083 .map = tegra210_usb3_port_map,

+1 -9

drivers/phy/tegra/xusb.c

reviewed

··· 954 954 return -EINVAL; 955 955 } 956 956 957 957 - usb3->supply = regulator_get(&port->dev, "vbus"); 958 958 - return PTR_ERR_OR_ZERO(usb3->supply); 957 957 + return 0; 959 958 } 960 959 961 960 static int tegra_xusb_add_usb3_port(struct tegra_xusb_padctl *padctl, ··· 1009 1010 struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port); 1010 1011 1011 1012 kfree(usb3); 1012 1012 - } 1013 1013 - 1014 1014 - void tegra_xusb_usb3_port_remove(struct tegra_xusb_port *port) 1015 1015 - { 1016 1016 - struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port); 1017 1017 - 1018 1018 - regulator_put(usb3->supply); 1019 1013 } 1020 1014 1021 1015 static void __tegra_xusb_remove_ports(struct tegra_xusb_padctl *padctl)

-2

drivers/phy/tegra/xusb.h

reviewed

··· 359 359 360 360 struct tegra_xusb_usb3_port { 361 361 struct tegra_xusb_port base; 362 362 - struct regulator *supply; 363 362 bool context_saved; 364 363 unsigned int port; 365 364 bool internal; ··· 380 381 tegra_xusb_find_usb3_port(struct tegra_xusb_padctl *padctl, 381 382 unsigned int index); 382 383 void tegra_xusb_usb3_port_release(struct tegra_xusb_port *port); 383 383 - void tegra_xusb_usb3_port_remove(struct tegra_xusb_port *port); 384 384 385 385 struct tegra_xusb_port_ops { 386 386 void (*release)(struct tegra_xusb_port *port);

+35 -7

drivers/phy/ti/phy-gmii-sel.c

reviewed

··· 50 50 const struct reg_field (*regfields)[PHY_GMII_SEL_LAST]; 51 51 bool use_of_data; 52 52 u64 extra_modes; 53 53 + u32 num_qsgmii_main_ports; 53 54 }; 54 55 55 56 struct phy_gmii_sel_priv { ··· 214 213 .use_of_data = true, 215 214 .regfields = phy_gmii_sel_fields_am654, 216 215 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), 216 216 + .num_ports = 4, 217 217 + .num_qsgmii_main_ports = 1, 218 218 + }; 219 219 + 220 220 + static const 221 221 + struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = { 222 222 + .use_of_data = true, 223 223 + .regfields = phy_gmii_sel_fields_am654, 224 224 + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), 225 225 + .num_ports = 8, 226 226 + .num_qsgmii_main_ports = 2, 217 227 }; 218 228 219 229 static const struct of_device_id phy_gmii_sel_id_table[] = { ··· 251 239 { 252 240 .compatible = "ti,j7200-cpsw5g-phy-gmii-sel", 253 241 .data = &phy_gmii_sel_cpsw5g_soc_j7200, 242 242 + }, 243 243 + { 244 244 + .compatible = "ti,j721e-cpsw9g-phy-gmii-sel", 245 245 + .data = &phy_gmii_sel_cpsw9g_soc_j721e, 254 246 }, 255 247 {} 256 248 }; ··· 394 378 static int phy_gmii_sel_probe(struct platform_device *pdev) 395 379 { 396 380 struct device *dev = &pdev->dev; 381 381 + const struct phy_gmii_sel_soc_data *soc_data; 397 382 struct device_node *node = dev->of_node; 398 383 const struct of_device_id *of_id; 399 384 struct phy_gmii_sel_priv *priv; 400 385 u32 main_ports = 1; 401 386 int ret; 387 387 + u32 i; 402 388 403 389 of_id = of_match_node(phy_gmii_sel_id_table, pdev->dev.of_node); 404 390 if (!of_id) ··· 412 394 413 395 priv->dev = &pdev->dev; 414 396 priv->soc_data = of_id->data; 397 397 + soc_data = priv->soc_data; 415 398 priv->num_ports = priv->soc_data->num_ports; 416 416 - of_property_read_u32(node, "ti,qsgmii-main-ports", &main_ports); 399 399 + priv->qsgmii_main_ports = 0; 400 400 + 417 401 /* 418 418 - * Ensure that main_ports is within bounds. If the property 419 419 - * ti,qsgmii-main-ports is not mentioned, or the value mentioned 420 420 - * is out of bounds, default to 1. 402 402 + * Based on the compatible, try to read the appropriate number of 403 403 + * QSGMII main ports from the "ti,qsgmii-main-ports" property from 404 404 + * the device-tree node. 421 405 */ 422 422 - if (main_ports < 1 || main_ports > 4) 423 423 - main_ports = 1; 424 424 - priv->qsgmii_main_ports = PHY_GMII_PORT(main_ports); 406 406 + for (i = 0; i < soc_data->num_qsgmii_main_ports; i++) { 407 407 + of_property_read_u32_index(node, "ti,qsgmii-main-ports", i, &main_ports); 408 408 + /* 409 409 + * Ensure that main_ports is within bounds. 410 410 + */ 411 411 + if (main_ports < 1 || main_ports > soc_data->num_ports) { 412 412 + dev_err(dev, "Invalid qsgmii main port provided\n"); 413 413 + return -EINVAL; 414 414 + } 415 415 + priv->qsgmii_main_ports |= PHY_GMII_PORT(main_ports); 416 416 + } 425 417 426 418 priv->regmap = syscon_node_to_regmap(node->parent); 427 419 if (IS_ERR(priv->regmap)) {

+38

drivers/phy/ti/phy-j721e-wiz.c

reviewed

··· 81 81 static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30); 82 82 static const struct reg_field pll1_refclk_mux_sel = 83 83 REG_FIELD(WIZ_SERDES_RST, 29, 29); 84 84 + static const struct reg_field pll1_refclk_mux_sel_2 = 85 85 + REG_FIELD(WIZ_SERDES_RST, 22, 23); 84 86 static const struct reg_field pll0_refclk_mux_sel = 85 87 REG_FIELD(WIZ_SERDES_RST, 28, 28); 88 88 + static const struct reg_field pll0_refclk_mux_sel_2 = 89 89 + REG_FIELD(WIZ_SERDES_RST, 28, 29); 86 90 static const struct reg_field refclk_dig_sel_16g = 87 91 REG_FIELD(WIZ_SERDES_RST, 24, 25); 88 92 static const struct reg_field refclk_dig_sel_10g = 89 93 REG_FIELD(WIZ_SERDES_RST, 24, 24); 90 94 static const struct reg_field pma_cmn_refclk_int_mode = 91 95 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29); 96 96 + static const struct reg_field pma_cmn_refclk1_int_mode = 97 97 + REG_FIELD(WIZ_SERDES_TOP_CTRL, 20, 21); 92 98 static const struct reg_field pma_cmn_refclk_mode = 93 99 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31); 94 100 static const struct reg_field pma_cmn_refclk_dig_div = ··· 321 315 J721E_WIZ_10G, /* Also for J7200 SR1.0 */ 322 316 AM64_WIZ_10G, 323 317 J7200_WIZ_10G, /* J7200 SR2.0 */ 318 318 + J784S4_WIZ_10G, 319 319 + J721S2_WIZ_10G, 324 320 }; 325 321 326 322 struct wiz_data { ··· 1000 992 switch (wiz->type) { 1001 993 case AM64_WIZ_10G: 1002 994 case J7200_WIZ_10G: 995 995 + case J784S4_WIZ_10G: 996 996 + case J721S2_WIZ_10G: 1003 997 of_clk_del_provider(dev->of_node); 1004 998 return; 1005 999 default: ··· 1133 1123 switch (wiz->type) { 1134 1124 case AM64_WIZ_10G: 1135 1125 case J7200_WIZ_10G: 1126 1126 + case J784S4_WIZ_10G: 1127 1127 + case J721S2_WIZ_10G: 1136 1128 ret = wiz_clock_register(wiz); 1137 1129 if (ret) 1138 1130 dev_err(dev, "Failed to register wiz clocks\n"); ··· 1217 1205 break; 1218 1206 case J721E_WIZ_10G: 1219 1207 case J7200_WIZ_10G: 1208 1208 + case J721S2_WIZ_10G: 1220 1209 if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII) 1221 1210 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); 1222 1211 break; ··· 1312 1299 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1313 1300 }; 1314 1301 1302 1302 + static struct wiz_data j784s4_10g_data = { 1303 1303 + .type = J784S4_WIZ_10G, 1304 1304 + .pll0_refclk_mux_sel = &pll0_refclk_mux_sel_2, 1305 1305 + .pll1_refclk_mux_sel = &pll1_refclk_mux_sel_2, 1306 1306 + .refclk_dig_sel = &refclk_dig_sel_16g, 1307 1307 + .pma_cmn_refclk1_int_mode = &pma_cmn_refclk1_int_mode, 1308 1308 + .clk_mux_sel = clk_mux_sel_10g_2_refclk, 1309 1309 + .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1310 1310 + }; 1311 1311 + 1312 1312 + static struct wiz_data j721s2_10g_data = { 1313 1313 + .type = J721S2_WIZ_10G, 1314 1314 + .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, 1315 1315 + .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, 1316 1316 + .refclk_dig_sel = &refclk_dig_sel_10g, 1317 1317 + .clk_mux_sel = clk_mux_sel_10g, 1318 1318 + .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, 1319 1319 + }; 1320 1320 + 1315 1321 static const struct of_device_id wiz_id_table[] = { 1316 1322 { 1317 1323 .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data, ··· 1343 1311 }, 1344 1312 { 1345 1313 .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data, 1314 1314 + }, 1315 1315 + { 1316 1316 + .compatible = "ti,j784s4-wiz-10g", .data = &j784s4_10g_data, 1317 1317 + }, 1318 1318 + { 1319 1319 + .compatible = "ti,j721s2-wiz-10g", .data = &j721s2_10g_data, 1346 1320 }, 1347 1321 {} 1348 1322 };

+20

include/dt-bindings/phy/phy-qcom-qmp.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 2 + /* 3 3 + * Qualcomm QMP PHY constants 4 4 + * 5 5 + * Copyright (C) 2022 Linaro Limited 6 6 + */ 7 7 + 8 8 + #ifndef _DT_BINDINGS_PHY_QMP 9 9 + #define _DT_BINDINGS_PHY_QMP 10 10 + 11 11 + /* QMP USB4-USB3-DP clocks */ 12 12 + #define QMP_USB43DP_USB3_PIPE_CLK 0 13 13 + #define QMP_USB43DP_DP_LINK_CLK 1 14 14 + #define QMP_USB43DP_DP_VCO_DIV_CLK 2 15 15 + 16 16 + /* QMP USB4-USB3-DP PHYs */ 17 17 + #define QMP_USB43DP_USB3_PHY 0 18 18 + #define QMP_USB43DP_DP_PHY 1 19 19 + 20 20 + #endif /* _DT_BINDINGS_PHY_QMP */