Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpio: ath79: use the generic GPIO chip lock for IRQ handling
This driver uses its own raw spinlock in interrupt routines while the
generic GPIO chip callbacks use a separate one. This is, of course, racy
so use the fact that the lock in generic GPIO chip is also a raw
spinlock and convert the interrupt handling functions in this module to
using the provided generic GPIO chip locking API.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20250910-gpio-mmio-gpio-conv-part4-v2-5-f3d1a4c57124@linaro.org
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
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drivers/gpio/gpio-ath79.c
+19
-32
drivers/gpio/gpio-ath79.c
···
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struct ath79_gpio_ctrl {
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struct gpio_generic_chip chip;
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void __iomem *base;
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-
raw_spinlock_t lock;
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unsigned long both_edges;
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};
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···
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{
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struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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-
unsigned long flags;
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gpiochip_enable_irq(&ctrl->chip.gc, irqd_to_hwirq(data));
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-
raw_spin_lock_irqsave(&ctrl->lock, flags);
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+
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guard(gpio_generic_lock_irqsave)(&ctrl->chip);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
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-
raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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static void ath79_gpio_irq_mask(struct irq_data *data)
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{
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struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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unsigned long flags;
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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+
scoped_guard(gpio_generic_lock_irqsave, &ctrl->chip)
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
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gpiochip_disable_irq(&ctrl->chip.gc, irqd_to_hwirq(data));
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}
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···
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{
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struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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unsigned long flags;
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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guard(gpio_generic_lock_irqsave)(&ctrl->chip);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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static void ath79_gpio_irq_disable(struct irq_data *data)
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{
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struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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unsigned long flags;
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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guard(gpio_generic_lock_irqsave)(&ctrl->chip);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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static int ath79_gpio_irq_set_type(struct irq_data *data,
···
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struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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u32 type = 0, polarity = 0;
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unsigned long flags;
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bool disabled;
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switch (flow_type) {
···
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return -EINVAL;
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}
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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guard(gpio_generic_lock_irqsave)(&ctrl->chip);
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if (flow_type == IRQ_TYPE_EDGE_BOTH) {
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ctrl->both_edges |= mask;
···
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ath79_gpio_update_bits(
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ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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return 0;
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}
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···
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struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
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struct ath79_gpio_ctrl *ctrl =
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container_of(gen_gc, struct ath79_gpio_ctrl, chip);
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unsigned long flags, pending;
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unsigned long pending;
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u32 both_edges, state;
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int irq;
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chained_irq_enter(irqchip, desc);
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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scoped_guard(gpio_generic_lock_irqsave, &ctrl->chip) {
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pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
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pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
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/* Update the polarity of the both edges irqs */
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both_edges = ctrl->both_edges & pending;
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if (both_edges) {
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state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
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both_edges, ~state);
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/* Update the polarity of the both edges irqs */
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both_edges = ctrl->both_edges & pending;
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if (both_edges) {
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state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
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both_edges, ~state);
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}
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}
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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for_each_set_bit(irq, &pending, gc->ngpio)
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generic_handle_domain_irq(gc->irq.domain, irq);
···
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ctrl->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(ctrl->base))
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return PTR_ERR(ctrl->base);
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-
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raw_spin_lock_init(&ctrl->lock);
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config = (struct gpio_generic_chip_config) {
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.dev = dev,