tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'renesas-clk-fixes-for-v7.0-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-fixes

Pull Renesas clk driver fixes from Geert Uytterhoeven:

- Fix ordering of module clocks arrays on Renesas RZ/V2H(P) and RZ/V2N
- Remove clocks for watchdogs meant for other CPU cores on the
Renesas RZ/V2H(P) SoC

* tag 'renesas-clk-fixes-for-v7.0-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r9a09g057: Remove entries for WDT{0,2,3}
clk: renesas: r9a09g056: Fix ordering of module clocks array
clk: renesas: r9a09g057: Fix ordering of module clocks array

Stephen Boyd e7a45dec c3692998

+38 -53
+18 -18
drivers/clk/renesas/r9a09g056-cpg.c
··· 289 289 BUS_MSTOP(5, BIT(13))), 290 290 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, 291 291 BUS_MSTOP(5, BIT(13))), 292 + DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20, 293 + BUS_MSTOP(11, BIT(0))), 294 + DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21, 295 + BUS_MSTOP(11, BIT(0))), 296 + DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22, 297 + BUS_MSTOP(11, BIT(0))), 298 + DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23, 299 + BUS_MSTOP(11, BIT(1))), 300 + DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24, 301 + BUS_MSTOP(11, BIT(1))), 302 + DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25, 303 + BUS_MSTOP(11, BIT(1))), 304 + DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26, 305 + BUS_MSTOP(11, BIT(2))), 306 + DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27, 307 + BUS_MSTOP(11, BIT(2))), 308 + DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28, 309 + BUS_MSTOP(11, BIT(2))), 292 310 DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29, 293 311 BUS_MSTOP(11, BIT(3))), 294 312 DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30, ··· 407 389 BUS_MSTOP(11, BIT(12))), 408 390 DEF_MOD("rsci9_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 14, 4, 14, 409 391 BUS_MSTOP(11, BIT(12))), 410 - DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20, 411 - BUS_MSTOP(11, BIT(0))), 412 - DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21, 413 - BUS_MSTOP(11, BIT(0))), 414 - DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22, 415 - BUS_MSTOP(11, BIT(0))), 416 - DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23, 417 - BUS_MSTOP(11, BIT(1))), 418 - DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24, 419 - BUS_MSTOP(11, BIT(1))), 420 - DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25, 421 - BUS_MSTOP(11, BIT(1))), 422 - DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26, 423 - BUS_MSTOP(11, BIT(2))), 424 - DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27, 425 - BUS_MSTOP(11, BIT(2))), 426 - DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28, 427 - BUS_MSTOP(11, BIT(2))), 428 392 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 429 393 BUS_MSTOP(3, BIT(14))), 430 394 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
+20 -35
drivers/clk/renesas/r9a09g057-cpg.c
··· 280 280 BUS_MSTOP(11, BIT(15))), 281 281 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10, 282 282 BUS_MSTOP(12, BIT(0))), 283 - DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11, 284 - BUS_MSTOP(3, BIT(10))), 285 - DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12, 286 - BUS_MSTOP(3, BIT(10))), 287 283 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, 288 284 BUS_MSTOP(1, BIT(0))), 289 285 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, 290 286 BUS_MSTOP(1, BIT(0))), 291 - DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, 292 - BUS_MSTOP(5, BIT(12))), 293 - DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, 294 - BUS_MSTOP(5, BIT(12))), 295 - DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, 296 - BUS_MSTOP(5, BIT(13))), 297 - DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, 298 - BUS_MSTOP(5, BIT(13))), 287 + DEF_MOD("rtc_0_clk_rtc", CLK_PLLCM33_DIV16, 5, 3, 2, 19, 288 + BUS_MSTOP(3, BIT(11) | BIT(12))), 289 + DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20, 290 + BUS_MSTOP(11, BIT(0))), 291 + DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21, 292 + BUS_MSTOP(11, BIT(0))), 293 + DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22, 294 + BUS_MSTOP(11, BIT(0))), 295 + DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23, 296 + BUS_MSTOP(11, BIT(1))), 297 + DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24, 298 + BUS_MSTOP(11, BIT(1))), 299 + DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25, 300 + BUS_MSTOP(11, BIT(1))), 301 + DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26, 302 + BUS_MSTOP(11, BIT(2))), 303 + DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27, 304 + BUS_MSTOP(11, BIT(2))), 305 + DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28, 306 + BUS_MSTOP(11, BIT(2))), 299 307 DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29, 300 308 BUS_MSTOP(11, BIT(3))), 301 309 DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30, ··· 404 396 BUS_MSTOP(11, BIT(12))), 405 397 DEF_MOD("rsci9_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 14, 4, 14, 406 398 BUS_MSTOP(11, BIT(12))), 407 - DEF_MOD("rtc_0_clk_rtc", CLK_PLLCM33_DIV16, 5, 3, 2, 19, 408 - BUS_MSTOP(3, BIT(11) | BIT(12))), 409 - DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20, 410 - BUS_MSTOP(11, BIT(0))), 411 - DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21, 412 - BUS_MSTOP(11, BIT(0))), 413 - DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22, 414 - BUS_MSTOP(11, BIT(0))), 415 - DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23, 416 - BUS_MSTOP(11, BIT(1))), 417 - DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24, 418 - BUS_MSTOP(11, BIT(1))), 419 - DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25, 420 - BUS_MSTOP(11, BIT(1))), 421 - DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26, 422 - BUS_MSTOP(11, BIT(2))), 423 - DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27, 424 - BUS_MSTOP(11, BIT(2))), 425 - DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28, 426 - BUS_MSTOP(11, BIT(2))), 427 399 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 428 400 BUS_MSTOP(3, BIT(14))), 429 401 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16, ··· 586 598 DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */ 587 599 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */ 588 600 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */ 589 - DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */ 590 601 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ 591 - DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */ 592 - DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */ 593 602 DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */ 594 603 DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */ 595 604 DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */