+1 -1

Documentation/devicetree/bindings/Makefile

reviewed

··· 5 5 DT_MK_SCHEMA_FLAGS := $(if $(DT_SCHEMA_FILES), -u) 6 6 7 7 quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<) 8 8 - cmd_chk_binding = $(DT_DOC_CHECKER) $< ; \ 8 8 + cmd_chk_binding = $(DT_DOC_CHECKER) -u $(srctree)/$(src) $< ; \ 9 9 $(DT_EXTRACT_EX) $< > $@ 10 10 11 11 $(obj)/%.example.dts: $(src)/%.yaml FORCE

+2 -2

Documentation/devicetree/bindings/arm/arm-boards

reviewed

··· 216 216 #size-cells = <0>; 217 217 218 218 A57_0: cpu@0 { 219 219 - compatible = "arm,cortex-a57","arm,armv8"; 219 219 + compatible = "arm,cortex-a57"; 220 220 reg = <0x0 0x0>; 221 221 device_type = "cpu"; 222 222 enable-method = "psci"; ··· 225 225 ..... 226 226 227 227 A53_0: cpu@100 { 228 228 - compatible = "arm,cortex-a53","arm,armv8"; 228 228 + compatible = "arm,cortex-a53"; 229 229 reg = <0x0 0x100>; 230 230 device_type = "cpu"; 231 231 enable-method = "psci";

+6 -6

Documentation/devicetree/bindings/arm/cpu-capacity.txt

reviewed

··· 118 118 }; 119 119 120 120 A57_0: cpu@0 { 121 121 - compatible = "arm,cortex-a57","arm,armv8"; 121 121 + compatible = "arm,cortex-a57"; 122 122 reg = <0x0 0x0>; 123 123 device_type = "cpu"; 124 124 enable-method = "psci"; ··· 129 129 }; 130 130 131 131 A57_1: cpu@1 { 132 132 - compatible = "arm,cortex-a57","arm,armv8"; 132 132 + compatible = "arm,cortex-a57"; 133 133 reg = <0x0 0x1>; 134 134 device_type = "cpu"; 135 135 enable-method = "psci"; ··· 140 140 }; 141 141 142 142 A53_0: cpu@100 { 143 143 - compatible = "arm,cortex-a53","arm,armv8"; 143 143 + compatible = "arm,cortex-a53"; 144 144 reg = <0x0 0x100>; 145 145 device_type = "cpu"; 146 146 enable-method = "psci"; ··· 151 151 }; 152 152 153 153 A53_1: cpu@101 { 154 154 - compatible = "arm,cortex-a53","arm,armv8"; 154 154 + compatible = "arm,cortex-a53"; 155 155 reg = <0x0 0x101>; 156 156 device_type = "cpu"; 157 157 enable-method = "psci"; ··· 162 162 }; 163 163 164 164 A53_2: cpu@102 { 165 165 - compatible = "arm,cortex-a53","arm,armv8"; 165 165 + compatible = "arm,cortex-a53"; 166 166 reg = <0x0 0x102>; 167 167 device_type = "cpu"; 168 168 enable-method = "psci"; ··· 173 173 }; 174 174 175 175 A53_3: cpu@103 { 176 176 - compatible = "arm,cortex-a53","arm,armv8"; 176 176 + compatible = "arm,cortex-a53"; 177 177 reg = <0x0 0x103>; 178 178 device_type = "cpu"; 179 179 enable-method = "psci";

+1 -1

Documentation/devicetree/bindings/arm/omap/crossbar.txt

reviewed

··· 41 41 Consumer: 42 42 ======== 43 43 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and 44 44 - Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for 44 44 + Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for 45 45 further details. 46 46 47 47 An interrupt consumer on an SoC using crossbar will use:

+1 -1

Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt

reviewed

··· 35 35 pin of the SoC. Refer to generic fixed rate clock bindings 36 36 documentation[1] for more information how to specify these clocks. 37 37 38 38 - [1] Documentation/devicetree/bindings/clock/fixed-clock.txt 38 38 + [1] Documentation/devicetree/bindings/clock/fixed-clock.yaml 39 39 40 40 Example: Clock controller node: 41 41

+13 -11

Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml

reviewed

··· 92 92 minItems: 2 93 93 maxItems: 4 94 94 95 95 + ranges: true 96 96 + 95 97 interrupts: 96 98 description: Interrupt source of the parent interrupt controller on 97 99 secondary GICs, or VGIC maintenance interrupt on primary GIC (see ··· 199 197 interrupt-controller@e1101000 { 200 198 compatible = "arm,gic-400"; 201 199 #interrupt-cells = <3>; 202 202 - #address-cells = <2>; 203 203 - #size-cells = <2>; 200 200 + #address-cells = <1>; 201 201 + #size-cells = <1>; 204 202 interrupt-controller; 205 203 interrupts = <1 8 0xf04>; 206 206 - ranges = <0 0 0 0xe1100000 0 0x100000>; 207 207 - reg = <0x0 0xe1110000 0 0x01000>, 208 208 - <0x0 0xe112f000 0 0x02000>, 209 209 - <0x0 0xe1140000 0 0x10000>, 210 210 - <0x0 0xe1160000 0 0x10000>; 204 204 + ranges = <0 0xe1100000 0x100000>; 205 205 + reg = <0xe1110000 0x01000>, 206 206 + <0xe112f000 0x02000>, 207 207 + <0xe1140000 0x10000>, 208 208 + <0xe1160000 0x10000>; 211 209 212 212 - v2m0: v2m@8000 { 210 210 + v2m0: v2m@80000 { 213 211 compatible = "arm,gic-v2m-frame"; 214 212 msi-controller; 215 215 - reg = <0x0 0x80000 0 0x1000>; 213 213 + reg = <0x80000 0x1000>; 216 214 }; 217 215 218 216 //... 219 217 220 220 - v2mN: v2m@9000 { 218 218 + v2mN: v2m@90000 { 221 219 compatible = "arm,gic-v2m-frame"; 222 220 msi-controller; 223 223 - reg = <0x0 0x90000 0 0x1000>; 221 221 + reg = <0x90000 0x1000>; 224 222 }; 225 223 }; 226 224 ...

+1 -1

Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt

reviewed

··· 23 23 - marvell,spi-base : List of GIC base SPI interrupts, one for each 24 24 ODMI frame. Those SPI interrupts are 0-based, 25 25 i.e marvell,spi-base = <128> will use SPI #96. 26 26 - See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt 26 26 + See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml 27 27 for details about the GIC Device Tree binding. 28 28 29 29 Example:

+1 -1

Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt

reviewed

··· 15 15 - power-supply: specifies the power source. It can either be a regulator 16 16 or a gpio which enables a regulator, i.e. a regulator-fixed as 17 17 described in 18 18 - Documentation/devicetree/bindings/regulator/fixed-regulator.txt 18 18 + Documentation/devicetree/bindings/regulator/fixed-regulator.yaml 19 19 20 20 Example: 21 21

+1 -1

Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt

reviewed

··· 24 24 Children nodes represent the available nand chips. 25 25 26 26 Other properties: 27 27 - see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. 27 27 + see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings. 28 28 29 29 Example demonstrate on AXG SoC: 30 30

+3 -3

Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt

reviewed

··· 101 101 number (e.g., 0, 1, 2, etc.) 102 102 - #address-cells : see partition.txt 103 103 - #size-cells : see partition.txt 104 104 - - nand-ecc-strength : see nand.txt 105 105 - - nand-ecc-step-size : must be 512 or 1024. See nand.txt 104 104 + - nand-ecc-strength : see nand-controller.yaml 105 105 + - nand-ecc-step-size : must be 512 or 1024. See nand-controller.yaml 106 106 107 107 Optional properties: 108 108 - nand-on-flash-bbt : boolean, to enable the on-flash BBT for this 109 109 - chip-select. See nand.txt 109 109 + chip-select. See nand-controller.yaml 110 110 - brcm,nand-oob-sector-size : integer, to denote the spare area sector size 111 111 expected for the ECC layout in use. This size, in 112 112 addition to the strength and step-size,

+3 -3

Documentation/devicetree/bindings/mtd/denali-nand.txt

reviewed

··· 22 22 select is connected. 23 23 24 24 Optional properties: 25 25 - - nand-ecc-step-size: see nand.txt for details. 25 25 + - nand-ecc-step-size: see nand-controller.yaml for details. 26 26 If present, the value must be 27 27 512 for "altr,socfpga-denali-nand" 28 28 1024 for "socionext,uniphier-denali-nand-v5a" 29 29 1024 for "socionext,uniphier-denali-nand-v5b" 30 30 - - nand-ecc-strength: see nand.txt for details. Valid values are: 30 30 + - nand-ecc-strength: see nand-controller.yaml for details. Valid values are: 31 31 8, 15 for "altr,socfpga-denali-nand" 32 32 8, 16, 24 for "socionext,uniphier-denali-nand-v5a" 33 33 8, 16 for "socionext,uniphier-denali-nand-v5b" 34 34 - - nand-ecc-maximize: see nand.txt for details 34 34 + - nand-ecc-maximize: see nand-controller.yaml for details 35 35 36 36 The chip nodes may optionally contain sub-nodes describing partitions of the 37 37 address space. See partition.txt for more detail.

+3 -3

Documentation/devicetree/bindings/mtd/fsmc-nand.txt

reviewed

··· 30 30 command is asserted. Zero means one cycle, 255 means 256 31 31 cycles. 32 32 - bank: default NAND bank to use (0-3 are valid, 0 is the default). 33 33 - - nand-ecc-mode : see nand.txt 34 34 - - nand-ecc-strength : see nand.txt 35 35 - - nand-ecc-step-size : see nand.txt 33 33 + - nand-ecc-mode : see nand-controller.yaml 34 34 + - nand-ecc-strength : see nand-controller.yaml 35 35 + - nand-ecc-step-size : see nand-controller.yaml 36 36 37 37 Can support 1-bit HW ECC (default) or if stronger correction is required, 38 38 software-based BCH.

+1 -1

Documentation/devicetree/bindings/mtd/gpmc-nand.txt

reviewed

··· 8 8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt 9 9 10 10 For NAND specific properties such as ECC modes or bus width, please refer to 11 11 - Documentation/devicetree/bindings/mtd/nand.txt 11 11 + Documentation/devicetree/bindings/mtd/nand-controller.yaml 12 12 13 13 14 14 Required properties:

+1 -1

Documentation/devicetree/bindings/mtd/hisi504-nand.txt

reviewed

··· 7 7 NAND controller's registers. The second contains base 8 8 physical address and size of NAND controller's buffer. 9 9 - interrupts: Interrupt number for nfc. 10 10 - - nand-bus-width: See nand.txt. 10 10 + - nand-bus-width: See nand-controller.yaml. 11 11 - nand-ecc-mode: Support none and hw ecc mode. 12 12 - #address-cells: Partition address, should be set 1. 13 13 - #size-cells: Partition size, should be set 1.

+7 -7

Documentation/devicetree/bindings/mtd/marvell-nand.txt

reviewed

··· 36 36 37 37 Required properties: 38 38 - reg: shall contain the native Chip Select ids (0-3). 39 39 - - nand-rb: see nand.txt (0-1). 39 39 + - nand-rb: see nand-controller.yaml (0-1). 40 40 41 41 Optional properties: 42 42 - marvell,nand-keep-config: orders the driver not to take the timings 43 43 from the core and leaving them completely untouched. Bootloader 44 44 timings will then be used. 45 45 - label: MTD name. 46 46 - - nand-on-flash-bbt: see nand.txt. 47 47 - - nand-ecc-mode: see nand.txt. Will use hardware ECC if not specified. 48 48 - - nand-ecc-algo: see nand.txt. This property is essentially useful when 46 46 + - nand-on-flash-bbt: see nand-controller.yaml. 47 47 + - nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified. 48 48 + - nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when 49 49 not using hardware ECC. Howerver, it may be added when using hardware 50 50 ECC for clarification but will be ignored by the driver because ECC 51 51 mode is chosen depending on the page size and the strength required by 52 52 the NAND chip. This value may be overwritten with nand-ecc-strength 53 53 property. 54 54 - - nand-ecc-strength: see nand.txt. 55 55 - - nand-ecc-step-size: see nand.txt. Marvell's NAND flash controller does 54 54 + - nand-ecc-strength: see nand-controller.yaml. 55 55 + - nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does 56 56 use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual 57 57 step size will shrink or grow in order to fit the required strength. 58 58 Step sizes are not completely random for all and follow certain 59 59 patterns described in AN-379, "Marvell SoC NFC ECC". 60 60 61 61 - See Documentation/devicetree/bindings/mtd/nand.txt for more details on 61 61 + See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on 62 62 generic bindings. 63 63 64 64

+3 -3

Documentation/devicetree/bindings/mtd/mxc-nand.txt

reviewed

··· 4 4 - compatible: "fsl,imxXX-nand" 5 5 - reg: address range of the nfc block 6 6 - interrupts: irq to be used 7 7 - - nand-bus-width: see nand.txt 8 8 - - nand-ecc-mode: see nand.txt 9 9 - - nand-on-flash-bbt: see nand.txt 7 7 + - nand-bus-width: see nand-controller.yaml 8 8 + - nand-ecc-mode: see nand-controller.yaml 9 9 + - nand-on-flash-bbt: see nand-controller.yaml 10 10 11 11 Example: 12 12

+3 -3

Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt

reviewed

··· 26 26 "hw" is supported. 27 27 - nand-ecc-algo: string, algorithm of NAND ECC. 28 28 Supported values with "hw" ECC mode are: "rs", "bch". 29 29 - - nand-bus-width : See nand.txt 30 30 - - nand-on-flash-bbt: See nand.txt 29 29 + - nand-bus-width : See nand-controller.yaml 30 30 + - nand-on-flash-bbt: See nand-controller.yaml 31 31 - nand-ecc-strength: integer representing the number of bits to correct 32 32 per ECC step (always 512). Supported strength using HW ECC 33 33 modes are: 34 34 - RS: 4, 6, 8 35 35 - BCH: 4, 8, 14, 16 36 36 - - nand-ecc-maximize: See nand.txt 36 36 + - nand-ecc-maximize: See nand-controller.yaml 37 37 - nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM 38 38 are chosen. 39 39 - wp-gpios: GPIO specifier for the write protect pin.

+1 -1

Documentation/devicetree/bindings/mtd/oxnas-nand.txt

reviewed

··· 1 1 * Oxford Semiconductor OXNAS NAND Controller 2 2 3 3 - Please refer to nand.txt for generic information regarding MTD NAND bindings. 3 3 + Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings. 4 4 5 5 Required properties: 6 6 - compatible: "oxsemi,ox820-nand"

+2 -2

Documentation/devicetree/bindings/mtd/qcom_nandc.txt

reviewed

··· 47 47 - #size-cells: see partition.txt 48 48 49 49 Optional properties: 50 50 - - nand-bus-width: see nand.txt 51 51 - - nand-ecc-strength: see nand.txt. If not specified, then ECC strength will 50 50 + - nand-bus-width: see nand-controller.yaml 51 51 + - nand-ecc-strength: see nand-controller.yaml. If not specified, then ECC strength will 52 52 be used according to chip requirement and available 53 53 OOB size. 54 54

+3 -3

Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt

reviewed

··· 6 6 "samsung,s3c2412-nand" 7 7 "samsung,s3c2440-nand" 8 8 - reg : register's location and length. 9 9 - - #address-cells, #size-cells : see nand.txt 9 9 + - #address-cells, #size-cells : see nand-controller.yaml 10 10 - clocks : phandle to the nand controller clock 11 11 - clock-names : must contain "nand" 12 12 ··· 14 14 Child nodes representing the available nand chips. 15 15 16 16 Optional child properties: 17 17 - - nand-ecc-mode : see nand.txt 18 18 - - nand-on-flash-bbt : see nand.txt 17 17 + - nand-ecc-mode : see nand-controller.yaml 18 18 + - nand-on-flash-bbt : see nand-controller.yaml 19 19 20 20 Each child device node may optionally contain a 'partitions' sub-node, 21 21 which further contains sub-nodes describing the flash partition mapping.

+3 -3

Documentation/devicetree/bindings/mtd/stm32-fmc2-nand.txt

reviewed

··· 24 24 - reg: describes the CS lines assigned to the NAND device. 25 25 26 26 Optional properties: 27 27 - - nand-on-flash-bbt: see nand.txt 28 28 - - nand-ecc-strength: see nand.txt 29 29 - - nand-ecc-step-size: see nand.txt 27 27 + - nand-on-flash-bbt: see nand-controller.yaml 28 28 + - nand-ecc-strength: see nand-controller.yaml 29 29 + - nand-ecc-step-size: see nand-controller.yaml 30 30 31 31 The following ECC strength and step size are currently supported: 32 32 - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming)

+1 -1

Documentation/devicetree/bindings/mtd/tango-nand.txt

reviewed

··· 11 11 - #size-cells: <0> 12 12 13 13 Children nodes represent the available NAND chips. 14 14 - See Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. 14 14 + See Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings. 15 15 16 16 Example: 17 17

+4 -4

Documentation/devicetree/bindings/mtd/vf610-nfc.txt

reviewed

··· 25 25 26 26 Required properties: 27 27 - compatible: Should be set to "fsl,vf610-nfc-cs". 28 28 - - nand-bus-width: see nand.txt 29 29 - - nand-ecc-mode: see nand.txt 28 28 + - nand-bus-width: see nand-controller.yaml 29 29 + - nand-ecc-mode: see nand-controller.yaml 30 30 31 31 Required properties for hardware ECC: 32 32 - - nand-ecc-strength: supported strengths are 24 and 32 bit (see nand.txt) 32 32 + - nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml) 33 33 - nand-ecc-step-size: step size equals page size, currently only 2k pages are 34 34 supported 35 35 - - nand-on-flash-bbt: see nand.txt 35 35 + - nand-on-flash-bbt: see nand-controller.yaml 36 36 37 37 Example: 38 38

+38

Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt

reviewed

··· 1 1 + DT compatible string versioning for SiFive open-source IP blocks 2 2 + 3 3 + This document describes the version specification for DT "compatible" 4 4 + strings for open-source SiFive IP blocks. HDL for these IP blocks 5 5 + can be found in this public repository: 6 6 + 7 7 + https://github.com/sifive/sifive-blocks 8 8 + 9 9 + IP block-specific DT compatible strings are contained within the HDL, 10 10 + in the form "sifive,<ip-block-name><integer version number>". 11 11 + 12 12 + An example is "sifive,uart0" from: 13 13 + 14 14 + https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43 15 15 + 16 16 + Until these IP blocks (or IP integration) support version 17 17 + auto-discovery, the maintainers of these IP blocks intend to increment 18 18 + the suffixed number in the compatible string whenever the software 19 19 + interface to these IP blocks changes, or when the functionality of the 20 20 + underlying IP blocks changes in a way that software should be aware of. 21 21 + 22 22 + Driver developers can use compatible string "match" values such as 23 23 + "sifive,uart0" to indicate that their driver is compatible with the 24 24 + register interface and functionality associated with the relevant 25 25 + upstream sifive-blocks commits. It is expected that most drivers will 26 26 + match on these IP block-specific compatible strings. 27 27 + 28 28 + DT data authors, when writing data for a particular SoC, should 29 29 + continue to specify an SoC-specific compatible string value, such as 30 30 + "sifive,fu540-c000-uart". This way, if SoC-specific 31 31 + integration-specific bug fixes or workarounds are needed, the kernel 32 32 + or other system software can match on this string to apply them. The 33 33 + IP block-specific compatible string (such as "sifive,uart0") should 34 34 + then be specified as a subsequent value. 35 35 + 36 36 + An example of this style: 37 37 + 38 38 + compatible = "sifive,fu540-c000-uart", "sifive,uart0";

+2 -2

MAINTAINERS

reviewed

··· 2768 2768 M: Andreas Klinger <ak@it-klinger.de> 2769 2769 L: linux-iio@vger.kernel.org 2770 2770 S: Maintained 2771 2771 - F: Documentation/devicetree/bindings/iio/adc/avia-hx711.txt 2771 2771 + F: Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml 2772 2772 F: drivers/iio/adc/hx711.c 2773 2773 2774 2774 AX.25 NETWORK LAYER ··· 14351 14351 M: Hans de Goede <hdegoede@redhat.com> 14352 14352 L: linux-fbdev@vger.kernel.org 14353 14353 S: Maintained 14354 14354 - F: Documentation/devicetree/bindings/display/simple-framebuffer.txt 14354 14354 + F: Documentation/devicetree/bindings/display/simple-framebuffer.yaml 14355 14355 F: drivers/video/fbdev/simplefb.c 14356 14356 F: include/linux/platform_data/simplefb.h 14357 14357

+1 -1

scripts/Makefile.lib

reviewed

··· 298 298 DT_TMP_SCHEMA := $(objtree)/$(DT_BINDING_DIR)/processed-schema.yaml 299 299 300 300 quiet_cmd_dtb_check = CHECK $@ 301 301 - cmd_dtb_check = $(DT_CHECKER) -p $(DT_TMP_SCHEMA) $@ ; 301 301 + cmd_dtb_check = $(DT_CHECKER) -u $(srctree)/$(DT_BINDING_DIR) -p $(DT_TMP_SCHEMA) $@ ; 302 302 303 303 define rule_dtc_dt_yaml 304 304 $(call cmd_and_fixdep,dtc,yaml)

+2 -2

scripts/checkpatch.pl

reviewed

··· 3027 3027 my @compats = $rawline =~ /\"([a-zA-Z0-9\-\,\.\+_]+)\"/g; 3028 3028 3029 3029 my $dt_path = $root . "/Documentation/devicetree/bindings/"; 3030 3030 - my $vp_file = $dt_path . "vendor-prefixes.txt"; 3030 3030 + my $vp_file = $dt_path . "vendor-prefixes.yaml"; 3031 3031 3032 3032 foreach my $compat (@compats) { 3033 3033 my $compat2 = $compat; ··· 3042 3042 3043 3043 next if $compat !~ /^([a-zA-Z0-9\-]+)\,/; 3044 3044 my $vendor = $1; 3045 3045 - `grep -Eq "^$vendor\\b" $vp_file`; 3045 3045 + `grep -Eq "\\"\\^\Q$vendor\E,\\.\\*\\":" $vp_file`; 3046 3046 if ( $? >> 8 ) { 3047 3047 WARN("UNDOCUMENTED_DT_STRING", 3048 3048 "DT compatible string vendor \"$vendor\" appears un-documented -- check $vp_file\n" . $herecurr);