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crypto: qat - fix firmware loading failure for GEN6 devices

QAT GEN6 hardware requires a minimum 3 us delay during the acceleration
engine reset sequence to ensure the hardware fully settles.
Without this delay, the firmware load may fail intermittently.

Add a delay after placing the AE into reset and before clearing the reset,
matching the hardware requirements and ensuring stable firmware loading.
Earlier generations remain unaffected.

Fixes: 17fd7514ae68 ("crypto: qat - add qat_6xxx driver")
Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Suman Kumar Chakraborty and committed by
Herbert Xu e7dcb722 4963b39e

+12 -1
+7
drivers/crypto/intel/qat/qat_common/adf_accel_engine.c
··· 1 1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) 2 2 /* Copyright(c) 2014 - 2020 Intel Corporation */ 3 + #include <linux/delay.h> 3 4 #include <linux/firmware.h> 4 5 #include <linux/pci.h> 5 6 #include "adf_cfg.h" ··· 163 162 static int adf_ae_reset(struct adf_accel_dev *accel_dev, int ae) 164 163 { 165 164 struct adf_fw_loader_data *loader_data = accel_dev->fw_loader; 165 + unsigned long reset_delay; 166 166 167 167 qat_hal_reset(loader_data->fw_loader); 168 + 169 + reset_delay = loader_data->fw_loader->chip_info->reset_delay_us; 170 + if (reset_delay) 171 + fsleep(reset_delay); 172 + 168 173 if (qat_hal_clr_reset(loader_data->fw_loader)) 169 174 return -EFAULT; 170 175
+1
drivers/crypto/intel/qat/qat_common/icp_qat_fw_loader_handle.h
··· 27 27 int mmp_sram_size; 28 28 bool nn; 29 29 bool lm2lm3; 30 + u16 reset_delay_us; 30 31 u32 lm_size; 31 32 u32 icp_rst_csr; 32 33 u32 icp_rst_mask;
+4 -1
drivers/crypto/intel/qat/qat_common/qat_hal.c
··· 20 20 #define RST_CSR_QAT_LSB 20 21 21 #define RST_CSR_AE_LSB 0 22 22 #define MC_TIMESTAMP_ENABLE (0x1 << 7) 23 + #define MIN_RESET_DELAY_US 3 23 24 24 25 #define IGNORE_W1C_MASK ((~(1 << CE_BREAKPOINT_BITPOS)) & \ 25 26 (~(1 << CE_CNTL_STORE_PARITY_ERROR_BITPOS)) & \ ··· 714 713 handle->chip_info->wakeup_event_val = 0x80000000; 715 714 handle->chip_info->fw_auth = true; 716 715 handle->chip_info->css_3k = true; 717 - if (handle->pci_dev->device == PCI_DEVICE_ID_INTEL_QAT_6XXX) 716 + if (handle->pci_dev->device == PCI_DEVICE_ID_INTEL_QAT_6XXX) { 718 717 handle->chip_info->dual_sign = true; 718 + handle->chip_info->reset_delay_us = MIN_RESET_DELAY_US; 719 + } 719 720 handle->chip_info->tgroup_share_ustore = true; 720 721 handle->chip_info->fcu_ctl_csr = FCU_CONTROL_4XXX; 721 722 handle->chip_info->fcu_sts_csr = FCU_STATUS_4XXX;