tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2025-11-08' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
"Back from travel, thanks to Simona for handling things. regular fixes,
seems about the right size, but spread out a bit.

amdgpu has the usual range of fixes, xe has a few fixes, and nouveau
has a couple of fixes, one for blackwell modifiers on 8/16 bit
surfaces.

Otherwise a few small fixes for mediatek, sched, imagination and
pixpaper.

sched:
- Fix deadlock

amdgpu:
- Reset fixes
- Misc fixes
- Panel scaling fixes
- HDMI fix
- S0ix fixes
- Hibernation fix
- Secure display fix
- Suspend fix
- MST fix

amdkfd:
- Process cleanup fix

xe:
- Fix missing synchronization on unbind
- Fix device shutdown when doing FLR
- Fix user fence signaling order

i915:
- Avoid lock inversion when pinning to GGTT on CHV/BXT+VTD
- Fix conversion between clock ticks and nanoseconds

mediatek:
- Disable AFBC support on Mediatek DRM driver
- Add pm_runtime support for GCE power control

imagination:
- kconfig: Fix dependencies

nouveau:
- Set DMA mask earlier
- Advertize correct modifiers for GB20x

pixpaper:
- kconfig: Fix dependencies"

* tag 'drm-fixes-2025-11-08' of https://gitlab.freedesktop.org/drm/kernel: (26 commits)
drm/xe: Enforce correct user fence signaling order using
drm/xe: Do clean shutdown also when using flr
drm/xe: Move declarations under conditional branch
drm/xe/guc: Synchronize Dead CT worker with unbind
drm/amd/display: Enable mst when it's detected but yet to be initialized
drm/amdgpu: Fix wait after reset sequence in S3
drm/amd: Fix suspend failure with secure display TA
drm/amdgpu: fix gpu page fault after hibernation on PF passthrough
drm/tiny: pixpaper: add explicit dependency on MMU
drm/nouveau: Advertise correct modifiers on GB20x
drm: define NVIDIA DRM format modifiers for GB20x
drm/nouveau: set DMA mask before creating the flush page
drm/sched: Fix deadlock in drm_sched_entity_kill_jobs_cb
drm/amd/display: Fix NULL deref in debugfs odm_combine_segments
drm/amdkfd: Don't clear PT after process killed
drm/amdgpu/smu: Handle S0ix for vangogh
drm/amdgpu: Drop PMFW RLC notifier from amdgpu_device_suspend()
drm/amd/display: Fix black screen with HDMI outputs
drm/amd/display: Don't stretch non-native images by default in eDP
drm/amd/pm: fix missing device_attr cleanup in amdgpu_pm_sysfs_init()
...

Linus Torvalds e811c33b 38a2c275

+311 -125
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
··· 1267 1267 1268 1268 (void)amdgpu_vm_bo_unmap(adev, bo_va, entry->va); 1269 1269 1270 + /* VM entity stopped if process killed, don't clear freed pt bo */ 1271 + if (!amdgpu_vm_ready(vm)) 1272 + return 0; 1273 + 1270 1274 (void)amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update); 1271 1275 1272 1276 (void)amdgpu_sync_fence(sync, bo_va->last_pt_update, GFP_KERNEL);
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 5243 5243 if (amdgpu_sriov_vf(adev)) 5244 5244 amdgpu_virt_release_full_gpu(adev, false); 5245 5245 5246 - r = amdgpu_dpm_notify_rlc_state(adev, false); 5247 - if (r) 5248 - return r; 5249 - 5250 5246 return 0; 5251 5247 } 5252 5248
+7 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 2632 2632 { 2633 2633 struct drm_device *drm_dev = dev_get_drvdata(dev); 2634 2634 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2635 + int r; 2635 2636 2636 - if (amdgpu_acpi_should_gpu_reset(adev)) 2637 - return amdgpu_asic_reset(adev); 2637 + if (amdgpu_acpi_should_gpu_reset(adev)) { 2638 + amdgpu_device_lock_reset_domain(adev->reset_domain); 2639 + r = amdgpu_asic_reset(adev); 2640 + amdgpu_device_unlock_reset_domain(adev->reset_domain); 2641 + return r; 2642 + } 2638 2643 2639 2644 return 0; 2640 2645 }
+4 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
··· 2355 2355 if (!ret && !psp->securedisplay_context.context.resp_status) { 2356 2356 psp->securedisplay_context.context.initialized = true; 2357 2357 mutex_init(&psp->securedisplay_context.mutex); 2358 - } else 2358 + } else { 2359 + /* don't try again */ 2360 + psp->securedisplay_context.context.bin_desc.size_bytes = 0; 2359 2361 return ret; 2362 + } 2360 2363 2361 2364 mutex_lock(&psp->securedisplay_context.mutex); 2362 2365
+2 -1
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
··· 407 407 return -EINVAL; 408 408 } 409 409 410 - if (adev->kfd.init_complete && !amdgpu_in_reset(adev)) 410 + if (adev->kfd.init_complete && !amdgpu_in_reset(adev) && 411 + !adev->in_suspend) 411 412 flags |= AMDGPU_XCP_OPS_KFD; 412 413 413 414 if (flags & AMDGPU_XCP_OPS_KFD) {
+5
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
··· 3102 3102 return r; 3103 3103 } 3104 3104 3105 + adev->gfx.gfx_supported_reset = 3106 + amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 3107 + adev->gfx.compute_supported_reset = 3108 + amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 3109 + 3105 3110 return r; 3106 3111 } 3107 3112
+5
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
··· 4399 4399 4400 4400 gfx_v7_0_gpu_early_init(adev); 4401 4401 4402 + adev->gfx.gfx_supported_reset = 4403 + amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 4404 + adev->gfx.compute_supported_reset = 4405 + amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 4406 + 4402 4407 return r; 4403 4408 } 4404 4409
+5
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
··· 2023 2023 if (r) 2024 2024 return r; 2025 2025 2026 + adev->gfx.gfx_supported_reset = 2027 + amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); 2028 + adev->gfx.compute_supported_reset = 2029 + amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 2030 + 2026 2031 return 0; 2027 2032 } 2028 2033
+3 -1
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
··· 2292 2292 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2293 2293 2294 2294 } else { 2295 - if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2295 + if (adev->in_suspend) 2296 + amdgpu_xcp_restore_partition_mode(adev->xcp_mgr); 2297 + else if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2296 2298 AMDGPU_XCP_FL_NONE) == 2297 2299 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2298 2300 r = amdgpu_xcp_switch_partition_mode(
+25 -1
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
··· 142 142 return err; 143 143 } 144 144 145 + static int psp_v11_wait_for_tos_unload(struct psp_context *psp) 146 + { 147 + struct amdgpu_device *adev = psp->adev; 148 + uint32_t sol_reg1, sol_reg2; 149 + int retry_loop; 150 + 151 + /* Wait for the TOS to be unloaded */ 152 + for (retry_loop = 0; retry_loop < 20; retry_loop++) { 153 + sol_reg1 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 154 + usleep_range(1000, 2000); 155 + sol_reg2 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 156 + if (sol_reg1 == sol_reg2) 157 + return 0; 158 + } 159 + dev_err(adev->dev, "TOS unload failed, C2PMSG_33: %x C2PMSG_81: %x", 160 + RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_33), 161 + RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81)); 162 + 163 + return -ETIME; 164 + } 165 + 145 166 static int psp_v11_0_wait_for_bootloader(struct psp_context *psp) 146 167 { 147 168 struct amdgpu_device *adev = psp->adev; 148 - 149 169 int ret; 150 170 int retry_loop; 171 + 172 + /* For a reset done at the end of S3, only wait for TOS to be unloaded */ 173 + if (adev->in_s3 && !(adev->flags & AMD_IS_APU) && amdgpu_in_reset(adev)) 174 + return psp_v11_wait_for_tos_unload(psp); 151 175 152 176 for (retry_loop = 0; retry_loop < 20; retry_loop++) { 153 177 /* Wait for bootloader to signify that is
+10 -2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 3563 3563 /* Do mst topology probing after resuming cached state*/ 3564 3564 drm_connector_list_iter_begin(ddev, &iter); 3565 3565 drm_for_each_connector_iter(connector, &iter) { 3566 + bool init = false; 3566 3567 3567 3568 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3568 3569 continue; ··· 3573 3572 aconnector->mst_root) 3574 3573 continue; 3575 3574 3576 - drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr); 3575 + scoped_guard(mutex, &aconnector->mst_mgr.lock) { 3576 + init = !aconnector->mst_mgr.mst_primary; 3577 + } 3578 + if (init) 3579 + dm_helpers_dp_mst_start_top_mgr(aconnector->dc_link->ctx, 3580 + aconnector->dc_link, false); 3581 + else 3582 + drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr); 3577 3583 } 3578 3584 drm_connector_list_iter_end(&iter); 3579 3585 ··· 8038 8030 "mode %dx%d@%dHz is not native, enabling scaling\n", 8039 8031 adjusted_mode->hdisplay, adjusted_mode->vdisplay, 8040 8032 drm_mode_vrefresh(adjusted_mode)); 8041 - dm_new_connector_state->scaling = RMX_FULL; 8033 + dm_new_connector_state->scaling = RMX_ASPECT; 8042 8034 } 8043 8035 return 0; 8044 8036 }
+2 -1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
··· 1302 1302 if (connector->status != connector_status_connected) 1303 1303 return -ENODEV; 1304 1304 1305 - if (pipe_ctx != NULL && pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments) 1305 + if (pipe_ctx && pipe_ctx->stream_res.tg && 1306 + pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments) 1306 1307 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments); 1307 1308 1308 1309 seq_printf(m, "%d\n", segments);
-18
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
··· 195 195 return ret; 196 196 } 197 197 198 - int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en) 199 - { 200 - int ret = 0; 201 - const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 202 - 203 - if (pp_funcs && pp_funcs->notify_rlc_state) { 204 - mutex_lock(&adev->pm.mutex); 205 - 206 - ret = pp_funcs->notify_rlc_state( 207 - adev->powerplay.pp_handle, 208 - en); 209 - 210 - mutex_unlock(&adev->pm.mutex); 211 - } 212 - 213 - return ret; 214 - } 215 - 216 198 int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) 217 199 { 218 200 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+2 -2
drivers/gpu/drm/amd/pm/amdgpu_pm.c
··· 4724 4724 ret = devm_device_add_group(adev->dev, 4725 4725 &amdgpu_pm_policy_attr_group); 4726 4726 if (ret) 4727 - goto err_out0; 4727 + goto err_out1; 4728 4728 } 4729 4729 4730 4730 if (amdgpu_dpm_is_temp_metrics_supported(adev, SMU_TEMP_METRIC_GPUBOARD)) { 4731 4731 ret = devm_device_add_group(adev->dev, 4732 4732 &amdgpu_board_attr_group); 4733 4733 if (ret) 4734 - goto err_out0; 4734 + goto err_out1; 4735 4735 if (amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT, 4736 4736 (void *)&tmp) != -EOPNOTSUPP) { 4737 4737 sysfs_add_file_to_group(&adev->dev->kobj,
-2
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
··· 424 424 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 425 425 enum pp_mp1_state mp1_state); 426 426 427 - int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en); 428 - 429 427 int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev); 430 428 431 429 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev);
+6
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
··· 2040 2040 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 2041 2041 return 0; 2042 2042 2043 + /* vangogh s0ix */ 2044 + if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) || 2045 + amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2)) && 2046 + adev->in_s0ix) 2047 + return 0; 2048 + 2043 2049 /* 2044 2050 * For gpu reset, runpm and hibernation through BACO, 2045 2051 * BACO feature has to be kept enabled.
+3
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
··· 2217 2217 uint32_t total_cu = adev->gfx.config.max_cu_per_sh * 2218 2218 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; 2219 2219 2220 + if (adev->in_s0ix) 2221 + return 0; 2222 + 2220 2223 /* allow message will be sent after enable message on Vangogh*/ 2221 2224 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 2222 2225 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
+2 -2
drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
··· 205 205 206 206 u64 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u64 count) 207 207 { 208 - return div_u64_roundup(count * NSEC_PER_SEC, gt->clock_frequency); 208 + return mul_u64_u32_div(count, NSEC_PER_SEC, gt->clock_frequency); 209 209 } 210 210 211 211 u64 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u64 count) ··· 215 215 216 216 u64 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u64 ns) 217 217 { 218 - return div_u64_roundup(gt->clock_frequency * ns, NSEC_PER_SEC); 218 + return mul_u64_u32_div(ns, gt->clock_frequency, NSEC_PER_SEC); 219 219 } 220 220 221 221 u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns)
+14 -2
drivers/gpu/drm/i915/i915_vma.c
··· 1595 1595 err_vma_res: 1596 1596 i915_vma_resource_free(vma_res); 1597 1597 err_fence: 1598 - if (work) 1599 - dma_fence_work_commit_imm(&work->base); 1598 + if (work) { 1599 + /* 1600 + * When pinning VMA to GGTT on CHV or BXT with VTD enabled, 1601 + * commit VMA binding asynchronously to avoid risk of lock 1602 + * inversion among reservation_ww locks held here and 1603 + * cpu_hotplug_lock acquired from stop_machine(), which we 1604 + * wrap around GGTT updates when running in those environments. 1605 + */ 1606 + if (i915_vma_is_ggtt(vma) && 1607 + intel_vm_no_concurrent_access_wa(vma->vm->i915)) 1608 + dma_fence_work_commit(&work->base); 1609 + else 1610 + dma_fence_work_commit_imm(&work->base); 1611 + } 1600 1612 err_rpm: 1601 1613 intel_runtime_pm_put(&vma->vm->i915->runtime_pm, wakeref); 1602 1614
+1
drivers/gpu/drm/imagination/Kconfig
··· 7 7 depends on DRM 8 8 depends on MMU 9 9 depends on PM 10 + depends on POWER_SEQUENCING || !POWER_SEQUENCING 10 11 select DRM_EXEC 11 12 select DRM_GEM_SHMEM_HELPER 12 13 select DRM_SCHED
+7
drivers/gpu/drm/mediatek/mtk_crtc.c
··· 283 283 unsigned int i; 284 284 unsigned long flags; 285 285 286 + /* release GCE HW usage and start autosuspend */ 287 + pm_runtime_mark_last_busy(cmdq_cl->chan->mbox->dev); 288 + pm_runtime_put_autosuspend(cmdq_cl->chan->mbox->dev); 289 + 286 290 if (data->sta < 0) 287 291 return; 288 292 ··· 621 617 spin_lock_irqsave(&mtk_crtc->config_lock, flags); 622 618 mtk_crtc->config_updating = false; 623 619 spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); 620 + 621 + if (pm_runtime_resume_and_get(mtk_crtc->cmdq_client.chan->mbox->dev) < 0) 622 + goto update_config_out; 624 623 625 624 mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle); 626 625 mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0);
+1 -23
drivers/gpu/drm/mediatek/mtk_plane.c
··· 21 21 22 22 static const u64 modifiers[] = { 23 23 DRM_FORMAT_MOD_LINEAR, 24 - DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | 25 - AFBC_FORMAT_MOD_SPLIT | 26 - AFBC_FORMAT_MOD_SPARSE), 27 24 DRM_FORMAT_MOD_INVALID, 28 25 }; 29 26 ··· 68 71 uint32_t format, 69 72 uint64_t modifier) 70 73 { 71 - if (modifier == DRM_FORMAT_MOD_LINEAR) 72 - return true; 73 - 74 - if (modifier != DRM_FORMAT_MOD_ARM_AFBC( 75 - AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | 76 - AFBC_FORMAT_MOD_SPLIT | 77 - AFBC_FORMAT_MOD_SPARSE)) 78 - return false; 79 - 80 - if (format != DRM_FORMAT_XRGB8888 && 81 - format != DRM_FORMAT_ARGB8888 && 82 - format != DRM_FORMAT_BGRX8888 && 83 - format != DRM_FORMAT_BGRA8888 && 84 - format != DRM_FORMAT_ABGR8888 && 85 - format != DRM_FORMAT_XBGR8888 && 86 - format != DRM_FORMAT_RGB888 && 87 - format != DRM_FORMAT_BGR888) 88 - return false; 89 - 90 - return true; 74 + return modifier == DRM_FORMAT_MOD_LINEAR; 91 75 } 92 76 93 77 static void mtk_plane_destroy_state(struct drm_plane *plane,
+3 -1
drivers/gpu/drm/nouveau/dispnv50/disp.c
··· 2867 2867 } 2868 2868 2869 2869 /* Assign the correct format modifiers */ 2870 - if (disp->disp->object.oclass >= TU102_DISP) 2870 + if (disp->disp->object.oclass >= GB202_DISP) 2871 + nouveau_display(dev)->format_modifiers = wndwca7e_modifiers; 2872 + else if (disp->disp->object.oclass >= TU102_DISP) 2871 2873 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers; 2872 2874 else 2873 2875 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
+1
drivers/gpu/drm/nouveau/dispnv50/disp.h
··· 104 104 extern const u64 disp50xx_modifiers[]; 105 105 extern const u64 disp90xx_modifiers[]; 106 106 extern const u64 wndwc57e_modifiers[]; 107 + extern const u64 wndwca7e_modifiers[]; 107 108 #endif
+22 -2
drivers/gpu/drm/nouveau/dispnv50/wndw.c
··· 786 786 } 787 787 788 788 /* This function assumes the format has already been validated against the plane 789 - * and the modifier was validated against the device-wides modifier list at FB 789 + * and the modifier was validated against the device-wide modifier list at FB 790 790 * creation time. 791 791 */ 792 792 static bool nv50_plane_format_mod_supported(struct drm_plane *plane, 793 793 u32 format, u64 modifier) 794 794 { 795 795 struct nouveau_drm *drm = nouveau_drm(plane->dev); 796 + const struct drm_format_info *info = drm_format_info(format); 796 797 uint8_t i; 797 798 798 799 /* All chipsets can display all formats in linear layout */ ··· 801 800 return true; 802 801 803 802 if (drm->client.device.info.chipset < 0xc0) { 804 - const struct drm_format_info *info = drm_format_info(format); 805 803 const uint8_t kind = (modifier >> 12) & 0xff; 806 804 807 805 if (!format) return false; 808 806 809 807 for (i = 0; i < info->num_planes; i++) 810 808 if ((info->cpp[i] != 4) && kind != 0x70) return false; 809 + } else if (drm->client.device.info.chipset >= 0x1b2) { 810 + const uint8_t slayout = ((modifier >> 22) & 0x1) | 811 + ((modifier >> 25) & 0x6); 812 + 813 + if (!format) 814 + return false; 815 + 816 + /* 817 + * Note in practice this implies only formats where cpp is equal 818 + * for each plane, or >= 4 for all planes, are supported. 819 + */ 820 + for (i = 0; i < info->num_planes; i++) { 821 + if (((info->cpp[i] == 2) && slayout != 3) || 822 + ((info->cpp[i] == 1) && slayout != 2) || 823 + ((info->cpp[i] >= 4) && slayout != 1)) 824 + return false; 825 + 826 + /* 24-bit not supported. It has yet another layout */ 827 + WARN_ON(info->cpp[i] == 3); 828 + } 811 829 } 812 830 813 831 return true;
+33
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
··· 179 179 return 0; 180 180 } 181 181 182 + /**************************************************************** 183 + * Log2(block height) ----------------------------+ * 184 + * Page Kind ----------------------------------+ | * 185 + * Gob Height/Page Kind Generation ------+ | | * 186 + * Sector layout -------+ | | | * 187 + * Compression ------+ | | | | */ 188 + const u64 wndwca7e_modifiers[] = { /* | | | | | */ 189 + /* 4cpp+ modifiers */ 190 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 0), 191 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 1), 192 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 2), 193 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 3), 194 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 4), 195 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 5), 196 + /* 1cpp/8bpp modifiers */ 197 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 0), 198 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 1), 199 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 2), 200 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 3), 201 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 4), 202 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 2, 2, 0x06, 5), 203 + /* 2cpp/16bpp modifiers */ 204 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 0), 205 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 1), 206 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 2), 207 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 3), 208 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 4), 209 + DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 3, 2, 0x06, 5), 210 + /* All formats support linear */ 211 + DRM_FORMAT_MOD_LINEAR, 212 + DRM_FORMAT_MOD_INVALID 213 + }; 214 + 182 215 static const struct nv50_wndw_func 183 216 wndwca7e = { 184 217 .acquire = wndwc37e_acquire,
+12 -12
drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c
··· 1695 1695 *pdevice = &pdev->device; 1696 1696 pdev->pdev = pci_dev; 1697 1697 1698 + /* Set DMA mask based on capabilities reported by the MMU subdev. */ 1699 + if (pdev->device.mmu && !pdev->device.pci->agp.bridge) 1700 + bits = pdev->device.mmu->dma_bits; 1701 + else 1702 + bits = 32; 1703 + 1704 + ret = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(bits)); 1705 + if (ret && bits != 32) { 1706 + dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32)); 1707 + pdev->device.mmu->dma_bits = 32; 1708 + } 1709 + 1698 1710 ret = nvkm_device_ctor(&nvkm_device_pci_func, quirk, &pci_dev->dev, 1699 1711 pci_is_pcie(pci_dev) ? NVKM_DEVICE_PCIE : 1700 1712 pci_find_capability(pci_dev, PCI_CAP_ID_AGP) ? ··· 1719 1707 1720 1708 if (ret) 1721 1709 return ret; 1722 - 1723 - /* Set DMA mask based on capabilities reported by the MMU subdev. */ 1724 - if (pdev->device.mmu && !pdev->device.pci->agp.bridge) 1725 - bits = pdev->device.mmu->dma_bits; 1726 - else 1727 - bits = 32; 1728 - 1729 - ret = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(bits)); 1730 - if (ret && bits != 32) { 1731 - dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32)); 1732 - pdev->device.mmu->dma_bits = 32; 1733 - } 1734 1710 1735 1711 return 0; 1736 1712 }
+19 -15
drivers/gpu/drm/scheduler/sched_entity.c
··· 173 173 } 174 174 EXPORT_SYMBOL(drm_sched_entity_error); 175 175 176 + static void drm_sched_entity_kill_jobs_cb(struct dma_fence *f, 177 + struct dma_fence_cb *cb); 178 + 176 179 static void drm_sched_entity_kill_jobs_work(struct work_struct *wrk) 177 180 { 178 181 struct drm_sched_job *job = container_of(wrk, typeof(*job), work); 179 - 180 - drm_sched_fence_scheduled(job->s_fence, NULL); 181 - drm_sched_fence_finished(job->s_fence, -ESRCH); 182 - WARN_ON(job->s_fence->parent); 183 - job->sched->ops->free_job(job); 184 - } 185 - 186 - /* Signal the scheduler finished fence when the entity in question is killed. */ 187 - static void drm_sched_entity_kill_jobs_cb(struct dma_fence *f, 188 - struct dma_fence_cb *cb) 189 - { 190 - struct drm_sched_job *job = container_of(cb, struct drm_sched_job, 191 - finish_cb); 182 + struct dma_fence *f; 192 183 unsigned long index; 193 - 194 - dma_fence_put(f); 195 184 196 185 /* Wait for all dependencies to avoid data corruptions */ 197 186 xa_for_each(&job->dependencies, index, f) { ··· 208 219 209 220 dma_fence_put(f); 210 221 } 222 + 223 + drm_sched_fence_scheduled(job->s_fence, NULL); 224 + drm_sched_fence_finished(job->s_fence, -ESRCH); 225 + WARN_ON(job->s_fence->parent); 226 + job->sched->ops->free_job(job); 227 + } 228 + 229 + /* Signal the scheduler finished fence when the entity in question is killed. */ 230 + static void drm_sched_entity_kill_jobs_cb(struct dma_fence *f, 231 + struct dma_fence_cb *cb) 232 + { 233 + struct drm_sched_job *job = container_of(cb, struct drm_sched_job, 234 + finish_cb); 235 + 236 + dma_fence_put(f); 211 237 212 238 INIT_WORK(&job->work, drm_sched_entity_kill_jobs_work); 213 239 schedule_work(&job->work);
+1
drivers/gpu/drm/tiny/Kconfig
··· 85 85 config DRM_PIXPAPER 86 86 tristate "DRM support for PIXPAPER display panels" 87 87 depends on DRM && SPI 88 + depends on MMU 88 89 select DRM_CLIENT_SELECTION 89 90 select DRM_GEM_SHMEM_HELPER 90 91 select DRM_KMS_HELPER
+7 -7
drivers/gpu/drm/xe/xe_device.c
··· 988 988 989 989 drm_dbg(&xe->drm, "Shutting down device\n"); 990 990 991 - if (xe_driver_flr_disabled(xe)) { 992 - xe_display_pm_shutdown(xe); 991 + xe_display_pm_shutdown(xe); 993 992 994 - xe_irq_suspend(xe); 993 + xe_irq_suspend(xe); 995 994 996 - for_each_gt(gt, xe, id) 997 - xe_gt_shutdown(gt); 995 + for_each_gt(gt, xe, id) 996 + xe_gt_shutdown(gt); 998 997 999 - xe_display_pm_shutdown_late(xe); 1000 - } else { 998 + xe_display_pm_shutdown_late(xe); 999 + 1000 + if (!xe_driver_flr_disabled(xe)) { 1001 1001 /* BOOM! */ 1002 1002 __xe_driver_flr(xe); 1003 1003 }
+2 -1
drivers/gpu/drm/xe/xe_exec.c
··· 165 165 166 166 for (num_syncs = 0; num_syncs < args->num_syncs; num_syncs++) { 167 167 err = xe_sync_entry_parse(xe, xef, &syncs[num_syncs], 168 - &syncs_user[num_syncs], SYNC_PARSE_FLAG_EXEC | 168 + &syncs_user[num_syncs], NULL, 0, 169 + SYNC_PARSE_FLAG_EXEC | 169 170 (xe_vm_in_lr_mode(vm) ? 170 171 SYNC_PARSE_FLAG_LR_MODE : 0)); 171 172 if (err)
+14
drivers/gpu/drm/xe/xe_exec_queue.c
··· 10 10 #include <drm/drm_device.h> 11 11 #include <drm/drm_drv.h> 12 12 #include <drm/drm_file.h> 13 + #include <drm/drm_syncobj.h> 13 14 #include <uapi/drm/xe_drm.h> 14 15 15 16 #include "xe_dep_scheduler.h" ··· 325 324 } 326 325 xe_vm_put(migrate_vm); 327 326 327 + if (!IS_ERR(q)) { 328 + int err = drm_syncobj_create(&q->ufence_syncobj, 329 + DRM_SYNCOBJ_CREATE_SIGNALED, 330 + NULL); 331 + if (err) { 332 + xe_exec_queue_put(q); 333 + return ERR_PTR(err); 334 + } 335 + } 336 + 328 337 return q; 329 338 } 330 339 ALLOW_ERROR_INJECTION(xe_exec_queue_create_bind, ERRNO); ··· 343 332 { 344 333 struct xe_exec_queue *q = container_of(ref, struct xe_exec_queue, refcount); 345 334 struct xe_exec_queue *eq, *next; 335 + 336 + if (q->ufence_syncobj) 337 + drm_syncobj_put(q->ufence_syncobj); 346 338 347 339 if (xe_exec_queue_uses_pxp(q)) 348 340 xe_pxp_exec_queue_remove(gt_to_xe(q->gt)->pxp, q);
+7
drivers/gpu/drm/xe/xe_exec_queue_types.h
··· 15 15 #include "xe_hw_fence_types.h" 16 16 #include "xe_lrc_types.h" 17 17 18 + struct drm_syncobj; 18 19 struct xe_execlist_exec_queue; 19 20 struct xe_gt; 20 21 struct xe_guc_exec_queue; ··· 155 154 /** @pxp.link: link into the list of PXP exec queues */ 156 155 struct list_head link; 157 156 } pxp; 157 + 158 + /** @ufence_syncobj: User fence syncobj */ 159 + struct drm_syncobj *ufence_syncobj; 160 + 161 + /** @ufence_timeline_value: User fence timeline value */ 162 + u64 ufence_timeline_value; 158 163 159 164 /** @ops: submission backend exec queue operations */ 160 165 const struct xe_exec_queue_ops *ops;
+3
drivers/gpu/drm/xe/xe_guc_ct.c
··· 200 200 { 201 201 struct xe_guc_ct *ct = arg; 202 202 203 + #if IS_ENABLED(CONFIG_DRM_XE_DEBUG) 204 + cancel_work_sync(&ct->dead.worker); 205 + #endif 203 206 ct_exit_safe_mode(ct); 204 207 destroy_workqueue(ct->g2h_wq); 205 208 xa_destroy(&ct->fence_lookup);
+30 -15
drivers/gpu/drm/xe/xe_oa.c
··· 10 10 11 11 #include <drm/drm_drv.h> 12 12 #include <drm/drm_managed.h> 13 + #include <drm/drm_syncobj.h> 13 14 #include <uapi/drm/xe_drm.h> 14 15 15 16 #include <generated/xe_wa_oob.h> ··· 1390 1389 return 0; 1391 1390 } 1392 1391 1393 - static int xe_oa_parse_syncs(struct xe_oa *oa, struct xe_oa_open_param *param) 1392 + static int xe_oa_parse_syncs(struct xe_oa *oa, 1393 + struct xe_oa_stream *stream, 1394 + struct xe_oa_open_param *param) 1394 1395 { 1395 1396 int ret, num_syncs, num_ufence = 0; 1396 1397 ··· 1412 1409 1413 1410 for (num_syncs = 0; num_syncs < param->num_syncs; num_syncs++) { 1414 1411 ret = xe_sync_entry_parse(oa->xe, param->xef, &param->syncs[num_syncs], 1415 - &param->syncs_user[num_syncs], 0); 1412 + &param->syncs_user[num_syncs], 1413 + stream->ufence_syncobj, 1414 + ++stream->ufence_timeline_value, 0); 1416 1415 if (ret) 1417 1416 goto err_syncs; 1418 1417 ··· 1544 1539 return -ENODEV; 1545 1540 1546 1541 param.xef = stream->xef; 1547 - err = xe_oa_parse_syncs(stream->oa, &param); 1542 + err = xe_oa_parse_syncs(stream->oa, stream, &param); 1548 1543 if (err) 1549 1544 goto err_config_put; 1550 1545 ··· 1640 1635 if (stream->exec_q) 1641 1636 xe_exec_queue_put(stream->exec_q); 1642 1637 1638 + drm_syncobj_put(stream->ufence_syncobj); 1643 1639 kfree(stream); 1644 1640 } 1645 1641 ··· 1832 1826 struct xe_oa_open_param *param) 1833 1827 { 1834 1828 struct xe_oa_stream *stream; 1829 + struct drm_syncobj *ufence_syncobj; 1835 1830 int stream_fd; 1836 1831 int ret; 1837 1832 ··· 1843 1836 goto exit; 1844 1837 } 1845 1838 1839 + ret = drm_syncobj_create(&ufence_syncobj, DRM_SYNCOBJ_CREATE_SIGNALED, 1840 + NULL); 1841 + if (ret) 1842 + goto exit; 1843 + 1846 1844 stream = kzalloc(sizeof(*stream), GFP_KERNEL); 1847 1845 if (!stream) { 1848 1846 ret = -ENOMEM; 1849 - goto exit; 1847 + goto err_syncobj; 1850 1848 } 1851 - 1849 + stream->ufence_syncobj = ufence_syncobj; 1852 1850 stream->oa = oa; 1853 - ret = xe_oa_stream_init(stream, param); 1851 + 1852 + ret = xe_oa_parse_syncs(oa, stream, param); 1854 1853 if (ret) 1855 1854 goto err_free; 1855 + 1856 + ret = xe_oa_stream_init(stream, param); 1857 + if (ret) { 1858 + while (param->num_syncs--) 1859 + xe_sync_entry_cleanup(&param->syncs[param->num_syncs]); 1860 + kfree(param->syncs); 1861 + goto err_free; 1862 + } 1856 1863 1857 1864 if (!param->disabled) { 1858 1865 ret = xe_oa_enable_locked(stream); ··· 1891 1870 xe_oa_stream_destroy(stream); 1892 1871 err_free: 1893 1872 kfree(stream); 1873 + err_syncobj: 1874 + drm_syncobj_put(ufence_syncobj); 1894 1875 exit: 1895 1876 return ret; 1896 1877 } ··· 2106 2083 goto err_exec_q; 2107 2084 } 2108 2085 2109 - ret = xe_oa_parse_syncs(oa, &param); 2110 - if (ret) 2111 - goto err_exec_q; 2112 - 2113 2086 mutex_lock(&param.hwe->gt->oa.gt_lock); 2114 2087 ret = xe_oa_stream_open_ioctl_locked(oa, &param); 2115 2088 mutex_unlock(&param.hwe->gt->oa.gt_lock); 2116 2089 if (ret < 0) 2117 - goto err_sync_cleanup; 2090 + goto err_exec_q; 2118 2091 2119 2092 return ret; 2120 2093 2121 - err_sync_cleanup: 2122 - while (param.num_syncs--) 2123 - xe_sync_entry_cleanup(&param.syncs[param.num_syncs]); 2124 - kfree(param.syncs); 2125 2094 err_exec_q: 2126 2095 if (param.exec_q) 2127 2096 xe_exec_queue_put(param.exec_q);
+8
drivers/gpu/drm/xe/xe_oa_types.h
··· 15 15 #include "regs/xe_reg_defs.h" 16 16 #include "xe_hw_engine_types.h" 17 17 18 + struct drm_syncobj; 19 + 18 20 #define DEFAULT_XE_OA_BUFFER_SIZE SZ_16M 19 21 20 22 enum xe_oa_report_header { ··· 249 247 250 248 /** @xef: xe_file with which the stream was opened */ 251 249 struct xe_file *xef; 250 + 251 + /** @ufence_syncobj: User fence syncobj */ 252 + struct drm_syncobj *ufence_syncobj; 253 + 254 + /** @ufence_timeline_value: User fence timeline value */ 255 + u64 ufence_timeline_value; 252 256 253 257 /** @last_fence: fence to use in stream destroy when needed */ 254 258 struct dma_fence *last_fence;
+15 -2
drivers/gpu/drm/xe/xe_sync.c
··· 113 113 int xe_sync_entry_parse(struct xe_device *xe, struct xe_file *xef, 114 114 struct xe_sync_entry *sync, 115 115 struct drm_xe_sync __user *sync_user, 116 + struct drm_syncobj *ufence_syncobj, 117 + u64 ufence_timeline_value, 116 118 unsigned int flags) 117 119 { 118 120 struct drm_xe_sync sync_in; ··· 194 192 if (exec) { 195 193 sync->addr = sync_in.addr; 196 194 } else { 195 + sync->ufence_timeline_value = ufence_timeline_value; 197 196 sync->ufence = user_fence_create(xe, sync_in.addr, 198 197 sync_in.timeline_value); 199 198 if (XE_IOCTL_DBG(xe, IS_ERR(sync->ufence))) 200 199 return PTR_ERR(sync->ufence); 200 + sync->ufence_chain_fence = dma_fence_chain_alloc(); 201 + if (!sync->ufence_chain_fence) 202 + return -ENOMEM; 203 + sync->ufence_syncobj = ufence_syncobj; 201 204 } 202 205 203 206 break; ··· 246 239 } else if (sync->ufence) { 247 240 int err; 248 241 249 - dma_fence_get(fence); 242 + drm_syncobj_add_point(sync->ufence_syncobj, 243 + sync->ufence_chain_fence, 244 + fence, sync->ufence_timeline_value); 245 + sync->ufence_chain_fence = NULL; 246 + 247 + fence = drm_syncobj_fence_get(sync->ufence_syncobj); 250 248 user_fence_get(sync->ufence); 251 249 err = dma_fence_add_callback(fence, &sync->ufence->cb, 252 250 user_fence_cb); ··· 271 259 drm_syncobj_put(sync->syncobj); 272 260 dma_fence_put(sync->fence); 273 261 dma_fence_chain_free(sync->chain_fence); 274 - if (sync->ufence) 262 + dma_fence_chain_free(sync->ufence_chain_fence); 263 + if (!IS_ERR_OR_NULL(sync->ufence)) 275 264 user_fence_put(sync->ufence); 276 265 } 277 266
+3
drivers/gpu/drm/xe/xe_sync.h
··· 8 8 9 9 #include "xe_sync_types.h" 10 10 11 + struct drm_syncobj; 11 12 struct xe_device; 12 13 struct xe_exec_queue; 13 14 struct xe_file; ··· 22 21 int xe_sync_entry_parse(struct xe_device *xe, struct xe_file *xef, 23 22 struct xe_sync_entry *sync, 24 23 struct drm_xe_sync __user *sync_user, 24 + struct drm_syncobj *ufence_syncobj, 25 + u64 ufence_timeline_value, 25 26 unsigned int flags); 26 27 int xe_sync_entry_add_deps(struct xe_sync_entry *sync, 27 28 struct xe_sched_job *job);
+3
drivers/gpu/drm/xe/xe_sync_types.h
··· 18 18 struct drm_syncobj *syncobj; 19 19 struct dma_fence *fence; 20 20 struct dma_fence_chain *chain_fence; 21 + struct dma_fence_chain *ufence_chain_fence; 22 + struct drm_syncobj *ufence_syncobj; 21 23 struct xe_user_fence *ufence; 22 24 u64 addr; 23 25 u64 timeline_value; 26 + u64 ufence_timeline_value; 24 27 u32 type; 25 28 u32 flags; 26 29 };
+4
drivers/gpu/drm/xe/xe_vm.c
··· 3606 3606 3607 3607 syncs_user = u64_to_user_ptr(args->syncs); 3608 3608 for (num_syncs = 0; num_syncs < args->num_syncs; num_syncs++) { 3609 + struct xe_exec_queue *__q = q ?: vm->q[0]; 3610 + 3609 3611 err = xe_sync_entry_parse(xe, xef, &syncs[num_syncs], 3610 3612 &syncs_user[num_syncs], 3613 + __q->ufence_syncobj, 3614 + ++__q->ufence_timeline_value, 3611 3615 (xe_vm_in_lr_mode(vm) ? 3612 3616 SYNC_PARSE_FLAG_LR_MODE : 0) | 3613 3617 (!args->num_binds ?
+15 -8
include/uapi/drm/drm_fourcc.h
··· 979 979 * 2 = Gob Height 8, Turing+ Page Kind mapping 980 980 * 3 = Reserved for future use. 981 981 * 982 - * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further 983 - * bit remapping step that occurs at an even lower level than the 984 - * page kind and block linear swizzles. This causes the layout of 985 - * surfaces mapped in those SOC's GPUs to be incompatible with the 986 - * equivalent mapping on other GPUs in the same system. 982 + * 22:22 s Sector layout. There is a further bit remapping step that occurs 983 + * 26:27 at an even lower level than the page kind and block linear 984 + * swizzles. This causes the bit arrangement of surfaces in memory 985 + * to differ subtly, and prevents direct sharing of surfaces between 986 + * GPUs with different layouts. 987 987 * 988 - * 0 = Tegra K1 - Tegra Parker/TX2 Layout. 989 - * 1 = Desktop GPU and Tegra Xavier+ Layout 988 + * 0 = Tegra K1 - Tegra Parker/TX2 Layout 989 + * 1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout 990 + * 2 = GB20x(Blackwell 2)+ 8 bpp surface layout 991 + * 3 = GB20x(Blackwell 2)+ 16 bpp surface layout 992 + * 4 = Reserved for future use. 993 + * 5 = Reserved for future use. 994 + * 6 = Reserved for future use. 995 + * 7 = Reserved for future use. 990 996 * 991 997 * 25:23 c Lossless Framebuffer Compression type. 992 998 * ··· 1007 1001 * 6 = Reserved for future use 1008 1002 * 7 = Reserved for future use 1009 1003 * 1010 - * 55:25 - Reserved for future use. Must be zero. 1004 + * 55:28 - Reserved for future use. Must be zero. 1011 1005 */ 1012 1006 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ 1013 1007 fourcc_mod_code(NVIDIA, (0x10 | \ ··· 1015 1009 (((k) & 0xff) << 12) | \ 1016 1010 (((g) & 0x3) << 20) | \ 1017 1011 (((s) & 0x1) << 22) | \ 1012 + (((s) & 0x6) << 25) | \ 1018 1013 (((c) & 0x7) << 23))) 1019 1014 1020 1015 /* To grandfather in prior block linear format modifiers to the above layout,