i3c: mipi-i3c-hci-pci: Add optional ability to manage child runtime PM

Some platforms implement the MIPI I3C HCI Multi-Bus Instance capability,
where a single parent device hosts multiple I3C controller instances. In
such designs, the parent - not the individual child instances - may need to
coordinate runtime PM so that all controllers runtime PM callbacks are
invoked in a controlled and synchronized manner.

For example, if the parent enables IBI-wakeup when transitioning into a
low-power state, every bus instance must remain able to receive IBIs up
until that point. This requires deferring the individual controllers'
runtime suspend callbacks (which disable bus activity) until the parent
decides it is safe for all instances to suspend together.

To support this usage model:

* Add runtime PM and system PM callbacks in the PCI driver to invoke
the mipi-i3c-hci driver's runtime PM callbacks for each instance.

* Introduce a driver-data flag, control_instance_pm, which opts into
the new parent-managed PM behaviour.

* Ensure the callbacks are only used when the corresponding instance is
operational at suspend time. This is reliable because the operational
state cannot change while the parent device is undergoing a PM
transition, and PCI always performs a runtime resume before system
suspend on current configurations, so that suspend and resume alternate
irrespective of whether it is runtime or system PM.

By that means, parent-managed runtime PM coordination for multi-instance
MIPI I3C HCI PCI devices is provided without altering existing behaviour on
platforms that do not require it.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260306085338.62955-5-adrian.hunter@intel.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

authored by

Adrian Hunter and committed by

Alexandre Belloni 2 months ago e813e7e3 82851828

+131

1 changed file

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drivers

i3c

master

mipi-i3c-hci

mipi-i3c-hci-pci.c

+131

drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c

··· 9 9 #include <linux/acpi.h> 10 10 #include <linux/bitfield.h> 11 11 #include <linux/debugfs.h> 12 + #include <linux/i3c/master.h> 12 13 #include <linux/idr.h> 13 14 #include <linux/iopoll.h> 14 15 #include <linux/kernel.h> ··· 21 20 #include <linux/pm_qos.h> 22 21 #include <linux/pm_runtime.h> 23 22 23 + #include "hci.h" 24 + 24 25 /* 25 26 * There can up to 15 instances, but implementations have at most 2 at this 26 27 * time. 27 28 */ 28 29 #define INST_MAX 2 29 30 31 + struct mipi_i3c_hci_pci_instance { 32 + struct device *dev; 33 + bool operational; 34 + }; 35 + 30 36 struct mipi_i3c_hci_pci { 31 37 struct pci_dev *pci; 32 38 void __iomem *base; 33 39 const struct mipi_i3c_hci_pci_info *info; 40 + struct mipi_i3c_hci_pci_instance instance[INST_MAX]; 34 41 void *private; 35 42 }; 36 43 ··· 49 40 int id[INST_MAX]; 50 41 u32 instance_offset[INST_MAX]; 51 42 int instance_count; 43 + bool control_instance_pm; 52 44 }; 53 45 54 46 #define INTEL_PRIV_OFFSET 0x2b0 ··· 220 210 .instance_count = 1, 221 211 }; 222 212 213 + static int mipi_i3c_hci_pci_find_instance(struct mipi_i3c_hci_pci *hci, struct device *dev) 214 + { 215 + for (int i = 0; i < INST_MAX; i++) { 216 + if (!hci->instance[i].dev) 217 + hci->instance[i].dev = dev; 218 + if (hci->instance[i].dev == dev) 219 + return i; 220 + } 221 + 222 + return -1; 223 + } 224 + 225 + #define HC_CONTROL 0x04 226 + #define HC_CONTROL_BUS_ENABLE BIT(31) 227 + 228 + static bool __mipi_i3c_hci_pci_is_operational(struct device *dev) 229 + { 230 + const struct mipi_i3c_hci_platform_data *pdata = dev->platform_data; 231 + u32 hc_control = readl(pdata->base_regs + HC_CONTROL); 232 + 233 + return hc_control & HC_CONTROL_BUS_ENABLE; 234 + } 235 + 236 + static bool mipi_i3c_hci_pci_is_operational(struct device *dev, bool update) 237 + { 238 + struct mipi_i3c_hci_pci *hci = dev_get_drvdata(dev->parent); 239 + int pos = mipi_i3c_hci_pci_find_instance(hci, dev); 240 + 241 + if (pos < 0) { 242 + dev_err(dev, "%s: I3C instance not found\n", __func__); 243 + return false; 244 + } 245 + 246 + if (update) 247 + hci->instance[pos].operational = __mipi_i3c_hci_pci_is_operational(dev); 248 + 249 + return hci->instance[pos].operational; 250 + } 251 + 252 + struct mipi_i3c_hci_pci_pm_data { 253 + struct device *dev[INST_MAX]; 254 + int dev_cnt; 255 + }; 256 + 257 + static bool mipi_i3c_hci_pci_is_mfd(struct device *dev) 258 + { 259 + return dev_is_platform(dev) && mfd_get_cell(to_platform_device(dev)); 260 + } 261 + 262 + static int mipi_i3c_hci_pci_suspend_instance(struct device *dev, void *data) 263 + { 264 + struct mipi_i3c_hci_pci_pm_data *pm_data = data; 265 + int ret; 266 + 267 + if (!mipi_i3c_hci_pci_is_mfd(dev) || 268 + !mipi_i3c_hci_pci_is_operational(dev, true)) 269 + return 0; 270 + 271 + ret = i3c_hci_rpm_suspend(dev); 272 + if (ret) 273 + return ret; 274 + 275 + pm_data->dev[pm_data->dev_cnt++] = dev; 276 + 277 + return 0; 278 + } 279 + 280 + static int mipi_i3c_hci_pci_resume_instance(struct device *dev, void *data) 281 + { 282 + struct mipi_i3c_hci_pci_pm_data *pm_data = data; 283 + int ret; 284 + 285 + if (!mipi_i3c_hci_pci_is_mfd(dev) || 286 + !mipi_i3c_hci_pci_is_operational(dev, false)) 287 + return 0; 288 + 289 + ret = i3c_hci_rpm_resume(dev); 290 + if (ret) 291 + return ret; 292 + 293 + pm_data->dev[pm_data->dev_cnt++] = dev; 294 + 295 + return 0; 296 + } 297 + 298 + static int mipi_i3c_hci_pci_suspend(struct device *dev) 299 + { 300 + struct mipi_i3c_hci_pci *hci = dev_get_drvdata(dev); 301 + struct mipi_i3c_hci_pci_pm_data pm_data = {}; 302 + int ret; 303 + 304 + if (!hci->info->control_instance_pm) 305 + return 0; 306 + 307 + ret = device_for_each_child_reverse(dev, &pm_data, mipi_i3c_hci_pci_suspend_instance); 308 + if (ret) 309 + for (int i = 0; i < pm_data.dev_cnt; i++) 310 + i3c_hci_rpm_resume(pm_data.dev[i]); 311 + 312 + return ret; 313 + } 314 + 315 + static int mipi_i3c_hci_pci_resume(struct device *dev) 316 + { 317 + struct mipi_i3c_hci_pci *hci = dev_get_drvdata(dev); 318 + struct mipi_i3c_hci_pci_pm_data pm_data = {}; 319 + int ret; 320 + 321 + if (!hci->info->control_instance_pm) 322 + return 0; 323 + 324 + ret = device_for_each_child(dev, &pm_data, mipi_i3c_hci_pci_resume_instance); 325 + if (ret) 326 + for (int i = 0; i < pm_data.dev_cnt; i++) 327 + i3c_hci_rpm_suspend(pm_data.dev[i]); 328 + 329 + return ret; 330 + } 331 + 223 332 static void mipi_i3c_hci_pci_rpm_allow(struct device *dev) 224 333 { 225 334 pm_runtime_put(dev); ··· 452 323 453 324 /* PM ops must exist for PCI to put a device to a low power state */ 454 325 static const struct dev_pm_ops mipi_i3c_hci_pci_pm_ops = { 326 + RUNTIME_PM_OPS(mipi_i3c_hci_pci_suspend, mipi_i3c_hci_pci_resume, NULL) 327 + SYSTEM_SLEEP_PM_OPS(mipi_i3c_hci_pci_suspend, mipi_i3c_hci_pci_resume) 455 328 }; 456 329 457 330 static const struct pci_device_id mipi_i3c_hci_pci_devices[] = {

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