tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/xe: Add reg read/write trace

This will help debug register read/writes and provides
a way to trace all the mmio transactions.

v2: Fix kunit error
v3: Print devid to help in multi-gpu setup
v3: rebase and use variable sized variant to display
dev name(Gustavo)
v4: Pass single argument to __asign_str to fix kunit error
v5: Remove unrelated include xe_tile.h and remove cast in trace

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240607182943.3572524-7-radhakrishna.sripada@intel.com

authored by

Radhakrishna Sripada and committed by
Matt Roper e81568a0 501c4255

+47 -4
+19 -4
drivers/gpu/drm/xe/xe_mmio.c
··· 21 21 #include "xe_gt_sriov_vf.h" 22 22 #include "xe_macros.h" 23 23 #include "xe_sriov.h" 24 + #include "xe_trace.h" 24 25 25 26 static void tiles_fini(void *arg) 26 27 { ··· 125 124 { 126 125 struct xe_tile *tile = gt_to_tile(gt); 127 126 u32 addr = xe_mmio_adjusted_addr(gt, reg.addr); 127 + u8 val; 128 128 129 - return readb((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr); 129 + val = readb((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr); 130 + trace_xe_reg_rw(gt, false, addr, val, sizeof(val)); 131 + 132 + return val; 130 133 } 131 134 132 135 u16 xe_mmio_read16(struct xe_gt *gt, struct xe_reg reg) 133 136 { 134 137 struct xe_tile *tile = gt_to_tile(gt); 135 138 u32 addr = xe_mmio_adjusted_addr(gt, reg.addr); 139 + u16 val; 136 140 137 - return readw((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr); 141 + val = readw((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr); 142 + trace_xe_reg_rw(gt, false, addr, val, sizeof(val)); 143 + 144 + return val; 138 145 } 139 146 140 147 void xe_mmio_write32(struct xe_gt *gt, struct xe_reg reg, u32 val) ··· 150 141 struct xe_tile *tile = gt_to_tile(gt); 151 142 u32 addr = xe_mmio_adjusted_addr(gt, reg.addr); 152 143 144 + trace_xe_reg_rw(gt, true, addr, val, sizeof(val)); 153 145 writel(val, (reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr); 154 146 } 155 147 ··· 158 148 { 159 149 struct xe_tile *tile = gt_to_tile(gt); 160 150 u32 addr = xe_mmio_adjusted_addr(gt, reg.addr); 151 + u32 val; 161 152 162 153 if (!reg.vf && IS_SRIOV_VF(gt_to_xe(gt))) 163 - return xe_gt_sriov_vf_read32(gt, reg); 154 + val = xe_gt_sriov_vf_read32(gt, reg); 155 + else 156 + val = readl((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr); 164 157 165 - return readl((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr); 158 + trace_xe_reg_rw(gt, false, addr, val, sizeof(val)); 159 + 160 + return val; 166 161 } 167 162 168 163 u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr, u32 set)
+28
drivers/gpu/drm/xe/xe_trace.h
··· 346 346 TP_ARGS(fence) 347 347 ); 348 348 349 + TRACE_EVENT(xe_reg_rw, 350 + TP_PROTO(struct xe_gt *gt, bool write, u32 reg, u64 val, int len), 351 + 352 + TP_ARGS(gt, write, reg, val, len), 353 + 354 + TP_STRUCT__entry( 355 + __string(dev, __dev_name_gt(gt)) 356 + __field(u64, val) 357 + __field(u32, reg) 358 + __field(u16, write) 359 + __field(u16, len) 360 + ), 361 + 362 + TP_fast_assign( 363 + __assign_str(dev); 364 + __entry->val = val; 365 + __entry->reg = reg; 366 + __entry->write = write; 367 + __entry->len = len; 368 + ), 369 + 370 + TP_printk("dev=%s, %s reg=0x%x, len=%d, val=(0x%x, 0x%x)", 371 + __get_str(dev), __entry->write ? "write" : "read", 372 + __entry->reg, __entry->len, 373 + (u32)(__entry->val & 0xffffffff), 374 + (u32)(__entry->val >> 32)) 375 + ); 376 + 349 377 #endif 350 378 351 379 /* This part must be outside protection */